CN101082880A - Method and system for prompting the speed of downloading data single-chip target memory from slave computer - Google Patents
Method and system for prompting the speed of downloading data single-chip target memory from slave computer Download PDFInfo
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Abstract
The invention discloses a downloading accelerating method and system from computer to goal memory of single-chip set, which consists of single-chip set and computer, wherein the computer contains main downloading control unit and interface unit; the single-chip set concludes goal memory to connect inner bus, RAM, conveying unit and interface unit; the goal memory needs to write extra order sequence when writing one-character data; PC writes each data and allocating information of data block into RAM of single-chip set after starting to download the local data in the memory equipment of single-chip set, which starts RAM in the single-chip set to convey data with goal memory to make character as unit to write data into the ordered position of goal memory until finishing conveying the data; PC downloads a next data block until the data block is downloaded completely. The invention accelerates the speed of data from computer to the goal memory of single-chip set.
Description
Technical field
The present invention relates to a kind of method from the downloaded data to the single-chip microcomputer storer.
Background technology
Continuous application along with singlechip technology, the user need utilize nor FLASH (nor type flash memory, FLASH in the literary composition all refers to nor FLASH) technology stores a large amount of codes and data, when the user utilizes PC (or other computing machine) to carry out emulation, debugging, data and code from downloading to the FLASH of single-chip microcomputer, PC are needed a large amount of time, have a strong impact on user's exploitation, thereby the utmost point need improve the speed to the nor of single-chip microcomputer FLASH data download from PC, to save the time of debugging and exploitation.
Referring to Fig. 1, download with u ' nSP Integrated Development Environment (IDE) is an example, illustrate original from the method for PC to single-chip microcomputer FLASH data download, this IDE forms at PC side operation corresponding software, it is by ICE (In-Circuit Emulation, in-circuit emulator) be responsible for communicating by letter between PC and single-chip microcomputer, this ICE is made up of PC side and the corresponding ICE interface unit of monolithic pusher side
To download the data instance of 1M word, word is a storage cell under this environment, also is referred to as " word " in the literary composition, and in u ' nSP, 1 word is 2 bytes.Because 1M word is not necessarily continuous, suppose that every 2K word is a continuous space, i.e. a data block (block), original method for down loading is as follows:
Step 1: according to the working rule of nor FLASH, nor FLASH with AMD/SST/GX is an example, IDE is before writing the data of a word to FLASH, need to write three orders (command) by interface ICE to FLASH earlier, some special addresses write the special data of a word in FLASH, just cry and write an order, order in the literary composition is implication for this reason all, different FLASH has different command address, but all need to write three times, these three orders are called a command sequence (command sequences), carry out the operation of write data after having write again;
Step 2: for each word in each data block, repeat one time step 1, write up to the data of this data block;
Step 3: the data block that will write FLASH is read and is done the correctness inspection, if incorrect prompting error message, and would allow the user determine whether to continue to download; If correctly then execution in step 4.
Read data does not need write order from NOR FLASH, and the data in data block can disposablely be read.
Step 4: carry out step 1 repeatedly～3, up to the data of having downloaded all 1M word.
The above-mentioned first step is the main bottleneck of restriction speed of download, for each word in each data block, IDE need write the operation of carrying out write data behind three subcommands again by ICE, it is the write operation that the data of a word of every download need be carried out four ICE, and write order and write data all are to write the data of a word (for ICE at every turn, write a word at every turn and write the needed time of a plurality of words much at one at every turn), the data of downloading 1M like this need be carried out the write operation of 4000000 ICE, and speed is extremely slow.Each downloaded a data block and all need to read out afterwards and carry out the correctness inspection, the data of 1M need be carried out the read operation of 500 ICE, and this also is a factor that restricts speed of download to a certain extent.
Summary of the invention
The technical problem to be solved in the present invention provides method and the system thereof of a kind of quickening from the downloaded data to the single-chip microcomputer target memory.
For solving the problems of the technologies described above, the present invention the method for a kind of quickening from the downloaded data to the single-chip microcomputer target memory is provided, when this target memory writes the data of a word, need additionally write a command sequence, this method may further comprise the steps:
(a) computing machine initiates once local data to be downloaded to the process of the described memory device of single-chip microcomputer, data downloaded in one or more data blocks;
(b) in the random access memory ram that computing machine is write single-chip microcomputer with the data and the configuration information thereof of a data block at every turn, this configuration information comprises that at least these data block data write the initial target address of target memory and the length of this data block;
(c) the data handling process between startup single-chip microcomputer internal RAM and target memory, it with the word assigned address that data block data that unit will write RAM are write this target memory successively, need carry out the operation of write commands sequence and the operation of write data when whenever writing a word, finish up to a data blocks of data carrying;
(d) computing machine judges whether that the data of all data blocks have all been downloaded after a data blocks of data carrying is finished, and if not, returns step (b), otherwise, finish.
Further, said method also can have following characteristics: described single-chip microcomputer target memory is meant the nor type flash memory on the single-chip microcomputer.
Further, said method also can have following characteristics: marked off data buffer area, configuration information district, code area and variable range among the described RAM, and each regional starting and ending address is fixed; The slow district of these data deposits the data that are used for temporary data block from the downloaded to RAM, this configuration information district is used to preserve the configuration information relevant with this data block, this code area is used to preserve the binary object code of carrying program, the variable that this variable range uses when being used to preserve this carrying program run.
Further, said method also can have following characteristics: the correctness of also checking the carrying data in the described step (c), promptly after writing a word in this target memory, also the data of this word are read from target memory with RAM in former data relatively, if both are identical, then this word writes correctly, otherwise this word writes and makes mistakes; Data as a data block all successfully write, and indication carry successfully when finishing this time to carry, and make mistakes or a word repeatedly writes when still makeing mistakes finding that a word writes, and finish handling process and indication and carry and fail; Computing machine judges according to described indication whether carrying is successful, as success, judges whether all data block data have been downloaded again after a data blocks of data carrying is finished, as failure, then make the fault reason, finishes.
Further, said method also can have following characteristics: in the described step (c), be provided with an initial value during beginning of data handling process and be 0 temporary variable, when the data of a word are write target memory in RAM, with the initial position of data block data in RAM and this temporary variable and as source address, with the data block data write the initial target address of target memory and this temporary variable and as destination address, after target memory writes the data of a word, this temporary variable is added 1 in success, and the data length of this temporary variable and this data block compared, both are identical to think that these data block data have been carried and finishes, otherwise, the data that continue to carry next word.
Further, said method also can have following characteristics: the configuration information that writes described RAM in the described step (b) comprises that also the order in the command sequence writes the destination address of target memory.
Further, said method also can have following characteristics: described data handling process is to be carried out by the carrying program on the computing machine, and in step (b) before, the binary object code that computing machine earlier should the carrying program is loaded among the RAM of this single-chip microcomputer.
Further, said method also can have following characteristics: in the described step (b), computing machine also is provided with breakpoint in two outlets of carrying program binary object code, one of them outlet is the end outlet in when failure carrying, and another is that the end of a data blocks of data when carry successfully exports.
The system of quickening provided by the invention from the downloaded data to the single-chip microcomputer memory device comprises continuous single-chip microcomputer and computing machine, comprise in the described computing machine and download main control unit and interface unit, comprise the target memory, random access memory ram and the interface unit that are connected to internal bus in the described single-chip microcomputer, this target memory need additionally write a command sequence when writing the data of a word, it is characterized in that, also comprise a carrying unit in the described single-chip microcomputer, wherein:
The data that described download main control unit is used to initiate and carry out from this locality to the single-chip microcomputer target memory are downloaded, interface unit by described computing machine and single-chip microcomputer, with the data block be unit will data downloaded and configuration information write among the RAM of single-chip microcomputer, start the carrying unit of single-chip microcomputer then and after the carrying of this unit is finished, continue the processing of next data block, finish up to all data downloads, described configuration information comprises that at least these data block data write the initial target address of target memory and the length of this data block;
The interface unit of described computing machine and single-chip microcomputer is used to realize the communication between computing machine and the single-chip microcomputer;
It is unit that described carrying unit is used for the word, write the assigned address of target memory successively with writing data block data among the single-chip microcomputer RAM, need carry out the operation of write commands sequence and the operation of write data when whenever writing a word, finish up to a data blocks of data carrying;
Described RAM is used to preserve data block data and the configuration information thereof from downloaded, and used object code and the variable thereof in described carrying unit.
Further, said system also can have following characteristics: the ingredient that download main control unit in the described computing machine and interface unit are Integrated Development Environment, target memory in the described single-chip microcomputer is a nor type flash memory, and the interface unit in described computing machine and the single-chip microcomputer is the ICE interface unit.
Further, said system also can have following characteristics: data block data, configuration information, object code and the variable of preserving among the described RAM is to be divided into 4 different zones to deposit, and each regional starting and ending address is fixed.
Further, said system also can have following characteristics: the correctness of carrying data is also checked in described carrying unit, promptly after writing a word in this target memory, also the data of this word are read from target memory with RAM in former data relatively, if both are identical, then this word writes correctly, otherwise this word writes and makes mistakes; Data as a data block all successfully write, and indication carry successfully when finishing this time to carry, and make mistakes or a word repeatedly writes when still makeing mistakes finding that a word writes, and finish handling process and indication and carry and fail; Described download main control unit judges according to the indication that this carrying unit provides whether carrying is successful, as success after a data blocks of data carrying is finished, download next data block data again, finish up to all data block data downloads, as the carrying failure, then make the fault reason, finish.
Further, said system also can have following characteristics: described carrying unit is provided with an initial value when the beginning of data handling process be 0 temporary variable, when the data of a word are write target memory in RAM, with the initial position of data block data in RAM and this temporary variable and as source address, with the data block data write the initial target address of target memory and this temporary variable and as destination address; After target memory writes the data of a word this temporary variable is being added 1 in success, and the data length of this temporary variable and this data block is being compared, both are identical to think that these data block data have been carried and finishes, otherwise, the data that continue to carry next word.
Further, said system also can have following characteristics: the variable of described variable range storage comprises: the carrying of expression " carrying " correctness sign, order as a result writes the destination address of target memory, the initial target address that the data block data write target memory, the data length of data block, and one is used to write down and carries number of words and as the temporary variable of address offset amount; The configuration information of preserving in the described configuration information district comprises: order writes the destination address of target memory, initial target address that the data block data write target memory and the data length of data block.
Further, said system also can have following characteristics: described download main control unit is before the carrying unit that starts single-chip microcomputer, also two outlets in carrying program binary object code are provided with breakpoint, one of them outlet is the end outlet in when failure carrying, and another is that the end of a data blocks of data when carry successfully exports.
Compared to prior art, when the present invention downloaded the data of a data block, IDE was earlier with the disposable ram region that downloads to of these data, and do not need the write command sequence this moment, and the number of times that uses ICE to read and write like this significantly reduces.The present invention is " carrying " program implementation the main time, because this section program is to carry out in that single-chip microcomputer is inner, and is that data with whole data block are transported to FLASH from RAM district during carrying, and the speed lifting is very obvious.In addition, the present invention also can finish the correctness inspection to the carrying data in " carrying " program, further saved download time, has improved speed.
Description of drawings
Fig. 1 be prior art from PC to single-chip microcomputer flash memory data download based on system architecture diagram.
Fig. 2 is the functional block diagram of embodiment of the invention system.
Fig. 3 is that the embodiment of the invention is from the process flow diagram of PC to single-chip microcomputer flash memory data download.
Embodiment
Basic thought of the present invention is that the operation that original IDE utilizes ICE to read and write FLASH is put into single-chip microcomputer inside, the data of a data block of every download, IDE is earlier with the disposable random-access memory (ram) zone that downloads to of these data, do not need the write command sequence this moment, and the number of times that utilizes ICE to read and write like this significantly reduces.By the single-chip microcomputer internal processes data of whole data block are transported to NOR FLASH from the RAM district then, thereby improve the speed of downloading greatly.
The present invention is described in detail below in conjunction with drawings and Examples:
Present embodiment also is based on hardware configuration shown in Figure 1, comprises single-chip microcomputer and coupled PC.As representing that with the functional module among Fig. 2 then the PC side comprises two correlation units: download main control unit and ICE interface unit, be the ingredient of IDE; Correlation unit on the single-chip microcomputer then comprises FLASH, RAM, ICE interface unit and the carrying unit that is connected to internal bus.
Download main control unit and be used to initiate and carry out data downloading task from the PC side to single-chip microcomputer FLASH, ICE interface unit by PC and single-chip microcomputer, with the data block be unit will data downloaded and configuration information write among the RAM of single-chip microcomputer, start the carrying unit of single-chip microcomputer and next data block of continuation download when detecting this unit and carry successfully, finish up to download, as detect this unit carrying failure, then make the fault reason.
The ICE interface unit of PC and single-chip microcomputer is used to realize the communication between PC and the single-chip microcomputer, comprises the mutual of control signal and data-signal.
For data are write single-chip microcomputer FLASH and carried out the correctness inspection from the ram space of single-chip microcomputer, need write one section carrying program (as assembly routine) earlier and it is compiled into binary object code.(model is u ' nSP by 16 8-digit microcontrollers in the single-chip microcomputer
TM) move this object code and finish the carrying function, relevant software and hardware has promptly constituted above-mentioned carrying unit.This carrying unit is used for the data block data of writing single-chip microcomputer RAM are write again the assigned address of FLASH, whenever write a word and need carry out the operation of several times write order and a data writing operation, it to be read after having write and do the correctness verification, finish carrying in the carrying success of 1 data block or when makeing mistakes, and carry as a result sign with one and represent this time to carry the result.
RAM is divided into 4 districts more effectively to utilize ram region.A kind of example of division is as shown in the table, but is not limited thereto:
| Variable range | The code area | The configuration information district | Data buffer area (buffer) |
0 0x100 0x1f9 0x200
Wherein:
Data buffer area (Buffer): be used for temporarily depositing from PC side data downloaded blocks of data.
Variable range: the variable of using when being used to store the carrying program run, comprise that carrying sign, the order (command) as a result of expression " carrying " correctness writes the data length of the destination address of FLASH, initial target address that the data block data write FLASH, data block (number with the word that comprises is represented) and wait variable, and one is used to write down and carries number of words and as the temporary variable of address offset amount.In addition, the initial position (0x200) that write data in buffer among the destination address of order of FLASH and the RAM is fixed, can be in program indirect assignment, do not get rid of certainly and write on variable range as variable.
The code area: be used to store the binary object code of carrying program, this field capacity wants to guarantee to load all binary object code, and before carrying out down operation, PC will download to this code area with binary object code that should the carrying program.
The configuration information district: be used for when data block of every download, the configuration information that storage PC sidelights on are gone into comprises: order (command) writes the destination address of FLASH, initial target address that the data block data write FLASH and the data length of data block.
The value that order in the variable range writes the variablees such as data length of the destination address of FLASH, initial target address that the data block data write FLASH and data block directly reads from the configuration information district.In addition because these values need not variation in handling process, in other embodiments, also can be directly with the address definition of these variablees in the relevant position in configuration information district, the memory location of these variablees promptly is not set in variable range again.
As shown in Figure 3, the method for present embodiment from the PC data download to single-chip microcomputer FLASH may further comprise the steps:
Step 10, PC initiates once to download data to the process of single-chip microcomputer FLASH, data downloaded in one or more data blocks;
In this step, if the binary object code of carrying program also is not loaded into the code area of single-chip microcomputer RAM, then the binary object code that will carry program earlier by PC downloads to the code area of single-chip microcomputer RAM.
Step 20, PC at every turn with the data write once of 1 data block in the data buffer area of single-chip microcomputer RAM, the configuration information that this data block is relevant writes the configuration information district of this RAM, and configuration information comprises that command sequence writes the destination address of FLASH, the data block data write the initial target address of FLASH and the length of this data block;
In the above-mentioned configuration information, the destination address that command sequence writes FLASH is optionally, does not for example need to specific address write command sequence, so do not need this configuration information when Intel nor FLASH write data.
Step 30, start the data handling process between single-chip microcomputer internal RAM and the FLASH, the initial value of correlated variables is set earlier, according to configuration information the variable of the data length of destination address that command sequence writes FLASH, initial target address that the data block data write FLASH and data block is set, the temporary variable initial value is changed to 0;
Step 40, with the word is that unit is transported to the data of data block among the RAM among the FLASH successively, during word of every carrying, need write the data of a command sequence and a word in FLASH, source address when writing data and destination address equal its initial value and current temporary variable sum separately;
Step 50, the data that write this word of FLASH are read and RAM in the former data of storing relatively, if identical, execution in step 60, otherwise, the carrying result is set is masked as vacation and stops handling process (step 50a), execution in step 70;
The last step can repeatedly write again to this word before this sign is set.
Step 60, after the temporary variable unit of adding step-length 1, judge whether it equals the length of this data block, the data that promptly judge whether 1 data block are all carried and are finished, if the carrying result is set is masked as true and stops handling process (step 60a), execution in step 70, otherwise, return step 40 and continue carrying;
Step 70, PC learns this handling process end, and (it is out of service to detect singlechip microprocessor as PC by ICE, perhaps initiatively send look-at-me to PC by the carrying program, or the like) after, read carrying sign judgement as a result carrying this time and make mistakes or success, as success, execution in step 80, otherwise, carry out error handling processing, finish;
Step 80, PC judges whether that all data blocks have downloaded to FLASH, if do not downloaded, returns step 20, as having downloaded, finishes.
From top flow process as can be seen, the carrying program has two outlets, and one is the end outlet in when failure carrying, and another is that the end of a data blocks of data when carry successfully exports.For program the time can be withdrawed from running to these two outlets, a kind of mode be computing machine in step 20, also these two outlets in carrying program binary object code are provided with breakpoint, but realize that the mode that withdraws from is not limited thereto.
When " carrying " program was carried out " carrying " of block data, the write operation of the nor FLASH of Intel and the FLASH of other manufacturers was different, divided " carrying " process of general " carrying " process and Intelnor FLASH to introduce respectively below:
For general " carrying " process, step is as follows:
Step 1, read the configuration information of the data block that needs carrying, destination address (relating to three orders), the data block data that order writes FLASH are set write the initial target address D esAddr of FLASH and the variablees such as data length of data block, and temporary variable I is set is 0;
Wherein order the destination address that writes FLASH to comprise the target address information of three orders that will write, this several values of different nor FLASH may be different, thus need configuration, but all not necessary in any condition.In addition, because the reference position SrcAddr of block deposit data is fixed on 0x200, the program of can writing direct also can be set to a variable.
Step 2 writes the destination address of FLASH according to order, the relevant position that the data of three orders in the command sequence are write FLASH;
Step 3 is write the data of a word among the RAM among the FLASH, and source address is SrcAddr+I, and destination address is DesAddr+I;
Step 4 is read the data that just write a word among the FLASH, compares with former data among the RAM, if equating to show writes correctly, continues next step; If mistake will carry then as a result that sign is changed to vacation (as in step 1 this sign being changed to vacation, then can no longer be provided with) herein, jump to the procedure failure place, withdraw from, finish carrying this time; Do (I not too understand to be written as " carry out error handling processing, finish " why not? thanks! )
Step 5 increases a step-length with temporary variable I, is to add 1 here, judges whether it equals the data length of data block, if do not wait, returns step 2, otherwise, will carry as a result that sign is changed to very, the program that jumps to is successfully located, and withdraws from, and finishes this and carries.
For the nor FLASH of Intel, " carrying " process steps is as follows:
Steps A will carry as a result that sign is changed to vacation, read the configuration information of the data block that needs carrying, the data block data are set write the initial target address D esAddr of FLASH and the variablees such as data length of data block, and temporary variable I is set be 0;
Equally, the reference position SrcAddr of data block deposit data also is 0x200.
In addition, have very big difference on Intel nor FLASH and other FLASH write methods, it does not need to specific address write command sequence, so configuration order does not write the destination address of FLASH, these variablees can be set yet.But, it can be unified the form of configuration information as configuration information, help guaranteeing the unanimity of PC upper layer software (applications) interface, thereby guaranteed that this method can be applied to different FLASH.
Step B, first order in FLASH write command sequence: buffer command, destination address is DesAddr+I, ([DesAddr+I]=0xe8);
Step C reads the value of XSR register to DesAddr+I, and this is worth the 7th is can carry out next step at 1 o'clock, otherwise continue to read this value, being worth the 7th up to this is 1, still is not 1 if surpass this value of certain hour, then jump to the procedure failure place, program withdraws from, and finishes this handling process;
Step D writes the data of a word among the RAM among the FLASH, and source address is SrcAddr+I, and destination address is DesAddr+I;
Step e, first order in FLASH write command sequence: confirm command, destination address is DesAddr+I, ([DesAddr+I]=0xd0), word carrying so far finishes;
Step F is read the data that just write a word among the FLASH, compares with former data among the RAM, if equating to show writes correctly, continues next step; If mistake then jumps to the procedure failure place, withdraw from, finish this handling process;
Step G, I adds 1 with temporary variable, judges whether it equals the data length of data block, if do not wait, returns step B, otherwise, will carry as a result that sign is changed to very, the program that jumps to is successfully located, and withdraws from, and finishes this handling process.
Be to download the typical data that test obtains below:
Utilize existing method and the inventive method respectively 1M word data to be downloaded to the single-chip microcomputer flash memory from PC, obtain following test data:
USB Probe: the about 7.8kb/s of speed of download before improving, the speed of download after the improvement is 16.3kb/s
Printer Probe: 0.85kb/s before improving, improve back 12kb/s
By above data as can be seen, adopt the acceleration effect of the inventive method data download very obvious, and the resource of downloading is big more, Block size is big more, and the effect of acceleration will be obvious more.
In sum, the operation that the inventive method utilizes ICE to read and write FLASH original IDE has been put into single-chip microcomputer inside, the data of a block of every download, IDE is earlier with the disposable ram region that downloads to of these data, because do not need the write command sequence when writing RAM, the number of times that utilizes ICE to read and write like this significantly reduces.
The main time of the inventive method is " carrying " program implementation, because this section program is in the inner execution of single-chip microcomputer, its speed is many than utilizing ICE to go out soon on PC, to write a word is example, originally need utilize ICE to carry out write operation 4 times by USB or printer port, now these write operations all have been put into single-chip microcomputer inside and carry out promptly from the RAM district of single-chip microcomputer and be transported to FLASH, and carrying the time is that data with whole block are transported to FLASH from RAM district, and the speed lifting is very obvious.
In addition, the inventive method has been finished the correctness inspection to the carrying data in " carrying " program, do not need as prior art, to have downloaded again again it to be read from the ICE interface after the block data and do the correctness inspection, further saved download time yet, improved speed.
Need to prove that the present invention not only is applicable to the above-mentioned occasion that downloads data to single-chip microcomputer nor FLASH from PC.Can know from above-mentioned analysis, for any when the data download, unit data of every download all needs to be undertaken by external interface the occasion of write data other write operation in addition, can utilize the inventive method, promptly earlier the data of a data block all are written to the internal RAM of single-chip microcomputer, again data are transported to target memory from this RAM, promptly can accelerate speed of download.Target memory is not limited to nor FLASH, and used IDE also is not limited to u ' nSP, and all interfaces are not limited to the ICE interface.No matter be applied to the IDE of what target memory and what type, its downloading process and the foregoing description all are essentially identical, but might not carry out verification to the correctness of data, and this is to be decided by used IDE.
In addition, some links of the foregoing description also can conversion, and for example, whether single-chip microcomputer is carried when successful to 1 data blocks of data of PC indication, also can indicate different carrying results with different look-at-mes by the mode of interrupting.
Claims (15)
1, a kind of method of accelerating from the downloaded data to the single-chip microcomputer target memory need additionally write a command sequence when this target memory writes the data of a word, and this method may further comprise the steps:
(a) computing machine initiates once local data to be downloaded to the process of the described memory device of single-chip microcomputer, data downloaded in one or more data blocks;
(b) in the random access memory ram that computing machine is write single-chip microcomputer with the data and the configuration information thereof of a data block at every turn, this configuration information comprises that at least these data block data write the initial target address of target memory and the length of this data block;
(c) the data handling process between startup single-chip microcomputer internal RAM and target memory, it with the word assigned address that data block data that unit will write RAM are write this target memory successively, need carry out the operation of write commands sequence and the operation of write data when whenever writing a word, finish up to a data blocks of data carrying;
(d) computing machine judges whether that the data of all data blocks have all been downloaded after a data blocks of data carrying is finished, and if not, returns step (b), otherwise, finish.
2, the method for claim 1 is characterized in that, described single-chip microcomputer target memory is meant the nor type flash memory on the single-chip microcomputer.
3, the method for claim 1 is characterized in that, has marked off data buffer area, configuration information district, code area and variable range among the described RAM, and each regional starting and ending address is fixed; The slow district of these data deposits the data that are used for temporary data block from the downloaded to RAM, this configuration information district is used to preserve the configuration information relevant with this data block, this code area is used to preserve the binary object code of carrying program, the variable that this variable range uses when being used to preserve this carrying program run.
4, the method for claim 1, it is characterized in that, also check the correctness of carrying data in the described step (c), promptly after writing a word in this target memory, also the data of this word are read from target memory with RAM in former data relatively, if both are identical, then this word writes correctly, otherwise this word writes and makes mistakes; Data as a data block all successfully write, and indication carry successfully when finishing this time to carry, and make mistakes or a word repeatedly writes when still makeing mistakes finding that a word writes, and finish handling process and indication and carry and fail; Computing machine judges according to described indication whether carrying is successful, as success, judges whether all data block data have been downloaded again after a data blocks of data carrying is finished, as failure, then make the fault reason, finishes.
5, the method of claim 1, it is characterized in that, in the described step (c), be provided with an initial value during beginning of data handling process and be 0 temporary variable, when the data of a word are write target memory in RAM, with the initial position of data block data in RAM and this temporary variable and as source address, with the data block data write the initial target address of target memory and this temporary variable and as destination address, after target memory writes the data of a word, this temporary variable is added 1 in success, and the data length of this temporary variable and this data block compared, both are identical to think that these data block data have been carried and finishes, otherwise, the data that continue to carry next word.
6, the method for claim 1 is characterized in that, the configuration information that writes described RAM in the described step (b) comprises that also the order in the command sequence writes the destination address of target memory.
7, the method for claim 1 is characterized in that, described data handling process is to be carried out by the carrying program on the computing machine, and in step (b) before, the binary object code that computing machine earlier should the carrying program is loaded among the RAM of this single-chip microcomputer.
8, the method for claim 1, it is characterized in that, in the described step (b), computing machine also is provided with breakpoint in two outlets of carrying program binary object code, one of them outlet is the end outlet in when failure carrying, and another is that the end of a data blocks of data when carry successfully exports.
9, a kind of system that accelerates from the downloaded data to the single-chip microcomputer target memory, comprise continuous single-chip microcomputer and computing machine, comprise in the described computing machine and download main control unit and interface unit, comprise the target memory, random access memory ram and the interface unit that are connected to internal bus in the described single-chip microcomputer, this target memory need additionally write a command sequence when writing the data of a word, it is characterized in that, also comprise a carrying unit in the described single-chip microcomputer, wherein;
The data that described download main control unit is used to initiate and carry out from this locality to the single-chip microcomputer target memory are downloaded, interface unit by described computing machine and single-chip microcomputer, with the data block be unit will data downloaded and configuration information write among the RAM of single-chip microcomputer, start the carrying unit of single-chip microcomputer then and after the carrying of this unit is finished, continue the processing of next data block, finish up to all data downloads, described configuration information comprises that at least these data block data write the initial target address of target memory and the length of this data block;
The interface unit of described computing machine and single-chip microcomputer is used to realize the communication between computing machine and the single-chip microcomputer;
It is unit that described carrying unit is used for the word, write the assigned address of target memory successively with writing data block data among the single-chip microcomputer RAM, need carry out the operation of write commands sequence and the operation of write data when whenever writing a word, finish up to a data blocks of data carrying;
Described RAM is used to preserve data block data and the configuration information thereof from downloaded, and used object code and the variable thereof in described carrying unit.
10, system as claimed in claim 9, it is characterized in that, the ingredient that download main control unit in the described computing machine and interface unit are Integrated Development Environment, target memory in the described single-chip microcomputer is a nor type flash memory, and the interface unit in described computing machine and the single-chip microcomputer is the ICE interface unit.
11, system as claimed in claim 9 is characterized in that, data block data, configuration information, object code and the variable of preserving among the described RAM is to be divided into 4 different zones to deposit, and each regional starting and ending address is fixed.
12, system as claimed in claim 9, it is characterized in that, the correctness of carrying data is also checked in described carrying unit, promptly after writing a word in this target memory, also the data of this word are read from target memory with RAM in former data relatively, if both are identical, then this word writes correctly, otherwise this word writes and makes mistakes; Data as a data block all successfully write, and indication carry successfully when finishing this time to carry, and make mistakes or a word repeatedly writes when still makeing mistakes finding that a word writes, and finish handling process and indication and carry and fail; Described download main control unit judges according to the indication that this carrying unit provides whether carrying is successful, as success after a data blocks of data carrying is finished, download next data block data again, finish up to all data block data downloads, as the carrying failure, then make the fault reason, finish.
13, method as claimed in claim 9, it is characterized in that, described carrying unit is provided with an initial value when the beginning of data handling process be 0 temporary variable, when the data of a word are write target memory in RAM, with the initial position of data block data in RAM and this temporary variable and as source address, with the data block data write the initial target address of target memory and this temporary variable and as destination address; After target memory writes the data of a word this temporary variable is being added 1 in success, and the data length of this temporary variable and this data block is being compared, both are identical to think that these data block data have been carried and finishes, otherwise, the data that continue to carry next word.
14, method as claimed in claim 11, it is characterized in that, the variable of described variable range storage comprises: the carrying of expression " carrying " correctness sign, order as a result writes the destination address of target memory, the initial target address that the data block data write target memory, the data length of data block, and one is used to write down and carries number of words and as the temporary variable of address offset amount; The configuration information of preserving in the described configuration information district comprises: order writes the destination address of target memory, initial target address that the data block data write target memory and the data length of data block.
15, method as claimed in claim 9, it is characterized in that, described download main control unit is before the carrying unit that starts single-chip microcomputer, also two outlets in carrying program binary object code are provided with breakpoint, one of them outlet is the end outlet in when failure carrying, and another is that the end of a data blocks of data when carry successfully exports.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2006100833364A CN100533404C (en) | 2006-06-02 | 2006-06-02 | Method and system for prompting downloading data to single-chip target memory from computer |
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| CNB2006100833364A CN100533404C (en) | 2006-06-02 | 2006-06-02 | Method and system for prompting downloading data to single-chip target memory from computer |
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| CN101082880A true CN101082880A (en) | 2007-12-05 |
| CN100533404C CN100533404C (en) | 2009-08-26 |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106803036A (en) * | 2017-02-16 | 2017-06-06 | 深圳前海生生科技有限公司 | The safety detection and fault-tolerance approach of data flow in system operation |
| CN106844116A (en) * | 2016-12-23 | 2017-06-13 | 惠州市蓝微电子有限公司 | It is a kind of to realize the method and apparatus that check test is calibrated in IC burnings |
| CN106874796A (en) * | 2017-02-16 | 2017-06-20 | 深圳前海生生科技有限公司 | The safety detection and fault-tolerance approach of instruction stream in system operation |
| CN117055928A (en) * | 2023-10-09 | 2023-11-14 | 深圳市好盈科技股份有限公司 | Method and device for detecting firmware errors of electronic speed regulator of target model airplane |
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2006
- 2006-06-02 CN CNB2006100833364A patent/CN100533404C/en not_active Expired - Fee Related
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106844116A (en) * | 2016-12-23 | 2017-06-13 | 惠州市蓝微电子有限公司 | It is a kind of to realize the method and apparatus that check test is calibrated in IC burnings |
| CN106803036A (en) * | 2017-02-16 | 2017-06-06 | 深圳前海生生科技有限公司 | The safety detection and fault-tolerance approach of data flow in system operation |
| CN106874796A (en) * | 2017-02-16 | 2017-06-20 | 深圳前海生生科技有限公司 | The safety detection and fault-tolerance approach of instruction stream in system operation |
| CN106803036B (en) * | 2017-02-16 | 2021-03-30 | 中云信安（深圳）科技有限公司 | Safety detection and fault tolerance method for data stream in system operation |
| CN106874796B (en) * | 2017-02-16 | 2021-03-30 | 中云信安（深圳）科技有限公司 | Safety detection and fault-tolerant method for instruction stream in system operation |
| CN117055928A (en) * | 2023-10-09 | 2023-11-14 | 深圳市好盈科技股份有限公司 | Method and device for detecting firmware errors of electronic speed regulator of target model airplane |
| CN117055928B (en) * | 2023-10-09 | 2024-01-26 | 深圳市好盈科技股份有限公司 | Method and device for detecting firmware errors of electronic speed regulator of target model airplane |
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| Publication number | Publication date |
|---|---|
| CN100533404C (en) | 2009-08-26 |
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