CN101078997A - Semiconductor integrated circuit system, semiconductor integrated circuit, operating system, and control method for semiconductor integrated circuit - Google Patents
Semiconductor integrated circuit system, semiconductor integrated circuit, operating system, and control method for semiconductor integrated circuit Download PDFInfo
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Abstract
A solution for improving a semiconductor integrated circuit performance through elimination of excessive margins. This semiconductor integrated circuit system comprises a program executing control target circuit, a system information monitor for outputting system information which indicates the state of the control target circuit, a circuit property monitor for acquiring and outputting the circuit properties of the control target circuit as circuit property information, a malfunction determination module for checking whether the control target circuit is operating normally based on the output system information, a reference circuit property storage module for retaining the circuit property information as reference circuit property information when the control target circuit is operating normally, a malfunction source determination module for locating a malfunction source based on the circuit property information acquired by the circuit property monitor and the reference circuit property information when the control target circuit is not operating normally and a correction target determination module for determining a correction target in the control target circuit based on the malfunction source and generating the target electric property information.
Description
The cross reference of related application
Quote full text that the Japanese patent application JP 2006-114814 that submitted on April 18th, 2006 and the JP 2007-57388 that submitted on March 7th, 2007 comprise claims, instructions and accompanying drawing as a reference at this.
Technical field
The present invention relates to SIC (semiconductor integrated circuit), relate in particular to the technology that prevents to change the fault that causes owing to the SIC (semiconductor integrated circuit) electrology characteristic.
Background technology
When SIC (semiconductor integrated circuit) designs, in order to guarantee not take place because the fault that noise causes, by carrying out the alleged signal integrity of Simulation execution (SI:Signal Integrity) checking (opening flat 9-305649 communique) with reference to the spy of Japan.In addition, noise margin improvement method based on substrate voltage control has been proposed.At this moment, in order to realize not relying on temperature conditions and process conditions, threshold voltage that is fixed or saturation current use reference circuit to carry out FEEDBACK CONTROL, determine substrate voltage (opening the 2001-156261 communique with reference to the spy of Japan).
In addition, also proposed to use trigger to detect the adjustment error that takes place in specific passageways, and when detecting the adjustment error, improve supply voltage and carry out the method for FEEDBACK CONTROL (with reference to Das, S. wait work " A Self-Tuning DVS Processor Using Delay-Error Detection and Correction (adopting the self-adjusting DVS processor of delay-error-detecting and calibration) ", 2005 Symposium on VLSI CircuitsDigest of Technical Papers, (U.S.), IEEE, on June 16th, 2005, pp.258-261 ").
When carrying out such FEEDBACK CONTROL, its prerequisite is to determine reference value and feedback function uniquely.For example, for control basal plate voltage, utilizing semi-conductive band gap is this fact of physical constant, uses the band gap reference circuit to generate reference voltage.In addition, about feedback function, be the relation that realizes substrate voltage and threshold voltage by mimic channel, or the relation of substrate voltage and saturation current, and by critical path and the relation that detects adjustment error trigger realization supply voltage and adjustment error.
But in the situation that guarantees not produce fault by simulation, must guarantee " not causing fault " in mode such as " 100% is no problem " or " specifying the long time cycle not have statistical problem ", so added superfluous tolerance limit, so just constituted the reason that circuit performance reduces.
In addition, except transistor characteristic, also because the problem that relates to signal integrity that the trait-treatment interaction of the relativeness of capacity, driving force etc. takes place between connecting up.For this reason, there are the generation difficulty of reference value etc. of relativeness of reference value, driving force of capacity or the decision that feedback function can not be unique, are difficult to adapt to the problem of control along with behaviour in service.And then, consider that signal integrity carries out timing, not only characteristics of transistor also needs the unbalanced object as correction with capacity between wiring., though the characteristic by can correcting transistor to the control of substrate voltage can not be proofreaied and correct the unbalanced of capacity between wiring to simple substrate voltage control.
Yet along with the miniaturization of circuit, the state of prediction circuit is more and more difficult, makes the influence of above problem become big.
Summary of the invention
The objective of the invention is to get rid of superfluous tolerance limit to improve the performance of SIC (semiconductor integrated circuit).
In order to address the above problem, the semiconductor IC system that structure the present invention relates to is to judge when controlling object is undesired in circuit the time of executive routine operation, to cause the reason of fault and control above-mentioned controlling object circuit according to judged result.
By such operation,, when circuit design, just there is no need to consider superfluous tolerance limit owing to can keep normal program work frequently.For this reason, can improve the key property of SIC (semiconductor integrated circuit).
More particularly, the semiconductor IC system that the present invention relates to has: the controlling object circuit of executive routine; The system information monitoring unit of the system information of the above-mentioned controlling object circuit state of output expression; Determine the circuit characteristic of above-mentioned controlling object circuit and export the circuit characteristic monitoring unit of this circuit characteristic as the output of circuit characteristic information; Judge the whether fault judgement portion of operate as normal of above-mentioned controlling object circuit according to said system information; During above-mentioned controlling object circuit operate as normal, the reference circuit characteristic maintaining part that the foregoing circuit characteristic information is kept as the reference circuit characteristic information; When above-mentioned controlling object circuit cisco unity malfunction, according to the failure cause judging part of detected circuit characteristic information of foregoing circuit characteristic monitoring unit and said reference circuit characteristic information failure judgement reason; Judge according to above-mentioned failure cause and calibration object in the above-mentioned controlling object circuit to generate and to export the above-mentioned calibration object judging part that is used for the target electronic characteristic information of calibration object; Control the characteristic electron control part of above-mentioned controlling object circuit according to above-mentioned target electronic characteristic information.
Therefore can carry out suitable control to the controlling object circuit, the work of program can be remained on normal state.For the reference value that is difficult to obtain circuit characteristic in advance, also can easily obtain the circuit characteristic that constitutes benchmark.For this reason, failure judgement reason flexibly.In addition, because using system information, so can realize feedback according to behaviour in service.
In addition, the semiconductor IC system of other that the present invention relates to comprises: the controlling object circuit with register; Supply with the characteristic electron control part of clock signal to above-mentioned controlling object circuit, wherein above-mentioned register is the adjustment error that is used for detecting in above-mentioned controlling object circuit, when register detected the adjustment error, above-mentioned characteristic electron control part can prolong the cycle of above-mentioned clock signal.
Therefore, when detecting the adjustment error, because the prolongation of the signal of clock, so can the high clock signal of frequency of utilization.Therefore, can be with the work high speed of controlling object circuit.
SIC (semiconductor integrated circuit) of the present invention has: a plurality of logical circuits; Connect above-mentioned a plurality of logical circuits metal line, near compensation (dummy) metal of above-mentioned metal line configuration, on the above-mentioned compensation metal or under the strong induced electricity body of configuration.
The operating system that the present invention relates to is the operating system of working on SIC (semiconductor integrated circuit), this operating system has: the software layer of linker and aforesaid operations system, wherein above-mentioned software layer are the functions that the practice condition of said procedure can be defined as independent variable.
The control method of the SIC (semiconductor integrated circuit) that the present invention relates to, it is the control method of the SIC (semiconductor integrated circuit) of the controlling object circuit in the control SIC (semiconductor integrated circuit), this control method comprises: according to the information of status system of the above-mentioned controlling object circuit of expression executive routine, judge the whether fault judgement step of operate as normal of above-mentioned controlling object circuit; During above-mentioned controlling object circuit operate as normal, the maintenance reference circuit characteristic step that the circuit characteristic information of above-mentioned controlling object circuit is kept as the reference circuit characteristic information; When above-mentioned controlling object circuit cisco unity malfunction, according to the failure cause determining step of the circuit characteristic information and the said reference circuit characteristic information failure judgement reason of above-mentioned controlling object circuit; Judge the calibration object determining step of the calibration object in the above-mentioned controlling object circuit according to above-mentioned failure cause; Generate the aligning step of the target electronic characteristic information in the above-mentioned calibration object.
Other control methods that the present invention relates to are control methods of the SIC (semiconductor integrated circuit) of the controlling object circuit in the control SIC (semiconductor integrated circuit), and this method comprises: the detection step that detects the adjustment error in the above-mentioned controlling object circuit; In above-mentioned detection step, detect when adjusting error, will supply to the controlled step of the clock signal period prolongation of above-mentioned controlling object circuit.
According to the present invention,, can get rid of superfluous tolerance limit, so can improve the performance of SIC (semiconductor integrated circuit) owing to can carry out suitable correction control.
Description of drawings
Fig. 1 is the block scheme that the semiconductor IC system of expression embodiments of the present invention constitutes;
Fig. 2 is the process flow diagram of technology in the semiconductor IC system of presentation graphs 1;
The key diagram of system information embodiment when the key diagram of system information embodiment when Fig. 3 A is the semiconductor circuit operate as normal of presentation graphs 1, Fig. 3 B are the semiconductor circuit non-normal workings of presentation graphs 1;
The key diagram of other embodiment of system information when the key diagram of other embodiment of system information when Fig. 4 A is the semiconductor circuit operate as normal of presentation graphs 1, Fig. 4 B are the semiconductor circuit non-normal workings of presentation graphs 1;
Fig. 5 is the block diagram that the SIC (semiconductor integrated circuit) of presentation graphs 1 constitutes embodiment;
Fig. 6 is the circuit diagram of embodiment of formation of the register of the error-detecting function of expression with Fig. 5;
Fig. 7 is the sequential chart of embodiment of the register work of presentation graphs 6;
Fig. 8 is the circuit diagram that expression has the embodiment that the characteristic electron monitoring unit of Fig. 1 constitutes;
The key diagram of the detection level of glitch (noise) when Fig. 9 A is expression detection positive pulse, the key diagram of the detection level of glitch (noise) when Fig. 9 B is expression detection negative pulse;
Figure 10 is the circuit diagram of first variation of formation of the circuit characteristic monitoring unit of presentation graphs 1;
Figure 11 A key diagram that to be expression detected object signal TS detect when " L " moves to " H " switching time, Figure 11 B key diagram that to be expression detected object signal TS detect when " H " moves to " L " switching time;
Figure 12 is the circuit diagram of second variation that constitutes of the circuit characteristic monitoring unit of presentation graphs 1;
Figure 13 is the circuit diagram of the 3rd variation of formation of the circuit characteristic monitoring unit of presentation graphs 1;
Figure 14 is a sequential chart of adjusting error about detecting;
The key diagram of the range of control example of the supply voltage that Figure 15 tries to achieve when being the each execution of expression BIST;
Figure 16 A is the wiring Butut of the part semiconductor circuit of presentation graphs 1, and Figure 16 B is the circuit diagram of the wiring capacity of presentation graphs 16A;
Figure 17 is the key diagram of expression path activity ratio;
Figure 18 is the block diagram that the circuit embodiments of common register is used in expression;
Figure 19 is the signal timing diagram of Figure 18 circuit;
Figure 20 is the block diagram of the embodiment of circuit of the expression register that uses Fig. 6;
Figure 21 is the signal timing diagram of the circuit of expression Figure 20;
Figure 22 is the block diagram of variation of the circuit of expression Figure 20;
Figure 23 is the signal timing diagram of the circuit of expression Figure 22;
Figure 24 is the key diagram of application interface.
Main symbol description:
10,20 SIC (semiconductor integrated circuit)
12,612,712 semiconductor circuits
14,214,314,414 circuit characteristic monitoring units
16 characteristic electron control parts
21 reference circuit characteristic maintaining parts
22 system information monitoring units
23 fault judgement portions
24 failure cause judging parts
25 calibration object judging parts
26 calibration history maintaining parts
36A, 36B, 36C register
131,132 main latch
134 error-detector circuits
135 clock delay circuits
812 application interfaces
820 operating systems
Embodiment
Following with reference to the description of drawings embodiments of the present invention.
Fig. 1 is the block scheme that the semiconductor IC system in the expression embodiment of the present invention constitutes.The system of Fig. 1 comprises SIC (semiconductor integrated circuit) (LSI) 10 and 20.LSI 10 has the Characteristics Control portion 16 of semiconductor circuit 12 as the controlling object circuit, circuit characteristic monitoring unit 14, electronics.LSI 20 has reference circuit characteristic maintaining part 21, system information monitoring unit 22, fault judgement portion 23, failure cause judging part 24, calibration object judging part 25, calibration history maintaining part 26.
Fig. 2 is a process flow diagram of locating technology in the semiconductor IC system of presentation graphs 1.The process flow diagram of Fig. 2 comprises: failure cause determining step S12, reference circuit characteristic keep step S14, failure cause determining step S22, calibration object determining step S24 and aligning step S26.
In fault judgement step S12, fault judgement portion 23, according to the system information that obtains from system monitoring portion 22, the judgement system is normally or unusual.When semiconductor circuit 12 operate as normal (system is normal), enter into the reference circuit characteristic and keep step S14, during semiconductor circuit 12 non-normal workings (system exception), enter failure cause determining step S22.
Keep among the step S14 in the reference circuit characteristic, reference circuit maintaining part 21 will keep as the reference circuit characteristic information from the circuit characteristic information that circuit characteristic monitoring unit 14 receives, and turns back to step S12.In this step, obtain the circuit characteristic reference value in advance for being difficult to, for example the circuit characteristic of the relativeness of capacity, driving force etc. also can easily be obtained the circuit characteristic that constitutes benchmark.
In the failure cause determining step 22, failure cause judging part 24 will compare from circuit characteristic monitoring unit 14 circuit characteristic information that obtains and the reference circuit characteristic information that remains on the reference circuit characteristic maintaining part 21.Both judge its reason (failure cause) not simultaneously.Failure cause judging part 24 for example carries out the judgement of following (A1)～(A4).Signal A, B are the internal signals of semiconductor circuit 12.
(A1) when the glitch aspect ratio reference circuit characteristic height of signal A and signal A switching time, (slew time) was bigger than reference circuit characteristic the time, 24 of failure cause judging parts judge that it is the reason of fault that the transistorized driving force of output signal A reduces.At this, be the needed time of migration of signal A voltage level switching time.
(A2) when switching time of the glitch aspect ratio reference circuit characteristic height of signal A and signal A than reference circuit characteristic hour, 24 transistorized driving force increases of judging defeated signal A of failure cause judging part are fault reasons.
(A3) when the switching time of the glitch aspect ratio reference circuit characteristic height of signal A or signal B and signal A and signal B, magnitude relationship was opposite with the magnitude relationship of reference circuit characteristic, 24 of failure cause judging parts judge that the transistorized driving force counter-rotating of output signal A and signal B is the fault reason respectively.
(A4) when the switching time of the glitch aspect ratio reference circuit characteristic height of signal A or signal B and signal A and signal B, magnitude relationship was with reference circuit characteristic big or small identical, it is the fault reason that 24 judgements of failure cause judging part transmit respectively between the wiring of signal A and signal B that electric capacity (coupling capacitance) increases.
In calibration object determining step S24, calibration object judging part 25 obtains system information from system information monitoring unit 22 respectively, obtain calibration history information from calibration history maintaining part 26, according to the failure cause that failure cause judging part 24 is obtained, judge the calibration object in the semiconductor circuit 12 that effectively prevents the fault generation.In calibration history maintaining part 26, store for previous executory calibration history signal.The calibration history maintaining part also stores the information of new correction.When using calibration history information, calibration object judging part 25 is retrieved in order to obtain calibration object, for example, as following (B1), (B2) judges calibration object like that.
(B1) if the ability of drive signal A reduces, and, when the correction that makes the ability of drive signal A increase is recorded in the calibration history, can judge because the aging reason that waits of the driving transistors of output signal A can not obtain sufficient calibration result.Therefore, in order to make the magnitude relationship of switching time between signal A and signal B near the reference circuit characteristic, the correction that calibration object judging part 25 will make drive signal B ability reduce is judged as calibration object.
(B2) ability of minimizing drive signal A, and the correction of transistorized driving force that increases the driving transistors position of approach signal A is when being recorded in the calibration history, can infer that in chip to produce characteristic unbalanced, and near the transistor characteristic of the driving transistors of output signal A is aging etc.Therefore, calibration object judging part 25 correction that the driving force of the driving transistors of output signal A will be increased is judged as calibration object.
In the aligning step 26, calibration object judging part 25 has generated the target electronic characteristic information CI that is judged as in the calibration object and has exported this target electronic characteristic information CI to characteristic electron control part 16.Characteristic electron control part 16 generates electronic characteristic control signal CC according to target electronic characteristic information CI, and exports this electronic characteristic control signal CC to semiconductor circuit 12, with the circuit characteristic of control semiconductor circuit 12.After this, turn back to step S12.
Below, specifically describe the specific embodiment of each several part of the semiconductor IC system of Fig. 1.
System has been shown in following program (C1)～(C5) among the fault judgement step S12 of the embodiment of system information and Fig. 2 whether has judged embodiment normally.
(C1) be that act work with system in the work sequence is viewpoint.System information monitoring unit 22 is exported the state of semiconductor circuit 12 as system information.The time (checkpoint) of this state is checked in decision in advance, and in this checkpoint, when the state of semiconductor circuit 12 was the state of being expected, semiconductor circuit 12 operate as normal were judged by fault judgement portion 23.Under other the situation, fault judgement portion 23 judges that semiconductor circuit 12 is a non-normal working.Because this method is by realizing with reference to counter and register, so can realize minimal resource investment.
(C2) with because operation result is improper, the work of the mistake system of resuming work of processing etc. is as viewpoint between overflowing continually, mending.Semiconductor circuit 12 carries out image/acoustic processing program for example, the information that system information monitoring unit 22 is called the error recovery routine in this program with expression is exported as system information.The prior benchmark of decision call number calls pre-determined number when above, and fault judgement portion 23 judgement semiconductor circuits 12 do not have operate as normal.Under other the situation, fault judgement portion 23 judges that semiconductor circuit 12 is an operate as normal.Because this method only is to use the part of information in the algorithm known, so can realize with the system variation of irreducible minimum.
(C3) with because the improper operation irregularity that causes memory access of address computation, and to detect systematic error and follow the act work of the system of the fault of restarting be viewpoint.System information monitoring unit 22 is that the information that expression OS normally closes is exported with system information.When OS did not last time normally close, fault judgement portion 23 judged that semiconductor circuit 12 does not have operate as normal when OS starts.When other situations, fault judgement portion 23 judges that semiconductor circuit 12 is an operate as normal.This method is owing to only being to use the work of already present OS, so can realize minimal system variation.
(C4) with because address computation is improper causes the memory access operation irregularity, and to detect application error and follow the act work of the system that uses the fault that ends be viewpoint.Semiconductor circuit 12 is being implemented for example application program, and system information monitoring unit 22 will represent that the information that error takes place during the executive utility exports with system information.When application error took place, fault judgement portion 23 judged that semiconductor circuit 12 does not have operate as normal.During other situation, fault judgement portion 23 judges that semiconductor circuits 12 are operate as normal.This method is owing to only being to use the work of already present OS, so can realize minimal system variation.
(C5) semiconductor circuit 12 comprises having the register of adjusting the error-detecting function.Detect when adjusting error, system exception is judged by fault judgement portion 23.This method is not appended necessity of circuit, is conceived to the judgement of critical path but that works as described later, so produce when relying on the fault that postpones correcting circuit characteristic effectively.
The key diagram of the system information example when Fig. 3 A is semiconductor circuit 12 operate as normal of presentation graphs 1.The key diagram of the system information example when Fig. 3 B is semiconductor circuit 12 non-normal workings of presentation graphs 1.Fig. 3 A and Fig. 3 B represent example (C1) particularly.
The situation of Fig. 3 can suppose that semiconductor circuit 12 comprises status register, the #0 that sequentially executes the task, and #1, #2 ... ...Status register is the register in conjunction with the variate of task executions or threading.System information monitoring unit 22 obtains the value of status register and exports as system information.
When the such operate as normal of Fig. 3 A, the numerical value of status register is to carry out or threading changes gradually in conjunction with task, so in the checkpoint of Fig. 3 A, the value of register becomes predetermined value C.
When Fig. 3 B, the fault of circuit takes place, stop the execution of task #1.At this moment, status register former state B value does not change, so do not become predetermined value C in this checkpoint.For this reason, system exception can be judged by fault judgement portion 23.
When Fig. 4 A is semiconductor circuit 12 operate as normal of presentation graphs 1, the key diagram of another embodiment of system information.When Fig. 4 B is semiconductor circuit 12 non-normal workings of presentation graphs 1, the key diagram of an embodiment again of system information.Fig. 4 A and Fig. 4 B represent example (C2) particularly.
The situation of Fig. 4 supposes that semiconductor circuit 12 is the circuit that carry out Flame Image Process.System information monitoring unit 22 obtains expression from semiconductor circuit 12 as system information and calls the routine call information of the error recovery routine that recovers Error processing, and exports this routine call information.
In the Flame Image Process supervisor, because data disappearance etc. are implemented the error recovery routine in order to carry out the adjustment of data (maximal value restriction, interpolation).During operate as normal, because the data disappearance is few, so the call number of the error recovery routine that image pattern 4A is such is few.
In Fig. 4 B, take place because the arithmetic eror of fault makes view data unusual.At this, in order to resume work, calling of error recovery routine taken place continually.Therefore, fault judgement portion 23 can the judgement system be unusual.
Fig. 5 is the block diagram of configuration example of the semiconductor circuit 12 of presentation graphs 1.The semiconductor circuit 12 of Fig. 5 comprises: register 32A, 32B, 32C, 36A, 36B and 36C and combinational logic 34.Combinational logic 34 has path 35A, 35B and 35C.Register 36A～36C has the function of adjusting error-detecting.
Fig. 6 is the circuit diagram of configuration example of the register 36A of the adjustment error function of expression with Fig. 5.Register 36A is the master-slave mode trigger, comprises main latch 131 and 132, from latch 133, error-detector circuit 134 and clock delay circuit 135. Register 36B and 36C have the formation of register 36A too.
Latch lock after main latch 131 makes register input D and clock signal clk and NCLK synchronously.Latch lock after main latch 132 makes register input D and delay clock signals CLKD and NCLKD synchronously.Latch value on the main latch 132 is to determine after the latch value of main latch 131 is determined. Main latch 131 and 132 has node NR0 and NR1 respectively.
When error signal NERR was " H ", the value of main latch 131 counter-rotating node NR0 and the value that will reverse outputed to from latch 133.When error signal ERR was " H ", the value of main latch 132 counter-rotating node NR1 and the value that will reverse outputed to from latch 133.The value and the clock signal NCLK that will import from latch 133 latch synchronously.
Fig. 7 is the sequential chart of work example of the register 36A of presentation graphs 6.Postpone DL and represent the delay of delay clock signals CLKD corresponding to clock signal clk.Value AAA, BBB, CCC sequentially supply to register 36A with register input D.
When input value AAA,, determine that register input D is value AAA by the rising edge (rising edge) of clock signal clk.For this reason, node NR0, the value of NR1 is the value of being defined as AAA all, makes can not adjust error.Its result, error signal NERR become " H ", the output of main latch 131 are input to from latch 133, as register output Q output valve AAA.
On the other hand, when input value BBB, by the rising edge of clock signal clk, register input D can not determine and is value BBB.Therefore, the value of node NR0 becomes exceptional value ZZZ, and error just takes place to adjust.After this, by the rising edge of delay clock signals CLKD, the register input D value of being defined as BBB makes the value of node NR1 become value BBB.
Because the value of node NR0 is different with the value of NR1, so error signal ERR becomes " H ", makes the output of main latch 132 be imported into from latch 133, and with register output Q output valve BBB.Just, even taking place to adjust, error also can export normal value.
Like this, not only can adjust the detection of error according to the register 36A of Fig. 6, and when taking place to adjust error, also can be corrected into correct output valve.In addition, the size of the delay that produces according to delay element 138 can the detection period of predictive error between, so can carry out the predetermined of error-detecting along with the situation of critical path.
Describe for generation with the circuit characteristic information of circuit characteristic monitoring unit 14.Circuit characteristic monitoring unit 14 is that one of them obtains circuit characteristic information with following (D1)～(D6).
(D1) when failure cause is noise, circuit characteristic monitoring unit 14 is measured the glitch height (size of noise) of certain line, and its result is as circuit characteristic information.In the method, because it is just enough just to measure voltage level, so can simplify circuit characteristic monitoring unit 14.
(D2) when failure cause is noise, circuit characteristic monitoring unit 14 is measured the switching time of certain line (Aggressor line or Victim line), and its result is as circuit characteristic information.Because noise is to rely on the relativeness of signal to take place, so this method can be proofreaied and correct according to situation about taking place.
(D3) when failure cause be when postponing, the delay that circuit characteristic monitoring unit 14 is measured on the specific passageways, with its result as circuit characteristic information.Owing to postpone to depend on the work pattern, this method can be proofreaied and correct according to the situation that postpones to take place.
(D4) when failure cause is maintenance patience deficiency, circuit characteristic monitoring unit 14 is measured the logic level from the output transmission of register and trigger, and its result is as circuit characteristic information.Before becoming standby mode, keep the value of logic level, by with standby mode after value compare failure judgement reason easily.
(D5) circuit characteristic monitoring unit 14 is measured the supply voltage or the temperature of semiconductor circuits 12 grades, with its result as circuit characteristic information.This method can be judged separately the reason beyond the process conditions.
(D6) when failure cause be when postponing, circuit characteristic monitoring unit 14 will be from the error-detecting result of one of them output of register 36A～36C of adjustment error-detecting function with Fig. 5 as circuit characteristic information.Which according to this information,, can constitute owing to postpone to cause the specific passageways of adjusting error owing to can judge from register output error signal.
Fig. 8 is the circuit diagram of configuration example of the circuit characteristic monitoring unit 14 of presentation graphs 1.The circuit of Fig. 8 is the work of carrying out program (D1) for semiconductor circuit 12 particularly.The circuit characteristic monitoring unit 14 of Fig. 8 comprises: NMOS (n NMOS N-channel MOS N) transistor 51 and 54, PMOS (p NMOS N-channel MOS N) transistor 52 and 53, NOR door 55, NAND door 56, holding circuit 61 and 62, RS latch (trigger) 63 and 64; OR door 65.A part of in Fig. 8, just having represented semiconductor circuit 12.
When reset signal RS became " H ", because PMOS transistor 53 and nmos pass transistor 54 conductings, N2 was positioned at electronegative potential (" L ") so dynamic node N1 becomes " H ", and latch 63 and 64 resets.Holding circuit 61 and 62 keeps the logic level of dynamic node N1 and N2 respectively.
Fig. 9 A is the key diagram of the detection level of glitch (noise) when detecting positive pulse.Fig. 9 B is the key diagram of the detection level of glitch (noise) when detecting negative pulse.The threshold voltage of nmos pass transistor 51 is expressed as Vtn, the threshold voltage of PMOS transistor 52 is expressed as Vtp.
Reference signal SS is " L " and detected object signal TS is than detecting level VREFL+Vtn when big shown in Fig. 9 A, and nmos pass transistor 51 conductings make the current potential of dynamic node N1 descend.So the output of NOR door 55 becomes " H ", so predetermined latch device 63 and OR door 65 will become " H " as the detection signal DS of circuit characteristic information.
Reference signal SS is " H " and detected object signal TS is than detecting level VREFH-Vtp hour shown in Fig. 9 B, and 52 conductings of PMOS transistor make the current potential of dynamic node N2 rise.So the output of NAND door 56 becomes " L ", so latch 64 is scheduled, OR door 65 becomes detection signal DS into " H ".
Like this, circuit preset reference voltage VREF L and VREF H according to Fig. 8 just can measure the glitch height.
Figure 10 is the circuit diagram of first variation of formation of the circuit characteristic monitoring unit 14 of presentation graphs 1.The circuit of Figure 10 is the work of semiconductor circuit 12 being carried out particularly program (D2).The circuit characteristic monitoring unit 214 of Figure 10 also comprises variable delay impact damper 265 and 266 except the element of the circuit characteristic monitoring unit 214 among Fig. 8.In Figure 10, just represent the part of semiconductor circuit 12.
The switching time of the signal of the wiring 42 of circuit characteristic monitoring unit 214 mensuration semiconductor circuits 12.Wiring 42 signal gives the door of nmos pass transistor 51 and PMOS transistor 52 as detected object signal TS.In addition, detected object signal TS gives NOR door 55 and NAND door 56 via variable delay impact damper 265 and 266 respectively as reference signal SS1 and SS2.Variable delay impact damper 265 and 266 is by delayed control signal DLC1 and DLC2 difference control lag.
When reference signal SS1 was " L ", the work of nmos pass transistor 51 was sent to the output of NOR door.When reference signal SS1 was " H ", the work of PMOS transistor 52 was sent to the output of NAND56 door.Therefore, when reference signal SS1 is " L ", can detects the detected object signal and move to the level of " H ", when reference signal SS2 is " H ", can detects the detected object signal and move to the level of " L " from " H " from " L ".The circuit characteristic monitoring unit 214 circuit characteristic monitoring unit 14 with Fig. 8 in other respects is identical.
Figure 11 A is the key diagram that detected object signal TS was detected from " L " switching time when " H " moves.Figure 11 B is the key diagram that detected object signal TS was detected from " H " switching time when " L " moves.
During the situation of Figure 11 A, can detect the migration of the level of detected object signal TS when having only reference signal SS1 to be " L ".At this, by delay controlling object circuit DLC1 the delay of variable delay impact damper 265 is reduced to little value from big value, carry out the detection of electrical level transfer simultaneously.Postpone when big, though can detect the migration of level, but postpone when arriving detection threshold, can not to detect the migration of level again, thus can from switching time of the electrical level transfer required time of obtaining detected object signal TS time delay of this moment as circuit characteristic information.
During the situation of Figure 11 B, can detect the migration of the level of detected object signal TS when having only reference signal SS2 to be " H ".At this, by delayed control signal DLC2 the delay of variable delay impact damper 266 is reduced to little value from big value, carry out the detection of electrical level transfer simultaneously.Postpone when big,, postpone when arriving detection threshold though can detect the migration of level, owing to can not detect the migration of level again, so can be from the switching time of obtaining detected object signal TS time delay of this moment.
Therefore, circuit preset reference voltage VREF_L and the VREF_F according to Figure 10 just can measure switching time.
Figure 12 is the 2nd variation of formation of the circuit characteristic monitoring unit 14 of presentation graphs 1.The circuit of Figure 12 is the work of semiconductor circuit 12 being carried out particularly program (D3).The circuit characteristic monitoring unit 314 of Figure 12 has trigger (latch) 364 and variable delay impact damper 366.In Figure 12, just represented the part of semiconductor circuit 12.
The signal of wiring 342 gives variable delay impact damper 366 as reference signal SS.The output signal of variable delay impact damper 366 gives trigger 364 with clock signal.The signal TS of wiring 344 delivers to the D input of trigger 364.Trigger 364 output detecting signal DS are as circuit characteristic information.Variable delay impact damper 366 is by delayed control signal DLC control lag.
When the delay of the retardation ratio determination object circuit 346 of variable delay impact damper 366 was much bigger, signal TS correctly was added on the trigger 364.After little by little changing delayed control signal DLC, (catch constantly unstable) constantly,, can obtain the length of delay of determination object circuit by the length of delay of variable delay impact damper 366 in the value variation of detection signal DS.
Figure 13 is the 3rd variation of formation of the circuit characteristic monitoring unit 14 of presentation graphs 1.The circuit of Figure 13 is the work of semiconductor circuit 12 being carried out particularly program (D4).The circuit characteristic monitoring unit 414 of Figure 13 comprises the trigger (latch) 464 and the XOR gate 468 of circuit as a comparison.In Figure 13, just represented the part of semiconductor circuit 12.
On the inlet D of trigger 464 and XOR gate 468, give the signal of the logic cone terminal 444 of trigger 446A～446C.In addition, lock-on signal CPT is awarded in the trigger 464 as clock signal.Trigger 464 outputs to XOR gate 468 with the signal of catching.
The power supply of power circuit that will be different with each trigger 446A～446C supplies on the trigger 464, semiconductor circuit 12 is before becoming standby mode, and trigger 464 will detect the signal of logic cone terminal 444 and catch as object signal TS according to lock-on signal CPT.
After this, semiconductor circuit 12 is moved to standby mode, makes the supply voltage that supplies to semiconductor circuit 12 descend.After this, semiconductor circuit 12 and then return to common pattern.At this moment, when the value of the trigger 446A～446C of determination object was unusual, the value of detected object signal TS was varied to and is different from the value that becomes before the standby mode, so XOR gate 468 outputs 1 are as detection signal (circuit characteristic information) DS.
For trigger 464, supply with the power supply with trigger 446A～446C same power supplies circuit, and, also can improve the maintenance patience of trigger 464.In addition, replace XOR gate 468, also can use the whether consistent comparer of two signals of expression input.
As mentioned above, owing to use the circuit signal of real work according to Fig. 8, Figure 10, Figure 12 and Figure 13, so can measure the characteristic of side circuit.
Calibration object judging part 25, the correction that using system information adapts to according to behaviour in service.In the calibration object determining step S24 of Fig. 2, calibration object judging part 25 can be inferred the operating position of semiconductor circuit 12 from system information, and decision correction feedback strategy is for example according to following (E1)～(E5) determine.
(E1) the system information monitoring unit 22, and the data of residual amount that expression constituted the battery of semiconductor circuit 12 power supplys are exported as system information.Calibration object judging part 25 in the residual amount of battery after a little while, as the strategy of correction feedback, the electric current that will not increase consumption is not to cause that fault is as the correction work condition.Concrete is to improve the supply voltage of semiconductor supply circuit 12 and the correction that reduces the frequency of operation of semiconductor circuit 12, generates the characteristic information CI of target electronic.Use this strategy, can avoid the shortening of working time, though reply degeneration, at first can be so that semiconductor circuit 12 work.
When (E2) environment of soft-error taking place easily in the grade in aircraft,, carry out temporary transient correction as the strategy of correction feedback.For example, by the dialogue etc. man-machine interactive affirmation or by with reference to the expression auxiliary mode information hold environment.Specifically, whether calibration object judging part 25 temporarily improves the voltage of semiconductor supply circuit 12, after this reduces supply voltage termly, thereby check when reducing supply voltage and break down.If when not breaking down,, generate the characteristic information CI of target electronic in order to stop improving the correction of supply voltage.By this strategy, can realize proofreading and correct according to environment, can not constitute super predetermined correction.
(E3) system information monitoring unit 22 is with the information of system information output about the temperature of semiconductor circuit 12.Semiconductor 12 is in hot environment following time, calibration object judging part 25, and as the tactful correction work condition of correction feedback, making does not increase leakage current, does not cause fault.Concrete is, calibration object judging part 25 improves the supply voltage of semiconductor supply circuit 12, and the substrate bias of semiconductor circuit 12 is made bigger back-biased correction, perhaps the revisal that the frequency of operation of semiconductor circuit 12 is reduced is such, generates target electronic characteristic information CI.Under hot environment, can know from the output of temperature sensor.By such strategy, can avoid the problem that leakage current increases under hot environment, simultaneously, at first can be though reply variation so that semiconductor circuit 12 work.
(E4) system information monitoring unit 22 is read the identiflication number of semiconductor circuit 12 (or LSI10), exports with system information.Identiflication number is the sequence number that writes semiconductor circuit 12 when making, processor ID, lot number etc., is corresponding the manufacturing period of semiconductor circuit 12.Calibration object judging part 25 is inferred manufacturing period (make year etc.) of semiconductor circuit 12 from system information, it is regarded as bring into use period.During the scheduled period,, make performance aging from manufacturing process in period, be difficult to cause fault as the tactful correction work condition of correction feedback.Concrete is that calibration object judging part 25 in order to improve the supply voltage of semiconductor supply circuit 12, generates target electronic characteristic information CI.According to this strategy,, can keep the performance of semiconductor circuit 12 though shortened the life-span of battery.
(E5) system information monitoring unit 22 is with the information of system information output about the supply voltage control of semiconductor circuit 12.Detect at once when adjusting error after the Control work of reduction supply voltage, owing to before it, may adjust error by over sight (OS), so calibration object judging part 25 can again change supply voltage.
Figure 14 is a sequential chart of adjusting error about detecting.With reference to Fig. 5 and Figure 14 illustrative examples (E5).For example, the register 36A～36C by Fig. 5 detects the adjustment error.Difference input signal PTA, PTB and PTC on register 36A～36C.Signal PTA, PTB and PTC are respectively the output of path 35A, 35B and 35C.
The error-detecting scope of each register 36A～36C is the retardation that depends on the delay element 138 of Fig. 6.For this reason, as shown in figure 14, the adjustment error can be detected, but the adjustment error of signal PTC can not be detected for signal PTB.
When reducing supply voltage, increased the delay of combinational logic 34, can not detect the adjustment error sometimes.At this, when detecting the adjustment error, calibration object judging part 25 generates the target electronic characteristic information CI that is used to improve supply voltage.Can prevent fault in advance thus.
In addition, example (E5) be by with the combination of built-in self-test (BIST:built-in selftest), can further improve and prevent the fault effect.Figure 15 is the key diagram of the supply voltage range of control example obtained when at every turn carrying out of expression BIST.For example, as shown in figure 15, semiconductor circuit 12 is implemented BIST termly.When implementing BIST, semiconductor circuit 12 activation path 35A～35C, Yi Bian change supply voltage, Yi Bian make register 36A～36C detect the adjustment error.
Calibration object judging part 25, during according to each execution BIST, the result of BIST obtains for path 35A～35C (signal PTA, PTB and PTC) and can not detect the power supply lower limit of adjusting error (Figure 15 *).In addition, 25 pairs of calibration object judging parts are each when carrying out BIST, and any one that obtain path 35A～35C all can not detect the scope of adjusting the such supply voltage of error, generates the target electronic characteristic CI of this scope of expression.Electronic Control portion 16 is detected after reducing supply voltage when adjusting error, improves supply voltage and makes the interior value of its scope that reaches the supply voltage of obtaining.Thus, can prevent to adjust error can not be detected.
For describing by the calibration object in the semiconductor circuit 12 of characteristic electron control part 16.Characteristic electron control part 16 according to target electronic characteristic CI, as following example (F1)～(F9), carries out the revisal of semiconductor circuit 12.
When (F1) reason of fault is noise, characteristic electron control part 16, in order to proofread and correct the driving force of node, as calibration object, change drives a plurality of driving transistors numbers that this node is connected in parallel.In the method, do not carry out substrate voltage control, constituting by the change circuit just can be corresponding.
When (F2) reason of fault is noise, characteristic electron control part 16, in order to proofread and correct the driving force of node, as calibration object, control basal plate voltage.In the method, can change the transistor self character.
When (F3) reason of fault is noise, characteristic electron control part 16, for the threshold voltage of correcting transistor, as calibration object, control basal plate voltage.In the method, can change the transistor self character.
When (F4) reason of fault is noise, characteristic electron control part 16, in order to proofread and correct the capacity between wiring, as calibration object, control is added in the bias voltage on the strong inductor.In the method, can change the characteristic of wiring capacity.
When (F5) reason of fault is delay, characteristic electron control part 16, for the driving force of correcting logic door, as calibration object, control basal plate voltage.In the method, can change the transistor self character.
When (F6) reason of fault is delay, characteristic electron control part 16, for the correction work condition, as calibration object, control basal plate voltage.In the method, do not carry out substrate voltage control, not changing the circuit formation just can calibrating semiconductor circuit 12.
(F7) reason of fault is when keeping patience not enough, characteristic electron control part 16, and for the correction work condition, as calibration object, the control supply voltage.In the method, not carrying out simultaneously that substrate voltage control and circuit change just can calibrating semiconductor circuit 12.
(F8) reason of fault is when keeping patience not enough, characteristic electron control part 16, and in order to proofread and correct the threshold voltage of trigger (latch), as calibration object, the control supply voltage.In the method, can change the transistor self character.
When (F9) reason of fault is delay, for the position cycle, as calibration object, control clock signal.For example the modulating clock frequency temporarily prolongs the clock period.Can prevent to adjust error like this.
Above-described example (F1)～(F4) respectively corresponding example (A1)～(A4).
For as calibration object, control the situation (example (F4)) that is added in the bias voltage on the strong inductor and describe.Figure 16 A is the arrangenent diagram of wiring of a part of the semiconductor circuit 12 of Fig. 1.Figure 16 B is the circuit diagram of the wiring capacity of presentation graphs 16A.Shown in Figure 16 A, semiconductor circuit 12 have the wiring 541,542 and 543 and the compensation (dummy) metal 544.
The noise effect that wiring 541 is accepted from other wirings perhaps gives noise effect to other wirings, and it is connected up as calibration object.Shown in Figure 16 A, 541 disposing compensation metal 544 near wiring, in semiconductor circuit 12, compensation metal 544 top or below have strong inductor 545.Characteristic electron control part 16 is according to the recompense bias voltage BM of metal 544 of target electronic characteristic information CI control.The value of the capacity between wiring 541 and ground GND is C10.
Characteristic electron control part 16 when strong inductor 545 adds electric charge, can be fixed on compensation metal 544 current potential of regulation by bias voltage BM.For example, fixed compensation metal 544 is at the VDD level, when wiring 541 from the GND level during to the VDD electrical level transfer, the effective value of wiring 541 and 544 capacity 547 of compensation metal becomes 0.At this moment, the parasitic capacitance value of wiring 541 becomes C10.On the other hand, when the GND electrical level transfer, the capability value of capacity 547 is C12 from the VDD level in wiring 541.At this moment, the parasitic capability value of wiring 541 becomes C10+C12 (with reference to Figure 16 B).
Just, by suitably changing the current potential of compensation metal 544, can change the parasitic capacity of wiring 541.Thus, can change the coupling coefficient of wiring 541 between connecting up with other.In addition, compensation metal 544 also can be fixed on the GND level.
Concrete example to example (F9) describes.Figure 17 is the key diagram about the activity ratio of individual channel.Hereinafter with reference to the background of Figure 17 description for example.
Usually, the output activity ratio of logic gate (signal value variation probability) is to obtain with each the long-pending of activity ratio of importing of this logic gate.As shown in figure 17, when the activity ratio of the input signal of each AND door was P0, P1, P2, P3 and P4, the activity ratio P (shortpath) of the path PAS that then the logic hop count is few (solid line of Figure 17) obtained by following:
P(shortpath)＝P0*P1
And the activity ratio P (longpath) of logic hop count path PAL (dotted line of Figure 17) how obtains by following:
P(longpath)＝P0*P1*P2*P3*P4。
At this, the path activity ratio is the activity ratio of the terminal section output of this path.
Because each activity ratio P0, P1, P2, P3 and P4 are below 1, so following formula is set up:
P(shortpath)≥P(longpath)。
Just, we can say that the activity ratio P (longpath) of the path of general time delay big (the logic hop count is many) is littler than the activity ratio P (shortpath) of the path of time delay little (the logic hop count is little).Usually, P (longpath) is smaller value.
Figure 18 is the block diagram that the circuit example of common register is used in expression.The circuit of Figure 18 has register 32A, 32B and 32C and logical circuit 71 and 72.Logical circuit 71 has the little path PT1 of delay and postpones big path PT2 than this path PT1.Logical circuit 72 has than the little path PT3 of path PT2 delay.
Figure 19 is the sequential chart of signal in the circuit of Figure 18.In order to prevent to produce the adjustment error, need provide the clock signal with longer cycle (with reference to the SYB of Figure 19) about the output signal SB of path PT2 in register 32B.For this reason, in the circuit of Figure 18, often the cycle with clock signal clk is predetermined to be bigger than the delay of path PT2.
Figure 20 is to use the circuit block diagram of the register of Fig. 6.The circuit of Figure 20 has semiconductor circuit 612, OR door 73 and digital multiplier 74.Circuit 612 in the circuit of Figure 18, is that the register 36A with Fig. 6 has replaced register 32B.Semiconductor circuit 612 is embodiment of semiconductor circuit 12.In Figure 20, OR door 73 and digital multiplier 74 have constituted the Characteristics Control portion of electronics.
Figure 21 is the sequential chart in the circuit of Figure 20.When adjusting error owing to the delay of path PT2, register 36A detects the adjustment error, and the error signal that expression is detected this error outputs to OR door 73.Also import error signal in addition at OR door 73 from register 36A.When detecting error, OR door 73 is with its notice digital multiplier 74.
Like this, by the circuit of Figure 20, when detecting error since cycle of clock signal be extended, so can the high clock signal of frequency of utilization.In addition, the terminal section output of big path PT2 does not change for time delay, does not detect error, and the cycle of clock signal clk I can not be extended.With reference to Figure 17, because the probability that the terminal section output of big path PT2 time delay changes is little, so the probability of the prolongation in the cycle of clock signal clk I is little.Therefore, the circuit of Figure 20 can shorten the average clock period than the circuit of Figure 18.
Although in Figure 20, use the means of digital multiplier 74 as the modulating clock frequency, not limited.Except using digital multiplier 74, also can use the fast phaselocked loop (phaselocked loop) of answer speed for example etc.
Figure 22 is the block diagram of Figure 20 circuit variation.The circuit of Figure 22 further comprises semiconductor circuit 712 except the circuit component of Figure 20, OR door 78,82 and 87, digital multiplier 79, register 81 and 86.Semiconductor circuit 712 comprises register 32D, 32E and 36B; Logical circuit 76 and 77 has same formation with the semiconductor circuit 612 of Figure 20.Register 36B and register 36A similarly have the function that detects the adjustment error.
The semiconductor circuit 612 and 712 of Figure 22 is examples of semiconductor circuit 12.In addition, OR door 73,78,82 and 87, digital multiplier 74 and 79 and register 81 and 86 constituted the Characteristics Control portion of electronics.Figure 23 is the sequential chart in the circuit of Figure 22.
Generally, clock control is critical in speed.When implementing to adjust the detection of errors, need logic that will a plurality of error signals and be used for logical signal to control with a plurality of registers, obtain logic and the time delay become problem.At this, in the circuit of Figure 22, register 81,1 circulation of output delay with OR door 73 outputs to OR door 87 as synchronizing signal SYN1.OR door 87 obtain synchronizing signal SYN1 and from the logic of the synchronizing signal of other circuit and, output to digital multiplier 79.
During from OR door 87 input sync signals, digital multiplier 79 prolongs in the next circulation of round-robin of all after dates of clock signal CLKI at digital multiplier 74 as shown in Figure 23, prolongs the cycle of clock signal CLK2, for this reason, can keep the synchronous of 2 of clock signal clk I and clock signal clks.
Equally, register 86 outputs to OR door 82 with 1 circulation of output delay of OR door 78 as synchronizing signal SYN2.OR door 82 obtain synchronizing signal SYN2 and from other circuit synchronizing signal logic and, output to multiplier 74.During from OR door 82 input sync signals, digital multiplier 74 prolongs in the next circulation of round-robin of all after dates of clock signal CLK2 at digital multiplier 79, prolongs the cycle of clock signal CLK1.
Therefore, according to the circuit of Figure 22, can simplify obtain logic and the formation of OR door 73, can reduce obtain logic and the time delay.
In addition, the circuit of Figure 20 and Figure 22 not only can improve clock frequency, and also can realize the bad detection and the output of normal value when delay fault takes place.
Application interface (ARI) between OS and application program below is described.ARI is the software layer that connects application program and OS.Judge the normal/abnormal of system for the movement from system, the information that obtains the inference system movement by ARI is indispensable.
Figure 24 is the key diagram of application interface.OS 820 carries out on the LSI 20 of Fig. 1, realizes the function of LSI20.OS 820 has the application A PI 812 of the information SEI that is used to notify system's movement of inferring 814 of OS 820 and application programs.Among Figure 24, function API F1 and APIF2 represent with the example of API812.Information SEI is the information of expression application program 814 practice conditions, is defined as independent variable in function API F1 and APIF2.
In function API F1, defining the Zhi Shiqi $statuspointer that is used for the status recognition register and the check point of Zhuan Taijicunqi $status checkpoint as independent variable.According to these information, OS820 can obtain the identifying information of status register to be detected, and the time of status register to be detected, thereby can judge that system is normal/abnormal according to the method for above-mentioned example (CI).
In function API F2, defining the Zhi Shiqi $error_recovery_pointer that is used for the identification error recovery routine as independent variable.According to these information, OS820 can obtain the identifying information of the error recovery routine of examine, thereby can realize the judgement that system is normal/abnormal according to the method for above-mentioned example (C2).
Although be in the above embodiments to using MOS transistor to be illustrated, also can using other transistor.
As mentioned above, when can getting rid of common operate as normal, the present invention crosses the residue limit, so be useful for require at a high speed and the semiconductor IC system of the work of low consumption electric power etc.
Claims (32)
1, a kind of semiconductor IC system comprises:
The controlling object circuit of executive routine;
The system information monitoring unit of the system information of the described controlling object circuit state of output expression;
Obtain the circuit characteristic of described controlling object circuit and the circuit characteristic monitoring unit that described circuit characteristic is exported as circuit characteristic information;
Judge the whether fault judgement portion of operate as normal of described controlling object circuit according to described system information;
When described controlling object circuit operate as normal, the reference circuit characteristic maintaining part that described circuit characteristic information is kept as the reference circuit characteristic information;
When described controlling object circuit cisco unity malfunction, according to the failure cause judging part of detected circuit characteristic information of described circuit characteristic monitoring unit and described reference circuit characteristic information failure judgement reason;
Judge calibration object in the described controlling object circuit according to described failure cause, generate and export the calibration object judging part of the characteristic information of the target electronic in the described calibration object; And
Control the characteristic electron control part of described controlling object circuit according to described target electronic characteristic information.
2, semiconductor IC system according to claim 1 is characterized in that:
Described system information monitoring unit with the state of described controlling object circuit as described system information output and
Described fault judgement portion when the state of described at the fixed time controlling object circuit is the state of being scheduled to, judges that described controlling object circuit is an operate as normal, and other situation judges that described controlling object circuit is a non-normal working.
3, semiconductor IC system according to claim 1 is characterized in that:
Described system information monitoring unit is exported the error recovery routine information that expression is called in the described program as described system information, and
Described fault judgement portion, the error recovery routine in described program is called stipulated number when above, judges that described controlling object circuit is a non-normal working, and other situation judges that described controlling object circuit is an operate as normal.
4, semiconductor IC system according to claim 1 is characterized in that
Described system information monitoring unit is exported the information that expression operating system is normally closed as system information, and
Described fault judgement portion when operating system is not last time normally closed, judges that described controlling object circuit is a non-normal working, and other situation judges that described controlling object circuit is an operate as normal.
5, semiconductor IC system according to claim 1 is characterized in that
Described system information monitoring unit, the information that error takes place when the described program of expression is carried out is exported as system information, and
Described fault judgement portion when described error takes place, judges that described controlling object circuit is a non-normal working, and other situation judges that described controlling object circuit is an operate as normal.
6, semiconductor IC system according to claim 1 is characterized in that described system information monitoring unit, and the size of determining the noise that produces on the prescribed route of described controlling object circuit is as described circuit characteristic.
7, semiconductor IC system according to claim 6 is characterized in that described circuit characteristic monitoring unit comprises:
Have the grid that is applied with as the detected object signal of the signal on the prescribed route, be applied with the source electrode of first reference voltage and be connected to a n transistor npn npn of the drain electrode of first dynamic node;
Have the grid that is applied with the detected object signal, be applied with the source electrode of second reference voltage and be connected a p transistor npn npn of the drain electrode of second dynamic node;
Have the 2nd p transistor npn npn of source electrode that is applied with supply voltage and the drain electrode that is connected with described first dynamic node, it charges to described first dynamic node according to reset signal;
Have source electrode that is applied with ground voltage and the 2nd n transistor npn npn that is connected the drain electrode of described second dynamic node, it discharges to described second dynamic node according to reset signal;
As output, have described first dynamic node, and reception is than the NOR circuit of the reference signal of the signal on the part of the described prescribed route of the element of the described wiring of the approaching driving of the part of the described wiring that provides described detected object signal;
As output, have described second dynamic node, and receive the NAND circuit of described reference signal;
First latch that output by described NOR circuit is provided with;
Second latch that output by described NAND circuit is provided with;
With the output logic of described first and second latch and the OR circuit of exporting as detection signal, described detection signal is represented the noise of the reference voltage of correspondence described first or second.
8, semiconductor IC system according to claim 1 is characterized in that described circuit characteristic monitoring unit, is size switching time of the signal in the described controlling object circuit prescribed route is obtained as described circuit characteristic.
9, semiconductor IC system according to claim 8 is characterized in that described circuit characteristic monitoring unit comprises:
Have the grid that is applied with as the detected object signal on the prescribed route, be applied with the source electrode of first reference voltage and be connected a n transistor npn npn of the drain electrode of first dynamic node;
Have the grid that is applied with described detected object signal, be applied with the source electrode of second reference voltage and be connected a p transistor npn npn of the drain electrode of second dynamic node;
Have the source electrode that is applied with supply voltage and be connected the 2nd p transistor npn npn that first dynamic node drains, it charges to described first dynamic node according to reset signal;
Have source electrode that is applied with ground voltage and the 2nd n transistor npn npn that is connected the drain electrode of described second dynamic node, it discharges to described second dynamic node according to reset signal;
Postpone described detected object signal according to first delayed control signal, and export the first variable delay impact damper of the detected object signal of described delay;
Postpone described detected object signal according to second delayed control signal, and export the second variable delay impact damper of the detected object signal of described delay;
Have as described first dynamic node of input and the NOR circuit of the output that receives the described first variable delay impact damper;
Have as described second dynamic node of input and the NAND circuit of the output that receives the described second variable delay impact damper;
First latch that output by described NOR circuit is provided with;
Second latch that output by described NAND circuit is provided with;
With the output logic of described first and second latch and the OR circuit of exporting as the detection signal that the switching time of representing corresponding described first and second variable delay buffer delay, size detection arrived.
10, semiconductor IC system according to claim 1 is characterized in that described circuit characteristic monitoring unit, is that the delay of signal in the intended path of described controlling object circuit is obtained as the characteristic of described circuit.
11, semiconductor IC system according to claim 10 is characterized in that described circuit characteristic monitoring unit comprises:
Postpone the signal of the initial point of described intended path according to delayed control signal, and export the variable buffering device of the signal of described delay; And
With the signal of described intended path terminal point and latch lock after the signal Synchronization of described variable buffering device output, and will represent the latch of the size of the described variable delay buffer delay of detected correspondence as detection signal output.
12, semiconductor IC system according to claim 1, it is characterized in that described circuit characteristic monitoring unit, when the power supply of described controlling object circuit reduces, obtain as described circuit characteristic according to the variation of the signal of the output of the predetermined holding circuit of described controlling object circuit.
13, semiconductor IC system according to claim 12 is characterized in that described circuit characteristic monitoring unit comprises:
With the detected object signal and the signal Synchronization of acquisition of the signal of the output of predetermined holding circuit, after latch is locked, export the latch of described latch lock signal;
The output of more described detected object signal and described latch, both export the comparator circuit of the detection signal of the described detected object signal variation of expression not simultaneously.
14, semiconductor IC system according to claim 1 is characterized in that described circuit characteristic monitoring unit, is the supply voltage or the temperature of described controlling object circuit are obtained as described circuit characteristic.
15, semiconductor IC system according to claim 1 is characterized in that
Described system information monitoring unit is exported the data of the residual amount of expression battery as described system information;
Described calibration object judging part in the residual amount of battery after a little while, generates described target electronic characteristic information, to improve the supply voltage of supplying with described controlling object circuit and the correction that reduces the frequency of operation of described controlling object circuit.
16, semiconductor IC system according to claim 1, it is characterized in that described calibration object judging part, generate described target electronic characteristic information, supply with the supply voltage of described controlling object circuit with temporary transient raising, then, reduce described supply voltage termly, when when reducing described supply voltage, not breaking down, the correction that stops improving supply voltage.
17, semiconductor IC system according to claim 1 is characterized in that
Described system information monitoring unit will be exported as described system information about the information of described controlling object circuit temperature;
Described calibration object judging part, generate described target electronic characteristic information, to improve the supply voltage of supplying with described controlling object circuit and to allow described controlling object circuit substrate bias voltage that bigger back-biased correction is provided, perhaps reduce the correction of the frequency of operation of described controlling object circuit.
18, semiconductor IC system according to claim 1 is characterized in that
Described system information monitoring unit is that the identifier of described controlling object circuit is exported as described system information;
Described calibration object judging part, infer the manufacturing period of described controlling object circuit from described system information, from described manufacturing period during, generate described target electronic characteristic information, to improve the supply voltage of supplying with described controlling object circuit above official hour.
19, semiconductor IC system according to claim 1 is characterized in that
Described controlling object circuit comprises and drives a plurality of driving transistors that node is connected in parallel;
Described characteristic electron control part when the reason of fault is noise, is controlled in described a plurality of driving transistors, drives the number of the driving transistors of described node.
20, semiconductor IC system according to claim 1 is characterized in that described characteristic electron control part, when the reason of fault is noise, the substrate voltage or the supply voltage of described controlling object circuit is controlled as calibration object.
21, semiconductor IC system according to claim 1 is characterized in that described controlling object circuit has:
Metal line;
The metal of the compensation of approaching described metal line configuration;
On the described compensation metal or under the configuration strong inductor.
22, semiconductor IC system according to claim 1 is characterized in that
Operating system is carried out work by each described system information monitoring unit, described fault judgement portion, described reference circuit maintaining part, described failure cause judging part and described calibration object judging part;
Described operating system has the software layer that connects described program and described operating system;
Described software layer is with the function of the described program implementation status of expression as the independent variable definition.
23, semiconductor IC system according to claim 1 is characterized in that
Described controlling object circuit has and detects the register of adjusting error and exporting its testing result;
Described system information monitoring unit is that the information of the described testing result of expression is exported as system information.
24, semiconductor IC system according to claim 23 is characterized in that described register comprises:
First main latch of latch lock input value, and
By second main latch of behind the described first main latch latch lock described input value latch being locked, wherein
When detecting the adjustment error, described register is exported the nodal value of described second main latch.
25, semiconductor IC system according to claim 23 is characterized in that described register comprises:
Delay clock signals is also exported the clock delay circuit of resulting delay clock signals;
First main latch with described input value and the synchronous back of described clock signal latch lock;
With the value of described input and second main latch of the synchronous back of described delay clock signals latch lock;
Latch lock described first main latch or described second main latch output from latch; And
Whether the nodal value of the nodal value of described first main latch and described second main latch is consistent, as the error-detector circuit of described testing result output; Wherein
Described first main latch, when described testing result is represented unanimity, the value of the node of described first main latch of correspondence is input to described from latch, and
Described second main latch is represented when inconsistent in described testing result, is input to the value of the node of described second main latch of correspondence described from latch.
26, semiconductor IC system according to claim 23 is characterized in that
Described controlling object circuit is carried out built-in self-test,
Described calibration object portion according to the result of described inside self test, does not obtain as described target electronic characteristic information detecting the supply voltage scope of adjusting error in the described controlling object circuit, and
Described characteristic electron control part after reducing described supply voltage, detects when adjusting error, and described supply voltage is risen to value in the described scope.
27, a kind of semiconductor IC system is characterized in that comprising:
Controlling object circuit with register; And
Clock signal is supplied with the characteristic electron control part of described controlling object circuit; Wherein
Described register detects the adjustment error in the described controlling object circuit;
Described characteristic electron control part is when described register detects the adjustment error, prolongs the cycle of described clock signal.
28, semiconductor IC system according to claim 27, it is characterized in that described characteristic electron control part, at cycle stretch-out the next circulation of round-robin of described clock signal in, prolong the cycle of other clock signals of supplying with described controlling object circuit.
29, a kind of SIC (semiconductor integrated circuit), it comprises:
A plurality of logical circuits;
Connect the metal line between described a plurality of logical circuit;
Compensation metal near described metal line configuration; And
On the described compensation metal or under the configuration strong inductor.
30, a kind of on described SIC (semiconductor integrated circuit) the operation system, described operating system has
The software layer of linker and described operating system, wherein
Described software layer is to represent the function of the information of described program implementation status as the independent variable definition.
31, a kind of control method of SIC (semiconductor integrated circuit) is the control method of the SIC (semiconductor integrated circuit) of the controlling object circuit in the described SIC (semiconductor integrated circuit) of control, and described control method comprises:
According to the system information of state of the described controlling object circuit of expression executive routine, judge the whether fault judgement step of operate as normal of described controlling object circuit;
When described controlling object circuit operate as normal, the maintenance reference circuit characteristic step that described circuit characteristic information is kept as the reference circuit characteristic information;
When described controlling object circuit cisco unity malfunction, according to the failure cause determining step of the circuit characteristic information and the described reference circuit characteristic information failure judgement reason of described controlling object circuit;
Judge the calibration object determining step of the calibration object in the described controlling object circuit according to described failure cause;
Generate the aligning step of the characteristic information of the target electronic in the described calibration object.
32, a kind of control method of SIC (semiconductor integrated circuit) is the control method of the SIC (semiconductor integrated circuit) of the controlling object circuit in the described SIC (semiconductor integrated circuit) of control, and this control method comprises:
Detect the detection step of the adjustment error in the described controlling object circuit;
In described detection step, detect when adjusting error, will supply to the controlled step of cycle stretch-out of the clock signal of described controlling object circuit.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2006114814 | 2006-04-18 | ||
| JP2006114814 | 2006-04-18 | ||
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102812373A (en) * | 2010-03-15 | 2012-12-05 | 国立大学法人九州工业大学 | Semiconductor device, detection method, and program |
| CN113391195A (en) * | 2020-03-11 | 2021-09-14 | 株式会社东芝 | Fault detection circuit and semiconductor device |
| CN117521588A (en) * | 2024-01-08 | 2024-02-06 | 深圳中安辰鸿技术有限公司 | Control method and device for preventing non-uniform aging of integrated circuit and processing chip |
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2007
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102812373A (en) * | 2010-03-15 | 2012-12-05 | 国立大学法人九州工业大学 | Semiconductor device, detection method, and program |
| CN102812373B (en) * | 2010-03-15 | 2014-12-10 | 国立大学法人九州工业大学 | Semiconductor device and detection method |
| CN113391195A (en) * | 2020-03-11 | 2021-09-14 | 株式会社东芝 | Fault detection circuit and semiconductor device |
| CN117521588A (en) * | 2024-01-08 | 2024-02-06 | 深圳中安辰鸿技术有限公司 | Control method and device for preventing non-uniform aging of integrated circuit and processing chip |
| CN117521588B (en) * | 2024-01-08 | 2024-05-10 | 深圳中安辰鸿技术有限公司 | Control method and device for preventing non-uniform aging of integrated circuit and processing chip |
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