CN101078950A - Power consumption reduction method for intellectual core and functional module for chip system - Google Patents
Power consumption reduction method for intellectual core and functional module for chip system Download PDFInfo
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Abstract
The invention discloses a power decreasing method of various intellective property core and functional module in SoC, which comprises the following steps: a) dividing all states of original functional module to two specie-' free' state and ' working' state; b) providing a logic circuit; connecting to the original functional module; constructing new low power functional module; finishing the logic function with the logic circuit; keeping clock close if without request for the original functional module; opening the clock if with the request for the original functional module; entering the original functional module into the ' working' state; closing the clock till the original functional module in ' free' state without bus request. This invention decreases dynamic state and leaking power consumption of IP core and auto-switches power source of the IP core at the same time.
Description
Technical field
The present invention relates to micro-processor architecture and integrated circuit technique, be particularly related to SOC (system on a chip) (System-on-Chip, hereinafter to be referred as SoC) in the method for reducing power consumption of various intellecture properties (Intellectual Property is hereinafter to be referred as IP) nuclear and functional module.
Background technology
As everyone knows, the key of raising SoC design efficiency depends on the reusable of IP kernel.IP kernel is the refinement of engineers research and design, the main function that realizes that some are common and certain design difficulty is arranged, these IP kernels generally all pass through checking, can make the devisers of SoC just can directly use these IP kernels without design iterations, thereby shorten the design cycle and improve system reliability.Therefore, IP kernel is the base unit of SoC, reduces the IP kernel that the SoC power consumption just needs the design low-power consumption.
The existing method of utilizing gated clock to reduce the IP kernel power consumption has two kinds: door control unit is inserted in a kind of register front that is to use electric design automation (Electronics Design Automation is hereinafter to be referred as EDA) instrument to have self feed back in IP kernel; Another kind is to add a programmable door control unit before the manual clock signal in whole module of IP kernel deviser is imported, and the user utilizes the clock of this IP kernel of software switch.The shortcoming of first method is to use specific eda tool in the existing technology, and can insert a large amount of door control units at random, original just very complicated rear end clock trees design is caused bigger difficulty, and when not working, IP kernel do not close the clock network of entire I P nuclear, though partial circuit meeting dormancy, power consumption reduces not thorough; And in the existing technology shortcoming of second method be can not the automatic switch IP kernel clock, but need the user software support, and depend on the monitoring that the user uses IP kernel, that is to say that the user needs according to own operating position to this IP kernel and functional module, determine the unlatching of its clock or close, thereby this kind method inefficiency and easily makeing mistakes.Such as, when IP kernel clock actual needs was closed, the user might not close clock, therefore lost unnecessary power consumption; And when can not close clock,, will cause system gross error to occur owing to closing that user's carelessness causes.
Therefore, the deficiencies in the prior art just need a kind of improved method of reducing power consumption that is used for SoC IP kernel and functional module.
Summary of the invention
The objective of the invention is to overcome in the prior art and to reduce power consumption not thoroughly and the problem of makeing mistakes easily, thereby the method for reducing power consumption of a kind of improved SoC of being used for IP kernel and functional module is provided.
In order to achieve the above object, the present invention takes following technical scheme.
A kind of improved method that is used for the reduction power consumption of SoC functional module comprises:
A) all states with original functional module are divided into two classes---" free time " attitude and " work " attitude, and " work " attitude promptly non-" free time " attitude, " free time " attitude i.e. the current state of effectively not working of this original functional module;
B) provide a logical circuit and described original functional module to connect and compose new low-power consumption functional module, this logical circuit is finished following logic function: if bus just keeps clock to close not to the request of original functional module; If bus has the request to this original functional module, then open the clock of original functional module, original functional module enters " work " attitude; Keep clock to open, be in " free time " attitude and do not have bus request, just close the original functional module clock and also keep closing, once more this functional module is filed a request up to bus up to original functional module.
In technique scheme, also comprise: the power supply of described logical circuit and the power supply of described original functional module are isolated, this logical circuit is also realized following logic function: when described original functional module that and if only if is in " free time " attitude and does not have bus request, close the power supply of original functional module; Otherwise open the original functional module power supply.
In technique scheme, in the described step a),, directly divide its " free time " state into a class in hardware description language, there being explicit state machine to describe, other state divides " operating conditions " into; For be not the explicit described original functional module state of description in hardware description language, but in other streamline of each grade, implicitly represent, need the result of the significance bit register in the streamline be encoded, finish the division of " free time " attitude and " work " attitude.
In technique scheme, logical circuit described in the step b) comprises that an effective latch of low level is connected with door with one two input; And when clock was high level, described latch cut out; When clock is low level, described latch conducting, described and door shields the transmission of burr.
A kind of improved method of reducing power consumption that is used for the SoC IP kernel comprises:
A) all states with original IP kernel are divided into two classes---" free time " attitude and " work " attitude, and " work " attitude promptly non-" free time " attitude, " free time " attitude i.e. the current state of effectively not working of this IP kernel;
B) provide a logical circuit and described original IP kernel to connect and compose new Low Power IP Core, this logical circuit is finished following logic function: if bus just keeps clock to close not to the request of original IP kernel; If bus has the request to this IP kernel, then open the clock of original IP kernel, original IP kernel enters " work " attitude; Keep clock to open, be in " free time " attitude and do not have bus request, just close the initial IP nuclear clock and also keep closing, once more this IP kernel is filed a request up to bus up to original IP kernel.
In technique scheme, also comprise: the power supply of described logical circuit and the power supply of described original IP kernel are isolated, this logical circuit is also realized following logic function: and if only if when described original IP kernel is in " free time " attitude and do not have bus request, closes the power supply of original IP kernel; Otherwise open original IP kernel power supply.
In technique scheme, in the described step a),, directly divide its " free time " state into a class in hardware description language, there being explicit state machine to describe, other state divides " operating conditions " into; For be not the explicit described initial IP nuclear state of description in hardware description language, but in other streamline of each grade, implicitly represent, need the result of the significance bit register in the streamline be encoded, finish the division of " free time " attitude and " work " attitude.
In technique scheme, when opening or closing the clock of IP kernel, cause gross error for fear of issuable clock bur (glitch), use an effective latch of low level (Latch) and one two input to build door control unit with door; And when clock is high level, thereby described latch cuts out the transmission that has shielded burr; When clock is low level, described latch conducting, described and goalkeeper shields the transmission of burr.
Compared with the prior art, advantage of the present invention is:
The present invention utilizes IP kernel self duty by improved design, and according to practical application, the clock of the real-time nuclear of switch entire I P automatically reduces the saltus step of IP kernel clock network, thereby reduces the dynamic power consumption of IP kernel; The power supply of while this IP kernel of automatic switch, the electricity leakage power dissipation of this IP kernel of reduction under the prerequisite that does not influence operate as normal.
Description of drawings
Fig. 1 is the synoptic diagram of one embodiment of the invention to the reduction power consumption of the original IP kernel of explicit state description;
Fig. 2 is the synoptic diagram of another embodiment of the present invention to the reduction power consumption of the original IP kernel of the state description of implicit expression.
Embodiment
Below in conjunction with the drawings and specific embodiments the present invention is described in further detail:
As shown in Figure 1, present embodiment is to the synoptic diagram of the reduction power consumption of the original IP kernel of explicit state description.
Step a) is divided into two classes with all states of original IP kernel---" free time " attitude and " work " attitude, and " work " attitude promptly non-" free time " attitude, " free time " attitude i.e. the current state of effectively not working of this IP kernel.Specific as follows:
Among the figure, be the working model of original IP kernel 10 in the square frame, the state of this original IP kernel 10 has " free time ", " request ", " preparation ", " RUN ", " end "; When being in " free time " attitude,,, then enter the " RUN " attitude if bus is sent request if not request of bus then remains on " free time " attitude; Circle is represented state among the figure, and arrow is represented transition, has indicated the next state of state machine.State realizes that by a series of registers (sequential circuit) transition is realized by combinational circuit in the side circuit of original IP kernel 10.Since in the present embodiment in hardware description language, there being explicit state machine to describe, state that directly will this original IP kernel 10 is divided into two classes-" free time " attitude and " work " attitude, " work " attitude is by " free time " attitude state formation in addition.
B) provide a logical circuit and described original IP kernel to connect and compose new Low Power IP Core, this logical circuit is finished following logic function: if bus just keeps clock to close not to the request of original IP kernel; If bus has the request to this IP kernel, then open the clock of original IP kernel, original IP kernel enters " work " attitude; Keep clock to open, be in " free time " attitude and do not have bus request, just close the initial IP nuclear clock and also keep closing, once more this IP is filed a request up to bus up to original IP kernel.
Specific as follows:
When original IP kernel 10 satisfies two conditions that dotted line is indicated among Fig. 1, close the clock of this IP kernel, otherwise keep the opening of clock, if promptly bus just keeps clock to close not to the request of original IP kernel; If bus has the request to this IP kernel, then open the clock of original IP kernel, original IP kernel enters " work " attitude; Keep clock to open, be in " free time " attitude and do not have bus request, just close the initial IP nuclear clock and also keep closing, once more this IP is filed a request up to bus up to original IP kernel.
As seen, present embodiment increases a logical circuit and realizes the clock switch logic on the basis of original IP kernel 10, just formed a new IP kernel, this nuclear is a Low Power IP Core 15, automatically switch entire I P examines 15 clock in real time, reduce the saltus step of IP kernel 15 clock networks, thereby reduce the dynamic power consumption of IP kernel 15.
Further, the power supply of logical circuit 11 and the power supply of described original IP kernel 10 are isolated, this logical circuit 10 is also realized following logic function: and if only if when described original IP kernel 10 is in " free time " attitude and do not have bus request, closes the power supply of original IP kernel 10; Otherwise open the power supply of original IP kernel 10.Such Low Power IP Core 15 can the original IP kernel 10 of automatic switch power supply, under the prerequisite that does not influence operate as normal, reduce the electricity leakage power dissipation of this IP kernel.
Embodiment 2
Fig. 2 is the synoptic diagram of another embodiment of the present invention to the reduction power consumption of the original IP kernel of the state description of implicit expression, and the concrete grammar when carrying out low-power consumption transforms is described.It is 3 level production lines that the streamline of this IP kernel original design is divided into, and each grade all is the tank of depositing that comprises numerous register-bit.The method that present embodiment reduces power consumption comprises:
Step a) is divided into two classes with all states of original IP kernel---" free time " attitude and " work " attitude, and " work " attitude promptly non-" free time " attitude, " free time " attitude i.e. the current state of effectively not working of this IP kernel.
The characteristics that the original IP kernel of present embodiment is different from most of IP kernels are, in the design code of describing with hardware description language, there is not explicit state machine to describe, its state is by the significance bit implicit representation of multi-stage pipeline, therefore need suitably handle, and is specific as follows:
At first the instruction of the outer bus 21 of original IP kernel 20 (frame of broken lines is interior among the figure) is monitored, judge whether it is effective request, if " request " signal is put 1, otherwise puts 0; Utilize the significance bit register in 1 grade 22 on the streamline, when " request " signal was put first rising edge clock after 1 and arrived, it was 1 that this significance bit is set, and promptly " streamline 1 grade effectively " signal is 1; Two level production lines subsequently, 2 grade 23 on streamline, streamline comprise a significance bit register for 3 grade 24 respectively, the numerical value of the significance bit register that streamline is 1 grade 22 passes to the significance bit of 2 grade 23 on streamline in following one-period, the significance bit that streamline is 2 grade 23 passes to the significance bit of 3 grade 24 on streamline in following one-period, by that analogy; With the input of the significance bit of 1 to 3 grade on streamline, be output as " streamline is busy " signal as first OR circuit 25; With " request " signal and of the input of " streamline is busy " signal as second OR circuit 26, be output as " clock enables " signal, data terminal input as the effective latch 27 of low level, outside clock signal is as the clock end input of this latch 27, latch 27 is output as " gate " signal, this signal and clock signal are output as the original IP kernel 20 inner clocks that use as two input ends of AND circuit 28.
First or door 25 be three inputs, second or door 26 be two inputs, with door 28 be two inputs.
Because " clock enables " signal is built by combinational circuit, the error of performance that causes IP kernel for fear of issuable clock bur (glitch), use latch (Latch) 27 and AND circuit 28 to build door control unit: when clock as high level the time, thereby latch 27 cuts out the transmission that has shielded burr; When clock is low level, latch 27 conductings will shield the transmission of burr with door 28.
Present embodiment increases logical circuit and realizes the clock switch logic on the basis of original IP kernel 20, just formed a new IP kernel 30, this nuclear is a Low Power IP Core 30, have identical logic function and sequential with original IP kernel, can be in real time the clock of switch entire I P nuclear automatically, reduce the saltus step of IP kernel clock network, thereby reduce the dynamic power consumption of IP kernel.
Further, the original IP kernel 20 and the power supply of other logical circuits are isolated, and with " gate " signal of latch 27 output or clock enable signal power switch signal as this IP kernel 20, when " gate " signal is 1, opening the power supply of this IP kernel 20, is to close the power supply of IP kernel 20 at 0 o'clock.The power supply that Low Power IP Core 30 can the original IP kernel 20 of automatic switch like this reduces the electricity leakage power dissipation of this IP kernel 20 under the prerequisite that does not influence operate as normal.
It should be noted last that above embodiment is only unrestricted in order to technical scheme of the present invention to be described.Although the present invention is had been described in detail with reference to embodiment, those of ordinary skill in the art is to be understood that, technical scheme of the present invention is made amendment or is equal to replacement, do not break away from the spirit and scope of technical solution of the present invention, it all should be encompassed in the middle of the claim scope of the present invention.
Claims (10)
1, a kind of method of reducing power consumption that is used for the SOC (system on a chip) functional module comprises:
A) all states with original functional module are divided into two classes---" free time " attitude and " work " attitude, and described " work " attitude is non-" free time " attitude, described " free time " attitude is the current state of effectively not working of this original functional module;
B) provide a logical circuit and described original functional module to connect and compose new low-power consumption functional module, this logical circuit is finished following logic function: if bus just keeps clock to close not to the request of original functional module; If bus has the request to this original functional module, then open the clock of original functional module, original functional module enters " work " attitude; Keep clock to open, be in " free time " attitude and do not have bus request, just close the original functional module clock and also keep closing, once more this functional module is filed a request up to bus up to original functional module.
2, according to the described method that is used for the reduction power consumption of SOC (system on a chip) functional module of claim 1, also comprise: step c) is isolated the power supply of described logical circuit and the power supply of described original functional module, this logical circuit is also realized following logic function: when described original functional module that and if only if is in " free time " attitude and does not have bus request, close the power supply of original functional module; Otherwise open the original functional module power supply.
3, the method for reducing power consumption that is used for the SOC (system on a chip) functional module according to claim 1, in the described step a), for in hardware description language, there being explicit state machine to describe, directly divide its " free time " state into a class, other state divides " operating conditions " into; For be not the explicit described original functional module state of description in hardware description language, but in other streamline of each grade, implicitly represent, need the result of the significance bit register in the streamline be encoded, finish the division of " free time " attitude and " work " attitude.
4, according to claim 1,2 or 3 each described method of reducing power consumption that are used for the SOC (system on a chip) functional module, logical circuit described in the step b) comprises that an effective latch of low level is connected with door with one two input; And when clock was high level, described latch cut out; When clock is low level, described latch conducting, described and door shields the transmission of burr.
5, a kind of method of reducing power consumption that is used for the SOC (system on a chip) intellectual property core comprises:
A) all states with original intellectual property core are divided into two classes---" free time " attitude and " work " attitude, and described " work " attitude is non-" free time " attitude, described " free time " attitude is the current state of effectively not working of this intellectual property core;
B) provide a logical circuit and described original intellectual property core to connect and compose new low-power consumption intellectual property core, this logical circuit is finished following logic function: if bus just keeps clock to close not to the request of original intellectual property core; If bus has the request to this intellectual property core, then open the clock of original intellectual property core, original intellectual property core enters " work " attitude; Keep clock to open, be in " free time " attitude and do not have bus request, just close original intellecture property nuclear clock and also keep closing, once more this intellectual property core is filed a request up to bus up to original intellectual property core.
6, the method for reducing power consumption that is used for the SOC (system on a chip) intellectual property core according to claim 5, also comprise: step c) is isolated the power supply of described logical circuit and the power supply of described original intellectual property core, this logical circuit is also realized following logic function: when described original intellectual property core that and if only if is in " free time " attitude and does not have bus request, close the power supply of original intellectual property core; Otherwise open original intellectual property core power supply.
7, the method for reducing power consumption that is used for the SOC (system on a chip) intellectual property core according to claim 5 or 6, in the described step a), for in hardware description language, there being explicit state machine to describe, directly divide its " free time " state into a class, other state divides " operating conditions " into; For be not the explicit described original intellecture property nuclear state of description in hardware description language, but in other streamline of each grade, implicitly represent, need the result of the significance bit register in the streamline be encoded, finish the division of " free time " attitude and " work " attitude.
8, the method for reducing power consumption that is used for the SOC (system on a chip) intellectual property core according to claim 5, logical circuit described in the step b) comprise that an effective latch of low level is connected with door with one two input; And when clock was high level, described latch cut out; When clock is low level, described latch conducting, described and door shields the transmission of burr.
9, the method for reducing power consumption that is used for the SOC (system on a chip) intellectual property core according to claim 7, logical circuit described in the step b) comprise that an effective latch of low level is connected with door with one two input; And when clock was high level, described latch cut out; When clock is low level, described latch conducting, described and door shields the transmission of burr.
10, according to the described method of reducing power consumption that is used for the SOC (system on a chip) intellectual property core one of in the claim 5,6 or 9, described logical circuit comprises: NAND gate circuit (12), two input ends of this NAND gate circuit (12) connect " free time " attitude marking signal of original intellectual property core (10) and the marking signal that bus does not have request respectively; Latch (13), the output terminal of described NAND gate circuit (12) is connected to the data input pin of latch (13), another input end of this latch (13) connects the work clock signal, the output terminal of latch (13) is connected to an input end of an AND circuit (14), another input end of described AND circuit (14) connects the work clock signal, and it is its input service clock signal that the output terminal of described AND circuit (14) is connected to original intellectual property core (10).
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| CN101227298B (en) * | 2008-01-09 | 2010-06-02 | 南京大学 | Router power consumption determination method based on network on chip |
| CN101853067A (en) * | 2009-03-30 | 2010-10-06 | 联发科技股份有限公司 | Reduce the method for rating of set consumption and have the device of embedded memory module |
| CN101959291A (en) * | 2009-07-16 | 2011-01-26 | 北京中电华大电子设计有限责任公司 | Clock management method for wireless local area network (WLAN) card chip |
| CN103091620A (en) * | 2012-12-29 | 2013-05-08 | 江苏东大集成电路系统工程技术有限公司 | Optimization method of capturing power consumption in scan test |
| CN103838295A (en) * | 2012-11-27 | 2014-06-04 | 中兴通讯股份有限公司 | Low-speed external module integration method and device |
| CN103913702A (en) * | 2012-12-28 | 2014-07-09 | 辉达公司 | System for reducing peak power during scan shift at the local level for scan based tests |
| CN104123117A (en) * | 2013-04-28 | 2014-10-29 | 中国科学院微电子研究所 | Microcontroller used for improving electromagnetic compatibility characteristic of automobile electronic control system |
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| CN1510591A (en) * | 2002-12-20 | 2004-07-07 | 中国科学院计算技术研究所 | Network computer design method and realization based on SOC |
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| CN101227298B (en) * | 2008-01-09 | 2010-06-02 | 南京大学 | Router power consumption determination method based on network on chip |
| CN101853067A (en) * | 2009-03-30 | 2010-10-06 | 联发科技股份有限公司 | Reduce the method for rating of set consumption and have the device of embedded memory module |
| CN101959291A (en) * | 2009-07-16 | 2011-01-26 | 北京中电华大电子设计有限责任公司 | Clock management method for wireless local area network (WLAN) card chip |
| CN101959291B (en) * | 2009-07-16 | 2012-10-03 | 北京中电华大电子设计有限责任公司 | Clock management method for wireless local area network (WLAN) card chip |
| CN103838295A (en) * | 2012-11-27 | 2014-06-04 | 中兴通讯股份有限公司 | Low-speed external module integration method and device |
| CN103913702A (en) * | 2012-12-28 | 2014-07-09 | 辉达公司 | System for reducing peak power during scan shift at the local level for scan based tests |
| CN103091620A (en) * | 2012-12-29 | 2013-05-08 | 江苏东大集成电路系统工程技术有限公司 | Optimization method of capturing power consumption in scan test |
| CN104123117A (en) * | 2013-04-28 | 2014-10-29 | 中国科学院微电子研究所 | Microcontroller used for improving electromagnetic compatibility characteristic of automobile electronic control system |
| CN111426947A (en) * | 2014-12-22 | 2020-07-17 | 三星电子株式会社 | System on chip comprising logic circuitry |
| CN111426947B (en) * | 2014-12-22 | 2022-03-29 | 三星电子株式会社 | System on chip comprising logic circuitry |
| CN106681472A (en) * | 2016-10-20 | 2017-05-17 | 南方电网科学研究院有限责任公司 | Heterogeneous multi-core processor power consumption control device and method |
| CN106681472B (en) * | 2016-10-20 | 2019-08-23 | 南方电网科学研究院有限责任公司 | Heterogeneous multi-nucleus processor power consumption control apparatus and its power consumption control method |
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