CN101075410B - Image display system and method for driving display assembly - Google Patents

Image display system and method for driving display assembly Download PDF

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Publication number
CN101075410B
CN101075410B CN 200710107528 CN200710107528A CN101075410B CN 101075410 B CN101075410 B CN 101075410B CN 200710107528 CN200710107528 CN 200710107528 CN 200710107528 A CN200710107528 A CN 200710107528A CN 101075410 B CN101075410 B CN 101075410B
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coupled
transistor
node
signal
period
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CN 200710107528
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CN101075410A (en )
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刘炳麟
彭杜仁
詹川逸
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奇美电子股份有限公司
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Abstract

A pixel driving circuit is prepared as arranging the first and the second nodes on storage capacity, setting grid on transistor and coupling said transistor between two said nodes, coupling shift circuit to the first node for transmitting data signal to the first node, coupling switch circuit to driving component and the first display component as well as the second display component for making said driving component be on diode-coupled at loading time intervals of the first data and the second data.

Description

影像显示系统和驱动显示组件的方法 Image display system and a method of driving a display assembly

技术领域 FIELD

[0001] 本发明涉及一种像素驱动电路,特别是涉及可补偿阈值电压和电源供应的像素驱动电路。 [0001] The present invention relates to a pixel driving circuit, particularly to compensate for the threshold voltage of the power supply and the pixel driving circuit.

背景技术 Background technique

[0002] 有机发光二极管(organic light-emitting diodes,OLEDs)显示器是采用有机化合物作为发光材料而能够发出光线的平面显示器,有机发光二极管显示器具有体积小、重量轻、可视范围广、高对比、以及高反应速度等优点。 [0002] The OLED (organic light-emitting diodes, OLEDs) display is employed as a luminescent material and an organic compound capable of emitting light of a flat display, an organic light emitting diode display having a small size, light weight, wide viewing range, high contrast, and the advantage of a high reaction rate.

[0003] 有源矩阵式有机发光二极管(Active Matrix OLED, AM0LED)显示器为新一代平面显示器,与有源矩阵式液晶显示器相比较,有源矩阵式有机发光二极管显示器具有许多优点,例如:较高的对比、较宽的视角、不需背光而有较薄的模块厚度、较低的功耗以及较低的成本,有源矩阵式液晶显示器由电压驱动,而有源矩阵式有机发光二极管显示器需要由电流源来驱动电致发光组件,电致发光组件的亮度正比于所通过的电流,流经电致发光组件的电流量的变异对于有源矩阵式有机发光二极管显示器的亮度均勻度有负面的影响,因此,像素驱动电路的质量对于有源矩阵式有机发光二极管显示器的画质非常重要。 [0003] The active matrix organic light emitting diode (Active Matrix OLED, AM0LED) display is a next-generation flat-panel display, compared with the active matrix liquid crystal display, active matrix organic light emitting diode display has many advantages, for example: high contrast, wide viewing angle, without backlight module has a thinner thickness, lower power consumption and lower cost, an active matrix liquid crystal display driven by a voltage, while the active matrix organic light emitting diode display requires by the current source to drive an electroluminescent component, the luminance of the electroluminescent component is proportional to the current through the variation of the amount of current flowing through the electroluminescent component with respect to the luminance uniformity of the active matrix organic light emitting diode display has a negative impact, therefore, the quality of the pixel drive circuit is very important for the quality of the active matrix organic light emitting diode display.

[0004] 图1显示一传统有源矩阵式有机发光二极管显示器的像素驱动电路10,像素驱动电路10具有晶体管Mx与My、电致发光组件EL与电容Cst。 [0004] FIG. 1 shows a conventional active matrix organic light emitting diode display pixel drive circuit 10, pixel drive circuit 10 includes a transistor Mx and My, electroluminescence device EL and the capacitor Cst. 当信号kan导通一晶体管Mx 时,图中以Vdata所示的数据会被加载一P型晶体管My的栅极,并储存于电容Cst内,因此,会有一固定的电流驱动电致发光组件EL发光,在典型的有源矩阵式有机发光二极管显示器中,电流源通常是一个P型薄膜晶体管(如图1中的My),栅极被一数据信号Vdata控制,且漏极与源极分别连接至电源Vdd与电致发光组件EL,如图1所示,电致发光组件EL的亮度相对于Vdata有以下的关系: When a signal is turned kan transistor Mx, FIG Vdata to the data will be shown in a loading gate of the P-type transistor My and stored in the capacitor Cst, and therefore, there will be a constant current driving electroluminescence device EL emission, in typical active matrix organic light emitting diode display, the current source is usually a P-type thin film transistor (in FIG. 1 My), a control gate is the data signal Vdata, source and drain are respectively connected to the to the power supply Vdd EL electroluminescent components, as shown in FIG electrically EL element EL luminance with respect to 1 Vdata has the following relationship:

[0005]亮度0^ 电流(Vdd-Vdata-Vth)2 [0005] Brightness 0 ^ current (Vdd-Vdata-Vth) 2

[0006] 其中,Vth为晶体管My的阈值电压,Vdd为电源供应电压。 [0006] wherein, Vth is the threshold voltage of the transistor My, Vdd is the power supply voltage. 由于在低温多晶硅工艺中,低温多晶硅薄膜晶体管通常会有阈值电压Vth的变异,若阈值电压Vth没有经过适当的补偿,有源矩阵式有机发光二极管显示器便会有不均勻的现象产生,再者,在电源线上的压降也会产生亮度不均勻的问题,为了解决这一问题,建构一可补偿阈值电压Vth与电源供应Vdd的像素电路便成了改善画质的重要课题。 Since the low-temperature polycrystalline silicon process, there is usually a low temperature polysilicon thin film transistor variation of the threshold voltage Vth, the threshold voltage Vth if not properly compensated, the active matrix organic light emitting diode display will be non-uniform phenomenon, furthermore, voltage drop on the power line also produce uneven brightness problem, to solve this problem, a construction of an important subject pixel circuit may compensate for a threshold voltage Vth of the power supply Vdd became improvement in picture quality.

发明内容 SUMMARY

[0007] 有鉴于此,本发明提供一种像素驱动电路。 [0007] Accordingly, the present invention provides a pixel driving circuit. 像素驱动电路包括一储存电容、一晶体管、一转移电路、一驱动组件和一开关电路。 Pixel driving circuit includes a storage capacitor, a transistor, a transfer circuit, a drive assembly and a switching circuit. 储存电容具有第一节点与第二节点。 A storage capacitor having a first node and a second node. 晶体管具有接收放电信号的一栅极并耦接于第一节点和第二节点之间,其中放电信号在第一放电时段和第二放电时段使晶体管导通使得储存电容放电。 A transistor having a gate receiving the discharge signal and coupled between the first node and the second node, wherein the discharge signal in a first period and a second discharge period of the discharge transistor is turned on so that the storage capacitor is discharged. 转移电路耦接储存电容的第一节点并且将一数据信号或一参考信号传送至储存电容的第一节点。 A transfer circuit coupled to the storage capacitor and the first node transmits a data signal or a reference signal to the storage node capacitance. 驱动组件具有耦接第一电平的第一端点、耦接第二节点的第二端点以及具有输出一驱动电流的第三端点。 Drive assembly having a first node coupled to a first level, the second node coupled to a second end and having a third output terminal of a driving current. 开关电路耦接驱动组件、第一显示组件和第二显示组件并可在第一数据加载时段和第二数据加载时段使驱动组件成二极管耦接,开关电路也可使驱动电流在第一发光时段和第二发光时段分别输出至第一显示组件和第二显示组件。 The switching circuit is coupled to the drive assembly, the first display assembly and the second display assembly and loading data loading period and a second period in the first data into the drive assembly is coupled to the diode, the switch circuit also allows the first light emitting period of the driving current and a second light emission period are output to the first display assembly and the second display assembly.

[0008] 根据本发明的一个方面,提供一种影像显示系统,包括一种像素驱动电路。 [0008] In accordance with one aspect of the invention, there is provided a system for displaying images comprising a pixel driving circuit. 该像素驱动电路包括:一储存电容,具有一第一节点与一第二节点;一晶体管,具有耦接至一放电信号的一栅极、耦接于上述第一节点的一漏极、和与上述第二节点耦接的一源极,其中上述放电信号在一第一时段使上述晶体管导通以使得上述储存电容放电;一转移电路,耦接至上述储存电容的第一节点,上述转移电路将一数据信号和一参考信号的一者传送至上述储存电容的第一节点;一驱动组件,具有耦接至一第一电平的一第一端点,耦接至上述第二节点的一第二端点,并具有输出一驱动电流的一第三端点;以及一开关电路,耦接于上述驱动组件与一显示组件之间,并可在一第二时段内使上述驱动组件成二极管耦接,并使得上述驱动电流可在一第三时段内输出至上述显示组件。 The pixel driving circuit comprises: a storage capacitor having a first node and a second node; a transistor having a gate coupled to a discharge signal, and a drain coupled to said first node, and a the second node is coupled to a source electrode, wherein said discharge signal in a first period of time so that the transistor is turned on to discharge the storage capacitor; a transfer circuit coupled to the first node of the storage capacitor, the shift circuit the one of a data signal and a reference signal is transmitted to the first node of the storage capacitor; a drive assembly, having a first terminal coupled to a first level, coupled to the second node a a second end, and outputs a driving current having a third terminal; and a switch circuit coupled between the drive assembly and a display assembly, and said drive assembly in a second diode coupled period , and so that the driving current can be output to the display assembly in a third period.

[0009] 根据本发明的另一个方面,提供一种影像显示系统,包括一种像素驱动电路。 [0009] According to another aspect of the invention, there is provided a system for displaying images comprising a pixel driving circuit. 该像素驱动电路包括:一储存电容,具有一第一节点与一第二节点;一晶体管,具有接收一放电信号的一栅极、耦接于上述第一节点的一漏极、和与上述第二节点耦接的一源极,其中上述放电信号在一第一放电时段和一第二放电时段使上述晶体管导通以使得上述储存电容放电;一转移电路,耦接至上述储存电容的第一节点,上述转移电路将一数据信号和一参考信号的一者传送至上述储存电容的第一节点;一驱动组件,具有耦接至一第一电平的一第一端点、耦接至上述第二节点的一第二端点以及具有输出一驱动电流的一第三端点;以及一开关电路,耦接至上述驱动组件、一第一显示组件和一第二显示组件,并在一第一数据加载时段和一第二数据加载时段使上述驱动组件成二极管耦接,并使得上述驱动电流分别在一第一发光时段和一第二发光时段内输 The pixel driving circuit comprises: a storage capacitor having a first node and a second node; a transistor having a gate receiving a discharge signal, and a drain coupled to said first node, and the first and a second node coupled to a source, wherein said discharge signal in a first period and a second discharge period of time so that the discharge transistor is turned on so that the discharge of the storage capacitor; a transfer circuit coupled to the first storage capacitor nodes, one of said transition circuit a data signal and a reference signal is transmitted to the first node of the storage capacitor; a drive assembly, having a first terminal coupled to a first level, coupled to the a second terminal of the second node and a third node having an output of a driving current; and a switch circuit, coupled to the drive assembly, a first display assembly and a second display assembly, and a first data loading period and a second period of time so that the data is loaded into a drive assembly coupled to the diode, and the driving current so that a first light emission period and light emission period within a second input, respectively, 至上述第一显示组件和上述第二显示组件。 To the first display assembly and the second display assembly.

[0010] 附图说明 [0010] BRIEF DESCRIPTION OF DRAWINGS

[0011] 图1显示一传统有源矩阵式有机发光二极管显示器的像素驱动电路。 [0011] Figure 1 shows a pixel circuit of a conventional active matrix driving organic light emitting diode display.

[0012] 图2显示依据本发明一实施例所披露一像素驱动电路图。 [0012] FIG. 2 shows a circuit diagram of a pixel drive according to a disclosed embodiment of the present invention.

[0013] 图3显示像素驱动电路的发光信号、放电信号、扫描线信号、以及水平时钟信号的时序图。 [0013] The light emission signal of a pixel driving circuit show in FIG. 3, the discharge signal, the scanning signal lines, and a timing chart of the horizontal clock signal.

[0014] 图4显示面板通过水平时钟信号分别将数据加载于红、绿和蓝三信号线。 [0014] Figure 4 shows the data loaded by the panels are horizontal clock signal to red, green and blue signal lines.

[0015] 图5显示依据本发明另一实施例所披露一像素驱动电路图。 [0015] FIG. 5 shows another embodiment according to the present invention is a circuit diagram of a pixel driving disclosed.

[0016] 图6显示像素驱动电路的发光信号、放电信号、扫描线信号、反扫描线信号、以及水平时钟信号的时序图。 [0016] The timing chart of light emission signal of a pixel driving circuit of FIG. 6 shows, the discharge signal, the scanning signal lines, inverse scan line signals, and a horizontal clock signal.

[0017] 图7显示根据本发明的另一实施例的影像显示系统。 [0017] Figure 7 shows an image display system according to another embodiment of the present invention.

[0018] 图8显示依据本发明一实施例所披露一像素驱动电路。 [0018] Figure 8 shows a pixel driving circuit according to an embodiment of the disclosed embodiment of the present invention.

[0019] 图9显示依据本发明一实施例所披露的帧信号、放电信号、扫描线信号以及发光信号的时序图。 [0019] Figure 9 shows the frame signal according to an embodiment of the disclosed embodiment of the present invention, the discharge signal, a timing diagram of the scan line signal and emission signal.

[0020] 图10显示根据本发明的另一实施例的影像显示系统。 [0020] FIG. 10 shows the image display system according to another embodiment of the present invention.

[0021] 附图符号说明 [0021] BRIEF DESCRIPTION OF REFERENCE NUMERALS

[0022] Vdd〜电源 [0022] Vdd~ power

[0023] Cst〜储存电容 [0023] Cst~ storage capacitor

5[0024] Scan〜扫描线信号 5 [0024] Scan~ scan line signals

[0025] Scanx〜反扫描线信号 [0025] Scanx~ inverse scan line signals

[0026] Vdata〜数据信号 [0026] Vdata~ data signal

[0027] PVdd〜电源供应 [0027] PVdd~ power supply

[0028] Vref〜参考信号 [0028] Vref~ reference signal

[0029] Vth〜阈值电压 [0029] Vth~ threshold voltage

[0030] Discharge〜放电信号 [0030] Discharge~ discharge signal

[0031] Emi、Emil〜发光信号 [0031] Emi, Emil~ emission signal

[0032] 210、510、810 〜转移电路 [0032] ~ 210,510,810 transfer circuit

[0033] 220、520、820 〜开关电路 [0033] 220,520,820 through switching circuit

[0034] R、G、B〜信号线 [0034] R, G, B~ signal line

[0035] SW1、SW2、SW3 〜开关 [0035] SW1, SW2, SW3 ~ switch

[0036] 10、200、500〜像素驱动电路 [0036] The pixel driving circuit 10,200,500~

[0037] CKH1、CKH2、CKH 3〜水平时钟信号 [0037] CKH1, CKH2, CKH 3~ horizontal clock signal

[0038] Ml、M2、M3、M4、M5、M6、M7、Mx、My 〜晶体管 [0038] Ml, M2, M3, M4, M5, M6, M7, Mx, My ~ transistor

[0039] rowl、row2、roWn 〜列1、列2、列η [0039] rowl, row2, roWn ~ column 1, row 2, column η

[0040] 400〜显示面板 [0040] The display panel 400~

[0041] 500〜电源供应器 [0041] Power Supply 500~

[0042] 600〜电子装置 [0042] The electronic device 600~

[0043] 850〜驱动电路 [0043] The driving circuit 850~

[0044] EL、ELl、EL2 〜显示组件 [0044] EL, ELl, EL2 ~ display assembly

[0045] Emit_l、Emit_2 〜发光信号 [0045] Emit_l, Emit_2 ~ emission signal

[0046] FRAME〜帧信号 [0046] FRAME~ frame signal

[0047] Si、S4〜放电时期 [0047] Si, S4~ discharge period

[0048] S2、S5〜数据加载时期 [0048] S2, S5~ data loading period

[0049] S3、S6〜发光时期 [0049] S3, S6~ emission period

[0050] SF〜帧时期 [0050] SF~ frame period

[0051] SF1、SF2〜次帧时期 [0051] SF1, SF2~ sub frame period

具体实施方式 detailed description

[0052] 为让本发明的上述和其它目的、特征、和优点能更明显易懂,下文特举出较佳实施例,并结合附图详细说明如下: [0052] In order to make the aforementioned and other objects, features, and advantages can be more fully understood by referring include preferred embodiments, in conjunction with the accompanying drawings and the following detailed description:

[0053] 图2显示依据本发明第一实施例所披露一像素驱动电路200,像素驱动电路200具有补偿阈值电压、补偿电源供应,与电源供应PVdd的电压可不受限于扫描线信的电压的特征。 [0053] FIG. 2 shows a voltage according to a first embodiment of the present invention to disclose a pixel driving circuit 200, the pixel driving circuit 200 has a threshold voltage compensation, compensation for power supply, and the power supply voltage may not be limited PVdd scan line of the letter feature. 像素驱动电路200包括一储存电容Cst、一转移电路210、一驱动晶体管M5、晶体管M6以及一开关电路220。 The pixel driving circuit 200 includes a storage capacitor Cst, a transferring circuit 210, a driving transistor M5, transistor M6 and a switch circuit 220.

[0054] 转移电路210耦接至储存电容Cst的第一节点A,并将一数据信号Vdata或一参考信号Vref转移至储存电容的第一节点A,参考信号Vref可以是一固定电压信号。 [0054] The transfer circuit 210 is coupled to the storage capacitor Cst first node A, and transfer a data signal Vdata or a reference signal Vref to the first node of the storage capacitor A, the reference signal Vref may be a fixed voltage signal. 驱动晶体管M5可为P型金属氧化物半导体(P-Channel MetalOxide kmiconductor,PM0S),驱动晶体管M5的源极耦接至第一电平PVdd,驱动晶体管M5的栅极耦接至储存电容Cst的第二节点B,更明确地说,第一电平为电源供应电压PVdd。 The driving transistor M5 may be a P-type metal oxide semiconductor (P-Channel MetalOxide kmiconductor, PM0S), the driving source of transistor M5 is coupled to a first level PVdd, the gate coupled to the driving transistor M5 is coupled to the first storage capacitor Cst two node B, more specifically, a first level of power supply voltage PVdd. 开关电路220耦接至驱动晶体管M5的漏极,开关电路220可被用以使驱动晶体管M5成二极管连接(diode-cormected)。 Switching circuit 220 is coupled to the drain of the driving transistor M5, the switch circuit 220 may be used to the driving transistor M5 is connected to a diode (diode-cormected). 显示组件EL耦接至开关电路220。 EL display assembly 220 is coupled to the switching circuit. 显示组件EL可以是一电致发光组件,此外,显示组件EL的阴极耦接至一第二电平,更明确地说,第二电平可为一接地电平VSS或者是接地电平。 EL display component may be an electroluminescence device, in addition, the cathode of EL display assembly coupled to a second level, more specifically, the second level may be a ground level or the ground level VSS.

[0055] 转移电路210包括第一晶体管Ml与第二晶体管M2,如图2所示。 [0055] The transfer circuit 210 includes a first transistor Ml and the second transistor M2, as shown in FIG. 在图2中,第一晶体管Ml与第二晶体管M2分别为N型金属氧化物半导体(N-Charmel Metal Oxide Semiconductor,NM0S)晶体管与PMOS晶体管。 In FIG. 2, the first transistor Ml and the second transistor M2 is an N-type metal-oxide semiconductor (N-Charmel Metal Oxide Semiconductor, NM0S) transistor and a PMOS transistor. 第一晶体管Ml的漏极接收数据信号Vdata, 第一晶体管Ml的栅极与源极分别连接至一扫描线信号kan以及储存电容Cst的第一节点A。 Receiving the data signal Vdata drain electrode of the first transistor Ml, the gate and the source electrode of the first transistor Ml is connected to a scan line and a signal kan first node A. The storage capacitor Cst 第二晶体管M2的源极接收一参考信号Vref,第二晶体管M2的栅极与漏极分别连接至一扫描线信号kan以及储存电容Cst的第一节点A。 The source of the second transistor M2 receives a reference signal Vref, the gate and drain of the second transistor M2 are respectively connected to the signal kan a scan line and a first node A. The storage capacitor Cst 更明确地说,第一晶体管Ml与第二晶体管M2可为多晶硅薄膜晶体管,可提供较高的电流驱动能力。 More specifically, the first transistor Ml and the second transistor M2 may be a polycrystalline silicon thin film transistors, providing higher current driving capability.

[0056] 当扫描线信号kan被拉到高电平时,转移电路210将一数据信号Vdata移转到储存电容Cst的第一节点A ;当扫描线信号kan被拉到低电平时,转移电路210将参考信号Vref移转至储存电容Cst的该第一节点A。 [0056] When the scanning signal lines are pulled high kan, a transfer circuit 210 to transfer the data signal Vdata to the first node of the storage capacitor Cst A; kan signal when the scan line is pulled low, the transfer circuit 210 the reference signal Vref transferred to the first node A. the storage capacitor Cst

[0057] 开关电路220包括第三晶体管M3与第四晶体管M4,如图2所示,第三晶体管M3可为PM0S,第四晶体管M4可为NMOS晶体管,第三晶体管M3的漏极连接至显示组件EL的阳极,晶体管M3的栅极与源极分别连接至一发光信号Emi以及驱动晶体管M5,第四晶体管M4 具有一源极耦接至驱动晶体管M5与第三晶体管M3,第四晶体管M4的漏极耦接至储存电容Cst的第二节点B、一晶体管M6的源极以及驱动晶体管M5的栅极,第四晶体管M4的栅极连接至一扫描线信号义皿。 [0057] The switching circuit 220 includes a third transistor M3 and the fourth transistor M4, as shown, the third transistor M3 may be PM0S 2, the fourth transistor M4 may be an NMOS transistor, the drain of the third transistor M3 is connected to the display EL anode assembly, the transistor M3 gate and source are connected to a lighting signal Emi and a driving transistor M5, the fourth transistor M4 having a source coupled to the driving transistor M5 and the third transistor M3, the fourth transistor M4 drain coupled to the storage capacitor Cst second point B, the source of transistor M6 and a gate of the driving transistor M5, the gate of the fourth transistor M4 is coupled to a scan line signal Yi dish. 较佳而言,第三晶体管M3与第四晶体管M4为多晶硅薄膜晶体管, 可提供较高的电流驱动能力。 Preferably, the third transistor M3 and the fourth transistor M4 is a polysilicon thin film transistor, provides high current drive capability.

[0058] 当扫描线信号kan被拉至高电平时,开关电路220内的第四晶体管M4会使得驱动晶体管M5成为一二极管连接(diode-cormected)的晶体管。 [0058] When the scanning signal line is pulled to a high level kan, the fourth transistor M4 within the switching circuit 220 so that the driving transistor M5 may be a diode-connected transistor (diode-cormected) a.

[0059] 晶体管M6的漏极耦接至储存电容Cst的第一节点A,晶体管M6的栅极耦接至一放电信号Discharge,晶体管M6的源极耦接至储存电容Cst的第二节点B、第四晶体管M4的漏极和驱动晶体管M5的栅极。 [0059] The drain of the transistor M6 is coupled to the storage capacitor Cst first node A, the gate of transistor M6 is coupled to a discharge signal Discharge, source of transistor M6 is coupled to the storage capacitor Cst second points B, the gate and drain of the driving transistor M5 fourth transistor M4.

[0060] 图3显示图2所示的像素驱动电路200的发光信号Emi、放电信号Discharge、扫描线信号kan、以及水平时钟信号CKHl、CKH2和CKH3的时序图。 [0060] The pixel driving circuit shown in FIG. 2 FIG. 3 shows the emission signal Emi 200, discharge signal Discharge, Kan scan line signal, a clock signal and a horizontal CKHl, CKH2 and CKH3 to a timing chart. 接着像素驱动电路的前一发光模式,当放电信号Discharge被拉至高电平且发光信号Emi维持在高电平时,图2内的像素驱动电路200会操作于一放电模式Sl,在此放电模式中,晶体管M6会导通,一高电平的参考信号Vref会输入到储存电容Cst的第一节点A和第二节点B,储存在储存电容Cst 内的电荷便可在放电模式中释放,储存电容Cst的放电可确保在后续步骤中的正常操作。 Then the pixel drive circuit before a lighting mode, when the discharge signal Discharge is pulled high and the emission signal is maintained at a high level Emi, the pixel driving circuit 200 in Figure 2 may operate in a discharge mode Sl is, in this discharge mode , transistor M6 will be turned on, a high level of the reference signal Vref will be input to the storage capacitor Cst first node a and the second point B, the stored charge in the storage capacitor Cst can be released in the discharge mode, the storage capacitor Cst ensures the normal operation of a discharge in the subsequent steps.

[0061] 接续储存电容Cst的放电之后,扫描线信号^^11被拉至高电平,然后像素驱动电路200会进入数据加载模式S2,当扫描线信被拉至高电平时,第一晶体管Ml与第四晶体管M4导通而第二晶体管M2与晶体管M6关闭,由于第一晶体管Ml与第四晶体管M4导通,储存电容Cst的第一节点A的电压等于数据信号Vdata的电压,且储存电容Cst的第二节点B的电压等于PVdd-Vth,其中,Vth为驱动晶体管M5的阈值电压,因此储存在储存电容的跨压为Vdata-(PVdd-Vth)。 After the [0061] discharge the storage capacitor Cst connection, the scanning signal line 11 is pulled high ^^, and then the pixel driving circuit 200 enters a data loading mode S2, when the scan line is pulled to a high level channel, and a first transistor Ml the fourth transistor M4 is turned on and the second transistor M2 and the transistor M6 is turned off, since the voltage of the first node a of the first transistor Ml and M4 is turned on, the storage capacitor Cst equals a voltage of the fourth transistor of the data signal Vdata, and the storage capacitor Cst voltage of the second node B is equal to PVdd-Vth, wherein, the threshold voltage Vth of the driving transistor M5, thus stored in the pressure across the Vdata- (PVdd-Vth) of the storage capacitor. [0062] 当扫描线信号kan被拉至低电平时,数据加载模式S2结束。 [0062] When the scanning signal line kan pulled low, ending the data loading mode S2. 当发光信号Emi 被拉至低电平时,像素驱动电路200会进入发光模式S3。 When the lighting signal Emi is pulled low, the pixel driving circuit enters emission mode S3 200. 并且因为扫描线信 Since the scanning lines and the letter

在低电平,第二晶体管M2导通,储存电容Cst的第一节点A的电压为参考电压Vref, 由于储存电容的跨压无法瞬间改变,因此储存电容Cst的第二节点B的电压也就变为Vref-[Vdata- (PVdd-Vth)],而流经显示组件的电流正比于(Vsg-Vth)2,也就是正比于(Vdata-Vref)2,因此流经显示组件EL的电流与驱动晶体管M5的阈值电压Vth以及驱动晶体管M5的电源供应PVdd无关,上述像素驱动电路的操作会一再重复,以控制像素的发光。 At a low level, the ON voltage of the second transistor M2 of the first node A of the storage capacitor Cst reference voltage Vref, since the voltage across the storage capacitor can not change instantaneously, and therefore the voltage of the second node B of the storage capacitor Cst also becomes Vref- [Vdata- (PVdd-Vth)], and the current flowing through the display assembly is proportional to (Vsg-Vth) 2, i.e. proportional to (Vdata-Vref) 2, and therefore the current flowing through the display assembly EL and the driving transistor M5 and the threshold voltage Vth of the driving transistor M5 PVdd independent power supply, the operation of the pixel driving circuit repeated to control the pixel.

[0063] 图4显示有源矩阵式有机发光二极管显示面板通过水平时钟信号CKHl、CKH2和CKH 3分别将数据加载红R、绿G和蓝B三信号线。 [0063] Figure 4 shows an active matrix organic light emitting diode display panel by a horizontal clock signal CKHl, CKH2 CKH 3, respectively, and load data of red R, green G and blue B three signal lines. 当扫描线信分别在列1、列2或列n(rowl, row2,…rown)高电平时,也就是在数据加载模式时,S2通过水平时钟信号CKH1、 CKH2和CKH3分别依序将开关SWl、SW2和SW3导通,并依序将数据载入红R、绿G和蓝B三信号线上。 When channel scanning lines in columns 1, 2 row or column n (rowl, row2, ... rown) high, i.e. when a data loading mode, S2 through horizontal clock signals CKH1, CKH2 and CKH3 are sequentially switches SWl , SW2 and SW3 is turned on, and sequentially loading data of red R, green G and blue B three signal lines.

[0064] 图5显示依据本发明另一实施例所披露一像素驱动电路500,像素驱动电路500也具有补偿阈值电压、补偿电源供应,与电源供应PVdd的电压可不受限于扫描线信的电压的特征。 [0064] FIG. 5 shows the voltage to another embodiment of the invention as disclosed in the pixel driving circuit 500, the pixel driving circuit 500 also has a threshold voltage compensation, the compensation power supply, and the power supply voltage PVdd scanning line may not be limited based on the letter Characteristics. 像素驱动电路500与像素驱动电路200类似。 Pixel driving circuit 500 is similar to the pixel driving circuit 200. 图2像素驱动电路200和图5 像素驱动电路500的不同处在于,图5的晶体管M7和晶体管M8为NMOS晶体管,而图2的第二晶体管M2和第三晶体管M3为PMOS晶体管,并且图5的晶体管M7的栅极耦接至一反扫描线信号kanX。 Different from the pixel driving circuit 200 in FIG. 2 and FIG. 5 in that the pixel driving circuit 500, transistor M7 and the transistor M8 is an NMOS transistor in FIG. 5 and FIG second transistor M2 and the third transistor M3 is a PMOS transistor 2, and FIG. 5 coupled to the gate of transistor M7 is coupled to an inverse scan line signal kanX. 反扫描线信号kanX是扫描线信号kan的反相信号。 Inverse scanning signal line is a scanning line signal kan kanX inverted signal.

[0065] 图6显示图5所示的像素驱动电路500的发光信号Emi 1、放电信号Discharge、扫描线信号kan、反扫描线信号kanX、以及水平时钟信号CKH1、CKH2和CKH3的时序图。 The pixel shown in [0065] FIG. 6 shows light emission driving signals 5 1 Emi circuit 500, discharge signal Discharge, Kan scan line signals, inverse scan line signals kanX, and a horizontal clock signals CKH1, CKH2 and CKH3 to a timing chart. 接着像素驱动电路的前一发光模式,当放电信号Discharge被拉至高电平且发光信号Emil维持在低电平时,图5内的像素驱动电路500会操作于一放电模式Si,在此放电模式中,晶体管M6会导通,一高电平的参考信号Vref会输入到储存电容Cst的第一节点A和第二节点B,储存在储存电容Cst内的电荷便可在放电模式中释放,储存电容Cst的放电可确保在后续步骤中的正常操作。 Then the pixel drive circuit before a lighting mode, when the discharge signal Discharge is pulled high and the emission signal is maintained at the low level Emil, the pixel driving circuit 500 will operate in a discharge mode in FIG. 5 Si, In this discharge mode, , transistor M6 will be turned on, a high level of the reference signal Vref will be input to the storage capacitor Cst first node a and the second point B, the stored charge in the storage capacitor Cst can be released in the discharge mode, the storage capacitor Cst ensures the normal operation of a discharge in the subsequent steps.

[0066] 图7显示根据本发明的另一实施例的影像显示系统,在本实施例中,影像显示系统可包括显示面板400或电子装置600,如图7所示显示面板400包括上述图2的像素驱动电路2 00,显示面板4 00可以是电子装置的一部分(例如:电子装置600),一般电子装置600包括显示面板400和一电源供应器500,甚者,电源供应器500耦接至显示面板400以提供电能至显示面板400,电子装置可以是:手机、数字相机、个人数字助理、笔记型计算机、 桌上型计算机、电视、或便携式DVD放影机。 [0066] Figure 7 shows an image display system according to another embodiment of the present invention, in the present embodiment, the image display system may include a display panel 400 or electronic device 600, as shown in FIG 7 includes a display panel 400 in FIG. 2 the pixel driving circuit 200, a display panel 400 may be part of an electronic device (for example: an electronic device 600), the electronic device 600 generally includes a display panel 400 and a power supply 500, worse, the power supply 500 coupled to The display panel 400 to provide electrical power to the display panel 400, the electronic device may be: cell phones, digital cameras, personal digital assistants, notebook computers, desktop computer, television, or portable DVD players.

[0067] 图5的工作原理也与图2的工作原理大致相同。 Works [0067] FIG. 5 is also substantially the same as the operation principle of FIG. 因此,流经图5的显示组件EL的电流正比于(Vsg-Vth)2,也正比于(Vdata-Vref)2,因此流经图5的显示组件EL的电流与驱动晶体管M5的阈值电压Vth以及驱动晶体管M5的电源供应PVdd无关,上述像素驱动电路的操作会一再重复,以控制像素的发光。 Thus, current flows through the EL display assembly in FIG. 5 is proportional to (Vsg-Vth) 2, also proportional to (Vdata-Vref) 2, so that the current of the driving transistor M5 EL display assembly in FIG. 5 flowing through the threshold voltage Vth and the driving transistor M5 regardless of the PVdd power supply, the operation of the pixel driving circuit will be repeated, in order to control the pixel.

[0068] 本发明实施例的像素驱动电路200和500与驱动晶体管M5的阈值电压Vth和电源供应PVdd无关,并且电源供应PVdd与扫描线信号kan的电压电平是互无关连的,因此扫描线信号kan的电压范围值并不会受到电源供应PVdd电压范围值的限制,反之亦然。 [0068] pixels embodiment of the present invention, the drive circuits 200 and 500 of the driving transistor M5 threshold voltage Vth and the power supply PVdd independent, and the power supply PVdd scan line signal kan voltage levels are mutually independent of that, the scan line kan voltage value of the signal range and is not limited by the power supply voltage PVdd range of values, and vice versa.

[0069] 由于显示面板的像素越来越多,并且为了使显示面板颜色色域较广,工程师一般会在显示面板内放入更多不同颜色的发光单元以增加显示面板的像素以及色域。 [0069] Since the display panel more pixels, and the display panel for wide color gamut, engineers typically will put more different colors of the light emitting units in order to increase the display panel and the display panel pixel color gamut. 传统发光单元包括一电致发光组件和相对应的驱动电路,由于驱动电路无法发光,因此驱动电路所占的面积要小,使发光单元的孔径比(Apertureratio)能较大,因此如何在固定尺寸的显示面板中放入较少驱动电路和较多电致发光组件是本发明的重点。 A conventional light-emitting unit comprises an electroluminescent assembly and the driving circuit corresponding to the drive circuit can not emit light, the area occupied by the drive circuit to be small, so that the aperture ratio of the light emitting unit (Apertureratio) can be large, and therefore how fixed size display panel and a driving circuit into smaller more electroluminescent assembly is the focus of the present invention.

[0070] 图8显示依据本发明一实施例所披露一像素驱动电路8 00,像素驱动电路800为5T1C+2T的电路设计并具有补偿阈值电压和补偿电源供应的能力,另外电源供应PVdd的电压可不受限于扫描线信号kan的电压。 [0070] Figure 8 shows the disclosed according to an embodiment of the present invention a pixel driving circuit 800, the pixel driving circuit 800 is designed and has a compensating threshold voltage and capacity compensating power supply the circuit 5T1C + 2T, the additional voltage power supply PVdd of It can not be limited to the voltage of the scanning line signal kan. 像素驱动电路800包括储存电容Cst、转移电路810、驱动晶体管M5、晶体管M6、开关电路820以及显示组件ELl和EL2。 The pixel driving circuit includes a storage capacitor Cst 800, the transfer circuit 810, the driving transistor M5, the transistor M6, the switch circuit 820 and a display assembly ELl and EL2. 显示组件ELl和EL2可以是电致发光组件并共享驱动电路850以减少驱动电路所占像素驱动电路200的面积,因此显示组件ELl和EL2在次帧时期SFl和SF2分别使用驱动电路850。 ELl and EL2 may display assembly electroluminescent component and a shared drive circuit 850 to reduce the area occupied by the pixel drive circuit of the driving circuit 200, display component so ELl and EL2 driver circuit 850 in the sub-frame periods SFl and SF2, respectively.

[0071] 转移电路810耦接至储存电容Cst的第一节点A,并将数据信号Vdata或参考信号Vref转移至储存电容的第一节点A上,参考信号Vref可以是一固定电压信号。 [0071] The transfer circuit 810 is coupled to the first node of the storage capacitor Cst A, or the data signal Vdata and the reference signal Vref on the storage capacitor is transferred to the first node A, the reference signal Vref may be a fixed voltage signal. 驱动晶体管M5可为P型金属氧化物半导体(P-Channel MetalOxide kmiconductor,PM0S),驱动晶体管M7的源极耦接至电源供应PVdd,电源供应PVdd为一直流电。 The driving transistor M5 may be a P-type metal oxide semiconductor (P-Channel MetalOxide kmiconductor, PM0S), the driving source of the transistor M7 is coupled to the power supply PVdd, as a direct current power supply PVdd. 驱动晶体管M5的栅极耦接至储存电容Cst的第二节点B。 The gate of the driving transistor M5 is coupled to the second node of the storage capacitor Cst B. 开关电路820耦接至驱动晶体管M5的漏极并可以使驱动晶体管M5成二极管连接(diode-cormected)。 Switching circuit 820 is coupled to the drain of the driving transistor M5 and the driving transistor M5 may be connected to a diode (diode-cormected). 显示组件ELl和EL2分别耦接至开关电路820的晶体管M3与晶体管M7。 Display assembly ELl and EL2 are respectively coupled to the transistor M3 and the transistor M7 of the switch circuit 820. 此外,显示组件ELl和EL2的阴极耦接至一第二电平,第二电平可以是一接地电平或一固定电压VSS。 Further, display component ELl and EL2 cathode coupled to a second level, a second level may be a fixed level or a ground voltage VSS.

[0072] 转移电路810包括第一晶体管Ml与第二晶体管M2。 [0072] The transfer circuit 810 includes a first transistor Ml and the second transistor M2. 在图2中,第一晶体管Ml与第二晶体管M2分别为N型金属氧化物半导体(N-Channel MetalOxide Semiconductor, NM0S)晶体管与PMOS晶体管。 In FIG. 2, the first transistor Ml and the second transistor M2 is an N-type metal-oxide semiconductor (N-Channel MetalOxide Semiconductor, NM0S) transistor and a PMOS transistor. 第一晶体管Ml的漏极和栅极分别接收数据信号Vdata和扫描线信号义皿,第一晶体管Ml的源极耦接储存电容Cst的第一节点A。 Drain and gate of the first transistor Ml respectively receive the data signal Vdata and the pan scan line signal Yi, a source electrode coupled to the first transistor Ml is connected to the first node A. The storage capacitor Cst 第二晶体管M2的源极和栅极分别接收参考信号Vref和扫描线信号kan,第二晶体管M2的漏极也耦接储存电容Cst的第一节点A。 The source and the gate of the second transistor M2 receives the reference signal Vref and the scanning signal lines kan, the drain of the second transistor M2 is also coupled to the storage capacitor Cst node A. 另外,第一晶体管Ml与第二晶体管M2可为多晶硅薄膜晶体管以提供较高的电流驱动能力。 Further, the first transistor Ml and the second transistor M2 may be to provide a higher current drive capability of the polycrystalline silicon thin film transistor.

[0073] 当扫描线信号kan被拉到高电平时,转移电路810将数据信号Vdata移转到储存电容Cst的第一节点A,当扫描线信号kan被拉到低电平时,转移电路810将参考信号Vref 移转至储存电容Cs t的该第一节点A。 [0073] When the scanning signal lines are pulled high kan, the transfer circuit 810 transfer the data signal Vdata to the storage capacitor Cst node A, when the scanning signal line kan is pulled low, the transfer circuit 810 transferring the reference signal Vref to the first node A. the storage capacitor Cs t

[0074] 开关电路820包括晶体管M3、晶体管M4和晶体管M7,其中晶体管M3和晶体管M7 可为PMOS或是NM0S,晶体管M4可为NMOS晶体管,晶体管M3和晶体管M7的漏极分别连接至显示组件ELl和EL2的阳极,晶体管M3的栅极接收发光信号Emit_l,晶体管M7的栅极接收发光信号Emit_2,晶体管M3和M7的源极皆耦接驱动晶体管M5,晶体管M4具有一源极耦接至驱动晶体管M5、晶体管M3和晶体管M7,晶体管M4的漏极耦接至储存电容Cs t的第二节点B、晶体管M6的源极以及驱动晶体管M5的栅极,晶体管M4的栅极接收扫描线信号Scan。 [0074] The switching circuit 820 includes a transistor M3, and transistor M7 transistor M4, wherein the transistors M3 and M7 may be a PMOS transistor or NM0S, transistor M4 may be an NMOS transistor, the drain of transistor M3 and transistor M7 are connected to the display assembly ELl EL2 and the anode, and a gate receiving a lighting signal Emit_l transistor M3, a gate receiving the light emission signal Emit_2 transistor M7, the transistor M3 and the source electrode of M7 are coupled to the driving transistor M5, the transistor M4 having a source coupled to the driving transistor M5, transistor M3 and the transistor M7, the drain of transistor M4 is coupled to the storage capacitor Cs t of the second point B, the source of transistor M6 and the gate driver transistor M5, the gate line receives the scan signal scan transistor M4. 根据本发明一实施例,晶体管M3与晶体管M7为多晶硅薄膜晶体管以提供较高的电流驱动能力。 According to an embodiment of the present invention, the transistors M3 and transistor M7 polysilicon thin film transistor to provide a high current drive capability. 当扫描线信被拉至高电平时,开关电路820内的晶体管M4会使得驱动晶体管M5成为二极管连接(diode-cormected)的晶体管,也就是驱动晶体管M7栅极和漏极短路,驱动晶体管M5可以看成是一个二极管。 When channel scanning line is pulled high, transistor M4 in the switch circuit 820 so that the driving transistor M5 may be diode-connected transistor (diode-cormected), that is, the driving transistor M7 and the gate-drain short, driving transistor M5 may see to be a diode.

[0075] 晶体管M6的漏极耦接至储存电容Cst的第一节点A,晶体管M6的栅极接收一放电信号Discharge,晶体管M6的源极耦接至储存电容Cst的第二节点B、晶体管M4的漏极和驱动晶体管M5的栅极。 [0075] The drain of the transistor M6 is coupled to the storage capacitor Cst is coupled to a first node A, the gate of transistor M6 receives a discharge signal Discharge, source of transistor M6 is coupled to the storage capacitor Cst second point B, the transistor M4 the gate and drain of the driving transistor M5.

[0076] 图9显示依据本发明一实施例所披露的帧信号FRAME、放电信号Discharge、扫描线信号kan以及发光信号Emit_l和Emit_2的时序图。 [0076] Figure 9 shows a frame signal FRAME to an embodiment of the disclosed embodiment of the present invention, the discharge signal Discharge, the scanning signal lines and a timing chart of a light emitting signal kan Emit_l and Emit_2 basis. 像素驱动电路200则根据帧信号FRAME判别出目前是次帧时期SFl或次帧时期SF2,另外一完整帧时期SF包括次帧时期SFl 和SF2。 The pixel driving circuit 200 according to the frame signal FRAME is discriminated current time frame or sub frame periods SFl period SF2, SF further comprising a full frame period of frame time periods SFl and SF2. 在次帧时期SFl时,当放电信号Discharge被拉至高电平且发光信号Emit_l维持在高电压电平时,像素驱动电路200会操作于一放电时期Si,在此放电时期中,晶体管M6会导通,由于扫描线信号kan为低电压电平,参考信号Vref会输入到储存电容Cst的第一节点A和第二节点B,储存在储存电容Cst内的电荷便可在放电时期中释放,储存电容Cst的放电可确保在后续步骤的正常操作。 When sub frame periods SFl, when the discharge signal Discharge signal is pulled high and the light emitting Emit_l maintained at a high voltage level, the pixel driving circuit 200 will operate in a discharge period Si, the discharge in this period, the transistor M6 will be turned on Since kan scan line signal to a low voltage level, the reference signal Vref will be inputted to the first node a of the storage capacitor Cst and the second point B, the charge stored in the storage capacitor Cst can be released in the discharge period, the storage capacitor Cst ensures the normal discharge operation subsequent steps.

[0077] 接续储存电容Cst放电之后,扫描线信号kan被拉至高电压电平,然后像素驱动电路200会进入数据加载时期S2,当扫描线信号kan被拉至高电压电平时,晶体管Ml与晶体管M4导通而晶体管M2与晶体管M6关闭,由于晶体管Ml与晶体管M4导通,储存电容Cst的第一节点A的电压等于数据信号Vdata的电压,且储存电容Cst的第二节点B的电压等于(PVdd-Vth),其中,Vth为驱动晶体管M5的阈值电压,因此此时储存电容的跨压为Vdata-(PVdd-Vth)。 After the [0077] connecting the storage capacitor Cst discharge kan scan line signal is pulled to a high voltage level, then the pixel driving circuit 200 enters the data loading period S2, when the scanning signal line kan pulled to a high voltage level, the transistor Ml and the transistor M4 conducting and transistor M2 and the transistor M6 is turned off, since the voltage of the first node a of the transistors Ml and M4 is turned on, the storage capacitor Cst equals a voltage of the data signal Vdata transistor, and the voltage of the second node B of the storage capacitor Cst equals (the PVdd -Vth), wherein, the threshold voltage Vth of the driving transistor M5, and therefore at this time the voltage across the storage capacitor is Vdata- (PVdd-Vth).

[0078] 当扫描线信号kan被拉至低电压电平时,数据加载时期S2结束。 [0078] When the scanning signal line kan pulled to low voltage level, the end of the data loading period S2. 当发光信号Emit_l被拉至低电压电平时,像素驱动电路200会进入发光时期S3。 When the lighting signal Emit_l pulled to a low voltage level, the pixel driving circuit 200 enters the light emitting period S3. 并且因为扫描线信号kan在低电压电平,晶体管M2导通,储存电容Cst的第一节点A的电压转变为参考电压Vref,由于储存电容的跨压无法瞬间改变,因此储存电容Cst的第二节点B的电压也就变为Vref- [Vdata- (PVdd-Vth)],而流经显示组件ELl和EL2的电流正比于(Vsg-Vth)2,也就是正比于(Vdata-Vref)2,因此在次帧时期SF1,流经显示组件ELl的电流与驱动晶体管M5的阈值电压Vth以及电源供应PVdd无关。 Kan and because the scan line signal at a low voltage level, the transistor M2 is turned on, a voltage transition of the first node A of the storage capacitor Cst reference voltage Vref, since the voltage across the storage capacitor can not change instantaneously, so the second storage capacitor Cst voltage at node B will become Vref- [Vdata- (PVdd-Vth)], and the current flowing through the display assembly ELl and EL2 is proportional to (Vsg-Vth) 2, i.e. proportional to (Vdata-Vref) 2, Therefore, the frame period SF1 times, regardless of the current flowing through the display of the driving transistor M5 assembly ELl threshold voltage Vth of the power supply and PVdd.

[0079] 在次帧时期SF2时,发光信号Emit_l维持高电压电平,放电信号Discharge、扫描线信和发光信号Emit_2重复上述次帧时期SFl的发光程序。 [0079] When sub-frame period SF2, Emit_l emission signal maintains a high voltage level, the discharge signal Discharge, the scanning signal line and the light emitting Emit_2 channel program repeats emission of said sub-frame periods SFl. 当放电信号Discharge 被拉至高电压电平且发光信号Emit_2维持在高电压电平时,图8内的像素驱动电路800会操作于放电时期S4,储存电容Cst放电,当扫描线信被拉至高电压电平,像素驱动电路800会进入数据加载时期S5,当扫描线信号kan再被拉至低电压电平时,数据加载时期S5结束。 When the discharge signal Discharge pulled to a high voltage level and the light emission signal Emit_2 maintained at a high voltage level, the pixel driving circuit 800 in Figure 8 will operate S4, the storage capacitor Cst during the discharge the discharge, when the scanning line is pulled to a high voltage channel level, the pixel driving circuit 800 enters the data loading period S5, when the scanning signal line kan then pulled to a low voltage level, the end of the data loading period S5. 当发光信号Emit_2被拉至低电压电平时,像素驱动电路800会进入发光时期S6, 其它发光方法和原理与次帧时期SFl相同,因此在次帧时期SF2,流经显示组件EL2的电流与驱动晶体管M5的阈值电压Vth以及驱动晶体管M5的电源供应PVdd无关。 When the lighting signal Emit_2 pulled to a low voltage level, the pixel driving circuit 800 enters the light emitting period S6, and the other light emitting principles and methods during the same time frame SFL, therefore SF2, EL2 current flowing through the display assembly and drive sub frame period transistor M5 and the threshold voltage Vth of the driving transistor M5 PVdd power supply independent. 另外,根据本发明一实施例,如图9所示,放电时期Si、数据加载时期S2、发光时期S3、放电时期S4、数据加载时期S5、发光时期S6依序发生。 Further, according to an embodiment of the present invention, shown in Figure 9, the discharge period Si, a data loading period S2, S3 emission period, a discharge period S4, data loading period S5, S6 sequentially occur during light emission.

[0080] 本发明实施例的像素驱动电路800与驱动晶体管M5的阈值电压Vth和电源供应PVdd无关,并且电源供应PVdd与扫描线信号kan的电压电平是互无关连的,因此扫描线信号kan的电压范围值并不会受到电源供应PVdd电压范围值的限制,并且显示组件ELl和EL2共享驱动电路850以增加像素驱动电路800的显示组件ELl和EL2的发光面积。 [0080] The pixel driving circuit of an embodiment of the present invention is 800 regardless of the threshold voltage Vth and the power supply PVdd driving transistor M5, and the power supply PVdd and the voltage level of the scanning line signal kan are mutually independent of that, the scan line signal kan voltage value range and is not limited by the power supply voltage PVdd range of values, and display assembly ELl and EL2 shared drive circuit 850 to increase the light emission area of ​​the pixel driving circuit 800 of the display assembly ELl and EL2 to.

[0081] 图10显示根据本发明的另一实施例的影像显示系统,在本实施例中,影像显示系统可包括显示面板400或电子装置600,如图10所示显示面板400包括上述图8的像素驱动电路800,显示面板400可以是电子装置的一部分(例如:电子装置600),一般电子装置600包括显示面板400和电源供应器500,另外,电源供应器500耦接至显示面板400以提供电能至显示面板400,电子装置可以是:手机、数字相机、个人数字助理、笔记型计算机、 桌上型计算机、电视、或便携式DVD放影机。 [0081] FIG. 10 shows the image display system according to another embodiment of the present invention, in the present embodiment, the image display system may include a display panel 400 or electronic device 600, as shown in FIG 10 includes the above display panel 400 shown in FIG. 8 the pixel driving circuit 800, display panel 400 may be part of an electronic device (for example: an electronic device 600), the general electronic device 600 includes a display panel 400 and power supply 500, Further, the power supply 500 is coupled to the display panel 400 providing power to the display panel 400, the electronic device may be: cell phones, digital cameras, personal digital assistants, notebook computers, desktop computer, television, or portable DVD players.

[0082] 本发明虽以较佳实施例披露如上,但其并非用以限定本发明的范围,本领域技术人员,在不脱离本发明的精神和范围的前提下,可做若干的更改与修饰,因此本发明的保护范围以本申请的权利要求为准。 [0082] Although the preferred embodiments of the present invention disclosed in the above embodiment, but it is not intended to limit the scope of the invention, those skilled in the art, without departing from the spirit and scope of the present invention, a number of changes and modifications do Therefore the scope of the present invention, the present application claims.

Claims (11)

  1. 1. 一种影像显示系统,包括: 一种像素驱动电路,包括:一储存电容,具有一第一节点与一第二节点;一晶体管,具有耦接至一放电信号的一栅极、耦接于上述第一节点的一漏极、和与上述第二节点耦接的一源极,其中上述放电信号在一第一时段使上述晶体管导通以使得上述储存电容放电;一转移电路,耦接至上述储存电容的第一节点,上述转移电路将一数据信号和一参考信号的一者传送至上述储存电容的第一节点;一驱动组件,具有耦接至一第一电平的一第一端点,耦接至上述第二节点的一第二端点,并具有输出一驱动电流的一第三端点;以及一开关电路,耦接于上述驱动组件与一显示组件之间,并可在一第二时段内使上述驱动组件成二极管耦接,并使得上述驱动电流可在一第三时段内输出至上述显示组件。 1. A video display system, comprising: A pixel driving circuit, comprising: a storage capacitor having a first node and a second node; a transistor having a gate coupled to a discharge signal is coupled a drain to said first node, and a source coupled to said second node electrode, wherein the discharge signal so that the transistor is turned on in a first period of time so that the discharge of the storage capacitor; a transfer circuit coupled the storage capacitor to the first node, said transfer circuit to one of a data signal and a reference signal is transmitted to the first node of the storage capacitor; a drive assembly having a first coupled to a first level terminal, a second terminal coupled to said second node and outputs a driving current having a third terminal; between a and a switching circuit coupled to the drive assembly and a display assembly, and in a that the second period of the drive assembly coupled to the diode, and such that the driving current can be output to the display assembly in a third period.
  2. 2.如权利要求1所述的影像显示系统,其中上述转移电路包括:一第一晶体管,具有一栅极耦接至一第一扫描线,具有一漏极接收上述数据信号,并具有一源极耦接至上述第一节点;以及一第二晶体管,具有一栅极耦接至上述第一扫描线,具有一源极接收上述参考信号,并具有一漏极耦接至上述第一节点。 2. The image display system according to claim 1, wherein the shift circuit comprises: a first transistor having a gate coupled to a first scan line, having a drain for receiving the data signal, and having a source electrode coupled to the first node; and a second transistor having a gate coupled to the first scan line, having a source receiving said reference signal and having a drain coupled to the first node.
  3. 3.如权利要求1所述的影像显示系统,其中上述转移电路包括:一第一晶体管,具有一栅极耦接至一第一扫描线,具有一漏极接收上述数据信号,并具有一源极耦接至上述第一节点;以及一第二晶体管,具有一栅极耦接至一第二扫描线,具有一源极接收上述参考信号,并具有一漏极耦接至上述第一节点。 3. The image display system according to claim 1, wherein the shift circuit comprises: a first transistor having a gate coupled to a first scan line, having a drain for receiving the data signal, and having a source electrode coupled to the first node; and a second transistor having a gate coupled to a second scan line having a source receiving said reference signal and having a drain coupled to the first node.
  4. 4.如权利要求1所述的影像显示系统,上述开关电路包括:一第三晶体管,具有耦接至一发光信号线的一栅极,具有耦接至上述显示组件的一漏极,并具有耦接至上述驱动组件的一源极;以及一第四晶体管,具有耦接至上述第二节点的一漏极,具有耦接至一第一扫描线的一栅极,并具有耦接至上述驱动组件的一源极。 4. The image display system according to claim 1, the switching circuit comprises: a third transistor having a gate coupled to a light emitting signal line having a drain coupled to said display assembly, and having coupled to a source electrode of the drive assembly; and a fourth transistor having a drain coupled to the second node, having a gate coupled to a first scan line, and having coupled to the a source electrode of the drive assembly.
  5. 5. 一种影像显示系统,包括: 一种像素驱动电路,包括:一储存电容,具有一第一节点与一第二节点;一晶体管,具有接收一放电信号的一栅极、耦接于上述第一节点的一漏极、和与上述第二节点耦接的一源极,其中上述放电信号在一第一放电时段和一第二放电时段使上述晶体管导通以使得上述储存电容放电;一转移电路,耦接至上述储存电容的第一节点,上述转移电路将一数据信号和一参考信号的一者传送至上述储存电容的第一节点;一驱动组件,具有耦接至一第一电平的一第一端点、耦接至上述第二节点的一第二端点以及具有输出一驱动电流的一第三端点;以及一开关电路,耦接至上述驱动组件、一第一显示组件和一第二显示组件,并在一第一数据加载时段和一第二数据加载时段使上述驱动组件成二极管耦接,并使得上述驱动电流分别在一第 A video display system, comprising: A pixel driving circuit, comprising: a storage capacitor having a first node and a second node; a transistor having a gate receiving a discharge signal is coupled to the a drain of the first node, and a source coupled to said second node electrode, wherein said discharge signal in a first period and a second discharge period of time so that the discharge transistor is turned on so that the discharge of the storage capacitor; a transfer circuit coupled to the first node of the storage capacitor, the shift circuit one of a data signal and a reference signal is transmitted to the first node of the storage capacitor; a drive assembly having a first electrically coupled to a flat first end, a second end coupled to said second node, and outputs a driving current having a third terminal; and a switch circuit, coupled to the drive assembly, a first display assembly and a second display assembly, and a second loading period and a data load period data so that the first diode is coupled to a drive assembly, and so that the driving current respectively, a first 一发光时段和一第二发光时段内输出至上述第一显示组件和上述第二显示组件。 And a light emission period within a second period of light emission output to the first display assembly and the second display assembly.
  6. 6.如权利要求5所述的影像显示系统,其中上述第一显示组件和上述第二显示组件共享上述驱动组件、上述转移电路、上述储存电容和上述晶体管。 Image as claimed in claim 5, wherein the display system, wherein the first display assembly and the second display assembly sharing said drive assembly, said shift circuit, the storage capacitor and the transistor.
  7. 7.如权利要求6所述的影像显示系统,其中上述第一显示组件于上述第一发光时段发光以及上述第二显示组件在上述第二发光时段发光。 7. The video display system of claim 6, wherein the first display in the second light emission component emitting the first light emission period in the light emitting period and the second display assembly.
  8. 8.如权利要求5所述的影像显示系统,其中上述驱动组件的上述第二端点和上述第三端点在上述第一数据加载时段和上述第二数据加载时段连接在一起使上述驱动组件成为上述二极管耦接。 8. The video display system of claim 5, wherein said second end of said drive assembly and said third terminal connected to said first data and said second data loading time period together so that the load becomes the above-described drive assembly diode coupled.
  9. 9.如权利要求5所述的影像显示系统,其中上述驱动电流在上述第一发光时段和上述第二发光时段正比于上述数据信号和上述参考信号的差的平方。 Image as claimed in claim 5, wherein the display system, wherein the driving current in the emission period of the first period and the second light emission proportional to the square of the difference between said data signal and said reference signal.
  10. 10.如权利要求5所述的影像显示系统,其中上述转移电路包括:一第一晶体管,具有接收一第一扫描信号的一栅极、接收上述数据信号的一漏极和耦接上述第一节点的一源极;以及一第二晶体管,具有接收上述第一扫描信号的一栅极、接收上述参考信号的一源极和耦接上述第一节点的一漏极。 10. The video display system of claim 5, wherein the shift circuit comprises: a first transistor having a gate receiving a first scan signal, and a drain for receiving said data signal and coupled to said first a source node electrode; and a second transistor having a gate receiving the first scan signal, a drain for receiving said reference signal and a source coupled to said first node.
  11. 11.如权利要求5所述的影像显示系统,其中上述开关电路包括:一第三晶体管,具有接收一第一发光信号的一栅极、耦接上述第一显示组件的漏极和耦接上述驱动组件的源极;一第四晶体管,具有耦接一第一扫描信号的栅极、耦接上述第二节点的漏极和耦接上述驱动组件的源极;以及一第五晶体管,具有接收一第二发光信号的一栅极、耦接上述第二显示组件的漏极和耦接上述驱动组件的源极。 11. The video display system of claim 5, wherein the switching circuit comprises: a third transistor having a gate receiving a first emission signal, the drain coupled to the first display module and coupled to the above-described above a source electrode of the drive assembly; a fourth transistor having a gate coupled to a first scan signal, a drain coupled to said second node and coupled to the drive source assembly; and a fifth transistor, having received a second source emitting a gate signal, a drain coupled to the second display assembly and the above-described drive assembly coupling the above pole.
CN 200710107528 2006-05-19 2007-05-18 Image display system and method for driving display assembly CN101075410B (en)

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