CN101069240A - Timing extraction device, and information reproduction apparatus and DVD device using the same - Google Patents
Timing extraction device, and information reproduction apparatus and DVD device using the same Download PDFInfo
- Publication number
- CN101069240A CN101069240A CNA2006800013344A CN200680001334A CN101069240A CN 101069240 A CN101069240 A CN 101069240A CN A2006800013344 A CNA2006800013344 A CN A2006800013344A CN 200680001334 A CN200680001334 A CN 200680001334A CN 101069240 A CN101069240 A CN 101069240A
- Authority
- CN
- China
- Prior art keywords
- mentioned
- frequency
- generating unit
- output
- clock generating
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/10009—Improvement or modification of read or write signals
- G11B20/10222—Improvement or modification of read or write signals clock-related aspects, e.g. phase or frequency adjustment or bit synchronisation
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
- H03L7/091—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal the phase or frequency detector using a sampling device
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
- H03L7/197—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division
- H03L7/1974—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division
- H03L7/1976—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division for fractional frequency division using a phase accumulator for controlling the counter or frequency divider
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Abstract
Processes are provided for producing organchlorosilanes and dipodal silanes in which an organic halide or alkene or chloralkene is reacted with a hydridochlorosilane in the presence of a quaternary phosphonium salt catalyst by providing sufficient heat to effect a dehydrohalogenative coupling reaction and/or a hydrosilylation reaction and venting the reaction to control reaction pressure and to remove gaseous byproducts from the reaction. The processes are preferably continuous using a catalyst in fluid form at reaction pressures not exceeding about 600 psi. The reactions may be carried out substantially isothermally and/or isobarically, for example in a plug flow reactor or continuous stirred tank reactor. The processes may produce novel silylated compounds including 1,2-bis (trichlorosilyl)decane or 1,2-bis (trimethoxysilyl)decane.
Description
Technical field
The present invention relates to from the replay signal of reading, extract the timing extraction device that is included in the timing information in this signal by recording mediums such as CDs.
Background technology
At present, the timing extraction device that uses in disc reproducing apparatus etc. for example has the reaction type timing extraction device shown in the patent documentation 1.This reaction type timing extraction device block structure as shown in figure 20 is such, quantize (quantization) by 1 pair of replay signal of being imported of A/D converter, and based on the data after quantizing, via skew (offset) correction portion 8 and in phase frequency comparator 13 calculating frequency sum of errors phase errors, and resulting digital correction is converted to the analogue value via loop filter 14 by D/A converter (not shown), the oscillation frequency of control VCO (voltage controlled oscillator) 15.By carrying out the control of such reaction type, the clock of seeking to drive A/D converter 1 and digital section 8,13,14 is synchronous with replay signal.For the decoding of data, because therefore the data synchronization after having taked clock and being quantized can decipher processing based on this quantized data.
Different therewith, in documents 2, studied the feed forward type timing extraction circuit that uses the frequency synthesizer that moves with fixed rate.Figure 21 illustrates the block structure of feed forward type timing extraction device.In this feed-forward mode, use is to generate and the fixed rate clock of the constant cycle oscillator 18 of the clock of output constant cycle (fixed rate) comes A/D converter 1 that replay signal is quantized, based on digit data sequence and the said fixing speed clock after quantizing by this A/D converter 1, infer the position, edge of synchronous clock by synchronous clock computing circuit 17, carry out the interpolation of quantized data handles with interpolating circuit 16, and, extract said fixing speed clock at interval and generate pseudo-synchronous clock Data CLK, use quantized data and pseudo-synchronous clock Data CLK after this interpolation is handled to decipher processing.
At this, in above-mentioned patent documentation 1 described existing reaction type structure, when the needs high-speed replay,, therefore will increase clock latency (latency) owing in digital circuit, need to be used for regularly streamline (pipe line) register of compensation.Therefore, the problem that in the reaction type structure, exists loop stability to be damaged easily.
Different therewith, feed forward type control is according to the data sequence computed correction after quantizing, and the data sequence that has quantized is implemented the mode of correcting process, therefore, has the advantage that not influenced by clock latency, is suitable for high-speed replay.
Patent documentation 1: TOHKEMY 2002-8315 communique
Patent documentation 2: Japanese kokai publication hei 8-161829 communique
Summary of the invention
But, in this feed forward type timing extraction device, the clock that needs to move with fixed rate all the time (usually in this clock generates frequency of utilization compositor etc.), the frequency of this clock with the playback frequency (replay rate) with respect to replay signal serve as take a sample (over sample) be prerequisite.Therefore, in case determine the playback frequency (replay rate) of replay signal, just the frequency setting of the needs clock that will move with fixed rate in advance is the frequency higher than the playback frequency of this replay signal.Therefore, when playback frequency (replay rate) when changing in time, the fixed rate clock is set to the high frequency of maximal value than playback frequency (replay rate).Therefore, under the low state of playback frequency (replay rate), will carry out above the crossing of required degree and take a sample, consider, will cause power consumption to increase from system aspects.Figure 22 illustrates replay rate when changing continuously fixation of C LK among Figure 21 and the relation of Data CLK.The fixed time interval that extracts (decimation) fixed clock when playback speed is fast at interval narrows down, and playback speed extracts the interval of fixed clock when slow at interval and broadens, and therefore can make digital circuit carry out high speed motion more than required degree, causes power consumption to increase.In addition, when the output stage of A/D converter connects the digital waveform equalizer that moves with constant clock, need change the setting of the coefficient etc. of waveform equalizer, the control complicated problems that becomes therefore also occur according to replay rate.
The present invention makes in view of above-mentioned existing issue, its purpose is, from replay signal, extracting in the feed forward type timing extraction device of timing information, even playback frequency (replay rate) changes in time, also can make the ratios constant that extracts fixed clock at interval, can seek the optimization of power consumption, and seek the control summary when the output stage of A/D converter connects the digital waveform equalizer that moves with constant clock.
To achieve these goals, in the feed forward type timing extraction device that extracts timing information from replay signal of the present invention, the branch frequency of adjusting the clock generating unit makes that the output clock of this clock generating unit is constant with the frequency ratio maintenance of the playback frequency (replay rate) of replay signal.
That is, the invention provides a kind of from replay signal the timing extraction device in the information reproducing device of the recording timing of extracted data and this record, it is characterized in that, comprising: clock generating unit, branch frequency corresponding clock that generates and set and output; Quantization device quantizes replay signal and exports with the timing of the output clock of above-mentioned clock generating unit; The frequency ratio calculating part, the appearance of measuring the AD HOC that in the output sequence of above-mentioned quantization device, comprised, AD HOC based on the output clock of above-mentioned clock generating unit at interval or the two, calculate the frequency ratio of frequency of the output clock of the playback frequency of above-mentioned replay signal and above-mentioned clock generating unit based on its measured value; Phase place correction calculating part calculates the phase place modified value of the output clock of above-mentioned clock generating unit with respect to the quantized signal of above-mentioned quantization device; Control part, the branch frequency of above-mentioned clock generating unit is calculated and set to frequency ratio that reception is calculated by said frequencies ratio calculating part and the phase place correction that is calculated by above-mentioned phase place correction calculating part and with respect to cycle of the output clock of the above-mentioned clock generating unit in playback cycle of above-mentioned replay signal; And pseudo-synchronous clock generating unit, based on as the output of above-mentioned control part, with respect to the cycle of the output clock of the above-mentioned clock generating unit in playback cycle of above-mentioned replay signal, the output clock that extracts above-mentioned clock generating unit at interval generates the clock pseudo-synchronous with the recording timing of above-mentioned record data.
The invention is characterized in: in above-mentioned timing extraction device, above-mentioned control part, when the enabling signal of having imported the processing of resetting or Restart Signal, set the branch frequency of above-mentioned clock generating unit so that the frequency ratio of said frequencies ratio calculating part is predefined value, upgrade the branch frequency of above-mentioned clock generating unit so that the frequency ratio of said frequencies ratio calculating part is in constant based on the phase place correction of above-mentioned phase place correction calculating part afterwards.
The invention is characterized in: in above-mentioned timing extraction device, above-mentioned control part, when the enabling signal of having imported the processing of resetting or Restart Signal, set the branch frequency of above-mentioned clock generating unit so that the frequency ratio of said frequencies ratio calculating part is predefined value, afterwards when the frequency ratio of said frequencies ratio calculating part has surpassed pre-set threshold, use the phase place correction of above-mentioned phase place correction calculating part upgrade above-mentioned clock generating unit the branch frequency so that the frequency ratio of said frequencies ratio calculating part in above-mentioned threshold value.
The invention is characterized in: in above-mentioned timing extraction device, above-mentioned control part, when the enabling signal of having imported the processing of resetting or Restart Signal, set the branch frequency of above-mentioned clock generating unit so that the frequency ratio of said frequencies ratio calculating part is predefined value, when variation has taken place the frequency ratio of said frequencies ratio calculating part, upgrade the branch frequency of above-mentioned clock generating unit afterwards so that the frequency ratio of said frequencies ratio calculating part is in constant.
The invention is characterized in: in above-mentioned timing extraction device, above-mentioned control part, when the enabling signal of having imported the processing of resetting or Restart Signal, set the branch frequency of above-mentioned clock generating unit so that the frequency ratio of said frequencies ratio calculating part is predefined value, afterwards when the frequency ratio of said frequencies ratio calculating part has surpassed pre-set threshold, upgrade above-mentioned clock generating unit the branch frequency so that the frequency ratio of said frequencies ratio calculating part in above-mentioned threshold value.
The invention is characterized in: in above-mentioned timing extraction device, has the Restart Signal generating unit, it is after the processing beginning of resetting, measure the appearance interval of the AD HOC that in the output sequence of above-mentioned quantization device, comprises based on the pseudo-synchronous clock of above-mentioned pseudo-synchronous clock generating unit, ideal value when measuring with synchronous clock compares, when continuous predefined number of times ground has surpassed predefined value, generate the Restart Signal of the branch frequency renewal that makes above-mentioned clock generating unit.
The invention is characterized in: in above-mentioned timing extraction device, has the Restart Signal generating unit, after the branch frequency that its above-mentioned control part when the enabling signal of having imported the processing of resetting or Restart Signal is set above-mentioned clock generating unit makes that the frequency ratio of said frequencies ratio calculating part is predefined value, when the continuous predefined number of times of the frequency ratio ground of said frequencies ratio calculating part has surpassed predefined value, generate Restart Signal.
The invention is characterized in: in above-mentioned timing extraction device, above-mentioned control part, when having imported when resetting the enabling signal handled or Restart Signal, the branch frequency of setting above-mentioned clock generating unit makes the frequency of output clock of above-mentioned clock generating unit be not less than predefined frequency.
The invention is characterized in: in above-mentioned timing extraction device, above-mentioned control part, use has been carried out the result of smoothing processing and the frequency ratio of said frequencies ratio calculating part to the phase place correction of above-mentioned phase place correction calculating part, calculating outputs to above-mentioned pseudo-synchronous clock generating unit with respect to the playback cycle of the above-mentioned clock generating unit in the playback cycle of above-mentioned replay signal.
The invention is characterized in: in above-mentioned timing extraction device, carried out with " 0 ", " 1 " under the situation of 2 values processing at the output sequence to above-mentioned quantization device, " 0 ", " 1 " continuous ratio are 14: 4 or 4: 14 when the medium that has write down above-mentioned record data is DVD-ROM/RAM in the above-mentioned AD HOC; Be 11: 11 when the medium that has write down above-mentioned record data is CD; Be 2: 9: 9 or 9: 9: 2 when the medium that has write down above-mentioned record data is Blu-ray.
The invention is characterized in: in above-mentioned timing extraction device, the appearance of the above-mentioned AD HOC of the output sequence of above-mentioned quantization device at interval, when measuring, be 1488 during for DVD-ROM/RAM at the medium that has write down above-mentioned record data with the replay rate of above-mentioned replay signal; Be 588 when the medium that has write down above-mentioned record data is CD; Be 1932 when the medium that has write down above-mentioned record data is Blu-ray.
The invention is characterized in: in above-mentioned timing extraction device, in the output of above-mentioned quantization device, be connected with the offset correction device of the skew that is used for revising the output that is included in above-mentioned quantization device, said frequencies ratio calculating part and above-mentioned phase place correction calculating part replace the output of above-mentioned quantization device and use the output of above-mentioned offset correction device to move.
The invention is characterized in: in above-mentioned timing extraction device, in the output of above-mentioned quantization device, be connected with the Waveform equalizing device of wave shape equalization that output clock based on above-mentioned clock generating unit carries out the output of above-mentioned quantization device, said frequencies ratio calculating part and above-mentioned phase place correction calculating part replace the output of above-mentioned quantization device and use the output of above-mentioned Waveform equalizing device to move.
The invention is characterized in: in above-mentioned timing extraction device, in the input of above-mentioned quantization device, be connected with the analog filter that the wave shape equalization of carrying out above-mentioned replay signal or high frequency noise are removed processing, the equalization characteristic of above-mentioned analog filter or cut-off characteristics changed according to branch frequency as the above-mentioned clock generating unit of the output of above-mentioned control part.
The invention is characterized in: in above-mentioned timing extraction device, be made of integral part and fraction part as the branch frequency of the above-mentioned clock generating unit of the output of above-mentioned control part, above-mentioned clock generating unit is the frequency synthesizer that can carry out fraction division control.
Information reproducing device of the present invention is characterized in that, comprising: the described timing extraction device of claim 1; And signal processing circuit, based on the output that is included in the pseudo-synchronous clock generating unit in the above-mentioned timing extraction device, the above-mentioned data from the output that is included in the quantization device in the above-mentioned timing extraction device are deciphered.
DVD device of the present invention is characterized in that, comprising: the described timing extraction device of claim 1; And signal processing circuit, based on the output that is included in the pseudo-synchronous clock generating unit in the above-mentioned timing extraction device, the above-mentioned data from the output that is included in the quantization device in the above-mentioned timing extraction device are deciphered.
The invention is characterized in: in above-mentioned timing extraction device, above-mentioned replay signal is via wireless communication line or comprise that the communication line of optical fiber, concentric cable, line of electric force provides.
The invention is characterized in: in above-mentioned timing extraction device, above-mentioned replay signal is to be provided by the CD that comprises DVD CD, CD CD, Blu-ray CD.
As mentioned above, in the present invention, from replay signal, extract in the timing extraction device of feed forward type of timing information, the frequency proportions calculating part, the appearance of measuring the AD HOC that in the output sequence of above-mentioned quantization device, comprised, AD HOC based on the output clock of clock generating unit at interval or the two, calculate the frequency ratio of frequency of the output clock of the playback frequency of replay signal and clock generating unit.And for the branch frequency that is set in the clock generating unit, control part makes that according to the branch frequency of the frequency ratio refresh clock generating unit that aforementioned calculation goes out for example this frequency ratio that calculates is predefined frequency ratio.Therefore, even the playback speed of signal accelerates or is slack-off, the frequency of the output clock of the frequency of replay signal and clock generating unit also is retained as constant frequency ratio all the time, therefore, the extraction of the output clock of clock generating unit can be made as in the constant or constant scope at interval, its result, with prior art consider like that signal playback speed variation and the situation that the output clock of clock generating unit is taken as the fixed rate clock of upper frequency is compared, do not need to make the digital circuit high speed motion, power consumption is reduced.
And, output stage at A/D converter connects under the situation of digital waveform equalizer, in case determine the coefficient control of this digital waveform equalizer, even if then the change frequency characteristic of waveform equalizer of the frequency of replay signal is also roughly the same, therefore control is very easy.
As mentioned above, according to timing extraction device of the present invention, in the feed forward type timing extraction device that from replay signal, extracts timing signal, control and make the frequency ratio of playback frequency (replay rate) and the frequency of the output clock of clock generating unit of replay signal become the steady state value of expectation or the value in the predefined scope, therefore, a kind of timing extraction device of the summary that can make the power consumption optimumization of system and can seek to control can be provided.
Description of drawings
Fig. 1 is the block diagram of the timing extraction device of expression first embodiment of the invention.
Fig. 2 is the figure of the data layout of expression DVD.
Fig. 3 is the structural drawing of presentation graphs 1 medium frequency ratio calculating part 2.
Fig. 4 is another structural drawing of presentation graphs 1 medium frequency ratio calculating part 2.
Fig. 5 is the output clock of standardized frequency synthesizer 6 has been carried out in expression with channel bit period the figure of phase state.
Fig. 6 is the figure of relation of the output sampling of the correction of expression phase place correction portion 3 and A/D converter 1.
Fig. 7 is the structural drawing of the control part 4 among Fig. 1.
Fig. 8 is the structural drawing of the smoothing filter 42 among Fig. 7.
Fig. 9 is the figure that the action of the control part in the presentation graphs 7 is handled.
Figure 10 is the structural drawing of pseudo-synchronous clock generating unit 5.
Figure 11 is the sequential chart of pseudo-synchronous clock generating unit 5.
Figure 12 is the figure of the structure example of presentation graphs 1 medium frequency compositor 6.
Figure 13 is the sequential chart of the timing extraction device among Fig. 1.
Figure 14 is the block diagram of the variation of expression timing extraction device shown in Figure 1.
Figure 15 is the figure of other variation of expression timing extraction device shown in Figure 1.
Figure 16 is the figure of other variation of expression timing extraction device shown in Figure 1.
Figure 17 is the figure of other variation of expression timing extraction device shown in Figure 1.
Figure 18 is the figure of other variation of expression timing extraction device shown in Figure 1.
Figure 19 is the block diagram of whole schematic configuration that expression has the information reproducing device of timing extraction device shown in Figure 1.
Figure 20 is the block diagram that is illustrated in the structure of the middle existing reaction type timing extraction devices that use such as disc reproducing apparatus.
Figure 21 is the block diagram that is illustrated in the structure of the middle existing feed forward type timing extraction devices that use such as disc reproducing apparatus.
Figure 22 is the sequential chart of the circuit of Figure 21.
Embodiment
Below, with reference to the description of drawings embodiments of the present invention.
(first embodiment)
Fig. 1 is the block diagram of first embodiment of expression timing extraction device of the present invention.The timing extraction device of present embodiment illustrates a kind of example of information reproducing device, and this information reproducing device is from carrying out extracting the resulting emulated for playback signal of playback time record data and data recording thereof regularly to being recorded in data on the recording medium such as CD.In Fig. 1, the 1st, A/D converter, the 2nd, frequency ratio calculating part, the 3rd, phase place correction calculating part, the 4th, control part, the 5th, pseudo-synchronous clock generating unit, the 6th, frequency synthesizer (clock generating unit).The below detailed action of each ingredient of explanation.
For the replay signal of being imported, A/D converter is taken a sample based on the output clock of frequency synthesizer 6, after quantizing with its output.
Frequency ratio calculating part 2, the appearance of from the output sequence of A/D converter (quantization device) 1, measuring AD HOC or AD HOC based on the output clock of frequency synthesizer 6 at interval or above-mentioned both, calculate the playback frequency (replay rate) of replay signal and the frequency ratio of the output clock of frequency synthesizer 6 based on the value of measuring.As AD HOC, for example adopt sync mark during from DVD or CD when replay signal.
Fig. 2 illustrates the data layout of DVD-ROM.DVD-ROM is made of ECC piece (ErrorCorrection Coding Block).1 ECC piece is made of 16 sectors, and 1 sector is made of 26 frames.1 frame is made of the data of 1488 channel bit, and its title division inserts sync mark.This sync mark is the AD HOC that is made of predetermined bit interval, for example when being DVD-ROM, constitute by continuous 14 channel bit " 1 " and continuous 4 channel bit " 0 ", perhaps constitute by continuous 14 channel bit " 0 " and continuous 4 channel bit " 1 ".At this moment, per 1488 channel bit of sync mark occur once.In addition, when being CD, sync mark is the combination of continuous 11 channel bit " 0 " and continuous 11 channel bit " 1 ", or its opposite combination, and per 588 channel bit occur once.Sync mark among the Blu-ray is the combination of continuous 2 channel bit " 0 ", continuous 9 channel bit " 1 ", continuous 9 channel bit " 0 ", or its opposite combination, and per 1932 channel bit occur once.Such sync mark is the pattern that does not appear in the user data.Therefore, by utilizing this sync mark, can calculate the playback frequency (replay rate) of replay signal and the frequency ratio of frequency synthesizer.
For example, in Fig. 3, constitute frequency ratio calculating part 2 by sync mark detector 21, divider 22, sync mark setting value 23.Sync mark detector 21 detects sync mark from the output sequence of A/D converter 1.But, in this structure, A/D converter 1 might not move with channel bit period, therefore output sequence 2 values of A/D converter 1 need be carried out the detection of sync mark at interval based on its state-transition.For example under the situation that is DVD-ROM, when the ratio that becomes the state-transition interval is the interval of 14: 4 (7: 2), just can detect sync mark.For the detection of this sync mark, also can be made as and make state-transition ratio at interval have tolerance limit.Like this, by obtaining sync mark of measuring and the sync mark (14T+4T that counts with channel bit period with the output clock of frequency synthesizer 6, wherein T is a channel bit period) ratio, can calculate the playback frequency (replay rate) of replay signal and the frequency ratio (or cycle ratio) of frequency synthesizer.
As another structure of frequency ratio calculating part 3, can consider structure shown in Figure 4.In Fig. 4, the 21st, sync mark detector, the 24th, the sync mark interval counter, the 22nd, divider, the 25th, sync mark is setting value at interval.Different with the mode of Fig. 3, in this structure, the output clock of frequency of utilization compositor 6 utilizes resulting measured value (output of sync mark interval counter 24) calculated rate ratio (or cycle ratio) to being counted by the interval between sync mark detector 21 detected 2 continuous sync marks.Sync mark per 1488 channel bit when being DVD-ROM occur once, therefore can utilize these sync marks to calculate the higher frequency ratio of precision (or cycle ratio).
If can calculate the playback frequency (replay rate) of replay signal and the frequency ratio (or cycle ratio) of the output clock of frequency synthesizer 6 like this, then can calculate frequency synthesizer with respect to the cycle ratio in the cycle of resetting, therefore can calculate the timing of in pseudo-synchronous clock generating unit 5, extracting the output clock of frequency synthesizer 6 at interval.And, for extracting at interval regularly, need to consider the shake (jitter) of replay signal or the output result that frequency variation reflects phase place correction calculating part 3.
Fig. 5 illustrates the sequential chart of the output clock of the channel clock of replay signal and frequency synthesizer 6.In Fig. 5, make reference edge along unanimity, the frequency that makes the output clock of frequency synthesizer 6 is 2.5 times of playback frequency (replay rate) of replay signal.As shown in Figure 5, when the playback cycle with replay signal was taken as 1, the phase state of the output clock of frequency synthesizer 6 was 0.4,0.8,0.2 (actual is 1.2, but be 1.2-1=0.2 with the channel bit period of replay signal during as benchmark).In the system of reality, the edge of the output clock of frequency synthesizer 6 is in and the inconsistent situation of reference point mostly, therefore need carry out the phase place correction.For phase error, as shown in Figure 6, the phase error perr that calculates the zero crossing from the reference value to the replay signal gets final product.In Fig. 6, because judged the ratio of playback frequency (replay rate) with the frequency of the output clock of frequency synthesizer 6 of replay signal, so can calculate phase theta 1, the θ 2 of 2 sampling values in zero crossing front and back of replay signal.In addition, be the output result of A/D converter 1 at magnitude of voltage V1, the V2 of these two phase theta 1, θ 2, be known therefore.Thus, phase error perr can be calculated by following formula 1 (wherein θ 2＞θ 1).
This phase error perr is taken as 1 and carried out standardized value and show by the playback cycle with replay signal.Also can adopt other computing method for phase error perr.Like this, phase place correction calculating part 3 carries out the output clock of frequency synthesizer 6 and the calculating of the phase place correction between replay signal.
As the structure of above-mentioned smoothing filter 42, can consider by part of carrying out the ratio computing for example shown in Figure 8 and the part of carrying out integral operation to constitute.In Fig. 8, before carrying out the frequency lock detection, selector switch 421 is output as 0, and also makes integrator be reset to 0, and the output of this piece becomes 0.After frequency lock detected, the phase place correction is divided into rate term and integral is carried out computing.For rate term, increase with gain G p by multiplier 422, for integral, increase the back by multiplier 423 with gain G i and carry out integral operation by integrator 424.Every carry out addition and handle by totalizer 425 after, output to the totalizer 43 that is connected with next stage as the output of smoothing filter 42.
And, in control part shown in Figure 74, totalizer 43 will be exported the cycle (channel bit period is taken as 1 has carried out standardized value) of the output clock of current frequency synthesizer 6 from the frequency ratio of said frequencies ratio calculating part 2 and the output addition of above-mentioned smoothing filter 42.The 44 target frequency ratios of setting frequency with the playback frequency of replay signal of the output clock be used for frequency synthesizer 6 in target frequency ratio configuration part, consideration makes the frequency of the output clock of frequency synthesizer 6 be not less than predefined frequency all the time and preestablishes this target frequency ratio.The branch frequency that frequency division calculating part 45 comes calculated rate compositor 6 based on the target frequency ratio of the information of the frequency ratio that is calculated by said frequencies ratio calculating part 42 and above-mentioned target frequency ratio configuration part 44.Fig. 9 illustrates about the action of the control part 4 of this minute frequency calculating and handles.For " calculating the branch frequency " such processing so that frequency ratio result of calculation equals the target frequency ratio, current frequency ratio is being taken as N1 (frequency/replay rate of the frequency synthesizer 6 that N1=is current), the branch frequency of frequency synthesizer 6 of this moment is being taken as DIV1; And, the target frequency ratio is taken as N2, when the branch frequency of frequency synthesizer 6 of this moment is taken as DIV2, following formula 2 and formula 3 are arranged then.
NI * DIV1=N2 * DIV2 ... (formula 2)
Therefore, can use the branch frequency of formula 3 setpoint frequency compositors 6.In Fig. 9, after having carried out the frequency ratio lock-in detection, the branch frequency is set in output change based on totalizer 43 once more, but only use the output change of smoothing filter 42 or the change of frequency ratio to come the branch frequency of frequency synthesizer 6 is calculated once more, so also can obtain same effect.In addition, also can control the feasible branch frequency of only under the situation that has surpassed pre-set threshold, setting once more to this change.
Figure 10 illustrates the structure of pseudo-synchronous clock generating unit 5.Synthesis cycle as the output of control part 4 is imported into edge generative circuit 51."AND" circuit 52 carries out the AND operation of the output clock of edge generative circuit and frequency synthesizer 6, and its result is exported as data clock.Edge generative circuit 51 carries out the mod1 computing of the synthesis cycle imported.Particularly, carry out the accumulation process of the synthesis cycle imported, at this moment, when operation result surpassed " 1 ", the value that will deduct 1 back gained was as accumulation result.For example, in example shown in Figure 11, the frequency that frequency synthesizer is shown is the situation of 1.33 (cycle of replay rate is taken as 1, and the cycle ratio of being converted into is 0.75) with the ratio of the frequency of replay rate.At this moment, synthesis cycle is a steady state value 0.75.Therefore, the output clock synchronization of edge generative circuit 51 and frequency synthesizer 6 is carried out 0.75 accumulation process.At this moment, if the result that only adds up then is 0,0.75,1.5 ..., but owing to carry out the mod1 computing at every turn, therefore as the Phase (phase place) of mod1 operation result be 0,0.75,0.5 (1.5 greater than 1, thereby deducts the result of 1 gained as the mod1 operation result with 1.5) ....When carrying out the mod1 computing, carrying out subtraction process back edge output becoming HI.Data CLK is the result after the output clock of this edge output and frequency synthesizer 6 carries out AND operation.
Then, Figure 12 illustrates the structure example of frequency synthesizer 6.At this, the frequency synthesizer of fraction division formula is shown.The 61st, be used for the phase frequency comparator, the 62nd of comparison reference signal and the phase of the signal that the output clock of frequency synthesizer has been carried out modulation, charge pump, the 63rd, loop filter, the 64th, VCO, the 65th carries out the frequency divider of N/N+1 frequency division to the output of VCO64, the 66th, swallow counter, the 67th, Δ ∑ modulator.By using such structure, the output clock frequency of frequency synthesizer can be set at and the corresponding value of the branch frequency of being imported (constituting) by integral part and fractional part.
In the present embodiment, use the frequency synthesizer of fraction division formula to be illustrated, still, use the clock generating unit that constitutes by oscillator, frequency divider, modulator also can access same effect its replacement as the clock generating unit.At this moment, change the modulation signal that modulator generated according to the branch frequency of being imported, the modulation signal after the change is used as the branch frequency of frequency divider.As modulator, generally adopt Δ ∑ modulator.
The sequential chart of the timing extraction device of the manner when the playback frequency (replay rate) of replay signal changes is shown in Figure 13.Like this, according to the playback frequency (replay rate) of the branch frequency of frequency synthesizer 6 and replay signal the ratio of the frequency of the playback frequency (replay rate) of replay signal and frequency synthesizer 6 is controlled to be steady state value (or within the specific limits), Data CLK can be set at steady state value (or within the specific limits) at interval with respect to the extraction of the output clock of frequency synthesizer 6 thus.
Figure 14～Figure 18 is the block diagram of variation of first embodiment of expression timing extraction device of the present invention.
In Figure 14, timing extraction device shown in Figure 1 is not directly imported startup/Restart Signal that slave controller (not shown) is imported, but generates startup/Restart Signal via starting/restart generating unit (Restart Signal generating unit) 71.Startup/Restart Signal generating unit 71 is detecting behind the frequency ratio lock detecting signal of control part 4 outputs, with Data CLK the output sequence of A/D converter 1 is resampled, ideal value when whether the appearance of confirming sync mark or sync mark equals to measure the interval of this sync mark or sync mark with synchronous clock at interval, and whether affirmation can normally detect the interval of this sync mark or sync mark, when surpassing predefined value when continuous predefined number of times, generation startup/Restart Signal is so that the branch frequency of setpoint frequency compositor 6 once more.
In Figure 15, timing extraction device shown in Figure 1, startup/Restart Signal that the playback that slave controller (not shown) is imported is handled is input to and starts/restart generating unit 72, by this startup/restart generating unit 72 to generate startup/Restart Signals.Above-mentioned startup/restart generating unit 72 detecting after the frequency ratio lock detecting signal of control part 4 outputs, the output sequence of A/D converter 1 is taken a sample with the output clock of frequency synthesizer 6, can affirmation normally detect the appearance interval of sync mark or sync mark, when surpassing predefined value when continuous predefined number of times, generation startup/Restart Signal is so that the branch frequency of setpoint frequency compositor 6 once more.
Figure 14 and startup shown in Figure 15/restarting generating unit 71,72 also can be when the continuous predefined number of times of the frequency ratio of frequency ratio calculating part 2 surpasses predefined value, the generation Restart Signal.
In Figure 16, timing extraction device shown in Figure 1 is adopted following structure, that is: also on the output stage of A/D converter 1, connect offset correction portion 8, after the offset correction of replay signal, carry out the timing extraction computing.
In Figure 17, timing extraction device shown in Figure 1 is adopted following structure, that is: also on the output stage of A/D converter 1, connect digital waveform equalizer 91, after handling, the wave shape equalization that numeric area is carried out replay signal carries out the timing extraction computing.In this structure, control and make that the ratio of frequency of output clock of playback frequency (replay rate) and frequency synthesizer 6 of replay signal is constant all the time or be in the certain limit, in case determined the coefficient control of digital waveform equalizer 91, even the frequency characteristic of playback frequency change so is also roughly the same, therefore control is very simplified.
In Figure 18, timing extraction device shown in Figure 1 is adopted following structure, that is: also connect analog filter 92, handle or after high frequency noise removes processing, carry out the timing extraction computing in the wave shape equalization that simulated domain has carried out replay signal in the prime of A/D converter 1.When the playback frequency (replay rate) of replay signal changes, need as one man adjust the filtering characteristic of analog filter 92 with this variation.This structure is made and can be adjusted the equalization characteristic of analog filter 92 or the structure of cut-off characteristics according to the branch frequency of the frequency synthesizer 6 of control part 4 output, therefore control is very simplified.
Figure 19 is the block diagram of whole schematic configuration of the information reproducing device of the expression LSI12 that contains built-in timing extraction device.If being applied to DVD replay device etc. describes, then information recording part 10 is recording medium (dvd medias), it is pick-ups from these recording medium playback record data that information is read portion 11, and LSI12 comprises the signal processing circuit (not shown) that replay signal waveform that use read by above-mentioned pick-up carries out wave shape equalization, error correction and data demodulates etc.Use the decoded data of this LSI12 output and demonstration that pseudo-synchronous clock carries out information and to the conversion of sound.
In the above description, the example that extracts the timing information that is contained in the replay signal from recording mediums such as DVD is illustrated, but also can uses the present invention under the situation of the timing information that in the signal that provides via wire communication lines such as wireless communication line or optical fiber, concentric cable, line of electric force is provided, contains.
In addition, timing extraction device of the present invention can certainly adopt following structure, that is: by controlling and extract timing information being built in target frequency ratio configuration part 44 in the control part for example shown in Figure 74 and the setting of the branch frequency in the branchs frequency calculating part 45 with software.
Industrial utilizability
As mentioned above, in the present invention, the timing extraction device of feed forward type by control with So that the playback frequency (replay rate) of replay signal and clock generating unit (frequency synthesizer) The frequency ratio of output clock frequency become desired value (in steady state value or the predefined scope Value), can seek the optimization of system power dissipation and the summary of control. Therefore, as from Extract in the replay signal the such information reproducing device of timing information for example the timing used of CD take out It is useful getting device etc.
Claims (19)
1. the timing extraction device in the information reproducing device of the recording timing of extracted data and this record from a replay signal is characterized in that, comprising:
The clock generating unit, the branch frequency corresponding clock that generates and set and with its output;
Quantization device quantizes its output replay signal with the timing of the output clock of above-mentioned clock generating unit;
The frequency ratio calculating part, the appearance of measuring the AD HOC that comprises in the output sequence of above-mentioned quantization device, AD HOC based on the output clock of above-mentioned clock generating unit at interval or its both and is calculated the frequency ratio of the output clock frequency of the playback frequency of above-mentioned replay signal and above-mentioned clock generating unit based on its measured value;
Phase place correction calculating part calculates the phase place modified value of the output clock of above-mentioned clock generating unit with respect to the quantized signal of above-mentioned quantization device;
Control part receives the frequency ratio that calculated by said frequencies ratio calculating part and calculates and set the branch frequency of above-mentioned clock generating unit and with respect to cycle of the output clock of the above-mentioned clock generating unit in playback cycle of above-mentioned replay signal by the phase place correction that above-mentioned phase place correction calculating part calculates; And
Pseudo-synchronous clock generating unit, based on the output of above-mentioned control part promptly with respect to cycle of the output clock of the above-mentioned clock generating unit in playback cycle of above-mentioned replay signal, come to extract at interval the output clock of above-mentioned clock generating unit, thereby generate the clock pseudo-synchronous with the recording timing of above-mentioned record data.
2. timing extraction device according to claim 1 is characterized in that:
Above-mentioned control part,
When the enabling signal of having imported the processing of resetting or Restart Signal, set the branch frequency of above-mentioned clock generating unit so that the frequency ratio of said frequencies ratio calculating part is predefined value, upgrade the branch frequency of above-mentioned clock generating unit so that the frequency ratio of said frequencies ratio calculating part is constant based on the phase place correction of above-mentioned phase place correction calculating part thereafter.
3. timing extraction device according to claim 1 is characterized in that:
Above-mentioned control part,
When the enabling signal of having imported the processing of resetting or Restart Signal, set the branch frequency of above-mentioned clock generating unit so that the frequency ratio of said frequencies ratio calculating part is predefined value, thereafter when the frequency ratio of said frequencies ratio calculating part surpasses pre-set threshold, use the phase place correction of above-mentioned phase place correction calculating part upgrade above-mentioned clock generating unit the branch frequency so that the frequency ratio of said frequencies ratio calculating part in above-mentioned threshold value.
4. timing extraction device according to claim 1 is characterized in that:
Above-mentioned control part,
When the enabling signal of having imported the processing of resetting or Restart Signal, set the branch frequency of above-mentioned clock generating unit so that the frequency ratio of said frequencies ratio calculating part is predefined value, when the frequency ratio of said frequencies ratio calculating part variation taken place, upgrade the branch frequency of above-mentioned clock generating unit so that the frequency ratio of said frequencies ratio calculating part be constant thereafter.
5. timing extraction device according to claim 1 is characterized in that:
Above-mentioned control part,
When the enabling signal of having imported the processing of resetting or Restart Signal, set the branch frequency of above-mentioned clock generating unit so that the frequency ratio of said frequencies ratio calculating part is predefined value, thereafter when the frequency ratio of said frequencies ratio calculating part surpasses pre-set threshold, upgrade above-mentioned clock generating unit the branch frequency so that the frequency ratio of said frequencies ratio calculating part in above-mentioned threshold value.
6. timing extraction device according to claim 1 is characterized in that:
It also has: the Restart Signal generating unit, after the processing beginning of resetting, measure the appearance interval of the AD HOC that in the output sequence of above-mentioned quantization device, comprises based on the pseudo-synchronous clock of above-mentioned pseudo-synchronous clock generating unit, and the ideal value when measuring with synchronous clock compares, when surpassing predefined value, generate the Restart Signal of the branch frequency renewal that makes above-mentioned clock generating unit when continuous predefined number of times.
7. timing extraction device according to claim 1 is characterized in that:
It also has: the Restart Signal generating unit, when the enabling signal of having imported the processing of resetting or Restart Signal, above-mentioned control part sets the branch frequency of above-mentioned clock generating unit so that the frequency ratio of said frequencies ratio calculating part is predefined value, when surpassing predefined value when the continuous predefined number of times of the frequency ratio of said frequencies ratio calculating part thereafter, generate Restart Signal.
8. timing extraction device according to claim 1 is characterized in that:
Above-mentioned control part,
When the enabling signal of having imported the processing of resetting or Restart Signal, set the branch frequency of above-mentioned clock generating unit so that the output clock frequency of above-mentioned clock generating unit is not less than predefined frequency.
9. timing extraction device according to claim 1 is characterized in that:
Above-mentioned control part,
The frequency ratio that use is carried out the result of smoothing processing and said frequencies ratio calculating part to the phase place correction of above-mentioned phase place correction calculating part is calculated the playback cycle with respect to the above-mentioned clock generating unit in the playback cycle of above-mentioned replay signal, and it is outputed to above-mentioned pseudo-synchronous clock generating unit.
10. timing extraction device according to claim 1 is characterized in that:
Carried out with " 0 " and " 1 " at the output sequence to above-mentioned quantization device under the situation of 2 values processing, the continuous ratio in " 0 " of above-mentioned AD HOC and " 1 " is 14: 4 or 4: 14 when the medium that records above-mentioned record data is DVD-ROM/RAM; Be 11: 11 when the medium that records above-mentioned record data is CD; Be 2: 9: 9 or 9: 9: 2 when the medium that records above-mentioned record data is Blu-ray.
11. timing extraction device according to claim 1 is characterized in that:
When the appearance of the above-mentioned AD HOC of the output sequence of above-mentioned quantization device is measured with the replay rate of above-mentioned replay signal at interval, be 1488 during for DVD-ROM/RAM at the medium that records above-mentioned record data; Be 588 when the medium that records above-mentioned record data is CD; Be 1932 when the medium that records above-mentioned record data is Blu-ray.
12. timing extraction device according to claim 1 is characterized in that:
In the output of above-mentioned quantization device, be connected with the offset correction device of the skew that is used for revising the output that is included in above-mentioned quantization device,
Said frequencies ratio calculating part and above-mentioned phase place correction calculating part replace the output of above-mentioned quantization device and use the output of above-mentioned offset correction device to carry out work.
13. timing extraction device according to claim 1 is characterized in that:
In the output of above-mentioned quantization device, be connected with the Waveform equalizing device of wave shape equalization that output clock based on above-mentioned clock generating unit carries out the output of above-mentioned quantization device,
Said frequencies ratio calculating part and above-mentioned phase place correction calculating part replace the output of above-mentioned quantization device and use the output of above-mentioned Waveform equalizing device to carry out work.
14. timing extraction device according to claim 1 is characterized in that:
In the input of above-mentioned quantization device, be connected with the analog filter that the wave shape equalization of carrying out above-mentioned replay signal or high frequency noise are removed processing,
According to the output of above-mentioned control part is that the branch frequency of above-mentioned clock generating unit changes the equalization characteristic of above-mentioned analog filter or cut-off characteristics.
15. timing extraction device according to claim 1 is characterized in that:
The output of above-mentioned control part is that the branch frequency of above-mentioned clock generating unit is made of integral part and fraction part,
Above-mentioned clock generating unit is the frequency synthesizer that can carry out fraction division control.
16. an information reproducing device is characterized in that, comprising:
The described timing extraction device of claim 1; With
Signal processing circuit based on the output that is included in the pseudo-synchronous clock generating unit in the above-mentioned timing extraction device, is deciphered the above-mentioned data from the output that is included in the quantization device in the above-mentioned timing extraction device.
17. a DVD device is characterized in that, comprising:
The described timing extraction device of claim 1; With
Signal processing circuit based on the output that is included in the pseudo-synchronous clock generating unit in the above-mentioned timing extraction device, is deciphered the above-mentioned data from the output that is included in the quantization device in the above-mentioned timing extraction device.
18. timing extraction device according to claim 1 is characterized in that:
Above-mentioned replay signal is via wireless communication line or comprise that the communication line of optical fiber, concentric cable or line of electric force provides.
19. timing extraction device according to claim 1 is characterized in that:
Above-mentioned replay signal is provided by the CD that comprises DVD CD, CD CD or Blu-ray CD.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2005341734 | 2005-11-28 | ||
| JP341734/2005 | 2005-11-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101069240A true CN101069240A (en) | 2007-11-07 |
Family
ID=38067003
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNA2006800013344A Pending CN101069240A (en) | 2005-11-28 | 2006-07-18 | Timing extraction device, and information reproduction apparatus and DVD device using the same |
Country Status (3)
| Country | Link |
|---|---|
| JP (1) | JP4124798B2 (en) |
| CN (1) | CN101069240A (en) |
| WO (1) | WO2007060765A1 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8059510B2 (en) | 2006-06-02 | 2011-11-15 | Panasonic Corporation | Information reproducing device |
| JP4837778B2 (en) * | 2007-04-05 | 2011-12-14 | パナソニック株式会社 | Reproduction signal processing device and video display device |
| JP2010211834A (en) * | 2007-06-29 | 2010-09-24 | Panasonic Corp | Information reproduced signal processing device |
| US8174949B2 (en) * | 2009-07-02 | 2012-05-08 | Lsi Corporation | Systems and methods for format efficient timing recovery in a read channel |
| JP5432271B2 (en) | 2009-09-15 | 2014-03-05 | ホーチキ株式会社 | smoke detector |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3368914B2 (en) * | 1992-03-19 | 2003-01-20 | 富士通株式会社 | Clock circuit and magnetic disk drive using the same |
| JP3477941B2 (en) * | 1994-11-25 | 2003-12-10 | ソニー株式会社 | Signal processing circuit of disc playback device |
| JPH08161829A (en) * | 1994-12-01 | 1996-06-21 | Canon Inc | Digital information reproducing device and digital pll device |
| JP3603025B2 (en) * | 1998-12-17 | 2004-12-15 | 松下電器産業株式会社 | Frequency control and phase locked loop |
| JP2002008315A (en) * | 2000-06-22 | 2002-01-11 | Matsushita Electric Ind Co Ltd | Optical disk device |
| JP3609721B2 (en) * | 2000-12-19 | 2005-01-12 | 株式会社東芝 | Digital data reproducing apparatus and digital data reproducing method |
-
2006
- 2006-07-18 JP JP2006552389A patent/JP4124798B2/en not_active Expired - Fee Related
- 2006-07-18 CN CNA2006800013344A patent/CN101069240A/en active Pending
- 2006-07-18 WO PCT/JP2006/314171 patent/WO2007060765A1/en active Application Filing
Also Published As
| Publication number | Publication date |
|---|---|
| WO2007060765A1 (en) | 2007-05-31 |
| JP4124798B2 (en) | 2008-07-23 |
| JPWO2007060765A1 (en) | 2009-05-07 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101069240A (en) | Timing extraction device, and information reproduction apparatus and DVD device using the same | |
| CN1163894C (en) | Frequence control/phase synchronizing circuit | |
| CN1359231A (en) | Audio signal reproducing method and apparatus without changing tone in fast or slow speed replaying mode | |
| CN1542825A (en) | BCA code extraction method and related device | |
| CN1366736A (en) | Compression method and device, decompression method and device, compression/decompression system, and recorded medium | |
| JP3596827B2 (en) | Digital PLL circuit | |
| CN1227661C (en) | Method and device for modulating and demodulating data | |
| CN1397940A (en) | Tracking error detector | |
| CN1165050C (en) | Message recording method and apparatus | |
| JP4630334B2 (en) | Timing extraction device and video display device | |
| CN1479274A (en) | Method and device for correcting read error by reconery disk drive | |
| CN1917376A (en) | Modulating apparatus and method, and dsv control bit producing method | |
| CN1217325C (en) | Recording/reproducing device | |
| CN1288850C (en) | Demodulating circuit, CD apparatus and semiconductor integrated circuit | |
| CN1138270C (en) | Recording and reproduction of information signal in/from track on record carrier | |
| CN1866362A (en) | Methods for tuning write strategy parameters utilizing data-to-clock edge deviations, and systems thereof | |
| CN1208766C (en) | Device and method for determining differences between phase referrence signal and oscillation signals | |
| CN1229782C (en) | Reproducing method and device | |
| CN1167075C (en) | Disk play machine | |
| CN1497580A (en) | Oscillation demodulator and oscillation demodulation method | |
| CN1650365A (en) | Data reproducing apparatus having phase difference corrector and data head detector | |
| CN1542835A (en) | Method and apparatus for detecting SYNC mark in a disk drive | |
| CN1143807A (en) | Rotation control circuit based on mean value of run length code generation patterns and reproducing apparatus equipped with rotation control circuit | |
| CN1145934C (en) | Information recording method and apparatus | |
| CN1627380A (en) | Optical disc apparatus, clock signal generation method, program, and control apparatus |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C02 | Deemed withdrawal of patent application after publication (patent law 2001) | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Open date: 20071107 |