CN101060644A - A high-speed space division cyclic selection circuit and its realizing method - Google Patents
A high-speed space division cyclic selection circuit and its realizing method Download PDFInfo
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- CN101060644A CN101060644A CN 200610076285 CN200610076285A CN101060644A CN 101060644 A CN101060644 A CN 101060644A CN 200610076285 CN200610076285 CN 200610076285 CN 200610076285 A CN200610076285 A CN 200610076285A CN 101060644 A CN101060644 A CN 101060644A
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Abstract
The disclosed HS cycle selection circuit comprises: connecting M-path inputs with input port o and port 1 of X-class base unit X1-Xk; cycle shifting one path of X1-Xk output ports to connect with Y-class basic unit Y1-Yk; deciding whether current end unit output path equal to N; yes to end the process; or else, taking current end unit as local-class unit, setting next unit behind this unit, selecting multiple paths from A and B ports to connect with next-class unit, ensuring any port of next unit selecting superior unit for output, and back to last step. This invention realizes selecting N from M arbitrarily, reduces PCB area and cost, and improves system reliability.
Description
Technical field
The present invention relates to a kind of high-speed space division cyclic selection circuit and its implementation, relate in particular to the high-speed space division cyclic selection circuit that uses in electronic data processing field (G06) and the electric communication technique field (H04).
Background technology
Base station BS (Base Station) up direction at TD-SCDMA, the antenna feeder radiofrequency signal is after rf board RB (RF Board) handles, its IQ signal is distributed to baseband board BB (Baseband Board) by power board SB (Switching Board) exchange, carries out Base-Band Processing again.Descending then opposite.In same base station BS, has polylith rf board RB, polylith power board SB and polylith baseband board BB.Therefore, how to realize the up-downgoing exchanges data of any RB and BB, be a major issue always, need study in great detail at everyways such as complete machine cost, reliability, maintainability, exchange efficiencies.In addition, the various test macros towards RB/SB/BB also are faced with same problem.
Existing IQ handshaking uses 2*2 high speed (greater than 500MHz) cross chips as base unit, as Fig. 1.
Fig. 1 is a 2*2 high speed cross chips.Port 0 and port one are input ports, and port A and port B are output ports, and port SA and port SB select port.When port SA (or SB) was low level, port A (or B) and port 0 were straight-through; When port SA (or SB) was high level, port A (or B) and port one were straight-through.Its truth table is as follows:
| Port SA | Port SB | Port A | Port B | Note | |
| Low | | Port | 0 | | One-to-two |
| Low | | Port | 0 | Port one | Transmit |
| High | Low | Port one | | Intersect | |
| High | High | Port one | Port one | One-to-two |
The circuit of its realization is as follows:
Realize that any 4 select 2 circuit as shown in Figure 3, at first, the 4 tunnel import into the back one-to-two becomes 8 the tunnel; Each 4 the tunnel realizes that separately 4 select 1 again; Thereby realized that any 4 select 2.Consume 10 base units altogether.
Realize that any 6 select 2 circuit as shown in Figure 5, the 6 tunnel import into the back one-to-two becomes 12 the tunnel; Each 6 the tunnel realizes that separately 6 select 1 again; Thereby realized that any 6 select 2.Consume 16 base units altogether.
Realize that any 8 select 2 circuit as shown in Figure 7, the 8 tunnel import into the back one-to-two becomes 16 the tunnel; Each 8 the tunnel realizes that separately 8 select 1 again; Thereby realized that any 8 select 2.Consume 22 base units altogether.
Above as can be seen 4 select 2,6 to select 2 and 8 to select 2 circuit to need 10,16,22 base units respectively.Inverse process is then opposite.Because the base unit of its use is too much, the IQ exchange efficiency is low, cost is high, maintainability is poor.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of implementation method of high-speed space division cyclic selection circuit, can so that to high-speed space division cyclic selection circuit the chip service efficiency, reduce the PCB area, reduce cost, improve system reliability.
In order to solve the problems of the technologies described above, the invention provides a kind of implementation method of high-speed space division cyclic selection circuit, this high-speed space division cyclic selection circuit is used to realize that any M selects the N function, and wherein M is the input way, and N is the output way, and this method may further comprise the steps:
(a) input of M road inserts X level base unit X respectively
1-X
kInput port 0 and port one;
(b) X
1-X
kOutput port A and port B respectively cyclic shift one road and Y level elementary cell Y
1-Y
kInput port 0 link to each other with port one, Y level elementary cell is current final stage elementary cell;
(c) judge whether the way that current final stage elementary cell is exported is N, if, obtain required any M and selected the N circuit, otherwise, next step carried out;
(d) present final stage elementary cell is considered as elementary cell at the corresponding levels, be provided with thereafter the next stage elementary cell with it as new final stage elementary cell, from the output port A of elementary cell at the corresponding levels and port B, select multichannel and be connected to its next stage elementary cell, and guarantee that can choose any one tunnel of its upper level elementary cell at the arbitrary port of this next stage elementary cell exports, and returns step (C).
Further, above-mentioned implementation method also can have following characteristics: described elementary cell is a 2*2 high speed cross chips, and each chip all has a pair of selection logic.
Further, above-mentioned implementation method also can have following characteristics: when described step (b) is carried out cyclic shift, be with X
1-X
kOutput port A respectively and Y
1-Y
kInput port 1 link to each other X
1-X
K-1Output port B respectively and Y
2-Y
kInput port 0 link to each other X
kOutput port B and Y
1Input port 0 link to each other; Perhaps, be with X
1-X
kOutput port B respectively and Y
1-Y
kInput port 0 link to each other X
2-X
kOutput port A respectively and Y
1-Y
K-1Input port 1 link to each other X
1Output port A and Y
kInput port 1 link to each other.
Further, above-mentioned implementation method also can have following characteristics: described step (d) when elementary cell at the corresponding levels is connected with the next stage elementary cell, a kind of or combination in any in the following ways:
A select 4 the tunnel arbitrarily from the output port A of 3 elementary cells of the corresponding levels and port B, but each elementary cell will select 1 the tunnel at least, then same next stage base unit is linked in 2 tunnel outputs on same base unit at the corresponding levels not;
B selects 1 the tunnel arbitrarily from the output port A of 4 elementary cells of the corresponding levels and port B, the output of non-conterminous 2 these unit of roadbed in 4 tunnel outputs is connected to same next stage base unit;
C, optional one the tunnel directly exports from 2 elementary cells at the corresponding levels, as final N road output, perhaps selects with the output of next stage elementary cell again.
The another technical problem that the present invention will solve provides a kind of high-speed space division cyclic selection circuit, can improve the chip service efficiency, reduces the PCB area, reduce cost, improves system reliability.
In order to solve the problems of the technologies described above, the invention provides a kind of high-speed space division cyclic selection circuit, be used to realize that any M selects the N function, wherein M is the input way, N is the output way, is characterized in:
The input of M road inserts X level base unit X respectively
1-X
kInput port 0 and port one; X
1-X
kOutput port A and port B respectively cyclic shift one road and Y level elementary cell Y
1-Y
kInput port 0 link to each other with port one; From Y level elementary cell, from the output port A of elementary cell at the corresponding levels and port B, select multichannel and be connected to its next stage elementary cell, and guaranteeing that can choose any one tunnel of its upper level elementary cell at the arbitrary port of this next stage elementary cell exports, its final stage has the output of N road.
Further, above-mentioned high-speed space division cyclic selection circuit also can have following characteristics: described elementary cell is a 2*2 high speed cross chips, and each chip all has a pair of selection logic.
Further, above-mentioned high-speed space division cyclic selection circuit also can have following characteristics: when described elementary cell at the corresponding levels is connected with the next stage elementary cell, adopt a kind of or combination in any in the following circuit:
A select 4 the tunnel arbitrarily from the output port A of 3 elementary cells of the corresponding levels and port B, but each elementary cell will select 1 the tunnel at least, then same next stage base unit is linked in 2 tunnel outputs on same base unit at the corresponding levels not;
B selects 1 the tunnel arbitrarily from the output port A of 4 elementary cells of the corresponding levels and port B, the output of non-conterminous 2 these unit of roadbed in 4 tunnel outputs is connected to same next stage base unit;
C, optional one the tunnel directly exports from 2 elementary cells at the corresponding levels, as final N road output, perhaps selects with the output of next stage elementary cell again.
Further, above-mentioned high-speed space division cyclic selection circuit also can have following characteristics: described final stage has N elementary cell, and optional 1 rood is exported to described N road in the output port of this N elementary cell respectively.
Further, above-mentioned high-speed space division cyclic selection circuit also can have following characteristics: described X
1-X
kOutput port A and port B respectively cyclic shift one road and Y level elementary cell Y
1-Y
kInput port 0 when linking to each other with port one, be with X
1-X
kOutput port A respectively and Y
1-Y
kInput port 1 link to each other X
1-X
K-1Output port B respectively and Y
2-Y
kInput port 0 link to each other X
kOutput port B and Y
1Input port 0 link to each other; Perhaps, be with X
1-X
kOutput port B respectively and Y
1-Y
kInput port 0 link to each other X
2-X
kOutput port A respectively and Y
1-Y
K-1Input port 1 link to each other X
1Output port A and Y
kInput port 1 link to each other.
Provided by the invention any 4 select 2 high-speed space division cyclic selection circuit to comprise 2 X level elementary cell X1, X2 and 2 Y level elementary cell Y1, Y2,4 tunnel inputs insert input port 0 and the port one of base unit X1 and X2 respectively, the output port A of X1 and X2 links to each other with port one with the input port 0 of port B difference cyclic shift one road and Y1 and Y2, chooses 1 the tunnel respectively wantonly as output in the output port of Y1 and Y2.
Provided by the invention any 6 select 2 high-speed space division cyclic selection circuit to comprise 3 X level elementary cell X1～X3,3 Y level elementary cell Y1～Y3, and 2 Z level elementary cell Z1～Z2; 6 tunnel inputs insert input port 0 and the port one of base unit X1, X2 and X3 respectively; The output port A of X1, X2 and X3 links to each other with port one with the input port 0 of port B difference cyclic shift one road and Y1, Y2 and Y3; Select 4 the tunnel arbitrarily among the output port A of Y1, Y2 and Y3 and the port B, but each elementary cell will select 1 the tunnel at least, same Z level base unit is linked on the same Y level base unit 2 tunnel output, chooses 1 the tunnel respectively wantonly as output in the output port of Z1 and Z2.
Provided by the invention any 8 select 2 high-speed space division cyclic selection circuit to comprise 4 X level elementary cell X1～X4,4 Y level elementary cell Y1～Y4, and 2 Z level elementary cell Z1～Z2; 8 tunnel inputs insert input port 0 and the port one of base unit X1, X2, X3 and X4 respectively; The output port A of X1, X2, X3 and X4 links to each other with port one with the input port 0 of port B difference cyclic shift one road and Y1, Y2, Y3 and Y4; Select 1 the tunnel arbitrarily among the output port A of Y1, Y2, Y3 and Y4 and the port B, the output of non-conterminous 2 these unit of roadbed in 4 tunnel outputs is connected to same Z level base unit, in the output port of Z1 and Z2, choose 1 the tunnel respectively wantonly as output.
As can be seen, a kind of high-speed space division cyclic selection circuit that the present invention proposes is on the basis of existing 2*2 high speed cross chips, level is selected to support after utilizing the secondary cycles topological sum, compared with prior art, the chip utilance has improved more than 100%, has reduced PCB area cost and device cost, has improved the reliability and maintainability of system.Reached the purpose of high efficiency, low cost, high reliability.
Description of drawings
Fig. 1 is the schematic diagram of 2*2 high speed cross chips.
Fig. 2 is the circuit diagram that any M of the present invention selects an example of N scheme
Fig. 3 is the circuit diagram that any 4 of prior art is selected 2 schemes.
Fig. 4 of the present invention any 4 selects the circuit diagram of an example of 2 schemes.
Fig. 5 is the circuit diagram that any 6 of prior art is selected 2 schemes.
Fig. 6 of the present invention any 6 selects the circuit diagram of an example of 2 schemes.
Fig. 7 is the circuit diagram that any 8 of prior art is selected 2 schemes.
Fig. 8 of the present invention any 8 selects the circuit diagram of an example of 2 schemes.
Fig. 9 of the present invention any 12 selects the circuit diagram of an example of 2 schemes.
Figure 10 of the present invention any 12 selects the circuit diagram of another example of 2 schemes.
Figure 11 is an application example of the present invention.
Embodiment
Core concept of the present invention is: on the basis of existing base unit (2*2 high speed cross chips), utilize behind the secondary cycles topological sum level to select to support, improve the data efficiency of selection.So-called empty the branch, refer to non-bus mode, in other words conj.or perhaps point-to-point mode.
Fig. 4 realizes that any 4 select an example of the circuit of 2 schemes, and circuit comprises 2 X level elementary cell X1, X2 and 2 Y level elementary cell Y1, Y2 as shown in Figure 4.
A kind of mode of cyclic shift is: the output port A of X1～X2 links to each other with the input port 1 of Y1～Y2 respectively, and the output port B of X1 and the input port 0 of Y2 link to each other, and the output port B of X2 and the input port 0 of Y1 link to each other.Certainly, by another sequence, the output port A of X1～X2 is linked to each other with the input port 1 of Y2～Y1 respectively, the output port B of X1 and the input port 0 of Y1 are linked to each other, it also is the same that the output port B of X2 and the input port 0 of Y2 link to each other.
Step 3 selects 1 the tunnel arbitrarily respectively from the output port of Y1 and Y2.
So just finished any 4 and selected 2 circuit, for example, when 0 tunnel of X1 will be from the output of the A road of Y1, route was X1:0 → X1:A → Y1:1 → Y1:A, and other any inputs can be from the A road output of Y2, such as X1:1 → X1:B → Y2:0 → Y2:A.Other situations similarly.This circuit consumes 4 base units altogether.
This circuit has only been used 4 base units, compares with Fig. 3 and has saved 60% resource.Select any 4 one tunnel input of 2 circuit need not obtain any 3 and select 2 circuit.
Fig. 6 realizes that any 6 select an example of the circuit of 2 schemes, circuit as shown in the figure:
A kind of mode of cyclic shift is: the output port A of X1～X3 links to each other with the input port 1 of Y1～Y3 respectively, and the output port B of X1～X2 links to each other with the input port 0 of Y2～Y3 respectively, and the output port B of X3 and the input port 0 of Y1 link to each other.Also another kind of endless form can be arranged.
Step 3 select 4 the tunnel arbitrarily from the output port A of Y1, Y2 and Y3 and port B, but each elementary cell will select 1 the tunnel at least, more same Z level base unit is linked in 2 tunnel outputs on same Y level base unit not, such as the connection of Fig. 6;
Step 4 selects 1 the tunnel arbitrarily respectively from the output port of Z1 and Z2.
So just finished any 6 and selected 2 circuit, for example: when 0 road during of X1 from the output of the A road of Z1, route is X1:0 → X1:A → Y1:1 → Y1:A → Z1:0 → Z1:A, and other any inputs can be from the A road output of Z2, such as X1:1 → X1:B → Y2:0 → Y2:B → Z2:0 → Z2:A.This circuit has only been used 8 base units, compares with Fig. 5 and has saved 50% resource.Select any 6 one tunnel input of 2 circuit need not obtain any 5 and select 2 circuit.
Fig. 8 realizes that any 8 select an example of the circuit of 2 schemes, circuit as shown in the figure:
A kind of mode of cyclic shift is: the output port A of X1～X4 links to each other with the input port 1 of Y1～Y4 respectively, and the output port B of X1～X3 links to each other with the input port 0 of Y2～Y4 respectively, and the output port B of X4 and the input port 0 of Y1 link to each other.Also another kind of endless form can be arranged
Step 3, from the output port A of Y1, Y2, Y3 and Y4 and port B, select 1 the tunnel arbitrarily respectively, the output of non-conterminous 2 these unit of roadbed in 4 tunnel outputs is connected to same Z level base unit, same Z level base unit is linked in 2 tunnel outputs that are Y1 and Y3, same Z level base unit is linked in 2 tunnel outputs of Y2 and Y4, such as the connection of Fig. 8.
Step 4 selects 1 the tunnel arbitrarily respectively from the output port of Z1 and Z2.
So just finished any 8 and selected 2 circuit, for example: when 0 road during of X1 from the output of the A road of Z1, route is X1:0 → X1:A → Y1:1 → Y1:A → Z1:0 → Z1:A, and other any inputs can be from the A road output of Z2, such as X3:0 → X3:B → Y4:0 → Y4:B → Z2:1 → Z2:A.Other situations similarly.Consume 10 base units altogether, compare with Fig. 7 and saved 55% resource.Select any 8 one tunnel input of 2 circuit need not obtain any 7 and select 2 circuit.
Fig. 9 realizes that any 12 select an example of the circuit of 2 schemes, circuit as shown in the figure:
A kind of mode of cyclic shift is: the output port A of X1～X6 links to each other with the input port 1 of Y1～Y6 respectively, and the output port B of X1～X5 links to each other with the input port 0 of Y2～Y6 respectively, and the output port B of X6 and the input port 0 of Y1 link to each other.
Step 3, from the output port A of Y1, Y2 and Y3 and port B, select 4 the tunnel arbitrarily, but each elementary cell will select 1 the tunnel at least, not linking on same Z level base unit Z1 and the Z2, adopt the output port that uses the same method Y4, Y5, Y6 and be connected with Z4 again with Z3 in the output of 2 tunnel on the same Y level base unit;
Step 4, from the output port A of Z1～Z4 and port B, select 1 the tunnel arbitrarily respectively, same Z ' level base unit is linked in the output of non-conterminous 2 these unit of roadbed, same Z ' level base unit is linked in 2 tunnel outputs that are Z1 and Z3, same Z ' level base unit is linked in 2 tunnel outputs of Z2 and Z4, such as the connection of Fig. 9;
Step 5 selects 1 the tunnel arbitrarily respectively from the output port of Z ' 1 and Z ' 2.
So just finished any 12 and selected 2 circuit, consumed 18 base units altogether, compared with prior art, also saved resource above 50%.Select any 12 one tunnel input of 2 circuit need not obtain any 11 and select 2 circuit.Select any 12 one tunnel input of 2 circuit need not obtain any 11 and select 2 circuit.
This any 12 selects 2 circuit to have 4 grades, X level, Y level, Z level and Z ' level, adopt cyclic shift to connect between the two-stage, for the later connection of second level output, earlier to 2 groups, 4 tunnel outputs of 3 every group Y level elementary cell, all realize that by the next stage elementary cell 4 select 2, any 6 to select the circuit after the output of 2 circuit Y levels be the same among this part circuit and Fig. 6, promptly is provided with the elementary cell of 2 next stage (being the Z level) here, and annexation no longer repeats.Then, 4 tunnel outputs for 4 elementary cells of Z level, elementary cell by next stage realizes selecting 2 one time 4 again, any 8 to select the circuit after the output of 2 circuit Y levels be the same among this part circuit and Fig. 8, also be provided with 2 next stage (being Z ' level) elementary cell here, annexation also not too repeats.
What pay special attention to is, in the epimere and other place is mentioned in the literary composition 4 selects 2 to be not to be meant that any 4 among Fig. 4 selects 2, but refer in particular to the second level and the second level 4 tunnel outputs of 3 or 4 elementary cells of other grade later on, by with obtain being connected of next stage elementary cell 2 the tunnel output, certainly this 2 tunnel output can be any one tunnel in previous stage 4 tunnel outputs, for this partial circuit, if 4 tunnel outputs of 3 elementary cells, its structure can adopt any 6 circuit that select after 2 circuit Y levels are exported among Fig. 6, if 4 tunnel outputs of 4 elementary cells, its structure can adopt any 8 circuit that select after 2 circuit Y levels are exported among Fig. 8.
But this connected mode is not unique.Figure 10 realizes that any 12 select another example of the circuit of 2 schemes, circuit as shown in the figure:
Step 3 selects 1 the tunnel arbitrarily from the output port A of Y1～Y4 and port B, same Z level base unit Z1 is linked in 2 tunnel outputs of Y1 and Y3, and same Z level base unit Z2 is linked in 2 tunnel outputs of Y2 and Y4, simultaneously, selects 1 the tunnel arbitrarily from Y5 and Y6;
Step 4, from Z1 and Z2, choose 1 the tunnel arbitrarily, 4 tunnel outputs have been constituted jointly with 2 tunnel of Y5, Y6 output, non-conterminous 2 tunnel outputs in this 4 tunnel output are connected respectively to same Z ' level base unit, the output that is Z1 and Y5 is connected to Z ' 1, the output of Z2 and Y6 is connected to Z ' 2, such as the connection of Figure 10;
Step 5 selects 1 the tunnel arbitrarily respectively from the output port of Z ' level base unit Z ' 1 and Z ' 2.
That finishes like this any 12 selects 2 circuit only to consume 16 base units altogether.
This any 12 selects 2 circuit to have 4 grades, X level, Y level, Z level and Z ' level, adopt cyclic shift to connect between the two-stage, for the later connection of second level output, this circuit is equivalent to earlier 4 tunnel of one group of 4 elementary cell be exported, and is undertaken 4 by next stage (being the Z level) elementary cell here and selects 2.Two Y level elementary cells of another group then optional 1 the tunnel are directly exported, and realize selecting 2 one time 4 by next stage (Z ' grade) elementary cell with 2 tunnel outputs of Z level again.
In addition,, utilize the another port of each unit of the 2nd grade reciprocal so, be connected just passable with other 2 afterbody unit again by identical annexation if realize that any 12 select 4.
According to any 12 analyses of selecting 2 circuit, in like manner can release, select 2 circuit for one any 10, still adopt cyclic shift mode to connect between the first order and the second level, for the later connection of second level output, can be with 3 Y level elementary cells as one group, other 2 Y level elementary cells are organized as another, first group output realizes that by third level elementary cell 4 select 2 to obtain 2 tunnel outputs, second group then directly obtains 2 tunnel outputs, to these 4 tunnel outputs of 2 groups, undertaken one time 4 by fourth stage elementary cell and select 2 then.Can realize that any 10 select 2 function.Select 2 situation for 9, as long as 1 tunnel input need not be just passable.
For the situation of the input of multichannel more, select 2 as any 16, any 24 select 2 also to be the same, select in 2 as any 16,, be divided into 2 groups for the later connection of second level output, per 4 Y level elementary cells are 1 group, every group output realizes that by third level elementary cell 4 select 2 to obtain 2 tunnel outputs, again by fourth stage elementary cell to upper level totally 4 tunnel outputs carry out one time 4 and select 2, get final product.
Therefore, any M is selected the performing step of circuit of N as follows, please refer to the circuit among Fig. 2:
Steps A, the input of M road inserts base unit (2*2 high speed cross chips) X respectively
1-X
kInput port 0 and port one;
Step B, X
1-X
kOutput port A and port B respectively cyclic shift one road and Y
1-Y
kInput port 0 link to each other with port one, with Y level elementary cell as the present elementary cell of afterbody;
A kind of mode of cyclic shift is X
1-X
kOutput port A respectively and Y
1-Y
kInput port 1 link to each other X
1-X
K-1Output port B respectively and Y
2-Y
kInput port 0 link to each other X
kOutput port B and Y
1Input port 0 link to each other.
Another kind is: X
1-X
kOutput port B respectively and Y
1-Y
kInput port 0 link to each other X
2-X
kOutput port A respectively and Y
1-Y
K-1Input port 1 link to each other X
1Output port A and Y
kInput port 1 link to each other.
Step C judges whether the way of current final stage elementary cell output is N, if, obtain required any M and selected the N circuit, otherwise, next step carried out;
Step D, present final stage elementary cell is considered as elementary cell at the corresponding levels, the next stage elementary cell is set thereafter again, this newly-installed elementary cell becomes new final stage elementary cell, from the output port A of elementary cell at the corresponding levels and port B, select multichannel and be connected to its next stage elementary cell, and guarantee that can choose any one tunnel of its upper level elementary cell at the arbitrary port of this next stage elementary cell exports, and returns step C.
The setting of next stage elementary cell is be connected can be by the following way in the top example:
As from 3 elementary cells at the corresponding levels, selecting 4 tunnel outputs, realize that by the next stage elementary cell 4 select 2, promptly 2 elementary cells are set at next stage, from the output port A of 3 elementary cells of the corresponding levels and port B, select 4 the tunnel arbitrarily, but each elementary cell will select 1 the tunnel at least, then same next stage base unit is linked in 2 tunnel outputs on same base unit at the corresponding levels not.
Perhaps select 4 tunnel outputs from 4 elementary cells at the corresponding levels, realize that by the next stage elementary cell 4 select 2, be that the third level is provided with 2 elementary cells, from the output port A of 4 elementary cells at the corresponding levels and port B, select 1 the tunnel arbitrarily respectively, the output of non-conterminous 2 these unit of roadbed in 4 tunnel outputs is connected to same next stage base unit.
Also having a kind of is to choose one the tunnel wantonly directly to export from 2 elementary cells at the corresponding levels, perhaps as final N road output, perhaps selects with the output of next stage elementary cell again.
Can see, owing to have certain selection arbitrariness in the step, so actual circuit is not unique, but not from its essence.
What pay particular attention to is, during specific implementation of the present invention, and need be in conjunction with selection logic SA and the SB of Fig. 1.Each base unit all has a pair of selection logic.
Flexibility of the present invention is to be not limited to above 3 kinds of selection situations, can draw other situations that any M selects N under the prerequisite that does not change essence of the present invention.
Flexibility of the present invention is that also for a certain selection situation, final scheme is not unique, can be under the guide of core concept, in conjunction with concrete wiring concrete decision.
Flexibility of the present invention also is, for a certain selection situation, the realization of its inverse process (select 2 for any 8, any exactly 2 select 8) can be released easily, promptly adopts identical circuit.
Elementary cell of the present invention also has other selection, as 4*4 high speed cross chips or more, but cost performance reasonable be 2*2 high speed cross chips.
Enforcement below in conjunction with a simple application example technical scheme of the present invention among Figure 11 is described in further detail again:
Suppose that the IQ link that 6 baseband board BB (BB0-BB5) are arranged needs to detect, each BB have 2 road IQ (link BBx_0 and BBx_1, x=0 ..., 5), therefore have 12 IQ links.Test board TB wishes that 2 blocks of BB plates can at a time choosing wantonly wherein detect and analyze.According to the present invention, selected method as Figure 11, promptly two " any 6 select 2 " is parallel, consumes 16 base units altogether.And original method needs 32 base units, so saved 50% resource.
Though describe embodiments of the invention in conjunction with the accompanying drawings in detail,, still can modify and do not change the spirit and scope of the invention to above-mentioned execution mode for those skilled in the art.
Claims (12)
1, a kind of implementation method of high-speed space division cyclic selection circuit, this high-speed space division cyclic selection circuit are used to realize that any M selects the N function, and wherein M is the input way, and N is the output way, and this method may further comprise the steps:
(a) input of M road inserts X level base unit X respectively
1-X
kInput port 0 and port one;
(b) X
1-X
kOutput port A and port B respectively cyclic shift one road and Y level elementary cell Y
1-Y
kInput port 0 link to each other with port one, Y level elementary cell is current final stage elementary cell;
(c) judge whether the way that current final stage elementary cell is exported is N, if, obtain required any M and selected the N circuit, otherwise, next step carried out;
(d) present final stage elementary cell is considered as elementary cell at the corresponding levels, be provided with thereafter the next stage elementary cell with it as new final stage elementary cell, from the output port A of elementary cell at the corresponding levels and port B, select multichannel and be connected to its next stage elementary cell, and guarantee that can choose any one tunnel of its upper level elementary cell at the arbitrary port of this next stage elementary cell exports, and returns step (c).
2, implementation method as claimed in claim 1 is characterized in that, described elementary cell is a 2*2 high speed cross chips, and each chip all has a pair of selection logic.
3, implementation method as claimed in claim 1 is characterized in that, when described step (b) is carried out cyclic shift, is with X
1-X
kOutput port A respectively and Y
1-Y
kInput port 1 link to each other X
1-X
K-1Output port B respectively and Y
2-Y
kInput port 0 link to each other X
kOutput port B and Y
1Input port 0 link to each other; Perhaps, be with X
1-X
kOutput port B respectively and Y
1-Y
kInput port 0 link to each other X
2-X
kOutput port A respectively and Y
1-Y
K-1Input port 1 link to each other X
1Output port A and Y
kInput port 1 link to each other.
4, implementation method as claimed in claim 1 is characterized in that, described step (d) when elementary cell at the corresponding levels is connected with the next stage elementary cell, a kind of or combination in any in the following ways:
A select 4 the tunnel arbitrarily from the output port A of 3 elementary cells of the corresponding levels and port B, but each elementary cell will select 1 the tunnel at least, then same next stage base unit is linked in 2 tunnel outputs on same base unit at the corresponding levels not;
B selects 1 the tunnel arbitrarily from the output port A of 4 elementary cells of the corresponding levels and port B, the output of non-conterminous 2 these unit of roadbed in 4 tunnel outputs is connected to same next stage base unit;
C, optional one the tunnel directly exports from 2 elementary cells at the corresponding levels, as final N road output, perhaps selects with the output of next stage elementary cell again.
5, a kind of high-speed space division cyclic selection circuit is used to realize that any M selects the N function, and wherein M is the input way, and N is the output way, it is characterized in that:
The input of M road inserts X level base unit X respectively
1-X
kInput port 0 and port one; X
1-X
kOutput port A and port B respectively cyclic shift one road and Y level elementary cell Y
1-Y
kInput port 0 link to each other with port one; From Y level elementary cell, from the output port A of elementary cell at the corresponding levels and port B, select multichannel and be connected to its next stage elementary cell, and guaranteeing that can choose any one tunnel of its upper level elementary cell at the arbitrary port of this next stage elementary cell exports, its final stage has the output of N road.
6, high-speed space division cyclic selection circuit as claimed in claim 5 is characterized in that, described elementary cell is a 2*2 high speed cross chips, and each chip all has a pair of selection logic.
7, high-speed space division cyclic selection circuit as claimed in claim 5 is characterized in that, when described elementary cell at the corresponding levels is connected with the next stage elementary cell, adopts a kind of or combination in any in the following circuit:
A select 4 the tunnel arbitrarily from the output port A of 3 elementary cells of the corresponding levels and port B, but each elementary cell will select 1 the tunnel at least, then same next stage base unit is linked in 2 tunnel outputs on same base unit at the corresponding levels not;
B selects 1 the tunnel arbitrarily from the output port A of 4 elementary cells of the corresponding levels and port B, the output of non-conterminous 2 these unit of roadbed in 4 tunnel outputs is connected to same next stage base unit;
C, optional one the tunnel directly exports from 2 elementary cells at the corresponding levels, as final N road output, perhaps selects with the output of next stage elementary cell again.
8, high-speed space division cyclic selection circuit as claimed in claim 5 is characterized in that, described final stage has N elementary cell, and optional 1 rood is exported to described N road in the output port of this N elementary cell respectively.
9, implementation method as claimed in claim 5 is characterized in that, described X
1-X
kOutput port A and port B respectively cyclic shift one road and Y level elementary cell Y
1-Y
kInput port 0 when linking to each other with port one, be with X
1-X
kOutput port A respectively and Y
1-Y
kInput port 1 link to each other X
1-X
K-1Output port B respectively and Y
2-Y
kInput port 0 link to each other X
kOutput port B and Y
1Input port 0 link to each other; Perhaps, be with X
1-X
kOutput port B respectively and Y
1-Y
kInput port 0 link to each other X
2-X
kOutput port A respectively and Y
1-Y
K-1Input port 1 link to each other X
1Output port A and Y
kInput port 1 link to each other.
10, a kind of any 4 select 2 high-speed space division cyclic selection circuit, it is characterized in that, comprise 2 X level elementary cell X1, X2 and 2 Y level elementary cell Y1, Y2,4 tunnel inputs insert input port 0 and the port one of base unit X1 and X2 respectively, the output port A of X1 and X2 links to each other with port one with the input port 0 of port B difference cyclic shift one road and Y1 and Y2, chooses 1 the tunnel respectively wantonly as output in the output port of Y1 and Y2.
11, a kind of any 6 select 2 high-speed space division cyclic selection circuit, it is characterized in that, comprise 3 X level elementary cell X1～X3,3 Y level elementary cell Y1～Y3, and 2 Z level elementary cell Z1～Z2; 6 tunnel inputs insert input port 0 and the port one of base unit X1, X2 and X3 respectively; The output port A of X1, X2 and X3 links to each other with port one with the input port 0 of port B difference cyclic shift one road and Y1, Y2 and Y3; Select 4 the tunnel arbitrarily among the output port A of Y1, Y2 and Y3 and the port B, but each elementary cell will select 1 the tunnel at least, same Z level base unit is linked on the same Y level base unit 2 tunnel output, chooses 1 the tunnel respectively wantonly as output in the output port of Z1 and Z2.
12, a kind of any 8 select 2 high-speed space division cyclic selection circuit, it is characterized in that, comprise 4 X level elementary cell X1～X4,4 Y level elementary cell Y1～Y4, and 2 Z level elementary cell Z1～Z2; 8 tunnel inputs insert input port 0 and the port one of base unit X1, X2, X3 and X4 respectively; The output port A of X1, X2, X3 and X4 links to each other with port one with the input port 0 of port B difference cyclic shift one road and Y1, Y2, Y3 and Y4; Select 1 the tunnel arbitrarily among the output port A of Y1, Y2, Y3 and Y4 and the port B, the output of non-conterminous 2 these unit of roadbed in 4 tunnel outputs is connected to same Z level base unit, in the output port of Z1 and Z2, choose 1 the tunnel respectively wantonly as output.
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| CNB2006100762852A CN100562140C (en) | 2006-04-21 | 2006-04-21 | A kind of high-speed space division cyclic selection circuit and its implementation |
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| CNB2006100762852A CN100562140C (en) | 2006-04-21 | 2006-04-21 | A kind of high-speed space division cyclic selection circuit and its implementation |
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| CN100562140C CN100562140C (en) | 2009-11-18 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102404849A (en) * | 2010-09-16 | 2012-04-04 | 中兴通讯股份有限公司 | Method for realizing baseband resource allocation in base station machine frame and system for realizing baseband resource allocation in base station machine frame |
| CN105827258A (en) * | 2016-05-09 | 2016-08-03 | 中国电子科技集团公司第三十八研究所 | Multi-channel receiving system |
-
2006
- 2006-04-21 CN CNB2006100762852A patent/CN100562140C/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102404849A (en) * | 2010-09-16 | 2012-04-04 | 中兴通讯股份有限公司 | Method for realizing baseband resource allocation in base station machine frame and system for realizing baseband resource allocation in base station machine frame |
| CN102404849B (en) * | 2010-09-16 | 2014-12-10 | 中兴通讯股份有限公司 | Method for realizing baseband resource allocation in base station machine frame and system for realizing baseband resource allocation in base station machine frame |
| CN105827258A (en) * | 2016-05-09 | 2016-08-03 | 中国电子科技集团公司第三十八研究所 | Multi-channel receiving system |
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| Publication number | Publication date |
|---|---|
| CN100562140C (en) | 2009-11-18 |
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