CN101059948A - Active component array baseplate - Google Patents
Active component array baseplate Download PDFInfo
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- CN101059948A CN101059948A CN 200710103828 CN200710103828A CN101059948A CN 101059948 A CN101059948 A CN 101059948A CN 200710103828 CN200710103828 CN 200710103828 CN 200710103828 A CN200710103828 A CN 200710103828A CN 101059948 A CN101059948 A CN 101059948A
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- active component
- grid
- protection element
- electrostatic protection
- bus
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- Thin Film Transistor (AREA)
Abstract
The invention provides an active component array baseboard comprising a baseboard, a plurality of scan lines, a plurality of data lines, a plurality of pixels, a total bus, and a plurality of voltage pull-down circuits. The pixels are at the cross part of the scan lines and the data lines, to be distributed on the baseboard as array and electrically connected with relative scan lines and data lines. Each voltage pull-down circuit is electrically connected between relative scan lines and the total line, while each circuit comprises a transistor and a static protective element, wherein each transistor is provided with a grid, a source and a grain electrically connected with a following scan line. Each grid via the static protective element is connected to the relative scan line, source, grain and total line. The static protective element can effectively avoid static discharge to destroy the active component array baseboard.
Description
Technical field
The invention relates to a kind of LCD, and particularly relevant for a kind of active component array base board.
Background technology
In recent years, because photoelectric technology and semiconductor fabrication maturing, drive the flourish of flat-panel screens (FlatPanel Display), wherein LCD (LCD:Liquid Crystal Display) is because of having advantages such as low voltage operating, radiationless line scattering, in light weight and volume be little, replace traditional cathode ray tube (CRT) display gradually, and become the main flow of display product.
(TFT-LCD:Thin-Film Transistor Liquid CrystalDisplay) is example with Thin Film Transistor-LCD, and Thin Film Transistor-LCD comprises that an active component array base board, constitutes at liquid crystal layer, a gate driver circuit and the one source pole driving circuit of the subtend substrate above the active component array base board, between active component array base board and subtend substrate.Gate driver circuit and source electrode drive circuit drive corresponding scanning line and data line respectively.Each pixel in the Thin Film Transistor-LCD is controlled by the thin film transistor (TFT) of correspondence, and thin film transistor (TFT) and corresponding scanning line and data line electrically connect.
When above-mentioned Thin Film Transistor-LCD showed, gate driver circuit can provide sweep signal to each bar sweep trace in regular turn, to open the thin film transistor (TFT) in the pixel that each bar sweep trace controlled in regular turn.When the thin film transistor (TFT) of being controlled when each bar sweep trace is unlocked, just can input in the pixel by the data voltage that source electrode drive circuit provided.It should be noted that when back one-level sweep trace is opened thin film transistor (TFT) in the next column pixel, must guarantee that the pairing thin film transistor (TFT) of these row pixel cuts out really, repeat to import in the same row pixel to avoid data voltage.Yet, along with the demand of Thin Film Transistor-LCD to large scale and high-res increases day by day, on the active component array base board each bar sweep trace the pixel quantity that must control increase, make the gate delay effect (gate delay) of each sweep trace get over seriously.
In order to improve the problem of above-mentioned gate delay effect, there have been several solutions in the prior art field, wherein a kind of method is to add a voltage pull-down circuits, a kind of voltage pull-down circuits of improving the gate delay effect of sweep trace that for example Fig. 1 illustrated on each bar sweep trace.Please refer to Fig. 1, voltage pull-down circuits 10 is electrically connected at sweep trace S at the corresponding levels
n, back one-level sweep trace S
N+1And one have the voltage level of closing V
GlBus 12.This practice can be at back one-level sweep trace S
N+1When the pixel of being controlled is unlocked, see through voltage pull-down circuits 10 with sweep trace S at the corresponding levels
nPromptly by the voltage level V that opens
GhBe pulled down to the voltage level V that closes
Gl, so can effectively improve the problem that above-mentioned gate delay effect is caused.
Yet, in the manufacture process of LCD, (for example the electricity of thin film deposition or dry ecthing manufacture craft is starched electric charge, the fricative electric charge of alignment film manufacture craft that gas produces when voltage pull-down circuits suffers static charge, or substrate carried out the switch on electric charge of generation of electric charge test institute) during the destruction of discharging, make voltage pull-down circuits lose its function easily, even can cause line defect (line defect).
Summary of the invention
In view of the problems referred to above that prior art suffered from, the present invention proposes a kind of active component array base board that can improve the gate delay effect.
The present invention proposes a kind of active component array base board, and it comprises that multi-strip scanning line and many data lines, a plurality of pixel, a bus and a plurality of voltage pull-down circuits are disposed on the substrate.A plurality of pixels are positioned at sweep trace and data line intersection, and with array format on substrate, and be electrically connected to corresponding scanning line and data line.Each voltage pull-down circuits is electrically connected between corresponding scanning line and the bus, and each voltage pull-down circuits comprises a transistor and an electrostatic protection element, wherein each transistor has grid, one source pole and a drain electrode that electrically connects with back one-level sweep trace, and each grid is connected to corresponding scanning line, source electrode, drain electrode and bus by electrostatic protection element.
The present invention proposes a kind of LCD in addition, and it comprises said active element array substrate, a subtend substrate, a frame glue and a liquid crystal layer.The subtend substrate is disposed at the active component array base board top.Frame glue is disposed between active component array base board and the subtend substrate, inject the space to form a liquid crystal between active component array base board and subtend substrate, and liquid crystal layer is positioned at liquid crystal injection space.
The present invention proposes a kind of voltage pull-down circuits in addition, is suitable for being electrically connected between two sweep traces and the bus, and it comprises a transistor and an electrostatic protection element.Each transistor has grid, one source pole and a drain electrode that electrically connects with sweep trace wherein, and each grid is connected to another sweep trace, source electrode and drain electrode by electrostatic protection element.
In one embodiment of this invention, each transistor comprises a thin film transistor (TFT).
In one embodiment of this invention, each electrostatic protection element comprises first diode and second diode, and wherein first diode is connected between grid and the corresponding scanning line, and second diode is connected between grid and the bus.In other embodiments, each electrostatic protection element also comprises first capacitor of connecting with first diode and second capacitor of connecting with second diode.
In one embodiment of this invention, each electrostatic protection element comprises first capacitor and second capacitor, and wherein first capacitor is connected between grid and the corresponding scanning line, and second capacitor is connected between grid and the bus.
In one embodiment of this invention, voltage pull-down circuits is electrically connected between the end and bus of each sweep trace.
In one embodiment of this invention, active component array base board comprises that also a gate driver circuit is disposed on the substrate, and electrically connects with sweep trace.
In one embodiment of this invention, voltage pull-down circuits is positioned at frame glue below.
In one embodiment of this invention, bus is positioned at frame glue below.
In one embodiment of this invention, LCD also comprises a plurality of separation materials, is disposed at liquid crystal and injects in the space.In other embodiments, voltage pull-down circuits is positioned at the separation material below.
Based on above-mentioned, the present invention can reduce the gate delay effect of active component array base board by being provided with of voltage pull-down circuits.In addition, voltage pull-down circuits of the present invention also has the function of electrostatic defending, with when promoting the display quality of LCD, prevents that voltage pull-down circuits itself from being destroyed by static discharge.
Description of drawings
Fig. 1 illustrates a kind of existing voltage pull-down circuits that is used to improve the gate delay effect of sweep trace.
Fig. 2 is the synoptic diagram of active component array base board embodiment of the present invention.
Fig. 3 A is the synoptic diagram of electrostatic protection element first embodiment of the present invention.
Fig. 3 B is the synoptic diagram of electrostatic protection element second embodiment of the present invention.
Fig. 3 C is the synoptic diagram of electrostatic protection element the 3rd embodiment of the present invention.
Fig. 4 is the synoptic diagram of LCD embodiment of the present invention.
Drawing reference numeral:
100: active component array base board
102: substrate
110: sweep trace
120: data line
130: pixel
140: bus
150: voltage pull-down circuits
160: gate driver circuit
170: source electrode drive circuit
180: transistor
182: grid
184: source electrode
186: drain electrode
190: electrostatic protection element
192: the first diodes
194: the second diodes
196: the first capacitors
198: the second capacitors
200: LCD
210: the subtend substrate
220: frame glue
230: liquid crystal layer
V
Gh, V
Gl: voltage level
Embodiment
For above-mentioned feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Fig. 2 is the synoptic diagram of active component array base board embodiment of the present invention.Please refer to Fig. 2, active component array base board 100 comprises that multi-strip scanning line 110 and many data lines 120, a plurality of pixel 130, a bus 140 and a plurality of voltage pull-down circuits 150 are disposed on the substrate 102.A plurality of pixel 130 arrayed and are electrically connected to corresponding scanning line 110 and data line 120 on substrate 102.In the present embodiment, active component array base board 100 comprises that also a gate driver circuit 160 electrically connects driven sweep line 110 and one source pole driving circuit 170 electrically connects driving data lines 120.Each voltage pull-down circuits 150 is electrically connected between corresponding scanning line 110 and the bus 140, and each voltage pull-down circuits 150 comprises a transistor 180 and an electrostatic protection element 190.In the present embodiment, transistor 180 for example is a thin film transistor (TFT), yet transistor 180 also can be the transistor of other form kenels.As shown in Figure 2, each transistor 180 has grid 182, an one source pole 184 and a drain electrode 186 that electrically connects with back one-level sweep trace 110, and each grid 182 is connected to corresponding scanning line 110, source electrode 184, drains 186 and bus 140 by electrostatic protection element 190.In Fig. 2, source electrode 184 is connected with corresponding scanning line 110,186 is connected with bus 140 and drain.
Generally speaking, the sweep signal that provides of gate driver circuit 160 has two kinds of voltage level V
GhWith V
Gl, when the voltage level of sweep signal is V
GhThe time, sweep trace 110 is unlocked, when the voltage level of sweep signal is V
GlThe time, sweep trace 110 promptly is closed.Present embodiment makes bus 140 be coupled to voltage level V
Gl, so, voltage pull-down circuits 150 can guarantee that the voltage level of voltage pull-down circuits 150 corresponding scanning line 110 promptly is pulled down to voltage level V when back one-level sweep trace 110 is unlocked
Gl, to reduce lock level late effect.Specifically, when after the sweep signal of one-level sweep trace 110 be V
GhThe time, the transistor 180 of each voltage pull-down circuits 150 is unlocked, so that corresponding scanning line 110 and bus 140 conductings, causes the identical (V of voltage level of corresponding scanning line 110 and bus 140
Gl), to close corresponding scanning line 110.In addition, each voltage pull-down circuits 150 in the present embodiment is disposed at the subtend of gate driver circuit 160, and is electrically connected between the end and bus 140 of each sweep trace 110.In other embodiments, each voltage pull-down circuits 150 can also be disposed at homonymy with gate driver circuit 160.
It should be noted that the design that is different from existing voltage pull-down circuits, for fear of the destruction of static discharge to voltage pull-down circuits, the present invention is provided with an electrostatic protection element 190 in each voltage pull-down circuits 150.The setting of electrostatic protection element 190 not only can be protected outside each voltage pull-down circuits 150; still can further protect in the active component array base board 100; all elements with each sweep trace 110 electric connection; the for example backguy of each sweep trace 110 pairing each pixel 130, gate driver circuit 160 or gate driver circuit 160 etc., and then reduce the point defect of active component array base board 100 or the fraction defective of line defect.
Fig. 3 A is the synoptic diagram of electrostatic protection element embodiment of the present invention.Please refer to Fig. 3 A, each electrostatic protection element 190 comprises first diode 192 and second diode 194, wherein first diode 192 be connected in and grid 182 and corresponding scanning line 110 between, second diode 194 is connected between grid 182 and the bus 140.Certainly, each electrostatic protection element 190 also can be looked demand and only is made of first diode 192, and the present invention does not limit the quantity of each electrostatic protection element 190 element.
Please continue the A with reference to Fig. 3, under normal operation, each first diode 192 and second diode 194 are in closed condition, can't influence the normal operation of each voltage pull-down circuits 150.Yet, when producing a forward bias static charge on the active component array base board 100, the forward bias static charge is opened first diode 192 and corresponding transistor 180 via corresponding scanning line 110, make the forward bias static charge can be promptly see through bus 140 and discharge, avoid transistor 180 destroyed by static discharge.
In practical operation, except using diode as the electrostatic protection element 190, the deviser can in time use capacitor on demand, and makes capacitor and diode polyphone.Shown in Fig. 3 B, first diode 192 and first capacitor, 196 polyphones, and second diode 194 is connected with second capacitor 198, to increase the pressure reduction of electrostatic protection element 190 when closing with conducting, strengthens the misoperation of electrostatic protection element 190 with this.
Fig. 3 C is the synoptic diagram of another embodiment of electrostatic protection element of the present invention.Shown in Fig. 3 C, electrostatic protection element 190 is made of first capacitor 196 and second capacitor 198, wherein first capacitor 196 be connected in and grid 182 and corresponding scanning line 110 between, second capacitor 198 then is connected between grid 182 and the bus 140.Certainly, electrostatic protection element 190 also can be looked demand and only is made up of first capacitor 196, does not limit the quantity of electrostatic protection element 190 element at this.
Form at electrostatic protection element 190 of the present invention is not limited to aforementioned three kinds of embodiment, and electrostatic protection element 190 can be the various combination of diode, capacitor, transistor or said elements.
Fig. 4 is the synoptic diagram of LCD embodiment of the present invention.Please refer to Fig. 4, LCD 200 comprises active component array base board 100, a subtend substrate 210, a frame glue 220 and a liquid crystal layer 230.Subtend substrate 210 is disposed at active component array base board 100 tops.Frame glue 220 is disposed between active component array base board 100 and the subtend substrate 210, inject the space to form a liquid crystal between active component array base board 100 and subtend substrate 210, and liquid crystal layer 230 is positioned at liquid crystal injection space.It should be noted that, the deviser can optionally be arranged at frame glue 220 belows with voltage pull-down circuits 150, bus 140 or said two devices, to avoid in signals transmission, pull-down circuit 150 and/or bus 140 have influence on the liquid crystal of its top and topple over situation, cause LCD 200 to produce light leakage phenomena.In addition, voltage pull-down circuits 150 and/or bus 140 are arranged at the capacitive load that frame glue 220 belows can reduce LCD 200, promote the performance of transistor 180 with the electrostatic protection element 190 of each voltage pull-down circuits 150.
In sum, voltage pull-down circuits of the present invention not only can reduce the gate delay effect, and is not vulnerable to the destruction of static discharge.Therefore, voltage pull-down circuits proposed by the invention can promote the product yield of LCD and prolong its serviceable life.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; the people who has common knowledge in the technical field under any; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when looking being as the criterion that claims define.
Claims (18)
1. an active component array base board is characterized in that, described active component array base board comprises;
One substrate;
Multi-strip scanning line and many data lines are disposed on the described substrate;
A plurality of pixels are positioned at described these sweep traces and described these data line intersections, and with array format on described substrate, and be electrically connected to corresponding scanning line and data line;
One bus is disposed at described substrate;
A plurality of voltage pull-down circuits, each described voltage pull-down circuits is electrically connected between corresponding scanning line and the described bus, and each described voltage pull-down circuits comprises a transistor and an electrostatic protection element, wherein each described transistor has grid, one source pole and a drain electrode that electrically connects with back one-level sweep trace, and each described grid is connected to corresponding scanning line, described source electrode, described drain electrode and described bus by described electrostatic protection element.
2. active component array base board according to claim 1 is characterized in that, each described transistor comprises a thin film transistor (TFT).
3. active component array base board according to claim 1 is characterized in that, each described electrostatic protection element comprises:
One first diode is connected between described grid and the corresponding scanning line; And
One second diode is connected between described grid and the described bus.
4. active component array base board according to claim 3 is characterized in that, each described electrostatic protection element also comprises:
One first capacitor is connected with described first diode; And
One second capacitor is connected with described second diode.
5. active component array base board according to claim 1 is characterized in that, each described electrostatic protection element comprises:
One first capacitor is connected between described grid and the corresponding scanning line; And
One second capacitor is connected between described grid and the described bus.
6. active component array base board according to claim 1 is characterized in that, described these voltage pull-down circuits are electrically connected between the end and described bus of each described sweep trace.
7. a LCD is characterized in that, described LCD comprises:
One active component array base board as claimed in claim 1;
One subtend substrate is disposed at described active component array base board top;
One frame glue is disposed between described active component array base board and the described subtend substrate, injects the space to form a liquid crystal between described active component array base board and described subtend substrate; And
One liquid crystal layer is positioned at described liquid crystal and injects the space.
8. LCD according to claim 7 is characterized in that, each described transistor comprises a thin film transistor (TFT).
9. LCD according to claim 8 is characterized in that, each described electrostatic protection element comprises:
One first diode is connected between described grid and the corresponding scanning line; And
One second diode is connected between described grid and the described bus.
10. LCD according to claim 9 is characterized in that, each described electrostatic protection element also comprises:
One first capacitor is connected with described first diode; And
One second capacitor is with described second diode polyphone.
11. LCD according to claim 7 is characterized in that, each described electrostatic protection element comprises:
One first capacitor is connected between described grid and the corresponding scanning line; And
One second capacitor is connected between described grid and the described bus.
12. LCD according to claim 7 is characterized in that, described these voltage pull-down circuits are electrically connected between the end and described bus of each described sweep trace.
13. LCD according to claim 7 is characterized in that, described these voltage pull-down circuits and described bus are positioned at described frame glue below.
14. a voltage pull-down circuits is suitable for being electrically connected between two sweep traces and the bus, described voltage pull-down circuits comprises:
One transistor; And
One electrostatic protection element, wherein each described transistor has grid, one source pole and a drain electrode that electrically connects with sweep trace wherein, and each described grid is connected to another sweep trace, described source electrode and described drain electrode by described electrostatic protection element.
15. voltage pull-down circuits according to claim 14 is characterized in that, each described transistor comprises a thin film transistor (TFT).
16. voltage pull-down circuits according to claim 14 is characterized in that, each described electrostatic protection element comprises:
One first diode is connected between described grid and the corresponding scanning line; And
One second diode is connected between described grid and the described bus.
17. voltage pull-down circuits according to claim 16 is characterized in that, each described electrostatic protection element also comprises:
One first capacitor is connected with described first diode; And
One second capacitor is connected with described second diode.
18. voltage pull-down circuits according to claim 14 is characterized in that, each described electrostatic protection element comprises:
One first capacitor is connected between described grid and the corresponding scanning line; And
One second capacitor is connected between described grid and the described bus.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200710103828XA CN100555400C (en) | 2007-05-16 | 2007-05-16 | Active component array base board |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB200710103828XA CN100555400C (en) | 2007-05-16 | 2007-05-16 | Active component array base board |
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| Publication Number | Publication Date |
|---|---|
| CN101059948A true CN101059948A (en) | 2007-10-24 |
| CN100555400C CN100555400C (en) | 2009-10-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB200710103828XA Active CN100555400C (en) | 2007-05-16 | 2007-05-16 | Active component array base board |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106200172A (en) * | 2016-07-14 | 2016-12-07 | 京东方科技集团股份有限公司 | A kind of array base palte and display device |
| CN110264929A (en) * | 2019-06-26 | 2019-09-20 | 京东方科技集团股份有限公司 | A kind of display panel, display device and detection method |
| WO2020253302A1 (en) * | 2019-06-18 | 2020-12-24 | 京东方科技集团股份有限公司 | Electrode structure, capacitor, goa circuit, array substrate, and display panel and device |
-
2007
- 2007-05-16 CN CNB200710103828XA patent/CN100555400C/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106200172A (en) * | 2016-07-14 | 2016-12-07 | 京东方科技集团股份有限公司 | A kind of array base palte and display device |
| WO2020253302A1 (en) * | 2019-06-18 | 2020-12-24 | 京东方科技集团股份有限公司 | Electrode structure, capacitor, goa circuit, array substrate, and display panel and device |
| US11803088B2 (en) | 2019-06-18 | 2023-10-31 | Beijing Boe Technology Development Co., Ltd. | Electrode structure, capacitor, goa circuit, array substrate, display panel and display device |
| CN110264929A (en) * | 2019-06-26 | 2019-09-20 | 京东方科技集团股份有限公司 | A kind of display panel, display device and detection method |
| CN110264929B (en) * | 2019-06-26 | 2023-09-19 | 京东方科技集团股份有限公司 | Display panel, display device and detection method |
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| Publication number | Publication date |
|---|---|
| CN100555400C (en) | 2009-10-28 |
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