CN101051605A - Ditching type capacitor and its producing method - Google Patents
Ditching type capacitor and its producing method Download PDFInfo
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- CN101051605A CN101051605A CN 200610074028 CN200610074028A CN101051605A CN 101051605 A CN101051605 A CN 101051605A CN 200610074028 CN200610074028 CN 200610074028 CN 200610074028 A CN200610074028 A CN 200610074028A CN 101051605 A CN101051605 A CN 101051605A
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Abstract
The method for fabricating canal type capacitor includes following steps: carrying out patternizing procedure by using patternized mask layer on substrate in order to form multiple canals in the substrate; forming low electrode in substrate of each canal surface; removing partial patternized mask layer to expose partial substrate on two sides of top portion of each canal; forming dielectric layer of capacitance on substrate and surface of each canal; being formed above the substrate, conductive layer fills in each canal, and covers dielectric layer of capacitance; removing patternized mask layer and partial conductive layer, and reserving partial conductive layer of covering the dielectric layer of capacitance in order to form up electrode.
Description
Technical field
The present invention relates to a kind of capacitor and manufacture method thereof of memory, relate in particular to a kind of ditching type capacitor and manufacture method thereof.
Background technology
Along with element miniaturization constantly, size of component is dwindled gradually, and for the memory element with capacitor, the space that can make capacitor is more and more little.The ditching type capacitor memory element is a kind ofly to utilize the space in the substrate to make capacitor to strive for the element of area, therefore, meets very much the demand of existing market.
The manufacture method of existing a kind of ditching type capacitor shown in Figure 1A, is to form earlier silicon oxide layer 102 and silicon nitride layer 104 on substrate 100 in regular turn.Then, carry out etch process, etching part silicon nitride layer 104 and silicon oxide layer 102 are to form the opening 106 that several expose substrate 100 surfaces.
Then, please refer to Figure 1B, is mask with silicon nitride layer 104 with silicon oxide layer 102, removes part substrate 100, to form several irrigation canals and ditches 108 in substrate 100.Afterwards, in the substrate 100 on irrigation canals and ditches 108 surfaces, form a doped region 110.
Then, please refer to Fig. 1 C, form one deck silicon oxide/silicon nitride/silicon oxide layer (Oxide/Nitride/Oxide, ONO) 112 in irrigation canals and ditches 108 surfaces.Afterwards, deposit one deck doped polysilicon layer 114 in irrigation canals and ditches 108, and carry out CMP (Chemical Mechanical Polishing) process, remove part doped polysilicon layer 114 to exposing silicon nitride layer 104 surfaces.
Subsequently, please refer to Fig. 1 D, remove silicon nitride layer 104 and silicon oxide layer 102, and remove part doped polysilicon layer 114 to exposing substrate 100 surfaces.
In above-mentioned existing method, Fig. 1 D removes silicon nitride layer 104, silicon oxide layer 102 and part doped polysilicon layer 114 to the step that exposes substrate 100 surfaces, easily damage is caused on silicon oxide/silicon nitride/silicon oxide layer 112 surface, and cause leakage current, influence technology reliability and yield.And, after the step of Fig. 1 D, simultaneously come out in silicon oxide/silicon nitride/silicon oxide layer 112 surface.Therefore, in the technology of then carrying out, for example define active area and form doping process and the etch process that element carried out, can cause damage to silicon oxide/silicon nitride/silicon oxide layer 112 surface of ditching type capacitor too.
In addition, United States Patent (USP) the 6th, 661,050B2 number (U.S.Pat.No.6,661,050B2) content has disclosed a kind of memory construction and manufacture method thereof with ditching type capacitor.United States Patent (USP) the 6th, 808,980B2 number (U.S.Pat.No.6,808,980B2) content has disclosed structure and the manufacture method thereof of a kind of random access memory about irrigation canals and ditches (1T-RAM).Yet the technology of above-mentioned two patent documentations of mentioning is comparatively complicated, and still can't effectively solve the above problems.
Summary of the invention
The manufacture method that the purpose of this invention is to provide a kind of ditching type capacitor can be avoided damage is caused on the capacitance dielectric layer surface, causes leakage current, and influences technology reliability and yield.
Another object of the present invention provides a kind of ditching type capacitor, can protect the surface of capacitance dielectric layer, and it is not sustained damage, to improve technology reliability and yield.
The present invention proposes a kind of manufacture method of ditching type capacitor, is to utilize the mask layer that is positioned at the patterning on the substrate to carry out Patternized technique earlier, to form a plurality of irrigation canals and ditches in substrate.Then, in the substrate on each irrigation canals and ditches surface, form bottom electrode.Then, remove partially patterned mask layer, to expose the part substrate of each both sides, irrigation canals and ditches top.Then, on substrate, form capacitance dielectric layer with each irrigation canals and ditches surface.Subsequently, form conductive layer in the substrate top, conductive layer is to fill up each irrigation canals and ditches at least, and covers capacitance dielectric layer.Then, remove the mask layer and the segment conductor layer of patterning, and keep the segment conductor layer that covers capacitance dielectric layer, to form top electrode.
Described according to embodiments of the invention, above-mentioned remove partially patterned mask layer, for example be the isotropic etching method with the method for the part substrate that exposes each both sides, irrigation canals and ditches top.
Described according to embodiments of the invention, above-mentioned after forming top electrode, also be included in the part substrate between conductive layer, capacitance dielectric layer and adjacent two irrigation canals and ditches and form isolation structure.Wherein, isolation structure for example be shallow slot isolation structure (shallow trench isolation, STI).
Described according to embodiments of the invention, above-mentioned capacitance dielectric layer for example is the dielectric materials layer of high-k, and the material of the dielectric materials layer of high-k for example is silicon oxide/silicon nitride/silicon oxide (ONO), nitrogenize silicon/oxidative silicon (NO), tantalum oxide (Ta
2O
5), zirconia (ZrO
2), hafnium oxide (HfO
2) and barium strontium (barium strontium titanate, BST).The formation method of capacitance dielectric layer for example is chemical vapour deposition technique or sputtering method (sputtering).
Described according to embodiments of the invention, the mask layer of above-mentioned patterning comprises that by substrate up be the pad oxide of patterning and the silicon nitride layer of patterning in regular turn.
Described according to embodiments of the invention, the material of above-mentioned conductive layer for example is a doped polycrystalline silicon, and its formation method for example is a chemical vapour deposition technique.
Described according to embodiments of the invention, above-mentioned bottom electrode for example is a doped region, and its formation method comprises ion implantation or thermal diffusion method.
The present invention proposes a kind of ditching type capacitor in addition, and it is disposed in the irrigation canals and ditches of substrate.Ditching type capacitor comprises bottom electrode, capacitance dielectric layer, top electrode and isolation structure.Wherein, bottom electrode is configured in the substrate on irrigation canals and ditches surface.Capacitance dielectric layer is disposed at the irrigation canals and ditches surface, and is positioned on the part substrate of irrigation canals and ditches top side.In addition, top electrode be disposed in the irrigation canals and ditches with substrate on, and cover capacitance dielectric layer.Isolation structure is configured in partition capacitance dielectric layer and the top electrode, and is arranged in the substrate of part.
Described according to embodiments of the invention, above-mentioned capacitance dielectric layer for example is the dielectric materials layer of high-k, and the material of the dielectric materials layer of high-k for example is silicon oxide/silicon nitride/silicon oxide, nitrogenize silicon/oxidative silicon, tantalum oxide, zirconia, hafnium oxide and barium strontium.The formation method of capacitance dielectric layer for example is chemical vapour deposition technique or sputtering method.
Described according to embodiments of the invention, above-mentioned top electrode for example is a conductor layer, and the material of conductor layer for example is a doped polycrystalline silicon.
Described according to embodiments of the invention, above-mentioned bottom electrode for example is a doped region.
Described according to embodiments of the invention, above-mentioned isolation structure for example is a shallow slot isolation structure.
The present invention removes the part mask layer, retreats (pullback) so that mask layer produces, and the part substrate of both sides, irrigation canals and ditches top is come out.Thus, the top electrode of follow-up formation has on the substrate that the subregion is formed at the both sides, irrigation canals and ditches top of being come out.Therefore, when carrying out doping process and etch process in subsequent technique, the surface of capacitance dielectric layer can be subjected to the protection of top electrode, and is difficult for causing damage (damage).That is be that it can avoid prior art because of damage is caused on the capacitance dielectric layer surface, and causes leakage current, influences technology reliability and yield.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, embodiment cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Figure 1A to Fig. 1 D illustrate is the profile of the manufacturing process of existing a kind of ditching type capacitor;
Fig. 2 A to Fig. 2 H is the manufacturing process profile according to the memory that the embodiment of the invention illustrated.
The main element symbol description
100,200: substrate
102: silicon oxide layer
104,204: silicon nitride layer
106: opening
108,206: irrigation canals and ditches
110: doped region
112: the silicon oxide/silicon nitride/silicon oxide layer
114: doped polysilicon layer
201,201a: mask layer
202: pad oxide
208: bottom electrode
210,215: arrow
212: capacitance dielectric layer
214: conductive layer
214a: conductor layer (top electrode)
218: active element
218a: grid
218b: source/drain
220: dielectric layer
222: contact hole
Embodiment
Fig. 2 A to Fig. 2 H is the manufacturing process profile according to the memory that the embodiment of the invention illustrated.
At first, please refer to Fig. 2 A, a substrate 200 is provided, form mask layer 201 on substrate 200, this mask layer 201 can for example be up to be one deck pad oxide 202 and one deck silicon nitride layer 204 in regular turn by substrate 200.The formation method of pad oxide 202 for example is a thermal oxidation method, and the formation method of silicon nitride layer 204 for example is chemical vapour deposition technique (CVD).Thereafter, with pad oxide 202 and silicon nitride layer 204 patternings, and etch substrate 200, in substrate 200, to form several irrigation canals and ditches 206.
Then, please refer to Fig. 2 B, in the substrate 200 on irrigation canals and ditches 206 surfaces, form bottom electrode 208.The formation method of bottom electrode 208 for example is the silicon oxide layer that forms doping earlier in the inner wall surface of irrigation canals and ditches 206, then, carries out thermal process, so that the dopant ion in the silicon oxide layer of this doping diffuses to irrigation canals and ditches 206, to form bottom electrode 208.Wherein, the ion that silicon oxide layer mixed of doping for example is an arsenic ion, and the formation method of the silicon oxide layer of this doping for example is Low Pressure Chemical Vapor Deposition (LPCVD).In addition, the formation method of bottom electrode 208 also can for example be to carry out a multi-angle ion implantation technology, forms doped region in the substrate 200 on irrigation canals and ditches 206 surfaces, with as bottom electrode 208.
Then, please refer to Fig. 2 C, remove part mask layer 201, to expose the part substrate 200 of both sides, irrigation canals and ditches 206 top.The above-mentioned method that removes part mask layer 201 for example is that mask layer 201 is carried out an isotropic etching, to remove part silicon nitride layer 204 and pad oxide 202.In other words, above-mentioned step retreats (pullback) so that mask layer 201 produces, and forms mask layer 201a, so that the part substrate 200 of both sides, irrigation canals and ditches 206 top comes out (shown in arrow 210) for removing part mask layer 201.
Afterwards, please refer to Fig. 2 D, on substrate 200, form capacitance dielectric layer 212 with irrigation canals and ditches 206 surfaces.Wherein, capacitance dielectric layer 212 for example is to use the dielectric materials layer of high-k, to improve the capacitance of capacitor.The material of the dielectric materials layer of high-k for example is silicon oxide/silicon nitride/silicon oxide (ONO), nitrogenize silicon/oxidative silicon (NO), tantalum oxide (Ta
2O
5), zirconia (ZrO
2), hafnium oxide (HfO
2), (barium strontium titanate, BST) or the dielectric material of other high-ks, and its formation method for example is chemical vapour deposition technique (CVD) or sputtering method (sputtering) to barium strontium.
Then, please refer to Fig. 2 E, form conductive layer 214 in substrate 200 tops, conductive layer 214 is to fill up irrigation canals and ditches 206 at least, and covers capacitance dielectric layer 212.Wherein, the material of conductive layer 214 for example is a doped polycrystalline silicon, and its formation method for example is a chemical vapour deposition technique.
Subsequently, please refer to Fig. 2 F, remove mask layer 201a and segment conductor layer 214, and keep the segment conductor layer 214 that covers capacitance dielectric layer 212, to form conductor layer 214a, this conductor layer 214a is as top electrode.Wherein, top electrode (conductor layer 214a), capacitance dielectric layer 212 constitute a ditching type capacitor with bottom electrode 208.
It should be noted that, because the top electrode (conductor layer 214a) of ditching type capacitor of the present invention, in being formed at irrigation canals and ditches 206 with substrate 200 on conductor material layer, also comprise the conductor material layer (shown in the arrow 215 of Fig. 2 F) that covers capacitance dielectric layer 212.Therefore, when carrying out doping process and etch process in subsequent technique, the surface of capacitance dielectric layer 212 can be subjected to the protection of top electrode (conductor layer 214a), and is difficult for causing damage (damage).That is be that it can avoid prior art because of damage is caused on capacitance dielectric layer 212 surfaces, and causes leakage current, influences technology reliability and yield.
On the other hand, the part top electrode shown in the arrow 215 of Fig. 2 F (conductor layer 214a) need not carry out photoetching process, and mode that promptly can autoregistration (self-alignment) forms, to cover capacitance dielectric layer 212.
Then, after the technology of finishing the channel capacitor device, also can carry out the making of active element.Please refer to Fig. 2 G, form an isolation structure 216 in the part substrate 200 between conductive layer 214a, capacitance dielectric layer 212 and adjacent two irrigation canals and ditches 206, and 216 of adjacent two isolation structures be define the element active area (Active Area, AA).Isolation structure 216 for example be shallow slot isolation structure (shallow trenchisolation, STI).The formation method of isolation structure 216 for example is capacitance dielectric layer 212, conductor layer 214a and the part substrate 200 that removes between adjacent two irrigation canals and ditches 206, and remove partially conductive layer 214a and partition capacitance dielectric layer 212 in two irrigation canals and ditches 206, to form an opening.Then, insert an insulation material layer in opening, to form isolation structure 216, wherein the material of insulation material layer for example is a silica, and its formation method for example is a chemical vapour deposition technique.
Afterwards, please refer to Fig. 2 H, above substrate 200, form an active element 218.The formation method of active element 218 for example is to form several grid structures with the surface of isolation structure 216 on the substrate 200 of element active area, and wherein the grid structure on the substrate 200 of active area can be used as the grid 218a of active element 218.Then, form clearance wall, then carry out an ion implantation technology, in the substrate 200 of grid 218a both sides, to form source/drain 218b in the grid structure sidewall.Wherein, grid 218a and source/drain 218b constitute an active element 218, and active element 218 is bottom electrode 208 electric connections by source/drain 218b and ditching type capacitor.Wherein, above-mentioned active element 218 can for example be N type metal oxide semiconductor transistor (NMOS) or P-type mos transistor (PMOS).
On be set forth in after active element 218 forms, also can proceed follow-up interconnecting process.Shown in Fig. 2 H, interconnecting process for example is to form one dielectric layer 220 in substrate 200 tops, forms contact hole 222 then in dielectric layer 220, forms lead (not illustrating) afterwards again to connect contact hole 222, and element and interelement can be electrically connected.Particularly, because the top electrode (conductor layer 214a) of ditching type capacitor of the present invention comprises the part top electrode (conductor layer 214a) (shown in the arrow 215 of Fig. 2 F) that covers capacitance dielectric layer 212.So, when the definition contact window, can have bigger process window (process window), to improve the accuracy of technology.
Next explanation utilizes the structure of the memory that method of the present invention produces.Please referring again to Fig. 2 H, memory comprises a ditching type capacitor and an active element 218.Ditching type capacitor comprises bottom electrode 208, capacitance dielectric layer 212, top electrode (conductor layer 214a) and isolation structure 216.Wherein, bottom electrode 208 is configured in the substrate 200 on irrigation canals and ditches 206 surfaces, and bottom electrode for example is a doped region.Capacitance dielectric layer 212 is disposed at irrigation canals and ditches 206 surfaces, and is positioned on the part substrate 200 of irrigation canals and ditches 206 top sides.Capacitance dielectric layer 212 for example is the dielectric materials layer of high-k, and the material of the dielectric materials layer of high-k for example is silicon oxide/silicon nitride/silicon oxide, nitrogenize silicon/oxidative silicon, tantalum oxide, zirconia, hafnium oxide and barium strontium.In addition, top electrode (conductor layer 214a) be disposed in the irrigation canals and ditches 206 with substrate 200 on, and cover capacitance dielectric layer 212, and its material for example is a doped polycrystalline silicon.Isolation structure 216 is configured in partition capacitance dielectric layer 212 and the top electrode (conductor layer 214a), and is arranged in the substrate 200 of part.Isolation structure 216 for example be shallow slot isolation structure (shallow trenchisolation, STI).
In addition, active element 218 comprises grid 218a and source/drain 218b, and grid 218a is disposed on the substrate 200 of ditching type capacitor side.Source/drain 218b is disposed in the substrate 200 of grid 218a both sides, and electrically connects with the bottom electrode 208 of ditching type capacitor.Wherein, the active element among the embodiment 218 can for example be N type metal oxide semiconductor transistor (NMOS) or P-type mos transistor (PMOS).
In sum, the present invention has following advantage at least:
1. the present invention can make the surface of capacitance dielectric layer be protected, and is difficult for causing damage (damage).That is be that it can avoid prior art because of damage is caused on the capacitance dielectric layer surface, and causes leakage current, influences technology reliability and yield.
2. the present invention need not carry out photoetching process, promptly can self aligned mode form the top electrode that covers capacitance dielectric layer, so that the surface of capacitance dielectric layer is protected, avoids its surface to cause damage, and influences technology reliability and yield.
3. the structure of ditching type capacitor of the present invention helps can have bigger process window, to improve the accuracy of technology when the definition contact window.
4. the present invention only need remove the part mask layer, so that mask layer produces the step that retreats, can reach the purpose on the surface of protection capacitance dielectric layer, and need not carry out loaded down with trivial details technology, therefore can improve process yield and save the technology cost.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; under the premise without departing from the spirit and scope of the present invention; can do a little change and retouching, so protection scope of the present invention is as the criterion when looking the claims person of defining.
Claims (19)
1. the manufacture method of a ditching type capacitor comprises:
The mask layer that utilization is positioned at the patterning on the substrate carries out a Patternized technique, to form a plurality of irrigation canals and ditches in this substrate;
In this substrate on each those irrigation canals and ditches surface, form a bottom electrode;
Remove the mask layer of this patterning of part, to expose this substrate of part of each those both sides, irrigation canals and ditches top;
On this substrate, form a capacitance dielectric layer with each those irrigation canals and ditches surface;
Form a conductive layer in this substrate top, this conductive layer fills up each those irrigation canals and ditches at least, and covers this capacitance dielectric layer; And
Remove the mask layer and this conductor layer of part of this patterning, and keep this conductor layer of part that covers this capacitance dielectric layer, to form a top electrode.
2. the manufacture method of ditching type capacitor as claimed in claim 1 wherein removes the partly mask layer of this patterning, and the method for this substrate of part of those both sides, irrigation canals and ditches top comprises the isotropic etching method to expose respectively.
3. the manufacture method of ditching type capacitor as claimed in claim 1 wherein after forming this top electrode, also is included in and forms an isolation structure in this substrate of part between this conductive layer, this capacitance dielectric layer and adjacent two those irrigation canals and ditches.
4. the manufacture method of ditching type capacitor as claimed in claim 3, wherein this isolation structure comprises shallow slot isolation structure.
5. the manufacture method of ditching type capacitor as claimed in claim 1, wherein this capacitance dielectric layer comprises the dielectric materials layer of a high-k.
6. the manufacture method of ditching type capacitor as claimed in claim 5, wherein the material of the dielectric materials layer of this high-k comprises silicon oxide/silicon nitride/silicon oxide, nitrogenize silicon/oxidative silicon, tantalum oxide, zirconia, hafnium oxide and barium strontium.
7. the manufacture method of ditching type capacitor as claimed in claim 1, wherein the formation method of this capacitance dielectric layer comprises chemical vapour deposition technique or sputtering method.
8. the manufacture method of ditching type capacitor as claimed in claim 1, wherein the mask layer of this patterning comprises that by this substrate up be the pad oxide of a patterning and the silicon nitride layer of a patterning in regular turn.
9. the manufacture method of ditching type capacitor as claimed in claim 1, wherein the material of this conductive layer comprises doped polycrystalline silicon.
10. the manufacture method of ditching type capacitor as claimed in claim 1, wherein the formation method of this conductive layer comprises chemical vapour deposition technique.
11. the manufacture method of ditching type capacitor as claimed in claim 1, wherein this bottom electrode comprises doped region.
12. the manufacture method of ditching type capacitor as claimed in claim 1, wherein the formation method of this bottom electrode comprises ion implantation or thermal diffusion method.
13. a ditching type capacitor is disposed in the irrigation canals and ditches of a substrate, this ditching type capacitor comprises:
One bottom electrode is configured in this substrate on this irrigation canals and ditches surface;
One capacitance dielectric layer is disposed at this irrigation canals and ditches surface, and is positioned on this substrate of part of this irrigation canals and ditches top side;
One top electrode, be disposed in these irrigation canals and ditches with this substrate on, and cover this capacitance dielectric layer; And
One isolation structure is configured in this capacitance dielectric layer of part and this top electrode, and is arranged in this substrate of part.
14. ditching type capacitor as claimed in claim 13, wherein this capacitance dielectric layer comprises the dielectric materials layer of a high-k.
15. ditching type capacitor as claimed in claim 14, wherein the material of the dielectric materials layer of this high-k comprises silicon oxide/silicon nitride/silicon oxide, nitrogenize silicon/oxidative silicon, tantalum oxide, zirconia, hafnium oxide and barium strontium.
16. ditching type capacitor as claimed in claim 13, wherein this top electrode comprises a conductor layer.
17. ditching type capacitor as claimed in claim 16, wherein the material of this conductor layer comprises doped polycrystalline silicon.
18. ditching type capacitor as claimed in claim 13, wherein this bottom electrode comprises doped region.
19. ditching type capacitor as claimed in claim 13, wherein this isolation structure comprises shallow slot isolation structure.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100740285A CN100490057C (en) | 2006-04-04 | 2006-04-04 | Ditching type capacitor and its producing method |
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|---|---|---|---|
| CNB2006100740285A CN100490057C (en) | 2006-04-04 | 2006-04-04 | Ditching type capacitor and its producing method |
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| Publication Number | Publication Date |
|---|---|
| CN101051605A true CN101051605A (en) | 2007-10-10 |
| CN100490057C CN100490057C (en) | 2009-05-20 |
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|---|---|---|---|
| CNB2006100740285A Active CN100490057C (en) | 2006-04-04 | 2006-04-04 | Ditching type capacitor and its producing method |
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|---|---|
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| CN100490057C (en) | 2009-05-20 |
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