CN101048761A - Method and device for synchronizing in multiprocessor system - Google Patents
Method and device for synchronizing in multiprocessor system Download PDFInfo
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Abstract
The invention relates to a method and to a device for synchronising in a multi-processor system comprising at least two processors and switching means which can be switched between at least two operational modes. The inventive device is embodied is such a manner that synchronisation is carried out by a stop signal which stops an advancing processor in order to synchronise the stop signal with the at least two processors.
Description
Background technology
In technology is used, as especially in automobile or in industrial field of articles (promptly for example mechanical field) and in automatic field, for application, constantly adopt increasing control and regulating system based on microprocessor or computing machine to the security requirement strictness.At this, duplex computer system or two-processor system (double-core) are the conventional computer system that is used for the application of security requirement strictness at present, especially in all anti-lock braking system, Electronic Stability Program (ESP) (ESP), conventional computer systems of line transmission control system (X-by-wire) system or the like as drive-by-wire (Drive-by-Wire) or drive-by wire (Steer-by-Wire) and line traffic control brake (Break-by-Wire) of being used in this way in the automobile, perhaps also the conventional computer system in other networked system.In order to satisfy the high security requirement in following the application, strong error recognition mechanism and fault processing mechanism are essential, especially so that tackle the transient error that for example forms when the semiconductor structure that makes computer system diminishes.At this, protect nuclear itself, be that processor is difficult relatively.Such as mentioned, be to use duplex computer system or the double-core system detects mistake to this solution.
Therefore, this processor unit with at least two integrated performance elements is called as double-core framework or multicore architecture.Mainly come this double-core framework of suggestion or multicore architecture according to present prior art for following two reasons:
Therefore, on the one hand, implementation efficiency improves, promptly realizes that performance improves in the following manner, and promptly these two performance elements or nuclear are regarded as and are taken as two computing units on the semiconductor module.In this configuration, these two performance elements or nuclear are carried out distinct program or task.Can improve by implementation efficiency thus, so this configuration is called as performance mode or performance mode.
Second reason that realizes double-core or multicore architecture is that security improves, and its mode is that these two performance elements are carried out identical program redundantly.The result of these two performance elements or CPU (i.e. nuclear) is compared, and can identify mistake when comparing consistance.Below this configuration is called safe mode (Safety-Mode) or is also referred to as the wrong identification pattern.
Therefore, there be the dual processor or the multicomputer system (referring to double-core or main frame-verifier (Master-Checker) system) of working at present on the one hand redundantly, and exist in dual processor or the multicomputer system of carrying out different pieces of information on the processor on the other hand in order to discern hard error.If now these two kinds of methods of operation are combined in dual processor or the multicomputer system and (also only mention two-processor system for the sake of simplicity now, can be used to multicomputer system but following invention is just the same), then these two processors obtain different data and obtain identical data under the wrong identification patterns under performance mode.
Present task of the present invention is to introduce a kind of unit and a kind of method, this unit is given at least two processors or the redundant ground of nuclear or instruction/data differently is provided according to pattern, and when allocate memory access right in performance mode especially, these memory access powers and functions enough are implemented in pattern and change two processors or nuclear synchronously and/or desynchronize.
A kind of like this unit is up to also not being disclosed at present.It can realize effective operation of two-processor system, and making to be in operation is converted to two kinds of patterns, be safe mode and performance mode.At this, refer to processor in addition, but this is at conceptive nuclear or the computing unit of comprising equally.
In addition, task of the present invention is to provide a kind of synchronous possibility that can realize multicomputer system.Up to also not disclosing at present such method or embodiment.Existence can only be operated in the multicomputer system under one of two kinds of patterns, but do not have clock synchronization ground work, can change and can clock the multicomputer system of comparing data accurately.Pass through the method introduced can clock accurately or clock synchronization ground carry out synchronously, but also may have the application that does not need this precise synchronization.So this method also can be employed, so that realize " losing (lose) " synchronously.This " mistake " be synchronously so synchronously, though two processors are carried out identical task under this synchronous situation, the time interval of carrying out can fluctuate in the scope given in advance by comparer.
The explanation of embodiments of the invention and advantage
Have two processors in duplex computer system, these two processors can be carried out identical or different tasks.Two processors of this of duplex computer system can clock synchronization ground or these tasks of clock skew ground execution.
In order to change between two kinds of patterns in the system of clock synchronization, these two processors must be synchronous, and wherein output data answers clock synchronously to be compared in the system of described clock synchronization.That is to say, if processor is from performance mode (=pattern, their are carried out different tasks and output data are not compared in this pattern) be converted to safe mode (=pattern, these two processors are carried out identical task and all its output are compared at each clock in this pattern), these two processors must be by synchronously in program process so.
Therefore, the present invention also shows a kind of method and a kind of equipment, wherein triggers the conversion hope by signal.This for example can produce (watch and whether carry out the conversion hope) by observing instruction bus, or the control signal of demoder (for example triggering of in another processor, interrupting, write register ...), and this processor jumps to program address given in advance thus.
In addition, eligibly, these two processors can according in multicomputer system for each processor unique sign, also be that ID jumps to different program points, and therefore desynchronized (importantly :) by the represented processor flag in processor ID position, condition redirect, from independent for each processor but have read-out processor ID position the memory block of identical address, leave the processor ID position in the internal processor register in.
The invention discloses and be used for carrying out synchronous method and apparatus at multicomputer system with at least two processors, wherein include conversion equipment, can between at least two kinds of operational modes, change by this conversion equipment, wherein this equipment so is configured, make and undertaken synchronously by stop signal, this stop signal stops leading processor, so that make this processor and at least the second processor synchronous.
Can be eligibly by the conversion hope of notifying at least one processor carry out synchronously (for example in another processor, trigger interrupt, write register ...) and this processor jump to program address given in advance thus.
The present invention also illustrates and is used in the unit of the system with at least two computing units from least one data source distribute data, wherein include conversion equipment (mode switch), can between at least two kinds of operational modes of this system, change by this conversion equipment, wherein so construct this unit, makes data allocations and/or data source (especially instruct storer, data-carrier store, high-speed cache) depend on operational mode.Equally also show system with this unit.
At this, first operational mode is corresponding to safe mode, and these two computing units are handled identical program and/or data in this safe mode, and are provided with comparison means, the consistance of the state that this comparison means comparison occurs when handling identical program.
Can in a two-processor system, realize two kinds of patterns according to unit of the present invention and the method according to this invention.
If these two processors are in down work of wrong identification pattern (F pattern), these two processors obtain identical data/commands so, and if their in performance mode (P pattern) work down, each processor can reference-to storage so.So described Single Component Management is to the only storer of existence or the visit of peripherals simply.
In the F pattern, this unit receives the data/address of a processor (being called main frame here), and this data/address is transmitted to assembly such as storer, bus etc.Second processor (slave here) wants to carry out identical visit.This data allocations unit receives this on second port, but this request is not forwarded to other assemblies.This data allocations unit transmits the data identical with main frame to slave, and compares the data of two processors.If these data are inequality, this data allocations unit (being DVE here) shows this point by rub-out signal so.Therefore only main frame is worked on bus/storer, and slave obtains identical data (working method is as in the double-core system).
In the P pattern, these two processors are carried out different program parts.Therefore memory access also is different.Therefore this DVE accepts the request of processor and result's/asked data is turned back to the processor of having asked this results/data.If present two processors are thought access component simultaneously, a processor is placed in waiting status so, up to another processor processed intact till.
Between two kinds of patterns and therefore the conversion between the different operating mode of data allocations unit realizes by control signal.This signal can be produced by one of two processors, is perhaps produced by the outside.
If this two-processor system does not move with clock skew in the P pattern with the clock skew operation in the F pattern, this DVE unit correspondingly postpones the data of slave so, perhaps the output data of storage host always can compare with the output data of slave with till carrying out wrong identification up to this output data.
Further set forth clock skew by Fig. 1.
Fig. 1 illustrates duplex computer system, and it has first computing machine 100 (especially principal computer) and second computing machine 101 (especially from computing machine).At this, total system is with clock that can be given in advance or moving by clock period (clock cycle) CLK given in advance.Input end of clock CLK1 by computing machine 100 and the input end of clock CLK2 by computing machine 101 flow to this duplex computer system with clock.In addition, in this duplex computer system, also exemplarily comprise the special characteristic that is used for identification error, wherein that is first computing machine 100 and second computing machine 101 with time migration, especially can be given in advance time migration or clock skew work that can be given in advance.At this, each random time that can time migration given in advance, and also can be given in advance about each any clock of the skew of clock period.This can be the integer skew of clock period (clock cycle), but also can be as shown in this example, for example being the skew of 1.5 clock period, wherein in 1.5 clock period work or the operation before second computing machine 101 just of this first computing machine 100.Can avoid by this skew, homophase mistake (being so-called common mode failure (common mode failure)) is interference calculation machine or processor (being the nuclear of double-core system) and therefore keep unrecognized in the same manner.That is to say that the different moment in program circuit relate to computing machine and therefore two computing machines produced different effects this homophase mistake owing to be offset, and can identify mistake thus.Avoid thus, do not have the same erroneous effects of clock skew may not be identified in comparison.In order in duplex computer system, to be implemented in this skew (especially is 1.5 clock period at this) aspect time or the clock, realize offset module 112 to 115.
In order to identify described homophase mistake, this system just in time for example is designed to time migration given in advance or clock period skew work, especially it is 1.5 clock period at this, promptly during this 1.5 clock period, computing machine, a for example computing machine 100 are directly made response to assembly, particularly external module 103 and 104, and second computing machine 101 is with respect to the just in time delay work of 1.5 clock period of computing machine 100.In order to produce desirable semiperiod delay (i.e. the delay of 1.5 clock period) in this case, on input end of clock CLK2, present anti-phase clock for computing machine 101.But, thus also must with the above-mentioned terminal of computing machine, be its data or instruction by the described clock period of bus delay, promptly especially postpone 1.5 clock period at this, as described, be provided with skew or Postponement module 112 to 115 for this reason.Except two computing machines or processor 100 and 101, also be provided with assembly 103 and 104, these assemblies 103 are connected with 101 by the bus 116 be made up of bus line 116A and 116B and 116C and by two computing machines 100 of bus 117 and this that bus line 117A and 117B form with 104.At this, the 117th, the instruction bus in this instruction bus, identifies instruction address bus with 117A, and instructs (data) bus with the 117B identification division.Address bus 117A is connected with computing machine 100 by instruction address terminal IA1 (instruction address 1), and is connected with computing machine 101 by instruction address terminal IA2 (instruction address 2).Instruction itself is transmitted by part instruction bus 117B, and this part instruction bus 117B is connected with computing machine 100 by instruction terminal II (instruction 1) and is connected with computing machine 101 by instruction terminal I2 (instruction 2).In the instruction bus of being made up of 117A and 117B 117, the centre has connected assembly 103 (for example command memory, especially reliable command memory etc.).Especially this assembly as command memory also moves with clock CLK in this example.In addition, represent data bus with 116, this data bus comprises data address bus or data/address line 116A and data bus or data line 116B.At this, 116A (being data/address line) is connected with computing machine 100 by data address terminal DA1 (data address 1), and is connected with computing machine 101 by data address terminal DA2 (data address 2).Equally, data bus or data line 116B are connected with computing machine 100 by data terminal D01 (data output 1) and are connected with computing machine 101 by data terminal D02 (data output 2).In addition, data bus line 116C belongs to data bus 116, and (data input 2) is connected with computing machine 100 or computing machine 101 respectively this data bus line 116C with data terminal DI2 by data terminal DI1 (data input 1).In this data bus 116 of being made up of circuit 116A, 116B and 116C, the centre has connected assembly 104 (for example data-carrier store, especially reliable data-carrier store etc.).In this example, also provide clock CLK for this assembly 104.
At this, assembly 103 and 104 is represented assembly arbitrarily, these arbitrarily assembly be connected with the computing machine of duplex computer system by data bus and/or instruction bus, and according to obtaining or send vicious data and/or instruction to the data of duplex computer system and/or the visit of instruction aspect write operation and/or the read operation.For fear of mistake, though be provided with wrong identification generator 105,106 and 107, these wrong identification generators 105,106 and 107 produce such as the error identifications of parity check bit or also produce such as error correcting code (be ECC, Error-Correction-Code) another error code of Denging.So also be provided with corresponding error identification check device or calibration equipment 108 and 109, be used to check corresponding error sign, i.e. for example parity check bit or another error code as ECC) for this reason.
As shown in FIG. 1, the data of implementing about redundancy in duplex computer system and/or the comparison of instruction realize in comparer 110 and 111.If but now exist between computing machine 100 and 101 by nonsynchronous two-processor system or in the synchronous two-processor system by wrong in synchronously or also as in this specific example owing to expecting that the time migration or the clock period that are used for wrong identification are offset (especially these 1.5 clock period skew) caused time migration, especially clock skew or clock period skew, then in this time migration or clock skew, computing machine (at this computing machine 100 especially) may write or read in assembly with vicious data and/or instruction, especially external module, such as at this particularly in the storer 103 or 104, but also may relate to other user or executive component or sensor.Like this, this computing machine also may be carried out write access rather than set read access by this clock skew in vicious mode.Self-evident, especially under the situation that does not clearly illustrate that the possibility that has just in time changed which data and/or instruction mistakenly, these situations cause the mistake of total system, also produce the recovery problem thus.
In order to address this problem, now with in the circuit that delay cell 102 is connected to data bus as illustrated and/or be connected in the instruction bus.For reason clearly, only show the access in the data bus.Aspect instruction bus, this is just the same naturally to be possible and can to imagine.Delay cell 102 (Delay Unit) so postpones visit, in this especially memory access, so that especially when wrong identification, for example repay possible time migration or clock skew by for example at least one direct subsidy of comparer 110 and 111, up in duplex computer system, producing rub-out signal, i.e. execution error identification in duplex computer system.Can realize various flexible program at this:
Delayed write operation and read operation, only delayed write operation even perhaps be not preferably, also postpones read operation.At this, the write operation that is delayed can be transformed into read operation by variable signal, especially rub-out signal, so that forbid vicious writing.
Now, by Fig. 2 exemplary implementation about data allocations unit (DVE) is shown below, this data allocations unit (DVE) is preferably formed by being used for device, mode switching unit and Iram (combining random access memory) and Dram (dynamic RAM) control module that (passing through IllOPDetect) detect the conversion hope:
IllOpDetect (IllOP detection): the conversion between two kinds of patterns is discerned by " transition detection (Switch-Detect) " unit.This unit is between high-speed cache on the instruction bus and processor and watch, and whether instruction IllOp is loaded in the processor.If detect this instruction, then give mode switching unit with this event notice.There is " transition detection " unit individually at each processor." transition detection " unit needn't be implemented as fault-tolerant because should " transition detection " unit be double and therefore exist redundantly.On the other hand, what can imagine is individually to implement this unit, still preferably redundant embodiment fault-tolerantly and therefore.
ModeSwitch (mode switch): the conversion between two kinds of patterns triggers by " transition detection " unit.If should carry out the conversion from the locking mode to the clastotype, then two " transition detection " unit detect this conversion, because two processors are carried out identical program code under locking mode." transition detection " unit of processor 1 1.5 clocks before " transition detection " unit of processor 2 identify this point." mode switch " unit makes processor 1 stop two clocks by waiting signal.Processor 2 is stopped behind 1.5 clocks equally, but only stops clock half, so that make this processor 2 synchronous with system clock.Then, at other assembly, status signal is switched to separation, and these two processors work on.Carry out different tasks now for these two processors, these tasks must be separated in program code.This is by directly carrying out the read access of processor ID is realized after being transformed into clastotype.The processor ID that is read is different in these two processors each.If now specified processor ID is compared, then then utilize the condition jump instruction that corresponding processor is guided to other program point.When clastotype is transformed into locking mode, at first find this point for one in a processor or this two processors.This processor includes conversion instruction with the executive routine code in this program code.Now, this writes down by " transition detection " unit and this is notified to mode switching unit.This mode switching unit stops corresponding processor and by interruption synchronous hope is notified to second processor.Second processor obtains to interrupt and can carry out the software routines that is used to finish its task now.This processor jumps to the program point that instruction was positioned at that is used to change equally now.Its " transition detection " unit is signaled the mode conversion hope to mode switching unit now equally.Now, be used for the waiting signal of processor 1, and be used for the waiting signal of processor 2 in the deactivation afterwards of 1.5 clocks in the system clock edge deactivation of next rising.Now, these two processors are again with the clock skew synchronous working of 1.5 clocks.
If this system is in locking mode, then two " transition detection " unit must the notification mode converting units, and clastotype is wanted to enter in these two " transition detection " unit.Realized the conversion hope iff a unit, then identified this mistake by comparing unit, because one of these two processors continue data are offered these comparing units, and these comparator unit are inconsistent with the processor that is stopped.
If these two processors all are in clastotype and a processor is not converted back to locking mode, then this can discern by the exterior monitoring timer.Under the situation of the trigger pip that is used for each processor, watchdog timer notices that the processor of wait is no longer reported.If only there is a watchdog timer signal for this processor system, then the triggering of this watchdog timer only allows to realize under locking mode.Therefore, watchdog timer may identify, and does not have the implementation pattern conversion.Mode signal exists as the double track signal.At this, " 10 " represent locking mode and " 01 " represents clastotype.Under the situation of " 00 " and " 11 ", mistake has appearred.
IramControl: the visit to the command memory of these two processors is controlled by IRAMControl.This IRAMControl must design reliably, because it is single failpoint.IRAMControl is used for the state automata of each processor, the i.e. iram1clkreset of each clock synchronization and asynchronous readiram1 by two.Under the pattern to the security requirement strictness, the state automata of these two processors is monitored mutually, and under performance mode, the state automata of these two processors is work separately.
Reloading by two state automatas (that is synchronous regime automat iramclkreset and asynchronous mode automat readiram) of two high-speed caches of processor controlled.By these two state automatas, memory access also is assigned with under clastotype.In this case, processor 1 has higher priority.After 1 pair of primary memory of processor has carried out visit,, then give processor 2 allocate memory access permissions if these two processors want to visit primary memory again now.Realize this two state automatas at each processor.Under locking mode, the output signal of automat is compared, so that can discern the mistake of appearance.
The data that are used for renewal high-speed cache 2 under locking mode are delayed 1.5 clocks at the IRAM control module.
Which encode to relating to nuclear in the position 5 in the register 0 of SysControl.Nuclear 1 be position 0 and under nuclear 2 situation this position be height.It is in 65528 the memory block that this register is mapped to the address.
When the memory access of nuclear 2, check at first which kind of pattern computing machine is in.If computing machine is in locking mode, then its memory access is suppressed.This signal is as rail signal existence altogether, because this signal is to the security requirement strictness.
The programmable counter of processor 1 is delayed 1.5 clocks, so that can compare with the programmable counter of processor 2 under locking mode.
Under clastotype, the high-speed cache of these two processors can differently be reloaded.If be transformed into locking mode now, then these two high-speed caches are uncorrelated each other.Thus, these two processors can separate, and therefore comparer is signaled mistake.For fear of this point, in IRAMControl, set up label table.Indicate in this label table, cache line is still write under clastotype under locking mode.Under locking mode, corresponding typing item is set to 0 when cache line reloads for cache line, and (even at the high-speed cache of the cache line of a high-speed cache only more under the news) is set to 1 under clastotype.If processor is only implemented memory access under locking mode now, check then whether cache line is updated, just whether identical in these two high-speed caches under locking mode.Under clastotype, processor is the access cache row always, and how to have nothing to do with Flag_Vector.This form must only exist once, because these two processors separate and therefore identify this mistake reliably on comparer when mistake.Since high relatively to the access time of center form, so this form also can be copied to each high-speed cache.
DramControl: in this assembly, be address signal, data-signal and the parity checking of storer control signal formation of each processor.
There is the process that is used to block storer at these two processors.This process needn't be implemented reliably, because discern vicious memory access by comparer under locking mode, and does not implement the relevant application of security under clastotype.At this, check whether processor wants to block the storer of another processor.This obstruction of data-carrier store is realized by reference-to storage Di Zhi $FBFF$=64511.Even constantly have wait command calling on processor, also should just in time there be a clock in this signal.The state automata that is used for the management data memory access is made up of two main states:
The locking of-processor state: these two processors are operated under the locking mode.That is to say that the function of data-carrier store locking is optional.The visit of processor 1 coordinate memory.
-processor state separates: now, it is essential that the access conflict of data storer is solved, and must can realize the storer obstruction.
State under the clastotype is divided into 7 states again, and these 7 states solve access conflicts and can be respectively at another processor blocking data storer.When these two processors wished to visit simultaneously, listed order was represented priority simultaneously.
-Core1 _ Lock: processor 1 is the blocking data storer.If processor 2 wants to visit this storer in this state, then this processor 2 is stopped by waiting signal, till processor 1 discharges this data-carrier store again.
-Core2 _ Lock: state be that present processor 2 has blocked data-carrier store, and processor 1 is stopped when data memory operations with identical in the past.
-lock1 _ wait: when processor 1 was intended for own reserved data storer equally, this data-carrier store got clogged by processor 2.Therefore, the storer next time of registration process device 1 blocks in advance.
-nex: this is identical for processor 2.Data-carrier store gets clogged by processor 1 between trial period at obstruction.Storer is kept for processor 2 in advance.Under the situation of the memory access that does not have normally to block,, then manage device 2 herein and can before processor 1, visit if taken turns to processor 1 before.
The memory access of-processor 1: storer does not get clogged in this case.Processor 1 is allowed to accesses data memory.If this processor 1 wants to block this storer, then this processor 1 can carry out this point in this state.
The memory access of-processor 2: in same clock, processor 1 is not thought reference-to storage, so storer is idle for processor 2.
-there is not processor to want accesses data memory.
DVE is made up of conversion hope pick-up unit (IllOPDetect), mode switching unit and Iram and DramControl as mentioned like that.
Set forth the working method of mode switch below once more by Fig. 3:
The conversion of two processors exemplarily triggers by the instruction IllOp in the program at this.Prerequisite is: each processor can be identified uniquely.Each processor all is assigned with a numeral for this reason.Here a nuclear is 1 in this example, and another nuclear is 0.This is encoded in processor status register.
These two processors at this in order to be stopped synchronously by wait command.Stop the clock (for example by stopping, and continue supply with clock with 1 OR logic) of the processor that should be stopped with 0 OR logic equally always.
" transition detection (Switch-Detect) " unit: the conversion between two kinds of patterns is discerned by " transition detection " unit.This unit on the instruction bus between high-speed cache and processor, and watch, whether instruction IllOp is loaded in the processor.If detect this instruction, then give mode switching unit with this event notice.This identification is notified to " mode switch " unit by " Core 1-Signal (examining 1 signal) " or " Core2-Signal (examining 2 signals) " (referring to Fig. 2).There is " transition detection " unit individually at each processor.Should " transition detection " unit needn't be implemented as fault-tolerant because it be double and therefore exist redundantly.
" mode switch (Mode-Switch) " unit: the conversion between two kinds of patterns triggers by " transition detection " unit.If should carry out the conversion from the locking mode to the clastotype, then two " transition detection " unit detect this conversion, because two processors are carried out identical program code in locking mode." transition detection " unit of processor 1 1.5 clocks before " transition detection " unit of processor 2 identify this point.Should make processor 1 stop 2 clocks by waiting signal in " mode switch " unit.Processor 2 is stopped after 1.5 clocks equally, but only stops clock half, so that make this processor 2 synchronous with system clock.Then, at other assembly, status signal is switched to separation, and these two processors work on.Carry out different tasks now for these two processors, these tasks must be separated in program code.This is by directly carrying out the read access of processor ID is realized after being transformed into clastotype.The processor ID that is read each in these two processors all is different.If now specified processor ID is compared, then then can utilize the condition jump instruction that corresponding processor is guided to other program point.The example that separates two processors sees below:
In detachment process, at first the address of status register is written among the r1, wherein in this status register, has deposited processor ID,
LDL?r1，248
LDL?r1，255
Then instruct and separate two processors by IllOp,
error
The load content of the status register of address r1 in r2,
LDW?r2，r1
Detect the 5th locational position of this status register.If 0, be exactly that processor 1,1 relates to processor 2 so,
BTEST?r2，5
By the condition redirect processor 2 is guided to another program point now.
JMPI_CT?10
When clastotype is transformed into locking mode, one of a processor or two processors are at first noticed this point.This processor includes execution the program code of conversion instruction.Now, this is recorded by " transition detection " unit, and this is notified to " mode switch " unit.This unit stops corresponding processor, and by interrupting (" message 1 " among Fig. 2 or " message 2 ") synchronous hope is notified to second processor.This second processor obtains to interrupt, and can carry out the software routines that is used to finish its task now.This processor jumps to the program point that instruction was positioned at that is used to change equally now.Its " transition detection " unit is signaled the mode conversion hope to mode switching unit now equally.Now, be used for the waiting signal of processor 1, and be used for the waiting signal of processor 2 in the deactivation afterwards of 1.5 clocks in the system clock edge deactivation of next rising.Now, these two processors are again with the clock skew synchronous working of 1.5 clocks.
If this system is in locking mode, then two " transition detection " unit must the notification mode converting units, and clastotype is wanted to enter in these two " transition detection " unit.Realized the conversion hope iff a unit, then identified this mistake by comparing unit, because one of these two processors continue data are offered these comparing units, and these comparator unit are inconsistent with the processor that is stopped.
If these two processors all are in clastotype and a processor is not converted back to locking mode, then this can discern by the exterior monitoring timer.Under the situation of the trigger pip that is used for each processor, watchdog timer notices that the processor of wait is no longer reported.If only there is a watchdog timer signal for this processor system, then the triggering of this watchdog timer only allows to realize under locking mode.Therefore, watchdog timer may identify, and does not have the implementation pattern conversion.There is (being called state in the drawings) in mode signal as the double track signal.At this, " 10 " represent locking mode and " 01 " represents clastotype.Under the situation of " 00 " and " 11 ", mistake has appearred.
Because the instruction that is used to change just is detected in the beginning of the streamline of processor, so in pipeline stages, after described detection, do not allow to exist redirect.Being used to avoid the simplest method of this point is to introduce two NOp before instruction IllOp.
The core of this aspect be as mentioned above mode conversion method general working method (carry out different data allocations and therefore also select operational mode according to pattern respectively) and this especially processor synchronously.
But described particular embodiment has solved the described task of beginning in addition.
Claims (32)
1. be used for carrying out synchronous method at multicomputer system with at least two processors, wherein include conversion equipment, can between at least two kinds of operational modes, change by this conversion equipment, wherein undertaken synchronously by stop signal, this stop signal stops leading processor, so that make this processor and at least the second processor synchronous.
2. according to claim 1 being used to carried out synchronous method, it is characterized in that, describedly triggers by synchronous hope synchronously, and wherein this synchronous hope can be produced by one or more processors.
3. according to claim 1 being used to carried out synchronous method, it is characterized in that, the waiting signal of processor is used as stop signal.
4. according to claim 1 being used to carried out synchronous method, it is characterized in that look-at-me is triggered as stop signal.
5. according to claim 1 being used to carried out synchronous method, it is characterized in that, described processor is in order to be stopped by ignoring the clock period synchronously.
6. according to claim 1 being used to carried out synchronous method, it is characterized in that, described processor is in order to be stopped by cutting off clock signal synchronously.
7. according to claim 1 being used to carried out synchronous method, it is characterized in that, described conversion is represented by the conversion hope, and this conversion hope triggers by signal.
8. according to claim 1 being used to carried out synchronous method, it is characterized in that, described conversion is represented by the conversion hope, wherein when two or more processors propose this conversion hope, just carried out described conversion.
9. according to claim 1 being used to carried out synchronous method, it is characterized in that, described conversion triggers by the conversion hope, wherein change the operational mode of described multicomputer system according to the conversion hope, and this conversion hope shows by signal.
10. according to claim 1 being used to carried out synchronous method, it is characterized in that, existing operational mode shows by mode signal.
11. according to claim 10 being used to carried out synchronous method, it is characterized in that, described mode signal is as coded signal, especially exist as the double track signal.
12. according to claim 10 being used to carried out synchronous method, it is characterized in that, described mode signal especially generates by two state automatas or by double rail logic redundantly.
13. according to claim 1 being used to carried out synchronous method, it is characterized in that, hope is directed into central location synchronously, and this central location is forwarded at least one other processor with described synchronous hope.
14. according to claim 1 being used to carried out synchronous method, it is characterized in that, and be described synchronous by notifying the conversion hope to carry out, and described processor jumps to program address given in advance thus.
15. according to claim 1 being used to carried out synchronous method, it is characterized in that, described processor is stopped always, till another processor has executed task and arrived identical program point equally then.
16. according to claim 1ly be used to carry out synchronous method, it is characterized in that, after synchronously, in order to desynchronize, described two processors according in described multicomputer system for each processor unique sign (ID) jump to different program points, and therefore desynchronized.
17. be used for carrying out synchronous equipment at multicomputer system with at least two processors, wherein include conversion equipment, can between at least two kinds of operational modes, change by this conversion equipment, wherein this equipment so is configured, make and undertaken synchronously by stop signal, wherein this stop signal stops leading processor, so that make this processor and at least the second processor synchronous.
18. according to claim 17ly be used to carry out synchronous equipment, it is characterized in that, first operational mode is corresponding to safe mode, two processors are carried out identical program in this safe mode, and be provided with comparison means, the consistance of the state that this comparison means comparison occurs when carrying out described identical program.
19. according to claim 1 being used to carried out synchronous equipment, it is characterized in that, described equipment so is configured, and makes the waiting signal of processor be used as stop signal.
20. according to claim 17 being used to carried out synchronous equipment, it is characterized in that, described equipment so is configured, and makes look-at-me be triggered as stop signal.
21. according to claim 17 being used to carried out synchronous equipment, it is characterized in that, described equipment so is configured, and makes described processor in order to be stopped by ignoring the clock period synchronously.
22. according to claim 17 being used to carried out synchronous equipment, it is characterized in that, described equipment so is configured, and makes described processor in order to be stopped by cutting off clock signal synchronously.
23. according to claim 17 being used to carried out synchronous equipment, it is characterized in that, described equipment so is configured, and makes existing operational mode show by mode signal.
24. according to claim 23 being used to carried out synchronous equipment, it is characterized in that, described equipment so is configured, and makes described mode signal as coded signal, especially exist as the double track signal.
25. according to claim 23 being used to carried out synchronous equipment, it is characterized in that, described equipment so is configured, and makes described mode signal especially generate by two state automatas or by double rail logic redundantly.
26. according to claim 17ly be used to carry out synchronous equipment, it is characterized in that, be provided with central location, and described equipment so is configured, make synchronous hope be directed into central location, and this central location is forwarded at least one other processor to described synchronous hope.
27. according to claim 17ly be used to carry out synchronous equipment, it is characterized in that, described equipment so is configured, and makes described processor be stopped always, till at least the second processor has executed task and arrived identical program point equally then.
28. according to claim 17ly be used to carry out synchronous equipment, it is characterized in that, described equipment so is configured, make after synchronously, in order to desynchronize, two processors according in described multicomputer system for each processor unique sign (ID) jump to different program points and therefore desynchronized.
29. according to claim 28 being used to carried out synchronous equipment, it is characterized in that, is provided with the processor register, and described sign is stored in this processor register.
30. equipment according to claim 28 is characterized in that, described sign is stored the outside at described processor, especially is stored in central location (DramCtrl).
31. according to claim 17 being used to carried out synchronous equipment, it is characterized in that, especially by state automata double or the realization of double rail logic is designed for the conversion equipment of conversion operation pattern fault-tolerantly.
32. have multicomputer system according to the described equipment of one of claim 17 to 31.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE200410051952 DE102004051952A1 (en) | 2004-10-25 | 2004-10-25 | Data allocation method for multiprocessor system involves performing data allocation according to operating mode to which mode switch is shifted |
| DE102004051937.4 | 2004-10-25 | ||
| DE102004051964.1 | 2004-10-25 | ||
| DE102004051950.1 | 2004-10-25 | ||
| DE102004051992.7 | 2004-10-25 | ||
| DE102004051952.8 | 2004-10-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101048761A true CN101048761A (en) | 2007-10-03 |
| CN100555233C CN100555233C (en) | 2009-10-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 200580036538 Pending CN101048754A (en) | 2004-10-25 | 2005-10-25 | Method and device for distributing data from at least data source in multiprocessor system |
| CN 200580036461 Expired - Fee Related CN100585567C (en) | 2004-10-25 | 2005-10-25 | Method and device for delaying multiprocessor system data and/or dictation visit |
| CN 200580036617 Expired - Fee Related CN100555233C (en) | 2004-10-25 | 2005-10-25 | Be used for carrying out synchronous method and apparatus at multicomputer system |
| CN 200580036488 Expired - Fee Related CN100511167C (en) | 2004-10-25 | 2005-10-25 | Method and device for monitoring memory cell of multiprocessor system |
| CN 200580036441 Pending CN101048745A (en) | 2004-10-25 | 2005-10-25 | Method and device for switching over in multiprocessor system |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 200580036538 Pending CN101048754A (en) | 2004-10-25 | 2005-10-25 | Method and device for distributing data from at least data source in multiprocessor system |
| CN 200580036461 Expired - Fee Related CN100585567C (en) | 2004-10-25 | 2005-10-25 | Method and device for delaying multiprocessor system data and/or dictation visit |
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| CN 200580036488 Expired - Fee Related CN100511167C (en) | 2004-10-25 | 2005-10-25 | Method and device for monitoring memory cell of multiprocessor system |
| CN 200580036441 Pending CN101048745A (en) | 2004-10-25 | 2005-10-25 | Method and device for switching over in multiprocessor system |
Country Status (2)
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| CN (5) | CN101048754A (en) |
| DE (1) | DE102004051952A1 (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102246155A (en) * | 2008-12-10 | 2011-11-16 | 飞思卡尔半导体公司 | Error detection in a multi-processor data processing system |
| CN103403634A (en) * | 2011-03-15 | 2013-11-20 | 欧姆龙株式会社 | Control device and system program |
| CN103415819A (en) * | 2011-03-15 | 2013-11-27 | 欧姆龙株式会社 | Control device and system program, and recording medium |
| CN111213062A (en) * | 2017-09-14 | 2020-05-29 | Bae系统控制有限公司 | Mitigating common mode computation failures using a multi-core processor |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106850944A (en) * | 2016-12-13 | 2017-06-13 | 北京元心科技有限公司 | Smart machine awakening method and device |
| CN110018907A (en) | 2019-01-16 | 2019-07-16 | 阿里巴巴集团控股有限公司 | Promote the method and device and electronic equipment of cpu performance |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE1269827B (en) * | 1965-09-09 | 1968-06-06 | Siemens Ag | Method and additional device for the synchronization of data processing systems working in parallel |
-
2004
- 2004-10-25 DE DE200410051952 patent/DE102004051952A1/en not_active Withdrawn
-
2005
- 2005-10-25 CN CN 200580036538 patent/CN101048754A/en active Pending
- 2005-10-25 CN CN 200580036461 patent/CN100585567C/en not_active Expired - Fee Related
- 2005-10-25 CN CN 200580036617 patent/CN100555233C/en not_active Expired - Fee Related
- 2005-10-25 CN CN 200580036488 patent/CN100511167C/en not_active Expired - Fee Related
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Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102246155A (en) * | 2008-12-10 | 2011-11-16 | 飞思卡尔半导体公司 | Error detection in a multi-processor data processing system |
| CN102246155B (en) * | 2008-12-10 | 2014-10-15 | 飞思卡尔半导体公司 | Error detection in a multi-processor data processing system |
| CN103403634A (en) * | 2011-03-15 | 2013-11-20 | 欧姆龙株式会社 | Control device and system program |
| CN103415819A (en) * | 2011-03-15 | 2013-11-27 | 欧姆龙株式会社 | Control device and system program, and recording medium |
| CN103415819B (en) * | 2011-03-15 | 2016-01-06 | 欧姆龙株式会社 | Control device and control method |
| CN103403634B (en) * | 2011-03-15 | 2016-08-10 | 欧姆龙株式会社 | Control device and control method thereof |
| CN111213062A (en) * | 2017-09-14 | 2020-05-29 | Bae系统控制有限公司 | Mitigating common mode computation failures using a multi-core processor |
| CN111213062B (en) * | 2017-09-14 | 2022-11-29 | Bae系统控制有限公司 | Mitigating common mode computation failures using a multi-core processor |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101048747A (en) | 2007-10-03 |
| CN101048754A (en) | 2007-10-03 |
| CN101048745A (en) | 2007-10-03 |
| DE102004051952A1 (en) | 2006-04-27 |
| CN100585567C (en) | 2010-01-27 |
| CN100511167C (en) | 2009-07-08 |
| CN100555233C (en) | 2009-10-28 |
| CN101048749A (en) | 2007-10-03 |
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