CN101047480A - Data mapping method and device - Google Patents
Data mapping method and device Download PDFInfo
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- CN101047480A CN101047480A CN 200610034802 CN200610034802A CN101047480A CN 101047480 A CN101047480 A CN 101047480A CN 200610034802 CN200610034802 CN 200610034802 CN 200610034802 A CN200610034802 A CN 200610034802A CN 101047480 A CN101047480 A CN 101047480A
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Abstract
A mapping device of data consists of hole punching module for carrying out three or four modes of hole punching on application data of data packet Block to obtain data P1, P2 and P3 or data P1, P2, P3 and P4 accordingly, interlacing module for interlacing data and for sending interlaced data to mapping module, and mapping module for mapping said Block into at least four time slots. Its mapping method is also disclosed.
Description
Technical field
The present invention relates to the communication technology, relate in particular to the data map technology in the communication system.
Background technology
Growing along with the high-speed multimedia data business demand, radio communication requires wideer band resource to satisfy the transmission of broadband data service, and the finiteness of band efficiency becomes the bottleneck of restriction broadband data service development, therefore how on limited bandwidth, to improve message transmission rate to greatest extent, just how to improve band utilization efficient to greatest extent and become one of key link of 3G (Third Generation) Moblie and future communications system.Simultaneously, to the demand of high-speed multimedia business, impel mobile radio system to adopt new technology to improve transmission rate and power system capacity.
EDGE (Enhanced Data rates for GSM Evolution, Enhanced Data rates for GSM Evolution) as GPRS (General Packet Radio Service, GPRS) enhancement mode evolution technology, can with UMTS (Universal Mobile Telecommunications System, universal mobile telecommunications system) shared core net, original base station sub-system BSS is developed into GSM (Global System for Mobilecommunications, global system for mobile communications)/EDGE wireless access network GERAN (GSM EDGERadio Access Network, GSM EDGE wireless access network), with UMTS Terrestrial radio access network UTRAN (UMTS Terrestrial radio access network, UMTS Terrestrial radio access network) and deposit, provide high-speed data service.
The high-speed data throughput of EDGE mainly is because adopt 8PSK (8Phase Shift Keying, 8 phase shift keyings) modulation technique, simultaneously, in conjunction with different entangle, the channel coding schemes of error detecing capability, EDGE provides 9 kinds of different MCS (Modulation and Coding Scheme, modulation coding mode) altogether, four kinds of CS (Coding Scheme that provide than the GPRS that uses single modulation technique, coded system), EDGE can adapt to more abominable, wireless propagation environment widely.
Described 9 kinds of MCS are divided into 3 groups according to correlation properties each other, promptly Family A (MCS-3, MCS-6, MCS-8, MCS-9), Family B (MCS-2, MCS-5, MCS-7) and Family C (MCS-1, MCS-4).Have between the structure of several encoding schemes in each group and comprise mutually or involved relation, be easier to realize the conversion of code rate.Transfer rate and effective two factors of Transfer Quality of needing the balance effective information in the practical application, it is less and low rate channel encoding scheme that comprise more redundant correcting bit more is applicable in the relatively poor environment of transmission quality to transmit effective information, as the MCS1-4 under cell boarder use speed preferably GMSK on the low side (Gaussian Minimum Shift Keying, Guassian Minimum Shift Keying GMSK) modulation system to compensate relatively poor link-quality; In propagation conditions better cell central area, can adopt the higher MCS of information rate.
At present, EDGE has adopted link adaptation and incremental redundancy function on data transmission and retransmission mechanism, and the data re-transmitting success rate on average improves 10-20% than GPRS.
Link adaptation functionality is promptly in time adjusted optimal MCS scheme according to real-time radio link quality between different MCS.The normal data piece transmits to change under the correct situation and can carry out between 9 kinds of data rates to obtain the optimum balance of transmission quality and throughput.When wireless environment worsens and causes wrong biography of data block and when needing to retransmit, code rate can but conversion mutually between can only several MCS in same group with inclusion relation, therefore data block entrained redundant information in front and back has enough correlations so that demodulation.
Thereby being EDGE, incremental redundancy in retransmission of information, adds the probability that more redundant information improves the correct demodulation of receiving terminal.When receiving terminal detected the fault frame, GPRS can delete the fault data piece of receiving, and required transmitting terminal to retransmit identical data block (using identical CS) once more, promptly simple mixed automatic retransmission request (HARQ) type one.EDGE has pardon on the same group owing to institute adopts between the MCS, mix re-send request may-HARQ type two so in fact the retransmission mechanism that EDGE adopts is exactly full increment, promptly the redundant correcting bit that adds in several data blocks in succession of front and back has part correlation, therefore EDGE can be in receiving terminal storage failure data block rather than deletion, transmitting terminal is retransmitted different MCS data blocks in the use on the same group, information bit in the comprehensive last time fault data piece of receiving terminal, redundant information, this information bit, information such as redundant informations etc. are in many ways comprehensively entangled, make correlation demodulation after error detection is analyzed and receive, with the amount of information raising reception success rate of " redundancy ".
Based on above-mentioned technology, GERAN is the speed that further improves transfer of data in the process of evolution, just need to reduce the time delay in the transmission as far as possible, reduce the research of propagation delay time at present and mainly concentrate both ways: quick A CK/NACK and RTTI (Reduced TTI, the TTI after the minimizing).
Transfer of data is Block at the minimum scheduling unit of physical layer at present, and each Block is made up of 4 time slots, and lays respectively at 4 continuous tdma frames, so the propagation delay time of each Block all is 20ms.As shown in Figure 1,52 time slots of 52 multi-frames are arranged according to figure below, have 12 Block:B
0, B
1, B
2, B
3, B
4, B
5, B
6, B
7, B
8, B
9, B
10, B
11, the cycle of each 52 multi-frame is 240ms, the evaluation duration of each Block equals 20ms like this, also is the length of a TTI (Transmission TimingInterval, transmission intercal).
Any high level data all must be encapsulated in the Block and transmit, like this each high-rise data time delay of passing through 20ms at least.When data volume hour, data also all are distributed in whole four time slots of whole Block and just seem unnecessary, and time delay is bigger, proposes a kind of Block of variable-size for this reason, i.e. VSRB (Variable-sized Radio Blocks, the piece of variable-size).
Some control informations during the professional main index of small data is reportedly defeated, as ACK/NACK, data are after the transmission some, and transmitting terminal need be waited for the affirmation message of receiving terminal, and the transmission speed that then improves this acknowledge message just seems extremely important.Because such affirmation message data is all very little, the data volume that can carry much smaller than a Block, so VSRB can reduce the transfer delay of data by the slot transmission that these acknowledge message data is placed on beginning as far as possible.
As shown in Figure 2, be the schematic diagram of a kind of data map process of prior art, the packet of an application layer (Block) 20 comprises data head A and application data P, and packet 20 is mapped to 4 time slots by interweaving: time slot 21,22,23,24.Data head A and application data P are evenly distributed in respectively in each time slot, and promptly 1/4th data head A (being A/4) the application data P (being P/4) that is mapped to time slot 21,22,23,24 and 1/4th respectively is mapped to time slot 21,22,23,24 respectively.The data placement of each time slot shown in Figure 2 only represents that A/4 has been placed on 4 time slots, does not represent that these A/4 are placed on time slot edge, and concrete laying method is the mapping structure schematic diagram of data by each time slot of mapping back that interweaves as shown in Figure 3.
As Fig. 3, each time slot comprises data (data) 31A, 31B, data head (header) 32A, 32B, and uplink state sign (USF, Uplink State Flag) 33A, 33B is used to indicate the SB34 of MCS mode.Wherein, magnitude relationship is:
data31A+data31B＝P/4，data31A＝data31B＝153bits；
header32A+header32B＝A/4，header32A＝15bits，header32B＝16bits；
USF33A＝6bits，USF33B＝3bits；
SB34＝2bits。
If do not adopt VSRB, then receiving terminal has only and all receives 4 time slots: behind the time slot 21,22,23,24, could demodulation obtain entrained data.
If but when adopting VSRB, according to what difference of data volume, receiving terminal may only need to receive the information that forward several time slots just can demodulate whole, particularly when data volume seldom the time, receiving terminal may only need to receive the data that preceding 1 or 2 time slots just can obtain whole Block.Then can make time slot data information the most forward in the VSRB, other remaining time slot transmits the redundant information of these data messages.Take all factors into consideration complexity and performance at present, general VSRB only gets the block size of 2 or 4 time slots, promptly or in 2 time slots has passed, or has passed data at whole 4 time slots.
Transmit in 2 time slots for realizing that the data of 4 slot transmission are placed on originally, then 2 of the front time slots just must comprise the entire header of 1 Block, and 2 time slots of back transmit the redundant information of these data messages.Therefore, data head A must all be mapped in preceding 2 time slots, and the data map structure chart of these preceding 2 time slots all as shown in Figure 4.
The data map structural representation of Fig. 4 is similar substantially to the data map structural representation of Fig. 3, and its difference is, has increased by two header in the data map structural representation of Fig. 4, and:
Header42A+header42B+header42C+header42D=A/2, header42A=header42C=16bits wherein, header42B=header32D=15bits.
As can be seen from Figure 4, when whole Block will be when preceding 2 time slots have passed, the header information that each time slot carries is just more, specifically be 2 times of above-mentioned non-VSRB, the header information that increases has taken the position of prior partial data, and then data41A, data41B are much smaller with respect to data31A, data31B.
During transfer of data, useful information transmits in preceding 2 time slots to be finished, and does not come when receiving terminal correctly demodulates data in preceding 2 time slots, just need continue to read 2 follow-up time slots, such 4 time slots demodulating data of joining together.Hence one can see that, and when preceding 2 time slots correctly received, actual TTI was 10ms, and current 2 time slots can not correctly be separated timing, and TTI just equals 20ms.
Summary of the invention
Have in view of that, the invention provides a kind of data mapping method and device, make data under the situation of preceding 2 slot transmission mistakes, also can obtain certain TTI and improve, TTI is further dwindled.
A kind of data mapping method wherein, mainly comprises:
Steps A is carried out three kinds of modes to the application data of packet Block and is punched, and obtains three segment datas: data P1, P2, P3;
Step B is mapped at least four time slots with packet Block, wherein the partial data head of the above-mentioned Block of the common carrying of first, second time slot and the above-mentioned data P1 of carrying jointly, and data P2 is mapped to the 3rd time slot, and data P3 is mapped to the 4th time slot at least.
A kind of data mapping method wherein, mainly comprises:
Steps A is carried out four kinds of modes to the application data of packet Block and is punched, and obtains four segment datas: data P1, P2, P3, P4;
Step B is mapped at least four time slots with packet Block, and wherein the partial data head of packet Block and data P1 are mapped to first time slot, and data P2 is mapped to second time slot, and data P3 is mapped to the 3rd time slot, and data P4 is mapped to the 4th time slot at least.
A kind of data mapping unit, mainly comprise the punching module, interleaving block and mapping block, wherein, the punching module is carried out three kinds of modes to the application data of packet Block and is punched, obtain three segment datas: data P1, P2, P3, and this three segment data passed to interleaving block, interleaving block interweaves to above-mentioned three segment datas and passes to mapping block, mapping block is with data head and the data P1 of packet Block, P2, P3 is mapped at least four time slots: partial data head and the data P1 of above-mentioned Block are mapped to first, second time slot, data P2 is mapped to the 3rd time slot, data P3 is mapped to the 4th time slot at least.
A kind of data mapping unit, mainly comprise the punching module, interleaving block and mapping block, wherein, the punching module is carried out four kinds of modes to the application data of packet Block and is punched, obtain four segment datas: data P1, P2, P3, P4, and this four segment data passed to interleaving block, interleaving block interweaves to above-mentioned four segment datas and passes to mapping block, mapping block just packet Block is mapped at least four time slots: partial data head and the data P1 of packet Block are mapped to first time slot, data P2 is mapped to second time slot, data P3 is mapped to the 3rd time slot, data P4 is mapped to the 4th time slot at least.
Compared with prior art, because data mapping method of the present invention adopts three kinds or four kinds of hole knockouts to the application data of packet Block, the corresponding data that obtain three sections or four sections, when this multiple segment data is mapped at least four time slots, because the 3rd time slot is the data segment of a certain hole knockout of carrying separately, so when these four time slots are sent and receive decoding, when first, when second slot decoder is incorrect, can carry out first, second, the combined decoding of the 3rd time slot, if decoding is correct, then can shorten TTI, and needn't carry out first, second, the 3rd, the combined decoding of the 4th time slot.
Description of drawings
Fig. 1 is that 52 time slots of 52 multi-frames of prior art are arranged schematic diagram.
Fig. 2 is the schematic diagram of a kind of data map process of prior art.
Fig. 3 is the structural representation of each time slot after the data map that does not adopt VSRB of prior art.
Fig. 4 is the data map structural representation of preceding 2 time slots after the data map of VSRB of prior art.
Fig. 5 is the data map step block diagram of the present invention's preferable first execution mode.
Fig. 6 is the data map process schematic diagram of the present invention's preferable first execution mode.
Fig. 7 shines upon the data map structural representation of each time slot of back for the Block of the present invention's preferable first execution mode by interweaving.
Fig. 8 is the data transmission procedure schematic diagram of the present invention's preferable first execution mode.
Fig. 9 is the data map step block diagram of the present invention's preferable second execution mode.
Figure 10 is the data map process schematic diagram of the present invention's preferable second execution mode.
Figure 11 is preferable a kind of data mapping unit block diagram of the present invention.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, below in conjunction with embodiment and accompanying drawing, the present invention is further detailed explanation.
As shown in Figure 5, be the data map step block diagram of the present invention's preferable first execution mode, the main process of this data mapping method is as described below.
As shown in Figure 6, be the data map process schematic diagram of present embodiment, the packet of an application layer (Block) 50 comprises data head A and application data, to this application data, adopts three kinds of modes to punch, and obtains data P1, P2, P3.In the reality, the length of data P1, P2, P3 is can the data carried by data size determine that but preferable, in the present embodiment, after the punching, the length relation of data is by lower floor: data P1＞data P2=data P3, and data P1 contains more useful information.
Block50 is mapped to 4 time slots by interweaving: time slot 51,52,53,54, be specially, and the complete data head A of packet Block and data P1 are carried jointly by time slot 51 and time slot 52, and data P2 is mapped to time slot 53, and data P3 is mapped to time slot 54.
Wherein, data head A is mapped to how much not limiting of time slot 51 and time slot 52, can obtain complete data head A as long as satisfy after time slot 51 is decoded with time slot 52.
Data head A whether is mapped to time slot 53 or time slot 54 does not limit, and if shine upon then data head A mapping what also do not limit, all or part of of data head A can be mapped to respectively on time slot 53 and the time slot 54; Can be not yet with the data map of data head A on time slot 53 and time slot 54; Also data head A all or part of can be mapped on the time slot 53 or the like, but when data head A all or part of is mapped to time slot 54, all or part of time slot 53 that is mapped to of data head A must be arranged.
Therefore, it is as described below that the data head A of Block50 is mapped to the main mode of time slot 51,52,53,54 by interweaving.
First kind of mapping mode: complete data head A is mapped to respectively on the time slot 51,52,53,54 by interweaving.
Second kind of mapping mode: complete data head A is carried jointly by time slot 51 and time slot 52, and all or part of data of data head A are mapped to respectively on the time slot 53,54 by interweaving.
The third mapping mode: complete data head A is carried jointly by time slot 51 and time slot 52, and all or part of data of data head A are mapped on the time slot 53 by interweaving, and the data map that does not have data head A is to time slot 53.
But in actual applications, consider the accuracy of decoding, generally all or part of data map of data head A can be arrived time slot 53, or all or part of data of data head A are mapped to time slot 53,54 respectively, preferable, be that complete data head A is mapped to time slot 53 or is mapped to time slot 53,54 respectively.
For reaching preferable effect, present embodiment adopts mapping mode as shown in Figure 6, and to complete data head A: 1/2nd data head A (A/2) are mapped to time slot 51,52 respectively, and complete data head A is mapped to time slot 53,54 respectively.Then, being mapped as of application data P1, P2, P3: 1/2nd data P1 (P1/2) are mapped to time slot 51,52 respectively; Data P2 is mapped to time slot 53; Data P3 is mapped to time slot 54.
Wherein, the arrangement of the partial data head A of the A/2 data head of time slot 51,52 mappings shown in Figure 6 and time slot 53,54 mappings only represents that the data head data are placed in these 4 time slots, do not represent that these data head data are placed on time slot edge, concrete laying method is the Block of the present embodiment data map structural representation by each time slot of mapping back that interweaves as shown in Figure 7.
As shown in Figure 7, blank box indicating application data data, box indicating Header1 with right tiltedly analysis line, box indicating Header2 with grid analysis line, has the tiltedly box indicating Header3 of analysis line of a left side, box indicating Header4 with vertical bar analysis line, the box indicating uplink state with horizontal stripe analysis line identifies USF, and the box indicating with shade is used to indicate the SB of coded system.
Then, to time slot 51:
The data sum of both sides equals P1/2; 2 Header1+2 Header2=A/2.
To time slot 52:
The data sum of both sides equals P1/2; 2 Header3+2 Header4=A/2.
To time slot 53:
The data sum of both sides equals P2;
2 Header1+2 Header2+2 Header3+2 Header4=A.
To time slot 54:
The data sum of both sides equals P3;
2 Header1+2 Header2+2 Header3+2 Header4=A.
Wherein, do not provide the size of every data block in each time slot (being each square frame) among the figure, this is because according to different modulation systems (GMSK or 8PSK), the size of data block also can be different, and the placement location of each data head is a kind of best placement among the figure, and the location swap of an interior data head of time slot does not influence effect of the present invention.
Because there is above-mentioned mapping method in Block50, thus when transmission, its transmission course as shown in Figure 8, concrete transmission course is as described below.
Because the application data to Block50 adopts three kinds of hole knockouts, obtain data P1, P2, P3, so, redundant information is more if the contained useful information of the application data of Block50 is few, in the time of then might punching useful information is concentrated on data P1 substantially, and when mapping, the complete data head A of time slot 51,52 common carrying Block50 and common carrying data P1, so transmitting terminal to the data of receiving terminal sending time slots successively 51,52, then might send more useful information to receiving terminal.
Redundant information is more if the contained useful information of the application data of Block50 is few, and the data P1 of the time slot 51,52 of then might decoding just can obtain correct decoding.Therefore, when decoding when correct, receiving terminal is to transmitting terminal feeding back ACK information, DTD, and then TTI is just less, is generally 10ms.
Incorrect if decode, then continue execution in step 803.
Transmitting terminal continues sending time slots 53, receiving terminal receiving slot 53, and carry out the combined decoding of time slot 51,52,53.
Because the application data to Block50 adopts three kinds of hole knockouts, obtain data P1, P2, P3 respectively, during mapping, data P1 is mapped to time slot 51,52, and data P2 is mapped to time slot 53, then can carry out the combined decoding of time slot 51,52,53, when if the data of useful information are not a lot, it is correct then might to decode, and for further improving the decoding accuracy, complete data head A can be mapped on the time slot 53.
At receiving terminal, if carrying out combined decoding, time slot 51,52,53 can decode correctly, then receiving terminal is to transmitting terminal feeding back ACK information, DTD, then TTI is just less, is generally 15ms.
If time slot 51,52,53 carries out combined decoding, it is correct to decode, and then receiving terminal continues execution in step 804.
Preferable first execution mode has only been described the mapping method that carries out three kinds of hole knockouts, but the present invention is not limited to three kinds of hole knockouts, can carry out at least three kinds hole knockout, but consider, generally carry out the hole knockout of three kinds and four kinds from the angle of complexity and performance.
As shown in Figure 9, be the data map step block diagram of the present invention's preferable second execution mode, the main process of this data mapping method is as described below.
Step 601 is carried out four kinds of modes to the application data of packet Block and is punched, to obtain four segment datas: data P1, P2, P3, P4;
As shown in figure 10, be the data map process schematic diagram of present embodiment, the packet of an application layer (Block) 60 comprises data head A and application data, to this application data, adopts four kinds of modes to punch, and obtains data P1, P2, P3, P4.In the reality, the length of data P1, P2, P3, P4 is can the data carried by data size to be determined by lower floor, but preferable, in the present embodiment, after the punching, the length relation of data is: data P1=data P2=data P3=data P4, and data P1 contains more useful information.
Block60 is mapped to 4 time slots by interweaving: time slot 61,62,63,64, be specially, complete data head A and the data P1 of packet Block are mapped to time slot 61, and data P2 is mapped to time slot 62, data P3 is mapped to time slot 63, and data P4 is mapped to time slot 64.
Wherein, what of data head data whether data head A is mapped to after time slot 62,63,64 and the mapping do not limit, and all or part of of data head A can be mapped to respectively on the time slot 62,63,64; Can be not yet with the data map of data head A to time slot 62,63,64, also all or part of time slot 62,63 that is mapped to respectively of data head A also can be mapped to all or part of of data head A respectively on the time slot 62, or the like.But when data head A had data map to arrive time slot 64, then data head A need have data map to arrive time slot 62,63; In like manner, when data head A had data map to arrive time slot 63, then data head A need have data map to arrive time slot 62.
But in actual applications, consider the accuracy of decoding, generally all or part of data map of data head A can be arrived time slot 62,63,64, when data head A whole are mapped to time slot 62,63,64, be to be mapped to time slot 62 at least by the complete data head A of 62, the 63 common carryings of the time slot at least in the time slot 62,63,64 or with partial data head A.Preferable, be that complete data head A is mapped to time slot 62, or be mapped to time slot 62,63 respectively, or be mapped to time slot 62,63,64 respectively.
For reaching preferable effect, present embodiment adopts mapping mode as shown in figure 10, and complete data head A is mapped to time slot 61,62,63,64 respectively, and promptly time slot 61,62,63,64 all carries complete data head A; Data P1 is mapped to time slot 61, and data P2 is mapped to time slot 62, and data P3 is mapped to time slot 63, and data P4 is mapped to time slot 64.
So packet Block60 is in when transmission, its transmission course is similar to the transmission course of the packet Block50 of second execution mode basically.
Its difference is, because the application data of Block60 is adopted four kinds of hole knockouts, obtains data P1, P2, P3, P4 respectively, during mapping, data P1 is mapped to time slot 61, and data P2 is mapped to time slot 62, data P3 is mapped to time slot 63, and data P4 is mapped to time slot 64.
So during packet Block60 transmission, transmitting terminal sending time slots 61, receiving terminal receiving slot 61 and decoding, when the contained useful information of packet Block60 was few, it was correct then might to decode, and then receiving terminal is to transmitting terminal feeding back ACK information, DTD, then TTI is very little, is generally 5ms; Incorrect if decode, transmitting terminal continues sending time slots 62.
Transmitting terminal continues sending time slots 62, and receiving terminal receiving slot 62 also carries out the combined decoding of time slot 61,62, if decoding is correct, receiving terminal is to transmitting terminal feeding back ACK information, DTD, and then TTI is less, is generally 10ms; Incorrect if decode, transmitting terminal continues sending time slots 63.
Transmitting terminal continues sending time slots 63, and receiving terminal receiving slot 63 also carries out the combined decoding of time slot 61,62,63, if decoding is correct, receiving terminal is to transmitting terminal feeding back ACK information, DTD, and then TTI is less, is generally 15ms; Incorrect if decode, transmitting terminal continues sending time slots 64.
Transmitting terminal continues sending time slots 64, and receiving terminal receiving slot 64 also carries out the combined decoding of time slot 61,62,63,64, if decoding is correct, receiving terminal is to transmitting terminal feeding back ACK information, DTD, and then TTI is generally 20ms; Incorrect if decode, receiving terminal feeds back nack message to transmitting terminal, and the request transmitting terminal carries out data re-transmission.
The present invention also provides a kind of data mapping unit, data mapping unit block diagram as shown in figure 11, this data mapping unit mainly comprises punching module, interleaving block, mapping block, the punching module is carried out the punching of three kinds of modes or four kinds of modes to the application data of packet Block, corresponding three segment datas or four segment datas of obtaining.
When the punching module is carried out three kinds of modes when punching to the application data of packet Block, obtain three segment data P1, P2, P3 and pass to interleaving block, interleaving block carries out interleaving treatment and passes to mapping block this three segment data, mapping block is mapped to four time slots with packet Block, make partial data head and the above-mentioned data P1 of common carrying of the above-mentioned Block of the common carrying of first, second time slot, data P2 is mapped to the 3rd time slot, data P3 is mapped to the 4th time slot.
Whether the data head of described packet Block is mapped to the 3rd time slot to mapping block or the 4th time slot does not limit, if and shine upon then data head mapping what also do not limit, mapping block can be mapped to all or part of of data head respectively on the 3rd time slot and the 4th time slot; Also not on data map to the three time slots and the 4th time slot with data head; Also can be only data head all or part of be mapped on the 3rd time slot or the like, but when mapping block is mapped to the 4th time slot with data head all or part of, must has partial data at least to be mapped to the 3rd time slot data head.
Consider the accuracy of decoding, mapping block generally can be with all or part of data map to the three time slots of data head, or all or part of data of data head are mapped to the 3rd, the 4th time slot respectively.Preferable, in actual applications, mapping block is that complete data head is mapped to the 3rd time slot or is mapped to the 3rd, the 4th time slot respectively.
During packet Block transmission, transmitting terminal sends first time slot, second time slot, receiving terminal receives first time slot, second time slot and carries out combined decoding, when the contained useful information of packet Block more after a little while, it is correct then might to decode, and then receiving terminal is to transmitting terminal feeding back ACK information, DTD, then TTI is very less, is generally 10ms; Incorrect if decode, transmitting terminal continues to send the 3rd time slot.
Transmitting terminal continues to send the 3rd time slot, and receiving terminal receives the 3rd time slot and carries out the combined decoding of first, second, third time slot.Because the application data to Block adopts three kinds of hole knockouts, obtain data P1, P2, P3 respectively, during mapping, data P1 is mapped to first, second time slot, and data P2 is mapped to the 3rd time slot, then can carry out the combined decoding of first, second, third time slot, when if the data of useful information are not a lot, it is correct then might to decode, and for further improving the decoding accuracy, complete data head A can be mapped on the 3rd time slot.If decoding is correct, receiving terminal is to transmitting terminal feeding back ACK information, DTD, and then TTI is less, is generally 15ms; Incorrect if decode, transmitting terminal continues to send the 4th time slot.
Transmitting terminal continue to send the 4th time slot, and receiving terminal receives the 4th time slot and carries out the combined decoding of first, second, third, fourth time slot, if decoding is correct, receiving terminal is to transmitting terminal feeding back ACK information, DTD, and then TTI is generally 20ms; Incorrect if decode, receiving terminal feeds back nack message to transmitting terminal, and the request transmitting terminal carries out data re-transmission.
When the punching module is carried out four kinds of modes when punching to the application data of packet Block, obtain four segment data P1, P2, P3, P4 and pass to interleaving block, interleaving block carries out interleaving treatment and passes to mapping block this four segment data, mapping block is mapped to four time slots with packet Block, partial data head and the data P1 of packet Block are mapped to first time slot, data P2 is mapped to second time slot, data P3 is mapped to the 3rd time slot, data P4 is mapped to the 4th time slot.
Whether mapping block is mapped to second time slot, the 3rd time slot or the 4th time slot with the data head of described packet Block does not limit, if and shine upon then data head mapping what also do not limit, mapping block can be mapped to all or part of of data head respectively on second time slot, the 3rd time slot and the 4th time slot; Can be not yet with the data map of data head on second time slot, the 3rd time slot and the 4th time slot; Also can be only data head all or part of be mapped on second time slot or the like.But when mapping block is mapped to the 4th time slot with data head all or part of, must there be partial data at least to be mapped to second time slot and the 3rd time slot with data head; When mapping block is mapped to the 3rd time slot with data head all or part of, must there be partial data at least to be mapped to second time slot with data head.
Consider the accuracy of decoding, mapping block generally can be with all or part of data map of data head to second time slot, or all or part of data of data head are mapped to second, third time slot respectively, or with all or part of data of data head be mapped to respectively second, third, the 4th time slot.Preferable, in actual applications, mapping block is that complete data head is mapped to second time slot, or is mapped to second, third time slot respectively, or be mapped to respectively second, third, the 4th time slot.
So during packet Block transmission, transmitting terminal sends first time slot, receiving terminal receives first time slot and decoding, when the contained useful information of packet Block was few, it was correct then might to decode, and then receiving terminal is to transmitting terminal feeding back ACK information, DTD, then TTI is very little, is generally 5ms; Incorrect if decode, transmitting terminal continues to send second time slot.
Transmitting terminal continue to send second time slot, and receiving terminal receives second time slot and carries out the combined decoding of first, second time slot, if decoding is correct, receiving terminal is to transmitting terminal feeding back ACK information, DTD, and then TTI is less, is generally 10ms; Incorrect if decode, transmitting terminal continues to send the 3rd time slot.
Transmitting terminal continue to send the 3rd time slot, and receiving terminal receives the 3rd time slot and carries out the combined decoding of first, second, third time slot, if decoding is correct, receiving terminal is to transmitting terminal feeding back ACK information, DTD, and then TTI is less, is generally 15ms; Incorrect if decode, transmitting terminal continues to send the 4th time slot.
Transmitting terminal continue to send the 4th time slot, and receiving terminal receives the 4th time slot and carries out the combined decoding of first, second, third, fourth time slot, if decoding is correct, receiving terminal is to transmitting terminal feeding back ACK information, DTD, and then TTI is generally 20ms; Incorrect if decode, receiving terminal feeds back nack message to transmitting terminal, and the request transmitting terminal carries out data re-transmission.
The data mapping method of foregoing description and device punch for the application data of packet Block is carried out three kinds or four kinds of modes, corresponding data P1, P2, P3 or data P1, P2, P3, the P4 of obtaining, process to above-mentioned data map to four time slot has only been described, but the present invention originally is not limited to four time slots, Block can be mapped at least four time slots.Punch when carrying out three kinds of modes, partial data head and the data P1 of this Block is mapped to first, second time slot, data P2 is mapped to the 3rd time slot, data P3 is mapped to the 4th time slot at least.Punch when carrying out four kinds of modes, partial data head and the data P1 of this Block is mapped to first time slot, respectively data P2, P3 are mapped to second, third time slot, data P4 is mapped to the 4th time slot at least.
From the 3rd time slot, partial data head or the partial data head of Block can be mapped at least the three time slot, but work as certain time slot, when the data head of Block shone upon, all time slots of the front of this time slot must also will be mapped with the data head of Block.
Above-mentioned only is better embodiment of the present invention; be not to be used to limit protection scope of the present invention; any those skilled in the art of being familiar with will be appreciated that; all within the spirit and principles in the present invention scope; any modification of being done, equivalence replacement, improvement etc. all should be included within the scope of the present invention.
Claims (14)
1. a data mapping method is characterized in that, mainly comprises:
Steps A is carried out three kinds of modes to the application data of packet Block and is punched, and obtains three segment datas: data P1, P2, P3;
Step B is mapped at least four time slots with packet Block, wherein the partial data head of the above-mentioned Block of the common carrying of first, second time slot and the above-mentioned data P1 of carrying jointly, and data P2 is mapped to the 3rd time slot, and data P3 is mapped to the 4th time slot at least.
2. a kind of data mapping method as claimed in claim 1 is characterized in that: partial data head or the partial data of described Block also are mapped to the 3rd time slot.
3. a kind of data mapping method as claimed in claim 2 is characterized in that: partial data head or the partial data of described Block also are mapped to the 4th time slot.
4. a data mapping method is characterized in that, mainly comprises:
Steps A is carried out four kinds of modes to the application data of packet Block and is punched, and obtains four segment datas: data P1, P2, P3, P4;
Step B is mapped at least four time slots with packet Block, and wherein the partial data head of packet Block and data P1 are mapped to first time slot, and data P2 is mapped to second time slot, and data P3 is mapped to the 3rd time slot, and data P4 is mapped to the 4th time slot at least.
5. a kind of data mapping method as claimed in claim 4 is characterized in that: partial data head or the partial data of described Block also are mapped to second time slot.
6. a kind of data mapping method as claimed in claim 5 is characterized in that: partial data head or the partial data of described Block also are mapped to the 3rd time slot.
7. a kind of data mapping method as claimed in claim 6 is characterized in that: partial data head or the partial data of described Block also are mapped to the 4th time slot.
8. data mapping unit, mainly comprise the punching module, interleaving block and mapping block, it is characterized in that, the punching module is carried out three kinds of modes to the application data of packet Block and is punched, obtain three segment datas: data P1, P2, P3, and this three segment data passed to interleaving block, interleaving block interweaves to above-mentioned three segment datas and passes to mapping block, mapping block is with data head and the data P1 of packet Block, P2, P3 is mapped at least four time slots: partial data head and the data P1 of above-mentioned Block are mapped to first, second time slot, data P2 is mapped to the 3rd time slot, data P3 is mapped to the 4th time slot at least.
9. a kind of data mapping unit as claimed in claim 8 is characterized in that: mapping block also is mapped to the 3rd time slot with partial data head or the partial data of described Block.
10. a kind of data mapping unit as claimed in claim 9 is characterized in that: mapping block also is mapped to the 4th time slot with partial data head or the partial data of described Block.
11. data mapping unit, mainly comprise the punching module, interleaving block and mapping block, it is characterized in that, the punching module is carried out four kinds of modes to the application data of packet Block and is punched, obtain four segment datas: data P1, P2, P3, P4, and this four segment data passed to interleaving block, interleaving block interweaves to above-mentioned four segment datas and passes to mapping block, mapping block just packet Block is mapped at least four time slots: partial data head and the data P1 of packet Block are mapped to first time slot, data P2 is mapped to second time slot, data P3 is mapped to the 3rd time slot, data P4 is mapped to the 4th time slot at least.
12. a kind of data mapping unit as claimed in claim 11 is characterized in that: mapping block also is mapped to second time slot with partial data head or the partial data of described Block.
13. a kind of data mapping unit as claimed in claim 12 is characterized in that: mapping block also is mapped to the 3rd time slot with partial data head or the partial data of described Block.
14. a kind of data mapping unit as claimed in claim 13 is characterized in that: mapping block also is mapped to the 4th time slot with partial data head or the partial data of described Block.
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| CN200610034802XA CN101047480B (en) | 2006-03-29 | 2006-03-29 | Data mapping method and device |
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| CN200610034802XA CN101047480B (en) | 2006-03-29 | 2006-03-29 | Data mapping method and device |
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| CN101047480B CN101047480B (en) | 2010-08-04 |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105933100A (en) * | 2016-06-27 | 2016-09-07 | 珠海市魅族科技有限公司 | HARQ feedback method, HARQ feedback device, base station and terminal |
| CN107294674A (en) * | 2016-03-31 | 2017-10-24 | 电信科学技术研究院 | Transmission method, equipment and system |
| WO2020042034A1 (en) * | 2018-08-29 | 2020-03-05 | Nokia Shanghai Bell Co., Ltd. | Hybrid harq feedback scheme for self-contained burst on nr-u |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6259744B1 (en) * | 1999-06-01 | 2001-07-10 | Motorola, Inc. | Method and apparatus for mapping bits to an information burst |
| US6625165B1 (en) * | 1999-07-27 | 2003-09-23 | Lucent Technologies Inc. | Data link protocol for wireless systems |
| CN100336330C (en) * | 2003-01-27 | 2007-09-05 | 西南交通大学 | Uniform and ununiform modulated constellation mapping based nonisoprotective mixed automatic retransmission inquiry method |
| JP2006050519A (en) * | 2003-10-24 | 2006-02-16 | Sony Corp | Wireless communications system, wireless communications apparatus, wireless communication method, and computer program |
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107294674A (en) * | 2016-03-31 | 2017-10-24 | 电信科学技术研究院 | Transmission method, equipment and system |
| US10651999B2 (en) | 2016-03-31 | 2020-05-12 | China Academy Of Telecommunications Technology | Transmission method, device and system |
| CN107294674B (en) * | 2016-03-31 | 2020-11-06 | 电信科学技术研究院 | Transmission method, device and system |
| CN105933100A (en) * | 2016-06-27 | 2016-09-07 | 珠海市魅族科技有限公司 | HARQ feedback method, HARQ feedback device, base station and terminal |
| CN105933100B (en) * | 2016-06-27 | 2019-09-17 | 珠海市魅族科技有限公司 | HARQ feedback method and device, base station and terminal |
| WO2020042034A1 (en) * | 2018-08-29 | 2020-03-05 | Nokia Shanghai Bell Co., Ltd. | Hybrid harq feedback scheme for self-contained burst on nr-u |
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