CN101040450A - Systems and methods for providing nonvolatile memory management in wireless phones - Google Patents

Abstract

The present invention is related to memory management, and in particular, to methods and systems for accessing and managing nonvolatile, such as in a wireless phone. A wireless phone memory controller is disclosed that, comprises a first interface circuit configured to be coupled to wireless phone nonvolatile memory, a second interface circuit configured to be coupled to wireless phone volatile memory, a first processor interface configured to be coupled to a first wireless phone processor, wherein the first processor interface is configured to provide the first processor with access to the wireless phone volatile memory, a second processor interface configured to be coupled to a second wireless phone processor, and a controller circuit configured to copy at least a portion of wireless phone nonvolatile memory data to the wireless phone volatile memory.

Description

In radio telephone, carry out the system and method for non-volatile memories management

Copyright protection

The disclosed content of document of the present invention comprises content protected by copyright.The owner of copyright does not oppose to be imitated by patent file and patent disclosure arbitrarily and duplicates, in any case but all keep its copyright.

Priority application

The application requires the 60/605th, No. 265 U.S. Provisional Application (applying date is on August 30th, 2004) according to U.S.C 119 (e), and the priority of the 60/611st, No. 219 U.S. Provisional Application (applying date is on September 20th, 2004).The full content of these two applications is incorporated this paper by reference into.

Technical field

The present invention relates to storage management, relate in particular to the method and system of the nonvolatile memory in a kind of access and management (for example) radio telephone.

Background technology

The appearance of electronic component little along with volume, that speed is fast and power consumption is few such as processor, internal memory and application-specific integrated circuit (ASIC) (ASIC), a lot of mobile phones provide be commonly called " application program (application) ", the function of diversification, for example multimedia messages and amusement further.Mobile phone also comprises radio communication modulating/demodulating ability, is referred to as " modulator-demodulator " usually.In order to use the function of modulator-demodulator and application program, a lot of mobile phone designs comprise two processors, by " application processor " controlling application program function, and " modem processor " control communication function.Some mobile phones comprise that also specialized designs is used for other processor of combine digital signal analysis (DSP) algorithm.Though there is the mobile phone of uniprocessor, a lot of existing polynary mobile phones comprise a plurality of processors.In a lot of tradition were used, each processor used non-volatile and volatile memory to carry out the function of these application programs.

In addition, traditionally, the NOR flash memory generally has been used as the nonvolatile memory of mobile phone.In recent years, several new flash memory technologies had appearred on the market.The high density flash memory that these are new relatively, for example AND flash memory and nand flash memory, be designed to lower than NOR flash memory cost, size is little and have higher storage capacity.Like this, the high density flash memory technology is through being usually used in the optimization technique of non-volatile mass data storage in polynary mobile phone.But traditional mobile phone of a lot of current use NOR flash memories does not design and/or board revision is to use AND or nand flash memory as interim substitute.This is because these high density flash memory technology are compared with the NOR flash memory different characteristics is arranged, and therefore needs special treatment.

For example, high density flash memory needs a large amount of initial-access times usually with the page-pattern access, therefore is not suitable for processor executive program code, and this is because processor need carry out arbitrary access with the grade of byte or word.Therefore, the program code that is stored in the high density flash memory preferentially moves to random asccess memory (RAM) usually, and processor is from RAM executive program code then.In addition, compare with the NOR flash memory, high density flash memory more likely makes the data of wherein storage mistake occur usually, therefore when the access high density flash memory, often needs to use error correction coding (ECC).What further, high density flash memory can only bear limited number of time usually repeats to wipe rewriting.For example replace and power fail recovery often is used to strengthen the durability and the reliability of these flash memory devices by average read-write (wear-leveling), garbage reclamation, bad block for the flash memory medium management technology.

Because the advantage of high density flash memory technology, a lot of mobile telephone system designs have added very complicated flash memory medium management algorithm and program in systems soft ware, adapt to the above-mentioned special characteristics of high density flash memory.These complicated algorithms and program have almost exhausted a large amount of calculating/control ability of flash memory access processor, and have reduced the performance of system like this.Therefore, it is favourable having a kind of like this control circuit in mobile phone, and promptly this control circuit is carried out the algorithm and the program of flash memory medium management technology and error correction coding, and makes the flash memory access processor free from these tasks.

In the electronic system that comprises processor, nonvolatile memory and volatile memory, the task that processor is generally carried out is that data are moved to another memory from a memory.Data move operation example comprises program code is moved to the volatibility random access storage device from the storage device of non-volatile page-mode, to allow processor executive program code.Another one data move operation example comprises program code is moved to nonvolatile memory from volatile memory, comes permanent storage data thus.And, providing multimedia function for example in the mobile phone of image and video, processor often moves to mobile telephone display (as LCD display) with view data from memory, come display image thus.Mobile data turnover memory is a process that repeats very much, and this process has consumed a large amount of calculating/control ability of processor.

Summary of the invention

In view of above shortcomings in the prior art, in order to reduce cost and the size of the whole dimension of wireless phone design (as cellular phone design), it is favourable having such memory management circuitry, be its memory span that can hold a plurality of processors, and need each processor to have its oneself Stand Alone Memory management circuit invariably.By reducing the pocket memory system, not only reduced the quantity of storage arrangement, and made the data in the processor transmit more effective.

Further, in view of above shortcomings in the prior art, it will be favourable having so a kind of accumulator system for portable phone, promptly, this accumulator system comprises highly dense flash memories, RAM memory and control circuit, they provide DMA function under one or more processor controls, transmit to carry out data in the storage card of memory, display (as lcd screen) and/or extrapolation.

Portable phone has and can carry out the accumulator system of ECC and user-defined flash memory medium management autonomously and allow the memory in the processor access accumulator system will bring further advantage under the intervention of smallest processor.The sort memory system allow the storage demand with a plurality of processors to be merged into seldom or even single accumulator system in, thereby reduce the size of cost and portable phone.The use that is used for the high density flash memory memory of mass data storage has further reduced phone cost and size.In addition, with the inferior grade function of processor, and discharge in execution ECC and the flash memory medium management, thereby the systematic function that improves portable phone is favourable from the execution mobile data.

But, should be appreciated that the execution mode that the present invention provides does not need to obtain all related advantages herein.

An embodiment of the invention provide a kind of wireless telephone stores device controller, can comprise the nonvolatile memory controller circuitry, are configured to be coupled with nonvolatile memory; The volatile memory controller circuitry is configured to be coupled with volatile memory; The guide controller circuit is configured to and described nonvolatile memory controller circuitry coupling, and is used for user-defined boot code is read the into memory of Memory Controller from nonvolatile memory; The first processor interface that comprises first reset signal, be configured to be coupled with the first radio telephone processor, wherein after described user-defined guidance code was read in the memory of described Memory Controller into, described Memory Controller discharged the described first radio telephone processor down from reset mode; And second processor interface that comprises second reset signal, being configured to and the coupling of the second radio telephone processor, wherein said second reset signal is configured at least in part by described first processor control.

Another one execution mode of the present invention provides the method that is used to transmit the radio telephone data of nonvolatile storage, comprising: behind electrification reset, use steering circuit to generate first address; In the described wireless telephonic non-volatile flash memory memory of access, comprise the data of the data that are stored in described first address at least; With access to storage in page-buffer; Determine access to data be guidance code or flash memories management code; If access to data are guidance codes, then these data are copied to the guiding random access memory from page-buffer; And if access to data are flash memories management code, then these data are copied to flash memory storage management random access memory from page-buffer.

Another one execution mode of the present invention also provides wireless telephone stores device controller, can comprise: first interface circuit is configured to be coupled with the radio telephone nonvolatile memory; Second interface circuit is configured to be coupled with the radio telephone volatile memory; The first processor interface is configured to and first radio telephone processor coupling, and makes the described first processor can the described radio telephone volatile memory of access; Second processor interface is configured to be coupled with the second radio telephone processor; And controller circuitry, be configured under the situation of the intervention that does not have the described first processor or second processor, at least a portion data in the described radio telephone nonvolatile memory are copied to described radio telephone volatile memory.

Another embodiment of the invention also provides the method that is used for operate wireless phone memory circuit, can comprise: reset signal is stopped to assert; Generate be stored in the radio telephone nonvolatile memory in the first corresponding address of vectoring information; In described radio telephone nonvolatile memory, begin to read boot code from described first address; The error-detecting of described boot code is provided; If detect first error, then proofread and correct first error at least; Described guidance code is loaded into volatile random access memory, if there is the guidance code of proofreading and correct, then described guidance code also comprises the guidance code of described correction; Flash memories hypervisor code is loaded into flash memory storage management volatile memory from described radio telephone nonvolatile memory; Make described flash memories hypervisor code carry out by the flash memories management circuit; From the first radio telephone processor of reset mode release with described wireless telephone stores device which couple; Make the described boot code of the described first radio telephone processor access; And make the second radio telephone processor access be stored in the code of described volatile memory.

Embodiments of the present invention also provide and have been used for that the data that are stored in or storing wireless telephonic nonvolatile memory are into carried out method of its error calibration and comprise: receive and be configured to first page data that is stored in the radio telephone nonvolatile memory, described first page comprises user data that is stored in User Part and the idle data that is stored in idle component; Generation is used for the page parity data of described first page data; Described page parity data is stored in the described radio telephone nonvolatile memory, and wherein said idle data comprises thin numeration certificate and/or the system marks that is used for the nonvolatile memory management; Generation is used for the parity data of described idle data, and it is stored in the described radio telephone nonvolatile memory; From described radio telephone nonvolatile memory, read the parity data of described idle data; And if necessary, use the parity information of described idle data, the idle data in the described radio telephone nonvolatile memory is carried out error-detecting and error correction.

Embodiments of the present invention also provide wireless telephone stores device system, comprise first port, are coupled with the radio telephone nonvolatile memory; Second port circuit is coupled with the radio telephone volatile memory; The first processor interface with the coupling of the first radio telephone processor, and is configured so that the described radio telephone volatile memory of described first processor access; And second processor interface, be coupled with the second radio telephone processor; One in the wherein said first processor and second processor is arranged to the control modulator-demodulator.

Another embodiment of the invention also provides wireless telephone stores device control device, comprising: first port is coupled with the radio telephone nonvolatile memory; Second port circuit is coupled with the radio telephone volatile memory; First device interface with the coupling of the first radio telephone processor, and is configured so that the described radio telephone volatile memory of described first processor access; And second device interface, optionally can be configured to be connected with the second radio telephone processor or radio telephone display.

Description of drawings

Will describe exemplary execution mode in conjunction with the accompanying drawings, accompanying drawing is only as illustration.

Fig. 1 is the block diagram that exemplary radio telephone electronic system is shown;

Fig. 2 is the exemplary wireless telephonic more detailed block diagram that illustrates as shown in Figure 1;

Fig. 3 is the block diagram that the storage system control circuit of first execution mode is shown;

Fig. 4 is the block diagram that exemplary control circuit resets and controls;

Fig. 5 is the block diagram that the control circuit interruption controls in the exemplary control circuit is shown;

Fig. 6 is the block diagram that example illustrates the nand flash memory page setup that is used for one-level ECC;

Fig. 7 is the block diagram that example illustrates the nand flash memory page setup that is used for secondary ECC;

Fig. 8 illustration the block diagram of flash memory medium management circuit;

Fig. 9 illustration the block diagram of nand flash memory memory space;

Figure 10 shows that the memory system flow chart of first execution mode of the boot carried out to normal mode of operation of state from power on;

Figure 11 shows that the flow chart that data is sent to the exemplary DMA transport process of volatibility SDRAM memory from non-volatile fast storage;

Figure 12 shows that the flow chart that data is sent to the exemplary DMA transport process of NAND fast storage from the SDRAM memory;

Figure 13 shows that memory system enters the flow chart of the example process of user model from normal mode of operation;

Figure 14 shows that the flow chart of the example process of primary processor run user loading application program;

Figure 15 shows that primary processor activates auxiliary processor and to the flow chart of the example process of interrupting reacting;

Figure 16 shows that the storage system second embodiment schematic diagram;

Figure 17 shows that the flow chart that example guidance that the storage system of second execution mode is carried out, that carry out from power supply opening state to a normal mode of operation is handled;

Figure 18 shows that the block diagram of the storage system of the 3rd execution mode;

Figure 19 shows that the flow chart of the storage system of the 3rd execution mode from the example guidance processing of power supply opening state to a normal mode of operation execution;

Figure 20 shows that the block diagram of the storage system of the 4th execution mode;

Shown in Figure 21 is the schematic block diagram of exemplary mobile phone electronic system;

Shown in Figure 22 is the block diagram of the storage system of the 5th execution mode;

Show to flowchart illustration among Figure 23 the data transfer procedure that data is sent to mobile telephone display as shown in figure 22 from volatile memory;

Figure 24 is the block diagram of another exemplary mobile phone electric system;

Shown in Figure 25 is the block diagram of the storage system of the 6th execution mode;

Shown in Figure 26 for data are sent to the flow chart of the transport process of extraction-type storage card as shown in figure 25 from volatile memory;

Shown in Figure 27 is the mobile phone schematic diagram of having described the storage system of the 7th execution mode;

Shown in Figure 28 is the more detailed block diagram of control circuit functional block shown in Figure 27;

Block diagram for the control that resets in the 7th execution mode of control circuit shown in Figure 29;

Shown in Figure 30 is the block diagram of the interrupt control circuit in the 7th execution mode of control circuit;

Shown in Figure 31 for uniting the flow chart of exemplary process of " flash memory reads (Flash read) " order of use with the 7th execution mode of control circuit; And

Shown in Figure 32 for uniting the flow chart of exemplary process of " flash memory write (Flash Write) " order of use with the 7th execution mode of control circuit.

Embodiment

The present invention relates to storage management, relate in particular to the method and system of the non-volatile and volatile memory in a kind of access and managing electronic equipment such as the radio telephone.

As described herein, some optional execution mode can reduce target device such as wireless telephonic cost and size.Further, with respect to storage management and the thin note of flash memory (Flashmemory bookkeeping), the storage management system of some execution mode of Miao Shuing by reducing the processing of processor for above-mentioned scrappy thing (chore), can alleviate processor load in this article.

Further, some optional execution mode allows user (for example mobile phone manufacturer) to write, provide and store themselves guidance code and themselves flash memory management (FMM) code (one or more average read-writes, garbage reclamation, bad block reparation and power fail recovery or the like), needn't rely on the code of storage management chip manufacturer.The FMM code can be write by storage management chip manufacturer rather than phone manufacturer alternatively.In some embodiments, these FMM codes can not know in advance which processor will be used for holder management system and/or storage management system and will use under which wireless telephonic situation and write.

Further; the storage management system that some execution modes comprise can be " shielded " with some address spaces or the zone definitions of flash memory; some of them processor such as modem processor or application processor are stopped in the protected field and rewrite, and therefore stop software to destroy (incorrect software modification).In order further to stop access memory without approval, and prevention software hacker, some execution modes comprise volatibility SDRAM memory, non-volatile flash memory and the memory manager that is arranged in single packaged chip, wherein, do not provide chip pin or bus (unless alternatively, by detecting pin) to allow direct access SDRAM memory and flash memory.Therefore, in this embodiment, the user can only pass through memory manager access SDRAM and flash memory, unless the user adopts extreme or expensive measure, for example opens packing chip and surveys the inside chip circuit, and these measures will cause the chip permanent damages.

Some execution modes provide the safe guidance function, and wherein before guide controller wake up process device, the code of preset sequence can copy the SDRAM memory to from flash memory, and/or the executive software safety detection.

In addition, some execution modes provide 2 grades of error correction codings (ECC) data protection, and the ECC of page-level wherein is provided, and the ECC of the idle component that is exclusively used in flash memory pages is provided.

Following description is with reference to radio telephone, mobile phone for example, and as exemplary execution mode, but the present invention is not limited to this.Other execution modes are used and are comprised portable, non-portable electronic equipment, for example personal digital assistant, portable electronic game machine, digital entertainment system and portable video device or the like.Radio telephone described here can comprise loud speaker, keyboard, microphone, volatibility and volatile memory and memory control system, but does not need all said elements (for example keyboard is inessential).Further, although quoted some concrete exemplary memory technologies presented for purpose of illustration, the present invention is not limited to these exemplary memory technologies.For example, the present invention is not limited to use flash memory or SDRAM memory.Non-volatile and the volatile memory of other types also can be used.In addition, unless clearly make opposite explanation, the phrase " transmission " in the context that transmits data is meant from a position and copies data to another position.

Further, with regard to execution mode step described here, not every treatment state all needs to obtain, and these states neither be carried out with illustrative order.Further, being described to some treatment states that serial carries out can executed in parallel.In addition, not all function described here or advantage are essential, can use different circuit or structure to carry out these functions.Although, some functions be described to by hardware for example the program code carried out of processor carry out, yet in other embodiments, can also use hard-wired circuit or state machine to carry out identical or similar function.Similarly, although some functions are described to be carried out by hard-wired circuit, in other embodiments, can also use the processor of run time version to finish identical or identity function.

As shown in Figure 1, in first execution mode, exemplary accumulator system (102) is provided as the part of mobile phone electronic system (101).Accumulator system (102) comprises high-density nonvolatile flash memory (104), volatile random access memory (105) and control circuit (103).Hereinafter, the unrestricted purpose for removing is positioned at accumulator system (102) but is not that the volatile random access memory of control circuit (a 103) part is called as " main RAM " (105).In exemplary accumulator system (102), flash memory (104) is connected with control circuit (103) with main RAM (105).The flash controller (will go through below) that provides control signal to operate flash memory (104) is provided control circuit (102), and provides control signal to operate main RAM (105) and the main RAM controller (equally will below go through) mutual with it.Following will go through like that, flash controller further provides ECC (error correction coding) circuit, this circuit is carried out the ECC Code And Decode, is stored in data integrity in the flash memory (104) in order to protection.

Control circuit (103) further provides processor interface, outside in the electronic equipment (106) of accumulator system (102) on physics and/or function, for example one or more processors can dispose and activation control circuit (103) comes task in the execute store system (102) by this interface.For example, this task can comprise permission electronic equipment (106) access master RAM (105), and the two-way DMA (direct access storage) that carries out between flash memory (104) and the main RAM (105) transmits.

In exemplary execution mode, control circuit (103) further provides the ability of carrying out user-defined flash memory medium management (FMM) algorithm and program alternatively, is called as " FMM program " in this article sometimes.For example, the FMM program includes but not limited to one or more average read-write (wear-leveling), garbage reclamation, bad block replacement and power fail recovery or the like.In exemplary execution mode, this FMM program can be externally under or the situation about not having minimum in the intervention of the processor of accumulator system (102), gets involved by the spontaneous execution of accumulator system (102).When access memory system (104), the FMM program is mapped as physical address space with logical address space, and converts logical page address (LPA) to physical page address (PPA).

As reference Fig. 3 went through below, in an exemplary execution mode, built-in control circuit processor (FMM_P in the FMM circuit 311) was carried out the FMM program.Volatile memory in the control circuit (FMM_RAM in the FMM circuit 311) is used for storing the FMM program code that is used for built-in control circuit processor (FMM_P of FMM circuit 311) execution.In exemplary execution mode, the FMM program code is based on a series of instructions of the instruction set of built-in control circuit processor (FMM_P).The FMM program is carried out with form of program code, and this program code is stored in non-volatile flash memory alternatively, and in one embodiment, is loaded into FMM_RAM by control circuit in the process of boot process that powers on.

Refer again to Fig. 1, exemplary control circuit (103) further provides the DMA function that actual figure reportedly send between flash memory (104) and main RAM (105).

Alternatively, exemplary control circuit (103) further comprises the Boot control procedures that powers on, its almost power on reset be stopped assert (deassert) or discharge after, activation control circuit (103) or make control circuit (103) that FMM program code and system initialization routine (SIP) (also being referred to as guidance code) are loaded into the main control circuit local storage from flash memory (104) automatically immediately.For example, the SIP code is loaded into branch and is used in the control circuit volatibility RAM (BOOT_RAM) that receives the SIP code, and the FMM code is loaded into the control circuit volatibility RAM (FMM_RAM) that branch is used in reception FMM code.Power on Boot control procedures then with built-in control circuit processor (FMM_P), with a part of peripheral electronic device (for example, selected processor) discharges down from reset mode, so that they can carry out corresponding separately program code from control circuit memory (for example, each is since FMM_RAM and BOOT_RAM).

The system initialization routine code powers on, be referred to as " system boot code " hereinafter, be the software that resets from power on and carry out when discharging at primary processor by first processor (be referred to as primary processor sometimes, but be not limited thereto), in order to some other part of initialization mobile phone electronic system.By the mode of example, first processor can serve as modem processor, perhaps serves as application processor.Similarly, second processor (being referred to as auxiliary processor sometimes in this article) can serve as modem processor or application processor.

In second execution mode of control circuit (103), control circuit (103) does not comprise BOOT_RAM.Almost be after last electrification reset, on the Boot control procedures that powers on load the SIP code immediately to main RAM (105), rather than load the SIP code to control circuit memory (BOOT_RAM), discharge primary processor then, with from main RAM (105) executive program code.Present embodiment will be carried out more detailed illustrating in this article.

In the 3rd execution mode, control circuit does not comprise the control circuit memory of distributing to the SIP code, and the control circuit memory of perhaps distributing to the SIP code is not reallocated and is used to store the SIP code.But, FMM circuit 311 rather than guide controller circuit (BOOT_CTLR3133) is obligated that system boot code is loaded into main RAM from flash memory.

In accumulator system the 4th execution mode, the accumulator system control circuit comprises a plurality of flash controllers and a plurality of main RAM controller, more multiple memory space so just not only is provided in accumulator system, and higher rate of data signalling is provided.

In the 5th execution mode, the accumulator system control circuit further provides control signal to come one or more display (as radio telephone LCD or OLED screen) is operated, and therefore makes display be connected by the control signal that the accumulator system control circuit provides with accumulator system.In the present embodiment, seldom or need not that ppu get involved to get involved, the primary processor activation control circuit is sent to display with view data from main RAM.

In the 6th execution mode, the accumulator system control circuit further provides control signal to the Stand Alone Memory module that moves or card (for example to come, SD, compact flash, memory stick, perhaps other removable memory devices) operate, wherein storage card is connected with accumulator system by the control signal that the accumulator system control circuit provides.When in radio telephone, using, the data space that radio telephone can accessing memory card provides.In this embodiment, primary processor can activate the accumulator system control circuit, with seldom or do not have to carry out data and transmit between main RAM and storage card under processor gets involved.

In the 7th execution mode, the accumulator system control circuit does not need main RAM just can operate.

With reference to the accompanying drawings, various execution mode will carry out more detailed discussion.The various execution modes of memory system architecture will be described, as the design and the operation of accumulator system control circuit.In addition, in order to further specify exemplary application, will the use of various execution modes in mobile phone of accumulator system be described.

For example, referring to Fig. 2, in the first embodiment, accumulator system (hereinafter for convenience but be not used in restriction, being referred to as " accumulator system " (202)) is provided as the part of mobile phone electronic system (201).Other parts of mobile phone electronic system are referred to as external electronic device (206) hereinafter.External electronic device can also comprise one or more processors except other elements, is referred to as ppu (for example processor 207 and 208) hereinafter.Accumulator system (202) is included in the high-density nonvolatile flash memory that is hereinafter referred to as flash memory (204), is called as the volatile random access memory of main RAM (205) and the control circuit that is called as " control circuit " (203) hereinafter hereinafter.

Flash memory (204) is connected with control circuit (203) with main RAM (205), and control circuit (203) provides and make flash memory (204) operation and the control signal mutual with it, and provides and make main RAM (205) operation and the control signal mutual with it.Control circuit (203) further provides processor interface, and by this interface, one or more ppus can dispose and activation control circuit (203) comes executable operations in accumulator system (202).Exemplary operation comprises permission ppu access master RAM (205), and carries out two-way DMA and transmit between flash memory (204) and main RAM (205).Seldom or do not have under the intervention of external electronic device, control circuit (203) is also carried out by its self-configuring and self-activating operation.

Should be understood that the element of accumulator system (202) (for example flash memory (204), main RAM (205) and/or control circuit (202)) needn't be implemented as the device that three individual packages are separated.Alternatively, the subclass of these elements can be embodied as single integrated circuit (IC) or a plurality of integrated circuit (IC).The present invention is the integration class of limits storage system (202) in physics realization not.

Should be understood that further in this specification, to be applicable to the mode of the repertoire of illustrating control circuit (203), control circuit (203) is divided into a plurality of functional blocks.The technical staff should be realized that under the present technique field, can use many different modes, control circuit (203) is divided into a plurality of functional blocks (different signals of communication connects these functional blocks), but still makes it be included in the identical repertoire of describing herein.How the execution mode of Miao Shuing to being divided into a plurality of functional blocks with control circuit (203) in this article, perhaps how functional block connected each other not limit.

In the present embodiment, control circuit (203) comprises controllability and the visuality that the configuration/control register that can write and readable result/status register provide the various functions of control circuit (203).Should be appreciated that these registers are to provide as example, how to dispose the various functions of control circuit under various patterns, to operate with explanation.Those skilled in the art are to be understood that, might make control circuit (203) more function configurable (or opposite) by increasing more register, maybe might be by reduce the register number and some functions of execution in fixing hard-wired circuit (can not be configured to carry out different operating) able to programmely.Further, configurable function needn't be returned in the identical mode of describing in this article of exemplary execution mode and is incorporated in the register.And, can increase more readable register alternatively, comprising the more multioperation result and the state of control circuit (203), thereby improve the visuality of the various functions of control circuit (203).

Comprise one or more nand flash memory (210) although exemplary flash memory (204) is shown as, also can use the flash memory of other types, for example the AND flash memory device.Similarly, main RAM (205) is described to comprise one or more SDRAM devices (211), still, also can use the volatile random access memory of other types, and for example, pseudo-static random is counted memory (PSRAM) device.PSRAM comprises dynamic ram (DRAM) unit of high density low level consumption, and the SRAM external interface.

Fig. 3 is the block diagram that exemplary control circuit is shown, and alternatively, this exemplary control circuit is corresponding to control circuit shown in Figure 2 (203).Various exemplary control circuit functional blocks will be described below, and the operation of exemplary accumulator system (301) also will be described thereafter.

Processor interface circuit (PI):

Exemplary PI circuit (302) provides interface to one or more ppu, so that the task that ppu configuration, control and/or supervision are carried out by control circuit, and access is stored in the data of accumulator system (301).This exemplary PI circuit (302) comprises processor bus controlled circuit (PBSc) (303,304).PSB to corresponding ppu separately for example processor (314,315) interface is provided.PBS is attached to the memory bus of its corresponding ppu, and according to access of memory bus data transfer protocol and control storage bus.Therefore, PBS is the storage arrangement (being known as " bus slave ") that is attached to the ppu memory bus for corresponding ppu just as PBS.

In optional execution mode, the interface protocol of the memory bus of ppu is " pulse mode SRAM (Burst Mode SRAM) " interface, and this interface is the memory bus protocol of well-known frequent use in modern portable phone.Two examples of storage arrangement of observing the current commercial of this agreement are pseudo SRAM (PSRAM) and pulse mode NOR flash memory.In other words, in optional execution mode, each PBS is for corresponding ppu, seems that the PSRAM device or the pulse train NOR flash memory that are connected on the processor memory bus are the same.Term " pulse mode " is meant that this agreement transmits after order and an address initiate transmission at one, supports the transmission of a plurality of consecutive words.The conventional lengths that pulse transmits is 1,4,8 or 16 word, and wherein " word " refers to the data-signal width (for example, word is 16 bit data that are used for the memory bus of 16 bit data signals) of memory bus.Also be not ready to serve at storage arrangement under the situation of order of from processor, this interface protocol further allows the storage arrangement on the memory bus to assert that (assert) " wait " signal temporarily interrupts transmitting in the data of bus.

Although should be noted that in the present embodiment pulse mode SRAM interface protocol being assumed to each ppu carries out mutual bus interface by itself and corresponding PBS, also can use other bus inferface protocols.For example, can also use at control circuit to be not ready for serving under the situation of ppu, allow PBS to send other bus inferface protocols that " wait " signal temporarily stops the data transmission of ppu initiation.

In exemplary execution mode shown in Figure 3, the outside reason device of first in the cellular phone (314) is appointed as " primary processor ", and other ppus (315) are appointed as " additional storage ".Similarly, a PBS (303) in the PI circuit (302) specifies with thinking that primary processor provides interface, and is called as " main PBS " (or PPBS).In the present embodiment, other PBS specify to use and think that they provide interface by the auxiliary processor of correspondence, and are called as " auxiliary PBS " (or SPBS) (304).By PI (302), ppu can access be stored in the data of SDRAM (318), yet the multiple function that primary processor (314) also is responsible for configuration extraly, is activated and monitor control circuit, for example, the DMA data between nand flash memory and the SDRAM transmit.

PPBS (303) will be order, data and address information from the conversion of signals of the memory bus of primary processor (314), then these information are passed to instruction control unit (CMD_CTLR 305), this instruction control unit is then followed the suitable part of activation control circuit, comes the operations associated in the execute store system (301).PPBS (303) further reads instruction control unit (305) from the control circuit each several part data, and waiting signal sends it back primary processor (314) by memory bus.In other words, PPBS (303) is primary processor (314) configuration, activates and the supervision control circuit, and access is stored in the interface of the data in the accumulator system (301).

When primary processor (314) access PPBS (303), PPBS (303) converts the memory bus control signal in the order shown in the following example one: " reading RAM ", " writing RAM ", " read register ", " writing register ", " downloading the DMA transmission " or " uploading the DMA transmission ", and order is sent to instruction control unit (305).Memory bus data and address signal provide data and the address information that is associated with order to instruction control unit (305).The memory bus of data-signal is two-way, transmits write data and read data information with this.Can not immediate execution command if control circuit is busy with other tasks, then instruction control unit (305) sends waiting signal by PPBS (303), and the data that temporarily stop on the memory bus transmit, and are performed up to described order.To describe instruction control unit (305) in this article and how carry out the details of primary processor order.

It is the SDRAM access request that SPBS is responsible for being used for the memory bus conversion of signals from its corresponding auxiliary processor, and send it to storage access distributor (MAD) circuit (308) with request access SDRAM (318), SPBS also is responsible for providing data and the waiting signal of reading from SDRAM (318) to processor by memory bus.MAD circuit (308) is responsible for being used to receiving the request from a plurality of access SDRAM (318) of the various parts of control circuit, and agrees that based on priority mechanism one of them initiates the request of requesting host.By SPBS, corresponding auxiliary processor can read and write data from SDRAM (318).

If MAD circuit (308) does not agree to initiate the SPBS access SDRAM (318) of request immediately, then SPBS sends waiting signal to stop at the data transmission on the memory bus, agrees SPBS access SDRAM (318) up to MAD circuit (308).Alternatively, SPBS is included as the data buffer (advance head as head and go out buffer, be known as FIFO) that the data that transmitting provide temporary transient storage between its corresponding auxiliary processor and SDRAM (318).The data buffer (not shown) allows the rate of data signalling of SPBS interface and the rate of data signalling of SDRAM (318) not to match.Two registers in the REGS circuit (306), promptly be respectively PI burst length (PI_BURST-LENGTH) register and SDRAM burst length (SDRAM_BURST-LENGTH) register, be used for defining the length that the pulse of length that the pulse of SPBS interface transmits and SDRAM (318) interface transmits.Alternatively, the size of the data word of each interface is determined by the width of interface data signal, but is not limited to specific size.

Now referring to Fig. 4, exemplary PI circuit (406) comprises reset signal, wherein alternatively, each ppu (412,413) has independently reset signal (410,411), and the PBS (407,408) that passes through their correspondence provides reset signal (410,411) to give ppu (412,413).Alternatively, reset signal (410,411) controlled at least in part circuit (401) control is as described in following.

Generate by BOOT_CTLR circuit (402) with the reset signal (401) of primary processor (412) coupling by PPBS (407).The reset signal of SPBS (408) the whereabouts auxiliary processor by their correspondence is the output signal of the RESET register (405) in the REGS circuit (404).The default value that powers on of RESET register makes auxiliary processor be in reset mode.When primary processor (412) activated, primary processor (412) can be write into suitable value RESET register (405) when needed.In other words, resetting of each auxiliary processor controlled by RESET register (405) by primary processor (412) alternatively, and resetting of primary processor (412) is that guiding control circuit (BOOT_CTLR 402) by control circuit is controlled.

Host apparatus (as portable phone) makes control circuit 401 and ppu (412,413) be in their reset mode to assert (assertion) of electrification reset (414).Electrification reset is being stopped to assert after (deassertion), BOOT_CTLR circuit (402) begins to execute the task the various functions of initialization control circuit (401), but at the same time, for keeping primary processor (412), the state of asserting is in reset mode by keeping its reset signal (410).After finishing initialization task, BOOT_CTLR circuit (402) is ended asserting of reset signal (410), with the reset mode of cancellation primary processor (412).After in case primary processor (412) activates, it can cancel asserting of one or more auxiliary processors then, and, when special applications needs, can make one or more auxiliary processors recover reset mode by writing into suitable value to RESET register (405).

Referring to Fig. 5, in exemplary execution mode, PI 507 comprises interrupt signal, wherein alternatively, has independently interrupt signal (515,516) for each ppu (512,513).Interrupt signal (515,516) is by corresponding PBS (508,509) and ppu (512,513) coupling.Alternatively, interrupt signal (515) to small part is controlled by instruction control unit (CMD_CTLR 502) by control circuit (501), as described in following.

When CMD_CTLR (502) finishes from order that primary processor (512) receives, generation is coupled to the interrupt signal (503) of REGS piece (504), be preferably short pulse signal, wherein REGS piece (504) comprises the multidigit register INT_RECORD (505) by register-bit record interruption pulse.Register INT_RECORD (505) can read and wipe by primary processor (512).

Exemplary SPBS (509) provides input port, by this input port, the corresponding auxiliary processor (513) of SPBS (509) sends to control circuit (501) with the interrupt signal (516) of whereabouts REGS piece (504), and this control signal is recorded in the INT_RECORD register (505) by the corresponding bits of distributing at control circuit (501).Therefore, the interrupt signal (503,516) of CMD_CTLR circuit (502) and auxiliary processor (513) generation is with the different corresponding bits records of INT_RECORD register (505).These interrupt signals (503,516) further be sent to or (OR) door (506), by the output port of PPBS interface (508), or the door (506) output signal enter primary processor (512).Therefore, the interrupt signal that auxiliary processor or CMD_CTLR circuit (502) produce is recorded in the INT_RECORD register (505), and be sent to primary processor (512), this primary processor then read register (505) should produce any interruption to find out, and interrupts carrying out correct program in response to this.The part that primary processor (512) is removed register (505) then or wherein chosen makes register (505) can write down more multiple interrupt.

As mentioned above, this exemplary execution mode preferably provides other mechanism of reset stage of primary processor (512) control auxiliary processor (513).This exemplary execution mode also preferably provides each auxiliary processor (513) can interrupt the mechanism of primary processor (512).But, in some portable phones, had the communication mechanism of inner treater, and do not needed the portable phone accumulator system.For example, in some cellular phone design, on one chip, can implement a plurality of processors, sufficient inner treater communication wherein can be provided in one chip.In this enforcement, for reaching this purpose, if resetting and interrupt mechanism of providing in the present embodiment can not used or be eliminated alternatively in existing other controls and monitor the mechanism of other ppus in the ppu in the portable phone.

In this exemplary execution mode, PI circuit (507) comprises PPBS (508) and two SPBS (509).If portable phone only has a processor, then this processor will be identified as primary processor (512), and be connected with PPBS (508).In this case, will not use or not implement SPBS (513).

Below with the instruction control unit (CMD_CTLR 305 among Fig. 3, the CMD_CTLR 502 among Fig. 5) of detailed description exemplary.But following description will be referring to the CMD_CTLR among Fig. 3, and the CMD_CTLR among Fig. 5 carries out identical or identity function alternatively, and comprises identical or similar circuit alternatively.

CMD_CTLR305 is responsible for being used for by order, data and the address information of PPBS (303) reception from primary processor (314) among Fig. 3, adjust functional block suitable in the control circuit or circuit then, so that the information and executing inter-related task that small part receives based on PPBS (303).When finishing order, CMD_CTLR 305 sends interrupt signal to primary processor (314) by PPBS (303).Transmit length and transmit length and can for example define by PI pulse length register (PI_BURST_LENGTH) and SDRAM pulse length register (SDRAM_BURST_LENGTH) respectively in the pulse of PPBS interface by one or more register definitions in the pulse of sdram interface.The size of the data word of each interface is determined by the data-signal width of above-mentioned interface, but is not limited to a length-specific.

The exemplary order that is sent to CMD_CTLR (305) by PPBS (303) configuration is " RAM reads ", " RAM writes ", " register read ", " register is write " and " downloading the DMA transmission " and " uploading the DMA transmission ", and is as described below:

" RAM reads " and " RAM writes ": although other exemplary execution modes are can direct accesses less or than multi-memory, but in this exemplary execution mode, two volatibility RAM with primary processor (314) energy direct access in accumulator system, that is, guiding RAM (BOOT_RAM 307) and SDRAM (318).With respect to primary processor (314), the RAM storage space in the accumulator system (301) is divided into two address realms: be used for access BOOT_RAM (307) address realm and be used for another address realm of access SDRAM (318).When primary processor (314) sent " RAM reads " or " RAM writes " order, CMD_CTLR (305) determined access BOOT_RAM (307) or access SDRAM (318) according to the address information that receives by PPBS (303).

If the address is in the BOOT_RAM address realm, CMD_CTLR (305) allows primary processor (314) to carry out pulse to send BOOT_RAM (307) to or transmit from the pulse of BOOT_RAM (307).Stipulated that from the address information that PPBS (303) receives first treats the position of the BOOT_RAM (307) of access pulse transmits.This is the mechanism that is used for primary processor (314), after discharging from reset mode at primary processor (314), carries out the system boot code that is stored in BOOT_RAM (307) immediately.

If the address is in the SDRAM scope, then CMD_CTLR (305) allows primary processor (314) to carry out pulse to send SDRAM (318) to or transmit from the pulse of SDRAM (318).Preferably, CMD_CTLR (305) further comprises the temporary storage that data buffer (being commonly referred to FIFO) transmits as data between primary processor (314) and the SDRAM (318).Data buffer allows the rate of data signalling of PPBS (303) interface and the rate of data signalling of SDRAM (318) interface not to match.

For the RAM that carries out primary processor (314) reads the write order with RAM, CMD_CTLR (305) at first sends access request to MAD circuit (308), with access SDRAM (318).Because the check (arbitration) in the MAD circuit (308), after access request sent to MAD circuit (308), CMD_CTLR (305) can allow or not allow immediate access SDRAM (318).Agreeing immediately not under the situation of access that CMD_CTLR (305) asserts for PPBS (303) piece and to suspend the memory bus of primary processor (314), obtains access permission up to CMD_CTLR (305) by " wait " signal.Order for " RAM writes ", after SDRAM (318) access allows, asserting of CMD_CTLR (305) cancellation waiting signal, and primary processor (314) sends pulse series data to data buffer by PPBS (303), by SDRAM_CTLR, CMD_CTLR (305) sends this pulse series data to SDRAM (318).

For " RAM reads " order, after SDRAM (318) access allowed, when copying the pulse series data among the SDRAM (318) to data buffer by SDRAM_CTLR, CMD_CTLR (305) continued to assert waiting signal.Along with SDRAM (318) data enter data buffer, CMD_CTLR (305) cancellation is asserted to waiting signal, and is allowed primary processor (314) to read pulse series data from data buffer.This is to be used for primary processor to carry out the program code that is stored in SDRAM (318), and access is stored in the user data of SDRAM (318).

Alternatively, the address realm that is used for BOOT_RAM (307) be the memory mapped that begins from address zero than lower part, this is because BOOT_RAM (307) is the part of ram space, after powering on, a lot of processors, move the program code of this ram space as example processor (314), and a lot of processor be designed to reset discharge after, extract first instruction from address zero.Should be appreciated that address realm is not in order to determine unique method of primary processor (314) access BOOT_RAM (307) or SDRAM (318).Other illustrative methods also include but not limited to, realization can by primary processor (314) carry out write operation, with and value can determine the configuration register of the data access destination of primary processor (314).

" register read " and " register is write ": for these two orders, CMD_CTLR (305) is to by carrying out the reading and writing operation from the register address information addressing of PPBS (303), in the REGS piece (305).By PPBS (303), the memory bus data-signal provides write data, and sends it back by the PPBS (303) that is read by primary processor (314) data-signal from the data that REGS reads.This is in order to control and monitor the operation of control circuit (301), the mechanism that primary processor (314) carries out reading and writing to the register in the REGS piece (306).

" download the DMA transmission " and " uploading the DMA transmission ": these two kinds of orders cause CMD_CTLR (305) to activate dma controller (DMA_CTLR312), carry out respectively from nand flash memory (317) to SDRAM (318), perhaps transmit from SDRAM (318) to the DMA between the nand flash memory (317).After DMA_CTLR (312) is activated by CMD_CTLR (305), obtain with REG piece (306) in DMA_CONFIG register DMA transmit relevant information, such as preferably with data volume to be moved, initial nand flash memory logical page address (LSP) and the initial SDRAM address of nand flash memory page-describing.

Therefore, for example, sending command dma to CMD_CTLR (305) before, primary processor (314) is loaded into the DMA_CONFIG register with suitable value.When DMA_CTLR (312) finished the DMA transmission, CMD_CTLR (305) sent interrupt signal by the PPBS interface and finishes the DMA transmission to primary processor (314) in order to demonstration.

The execution mode of register (REGS 306) now will be described.

Exemplary REGS piece (306) comprises the configuration register in order to the operator scheme of configuration feature piece under primary processor control, and comprises the operating result of control circuit execution and the status register of mode of operation.REGS piece (306) is by CMD_CTLR (305) control, receive " register is write " or " register read " order by PPBS (303) interface from primary processor (314) after, CMD_CTLR reads or writes the register in the REGS piece (306).In other words, REGS piece (306) offers primary processor (314) configuration, activates and monitors the ability of the operation of control circuit execution.

In the exemplary embodiment, REGS piece (306) comprises one or more column registers down: the DMA_CONFIG register comprises about the DMA information transmitted between NAND flash memory (317) and SDRAM (318), as the nand flash memory page number of initial nand flash memory LPA, initial SDRAM address and transmission.The pulse train of each PBS interface transmits length in the PI_BURST_LENGTH register definitions PI circuit.The pulse train of SDRAM_BURST_LENGTH register definitions sdram interface transmits length.The initial SDRAM address of each auxiliary processor of SDRAM_PARTITION register definitions access, wherein each auxiliary processor is assigned with the initial SDRAM address of oneself alternatively.The RESET register is controlled resetting of each auxiliary processor separately.The MAD_PRIORITY register definitions is used for the check of the SDRAM main frame of SDRAM access.

INT_RECORDS register record is from the interrupt signal of CMD_CTLR (305) and each auxiliary processor.When primary processor (314) write " effectively " order in power-off (POWER_OFF) register, this register activated FMM circuit (311) and carries out the power-off program with accumulator system.After FMM circuit (311) was finished the power-off program, the value of POWER_OFF register was returned the default value " free time " that this register powers on by the signal change from FMM register (311).Alternatively, increasing other writes control/preparation register and/or reads result/status register to increase the controllability of primary processor to control circuit.The above-mentioned register of mentioning only is shown the operation of the control circuit of illustrated example, and is not used in restriction the present invention.

Referring to Fig. 3, the execution mode of guiding RAM (BOOT_RAM 307) will be described now:

In this exemplary execution mode, BOOT_RAM 307 is static RAM (SRAM), is used to store " system initialization " program code that primary processor (314) discharges the back, carries out from reset mode.BOOT_RAM (307) is subjected to the control of BOOT_CTLR (313) or CMD_CTLR (305), but is not both Be Controlled simultaneously alternatively.Behind electrification reset, BOOT_CTLR (313) is access BOOT_RAM (307) acquiescently, and initialization control circuit partly, the suitable part of BOOT_CTLR (313) activation control circuit will be being loaded into BOOT_RAM (307) from " system initialization " program code of nand flash memory.After the control circuit initialization, BOOT_CTLR (313) transfers the control of BOOT_RAM (307) to CMD_CTLR (305), discharge primary processor (314) down from reset mode then, make primary processor (314) to carry out the program code that is stored in BOOT_RAM (307) by CMD_CTLR (305).

Referring to Fig. 3, the execution mode of storage access distributor (MAD308) will be described now:

In control circuit, has the functional block of a plurality of initiation access SDRAM (318) request, (CMD_CTLR (305) for example, DMA_CTLR (312), FMM (311) and SPBS).Any functional block that can access SDRAM is referred to as " SDRAM main frame " hereinafter or is called for short " main frame ".MAD circuit (308) is to testing from the request of a plurality of SDRAM main frames, and based on priority scheme, authorizes the access permission of the main frame with highest priority.Priority scheme is configured by the MAD priority register in the REGS piece (306) alternatively.In case main frame is awarded access permission, MAD circuit (308) allows the access of the main frame acquisition of permission to SDRAM_CTLR (309), and stop other main frame accesses SDRAM_CTLR (309), just as the main frame of permitting is directly connected to SDRAM_CTLR (309).Then, by with transmit relevant information (as SDRAM address and transmission type (as reading or writing)) and send to SDRAM_CTLR (309), the main frame of permission brings into use SDRAM_CTLR (309) to come to send pulse train or the reception pulse train from SDRAM (318) to SDRAM (318).For the write pulse train of giving SDRAM (318), the main frame of permission provides pulse series data by MAD circuit (308) to the SDRAM_CTLR (309) that is used for data are written to SDRAM (318).For the read pulse string from SDRAM (318), SDRAM_CTLR (309) reads pulse series data from SDRAM (318), and the data that read is sent to the main frame of permission by MAD circuit (308).

Referring to Fig. 3, sdram controller (SDRAM_CTLR 309) will be described now:

SDRAM_CTLR circuit (309) is responsible for being used for according to the sdram interface agreement, provides control data and address signal to SDRAM, in order to operation SDRAM.The data transfer protocol of SDRAM (318) interface is well-known in the prior art, therefore no longer describes in the present invention.The operation that SDRAM_CTLR (309) carries out comprises: according to the sdram interface agreement, read pulse series data and to its write pulse train data from SDRAM (318), and when needed to SDRAM (318) pre-charge with refresh.SDRAM_CTLR (309) obtains the information relevant with special transmission by the MAD piece, as is used to write write data, the SDRAM address of transmission, and from the transmission type (as reading or writing) of the SDRAM main frame of permitting.MAD circuit (308) is tested in the SDRAM main frame of request access SDRAM (318), and allows the main frame of permission to send data, address and transmission type information to SDRAM_CTLR (309).Obtain the length that pulse train transmits in the SDRAM_BURST_LENGTH register of SDRAM_CTLR (309) from REGS piece (306), in the power up of control circuit, this pulse train transmits length and is loaded default value, and in the common course of work, it is changed by primary processor (314).

In optional execution mode, " memory is cut apart " function that SDRAM_CTLR (309) is provided for primary processor (314) is stipulated the address realm among the SDRAM (318) of each auxiliary processor access.For each SDRAM access that auxiliary processor is initiated, SDRAM_CTLR (309) increases a side-play amount for the address from this auxiliary processor, obtains one and be used as the actual address of SDRAM access.The SDRAM_PARTITION register (primary processor (314) can to it be written into suitable value) of SDRAM_CTLR (309) from REGS piece (306) obtains to be used for the side-play amount of each auxiliary processor.

Therefore, in this optional execution mode,, similarly be to carry out the SDRAM access from the initial address realm of address zero for each auxiliary processor, SDRAM_CTLR (309) in fact from the initial address realm of the side-play amount of primary processor (314) regulation, carries out the SDRAM access.This mechanism allows a plurality of auxiliary processors to operate at the different address realms of SDRAM storage space, and the software that does not need to revise auxiliary processor adapts to each the different address realm among the SDRAM (318).The address realm of each ppu can overlap each other according to application or be not overlapping.When an overlapping address realm, this overlapping address realm can be as the zone of the shared storage of two ppu exchange messages.Alternatively, therefore the SDRAM address that primary processor (314) access is all can use SDRAM (318) and auxiliary processor to come exchange message.

Alternatively, SDRAM_CTLR (309) further has the ability of a plurality of SDRAM devices of operation.In one embodiment, SDRAM_CTLR (309) sends a plurality of chip select signals to the control circuit circuit external by a plurality of output ports, and wherein given chip select signal is connected with the chip selection input port of separately SDRAM device.Alternatively, except chip select signal, a plurality of SDRAM devices are shared other controls, address and the data-signal from SDRAM_CTLR (309).According to being built in map addresses among the SDRAM_CTLR (309) or that be stored in mapping memory, the SDRAM storage space is divided into a plurality of address realms, and wherein each address realm is corresponding to a chip select signal.SDRAM_CTLR (309) determines which SDRAM device of access, perhaps based on by the MAD circuit from the address realm that the address fell into that receives of permission main frame, determine to assert (assert) which chip select signal of equal valuely.Under this mechanism, the SDRAM storage space of accumulator system (301) can be expanded and surpass the maximum space that single SDRAM device provides.

Referring to Fig. 3, now will explain flash controller (FLASH_CTLR 310):

The data transfer protocol that FLASH_CTLR 310 is responsible for being used for according to the nand flash memory interface provides control signal to operate nand flash memory.

The data transfer protocol of nand flash memory interface is well-known, therefore will be not described in detail at this.The various functions that the nand flash memory device can be activated and carry out with by the nand flash memory interface, for example " data input ", " auto-programming ", " reading mode " " idle reading mode ", " piece is wiped " and " device resets " etc. also is well-known, therefore is not described in detail at this.

FLASH_CTLR (310) can be under the control of BOOT_CTLR (313) or FMM, but alternatively, is not to be subjected to both control simultaneously.After electrification reset was stopped to assert, BOOT_CTLR (313) controlled FLASH_CTLR (310) acquiescently, and used FLASH_CTLR (310) to read FMM program code and system boot code from NAND flash memory (317).Then, BOOT_CTLR (313) transfers the control of FLASH_CTLR (310) to FMM (311), FMM (311) uses FLASH_CTLR (310) to be accessed in DMA between NAND flash memory (317) and the SDRAM (308) nand flash memory in transmitting, perhaps carry out FMM bookkeeping task, for example read ATT or upgrade ATT the NAND flash memory (317) from NAND flash memory (317).

FLASH_CTLR (310) comprises buffer, and it is the SRAM form alternatively, hereinafter, is referred to as PAGE_BUFF sometimes.PAGE_BUFF is used to transmit the interim storage of the data that pass in and out the nand flash memory page, and when carrying out ECC error correction, is used to store data.When FLASH_CTLR (310) is subjected to the control of BOOT_CTLR (313), BOOT_CTLR (313) but access PAGE_BUFF.When FLASH_CTLR (310) is subjected to FMM (311) control, FMM (311) or DMA_CTLR (312) access PAGE_BUFF.When the DMA transmission between FMM (311) use FLASH_CTLR (310) execution NAND flash memory (317) and the SDRAM (318), DMA_CTLR (312) access PAGE_BUFF.When FMM (311) uses FLASH_CTLR (310) to carry out conventional FMM bookkeeping task, FMM (311) access PAGE_BUFF.

FLASH_CTLR (310) further comprises error correcting code (ECC) circuit, is used to carry out ECC coding, decoding and proofreaies and correct the error of introducing with processing and protection nand flash memory medium that is stored in data wherein.When FLASH_CTLR (310) with data when PAGE_BUFF sends the nand flash memory device to, the ECC circuit is carried out coding (as based on the data computation parity check code that transmits).Parity check code also transmits and is stored in the nand flash memory device.When FLASH_CTLR (310) with data and parity check code when nand flash memory sends PAGE_BUFF to, the ECC circuit is carried out decoding, and determines whether error to occur in the data that transmit.If the discovery error, then the ECC circuit is for example read-is revised-write operation PAGE_BUFF by carrying out, and comes data are proofreaied and correct.

Alternatively, FLASH_CTLR (310) further comprises the configuration register (not shown), and BOOT_CTLR (313) and FMM (311) can programme to it, so that the information that need operate the nand flash memory device to be provided.The F_COMMAND register comprises the information of the action type that indication FLASH_CTLR (310) carries out, as " page or leaf is write ", " page or leaf is read ", " the page or leaf free time reads ", " piece is wiped ", " device resets " etc.The PPA register comprises the operation that need the be used for particular address physical page address (PPA) as " page or leaf is write ", " page or leaf is read " and " piece is wiped ".Can carry out write operation to the F_IDLE register, in order to FLASH_CTLR (310) is discharged from idle pulley, and can carry out read operation, to obtain the state of FLASH_CTLR (310) to it.Alternatively, the default value that powers on of this register is " idle (idle) ", and " free time " expression FLASH_CTLR (310) is in idle pulley.

When writing " activating (active) " order, the F_IDLE register discharges FLASH_CTLR (310) from idle condition, to carry out the operation of appointment in the F_COMMAND register.After finishing aforesaid operations, FLASH_CTLR (310) changes back " free time " with the value of register.Before FLASH_CTLR (310) is activated, the F_COMMAND register is set and the PPA register is set alternatively, and write suitable value.After FLASH_CTLR (310) activated, the F_IDLE register was by the mode of operation of taking turn (poll) with definite FLASH_CTLR (310).And, the F_IDLE register be written into be used to activate " activation " value of FLASH_CTLR (310) before, the F_IDLE register is comprised " free time " value by taking turn up to this register, is in idle pulley to guarantee FLASH_CTLR (310).

Fig. 6 has described the structured flowchart of the nand flash memory page exemplary, that be used for one-level ECC.The exemplary nand flash memory page (601) is divided into " User Part " (602) and " idle component " (603,604).User Part (602) hints as title, is used for storaging user data.Idle component (603,604) is used to store ECC parity check code (604), and stores idle data (603) alternatively.Idle data is such as but not limited to comprising one or more file system mark or being used for the thin note record of FMM circuit.

Current, in a lot of commercial available nand flash memory devices, these two parts are planned, thereby make that if the page comprises 528 bytes, then User Part accounts for low 512 bytes of the page, idle component accounts for high 16 bytes of the page, if perhaps each page comprises 2112 bytes, then User Part accounts for low 2048 bytes, and idle component accounts for the page 64 bytes.In the available flash memory device of some other commerce, flash memory device manufacturer can not be two parts with page division.In this case, the page still by the user of flash memory device at the conceptive two parts that are divided into, a part is as " User Part ", and other parts are as " idle component ".Alternatively, do not need ECC or need in flash memories, not store the system related information that is used for FMM (as, file system mark or bookkeeping record) in the flash memory device or system, flash memory device does not comprise " idle component " alternatively in each page, and full page is considered to " User Part ".

Fig. 6 also shows every page exemplary ECC parity check code and how to be stored in the page.In the present embodiment, the ECC function is assumed that one-level ECC.In other words, the ECC parity check code is based on a specific ECC sign indicating number, calculates from the data that are stored in " User Part " and the data that are stored in " idle component " alternatively.The data and the ECC parity check code that therefrom calculate the ECC parity check code itself are known " code words ".Therefore in page write operation, one-level ECC is stored in a single code word in the page.In the page or leaf read operation, in order to carry out error-detecting and error correction in order to ECC, whole codeword need be read from the page.Therefore, read from the page iff the segment such as the idle component data that are code word, then one-level ECC does not provide data protection.

The task that FMM algorithm and program are carried out is from nand flash memory page idle component sense data, and need not read the data of User Part, and in order to the relevant information of acquisition system, for example file system mark or some FMM approach the note record.In this case, one-level ECC can not provide data protection, and perhaps FMM algorithm and program can receive the information of destruction.Therefore, alternatively, the ECC function can be implemented as secondary ECC.

As shown in Figure 7; in exemplary execution mode; the ECC circuit is that the nand flash memory page (701) provides the two-stage data protection, data of first class of protection idle component (703) wherein, and the outer protection of another grade comprises the full page (701) of the data of the data of User Part and idle component.For the protection of idle component, the ECC circuit is based on the data computation ECC parity check code that is stored in idle component (idle parity check code 704).In order to protect full page, based on the data that are stored in User Part (702) and idle component (703,704 and 705), ECC calculates ECC parity check code (page or leaf parity check code 705).

Work as FLASH_CTLR, FLASH_CTLR as shown in Figure 3 (310), carrying out the page writes fashionable, except user data being write User Part and idle data being write into the idle component, two ECC parity check codes (idle parity check code (704) and page or leaf parity check code (705)) also write idle component.In other words, all store two-stage ECC code word in each Hash memory pages.When FLASH_CTLR (310) reads full page from the NAND flash memory, based on the page or leaf parity check code, the error in ECC electric circuit inspection and the correction full page.When FLASH_CTLR (310) only reads the idle component of the page, based on idle parity check code, ECC electric circuit inspection and the error of proofreading and correct idle data.

The page or leaf parity check code be separately based on the data of User Part alternatively, and not based on the data computation of idle component, and still idle parity check code also is based on the data computation of idle component alternatively.In this case, as FLASH_CTLR (310) when reading full page, ECC carries out error-detecting and correction based on page or leaf parity check code and idle parity check code, in order to provide protection to the data of User Part and the data of idle component respectively.The User Part of only reading the page as FLASH_CTLR (310) is during with relevant page or leaf parity check code, and the ECC circuit is carried out error-detecting and correction based on the page or leaf parity check code separately alternatively.

The error correcting code that the ECC circuit uses is block code alternatively, and the invention is not restricted to specific ECC sign indicating number or specific ECC block code.Two embodiment of the block code of known use are reed-solomon code (REED-Solomon Code) and Hamming code.The Code And Decode algorithm that is used for block code also is well-known, therefore is not described in detail at this.If use secondary ECC, alternatively, two ECC parity check codes are based on two different block codes.

Referring to Fig. 3, FLASH_CTLR (310) carries out the nand flash memory page and reads or page write operation, and need not consider logical page address (LPA) based on the physical page address from FMM circuit (311) or BOOT_CTLR reception again.Alternatively, when reading the NAND flash memory, BOOT_CTLR only reads from the leader of NAND flash memory (317), and directly generates PPA, because it is in exemplary execution mode, as broad as long between the page PPA of leader and LPA address.Therefore, BOOT_CTLR (313) can directly use FLASH_CTLR (310) to come access NAND flash memory, needn't actuating logic to the conversion of physical address.But, in the DMA transmission between NAND flash memory (317) and SDRAM (318), DMA_CTLR (312) is by sending logical page address to FMM circuit (311), this FMM circuit then becomes the PPA address with the LPA address transition, use the nand flash memory page of FLASH_CTLR (310) access PPA addressing then, thereby activate access each nand flash memory page.

Alternatively, FLASH_CTLR (310) further has the ability that a plurality of nand flash memory devices of control are provided.In order to realize this ability, in exemplary execution mode, FLASH_CTLR (310) sends the external circuit of a plurality of chip select signals to control circuit by a plurality of output ports.In this illustrative embodiments, given chip select signal selects input port to be connected with the corresponding chip of separately nand flash memory device.Alternatively, except chip select signal, a plurality of nand flash memory devices are shared other control and the I/O signals go to FLASH_CTLR (310), and control and I/O signals from other of FLASH_CTLR (310).According to the hard-wired address in FLASH_CTLR (310) circuit mapping or be stored in map addresses in the programmable storage, the nand flash memory memory space is divided into a plurality of address realms, so each address realm is corresponding with chip select signal.Which address realm FLASH_CTLR (310) falls into based on the PPA that receives from BOOT_CTLR or FMM circuit (311), determines which NAND flash memory of access, or of equal value determines which chip select signal is asserted.Under this mechanism, the nand flash memory memory space of accumulator system can be expanded and exceed an independent maximum space that the nand flash memory device provides.

The certain operations that exemplary FLASH_CTLR (310) is activated and carries out now will be described.Except the operation of describing, FLASH_CTLR (310) also can carry out the more eurypalynous operation about the nand flash memory device.Alternatively, FLASH_CTLR (310) can carry out other or with the different function of those functions described here.In exemplary execution mode, the operation that the F_COMMAND register value has specified FLASH_CTLR (310) to carry out, and the operation do not carried out of nand flash memory device.

" page is write " operation relates to the nand flash memory page that the data among the PAGE_BUFF is sent to the PPA addressing.Traditionally, before " page is write " operation was activated, PAGE_BUFF was mounted with the data of the nand flash memory page to be written, comprised in the data of the data of User Part and idle component.The PPA register at first writes the PPA address, and the F_COMMAND register writes " page is write " order.When the F_IDLE register write " activation ", FLASH_CTLR (310) was activated then.As employed in this paper bosom, when using phrase " to write " to be when related command or state write into register, what in fact writing is the digital value (can be by the expression of " 00000001 " value representation or other expectations as " activation ") of corresponding order or state.FLASH_CTLR (310) then activates " data input " function in the nand flash memory device, and begins data are sent to from PAGE_BUFF the internal data register of nand flash memory device.Alternatively, the ECC circuit can be simultaneously based on the data computation ECC parity check code that sends the nand flash memory device to.

After data in PAGE_BUFF send the nand flash memory device to, transmit the ECC parity check code following closely.Then, FLASH_CTLR (310) activate " auto-programming " function in the nand flash memory device with the storage in the internal data register in flash memory cell.After finishing " auto-programming " function of NAND device, it is " free time " that FLASH_CTLR (310) changes back the value of F_IDLE register.

" page is read " operation relates to, and sends the User Part data in the nand flash memory page of PPA addressing to PAGE_BUFF and sends the data of idle component to PAGE_BUFF, and proofread and correct the potential errors that flash media is introduced possibly.The PPA register at first writes PPA, and the F_COMMAND register writes " page is read " order.Then, when the F_IDLE register write " activation ", FLASH_CTLR (310) was activated.FLASH_CTLR (310) then activates " reading mode " function of NANA flash memory device, the data in the flash memory cell page of PPA addressing are read in the internal data register of nand flash memory device.Then, FLASH_CTLR (310) gives PAGE_BUFF with page data and ECC parity check code from the internal data register transfer of nand flash memory device, and makes the error in the ECC circuit check data simultaneously, and carries out error correction in PAGE_BUFF.After finishing error checking, FLASH_CTLR (310) changes back " free time " with the F_IDLE register value.

" page free time reads " operation comprises that the data of idle component that will be stored in the nand flash memory page of PPA addressing send PAGE_BUFF to.The PPA register at first writes the PPA address, and the F_COMMAND register writes " page free time reads " order.When the F_IDLE register write " activation ", FLASH_CTLR (310) was activated.FLASH_CTLR (310) then activates NANA flash memory device " idle reading mode " function, reads in the internal data register of nand flash memory device with the page idle component with the flash memory cell of PPA addressing.Then, FLASH_CTLR (310) sends the free page data in the internal data register of nand flash memory device to PAGE_BUFF.If use secondary ECC, also from nand flash memory, read idle parity check code, the ECC circuit uses the error in the idle parity check code check idle data of reading, and carries out the error correction among the PAGE_BUFF.FLASH_CTLR (310) changes back " free time " with the F_IDLE register value.

" piece is wiped " operation comprises the erase unit (being known as " piece ") of wiping whole nand flash memory." piece " comprises a plurality of pages.Therefore, in the exemplary embodiment mode, FLASH_CTLR (310) obtains block address by the least significant bit that removes it from PPA.For example, if block comprises 32 pages, and then the least significant bit by removing PPA is 5, obtains block address.The PPA register at first writes PPA, and FLASH_CTLR (310) becomes block address with this address transition, and the F_COMMAND register is write " piece is wiped " order.Then, when the F_IDLE register write " activation " order, FLASH_CTLR (310) was activated.FLASH_CTLR (310) then activates " piece is wiped " function in the nand flash memory device.After " piece is wiped " function in finishing the nand flash memory device, FLASH_CTLR (310) changes back " free time " with the F_IDLE register value.

" device resets " operation comprises the default conditions that power on that the circuit in the nand flash memory device recovered back it.The F_COMMAND register at first writes " device resets " order.When the F_IDLE register write " activation " order, FLASH_CTLR (310) was activated.FLASH_CTLR (310) then activates " device resets " function in the nand flash memory device.After " device resets " function in finishing the nand flash memory device, FLASH_CTLR (310) changes back " free time " with the F_IDLE register value.

Exemplary flash memory medium management device (FMM) now will be described:

Exemplary " flash memory medium management " process includes but not limited to one or more following technology: average read-write, garbage reclamation, bad piece substitute and power fail recovery.These technology are used for overcoming the problem that exists in the high density flash memory technology to wiping of carrying out of specific erase unit-rewrite cycle number of times sensitivity.Erase unit is defined as the zone that can be wiped free of on the storage medium under single erase operation.In the NAND flash memory, erase unit is equivalent to piece, comprise a plurality of pages (as 32 or 64 pages), wherein page or leaf (as 528 or 2112 bytes) is a data access unit, and this data access unit can use independent write order to write into storage medium or use read command memory read medium.When the piece of having finished writing need be replaced with new data, before new data can write this piece, monoblock need be wiped.Erase block and then with the process of new data write-in block count one in work and is wiped-rewrite cycle.

In current high density flash memory device, piece can bear 10,000 to 100,000 times usually and wipe-rewrite cycle, after these times circulation, more wipe-rewrite cycle will very might cause the piece defective, and piece will be stored data no longer reliably.Defect block that can not the reliable memory data is referred to as " bad piece ", and no longer is used for storing data.In theory, when more and more wipe-when rewrite cycle was applied in the flash memories, useful piece will be fewer and feweri, or else have at last and use piece.

If when software program such as operating system were not considered limited the wiping of high density flash memory memory-rewrite cycle, software might be with the position that has no to repeat to replace with new data some flash memories with retraining.For example be the file allocation table (FAT) in the file system, this table upgrades very continually.Cause some pieces to arrive the limit of they wipe-rewrite cycle soon like this, and become bad piece.Replaced bad piece even make good use of piece by software, wherein, good piece is used for storing otherwise will be stored in data in the bad piece, but the same position that in fact has no the manifolding flash memory device has still consumed all the good pieces in the whole flash memory with retraining soon, perhaps wherein effectively a part of, and in unacceptable short time interval, the life-span of the flash memory device that is through with.

In order to increase or maximize the useful life of flash memory device, so occurred arranging in a lot of flash medias and the method for tracking data.These methods often comprise separates " logic " address space from " physics " address space, wherein the higher level systems soft ware is according to the memory space of " logic " flash memory address operation flash data.Address transition mechanism converts logical address to physical address, and the drive software of inferior grade device uses this physical address to come the access flash media then.

For the relation between service logic and the physical address, use ATT usually.When the systems soft ware of higher level is not to wipe relevant physical address, and new data write into same physical address, but when replacing the logical address write with new data, in fact the software of lower grade find the physical address of not writing, and new data write into the physical address that this finds recently again.Scheduler conversion table then is with the new relation between reflection logic and the physical address.This technology so-called " average read-write " is because a plurality of the writing of same logical address has been assigned to a plurality of different physical addresss, therefore makes loss minimum in particular physical address.

When logical address was repeatedly rewritten, the latest data of this logical address was included in the physical address, but previous a lot of other physical addresss relevant with this logical address will comprise outdated data.These out-of-date physical addresss can reclaim it by they being carried out erase operation, and they are changed into the physical address of " not writing ".This technology is referred to as " garbage reclamation " usually.

Even use the average read-write technology, some pieces may finally still become bad piece, and can not be used for storing reliably data, and are therefore substituted by good piece.In other words, when piece becomes bad piece, choose piece and store data, otherwise will be stored in the bad piece.This technology is referred to as " bad piece replacement " usually.

Aforementioned techniques generally includes the record of safeguarding some bookkeepings, as one or more logical-physical address conversion tables, bad piece position with comprise physical address of fault data or the like.In order to follow the tracks of the data placement in the flash memories, these records are stored in the flash memories, and often are updated, to be enough to react the latest data arrangement in the flash memories.If but the record in flash memories unexpected power failure occurred before correct the renewal,, write down and can not comprise the most current information then when main device (as portable phone) when powering on once more.In order to overcome this potential danger, a lot of prior aries have appearred, in order to the record of the up-to-date bookkeeping of recovery under the power failure situation.These technology are referred to as " power fail recovery " technology usually.

Above-mentioned mentioned technology is generically and collectively referred to as " flash memory medium management " in this article.Have a lot of can be by spendable flash memory medium management technology known to those of skill in the art.But different with the accumulator system of a lot of existing portable phones, execution mode provides not to be had or seldom under the intervention of ppu, is realizing the method for user-defined flash memory medium management mechanism in the accumulator system.

Referring to Fig. 3, the circuit of flash memory medium management algorithm and program is carried out in the representative of flash memory medium management device (FMM 311) piece, and this circuit is as the interface between logic nand flash memory address space and the nand flash memory physical address space.Exemplary FMM circuit (311) comprises the random access memory (as static RAM (SRAM)) of internal processor alternatively.As described, internal processor is called as " FMM_P ", and the FMM random access memory is called as " FMM_RAM ".FMM_RAM provides the volatibility random access memory, and it can be used to store the FMM program code, and FMM_P can carry out this program code.BOOT_CTLR (313) and FMM_P energy access FMM_RAM, but be not both accesses simultaneously.

In the bootup process that powers on, BOOT_CTLR (313) is loaded into FMM_RAM with the FMM program code, discharges FMM_P then and carries out the wherein FMM program code of storage with access FMM_RAM.The FMM program code is based on a series of instructions of FMM_P instruction set.By obtaining instruction from FMM_RAM, FMM_P carries out the FMM program code.Average information that produces when alternatively, FMM_P also uses FMM_RAM to come storage running FMM program code and the bookkeeping record that is used for the FMM algorithm.Can carry out user-defined flash memory medium management algorithm with the FMM program code, FMM_P carries out this FMM program code and realizes these algorithms.

Fig. 8 has shown the block diagram of exemplary FMM_P (801), and FMM_P (801) is used in the system shown in Figure 3 alternatively.Exemplary FMM_P (801) includes but not limited to, internal register (802), ALU (804), IP (IP) (803) and control unit (CU) (805).Internal register (802) is used for the data that FMM_P (801) are read in temporary transient storage, also is used for temporarily storing the data that FMM_P (801) reads.ALU (804) carries out arithmetic operation such as addition, subtraction and as internal register and or and the logical operation of XOR.IP (803) is the register that comprises the FMM_RAM location address, and this FMM_RAM position comprises the next instruction of FMM_P to be read in (801).CU (805) control command is executed the task, as change the IP value, read instruction and the data of FMM_RAM, write data advances FMM_RAM, receive other functional blocks of making from the interrupt signal of the various parts of control circuit with to this interrupt signal in anticaustic, configuration and the activation control circuit or the like.

Again referring to Fig. 3, FMM (311) further provides the configuration register (not shown), as the device that is used for BOOT_CTLR (313) and DMA_CTLR (312) configuration and activation FMM (311).The LPA register comprises the LPA of the nand flash memory page for the treatment of access.The operation that comprises FMM (311) execution in the FMM_COMMAND register is as " page is read ", " page is write " or the like.After powering on, FMM (311) ignores this register and finishes initialization task up to FMM (311).Whether the FMM_INIT register is used to indicate FMM (311) initialization.The default value that powers on of this register is " no initializtion ", and after FMM (311) finished initialization task, FMM (311) changed this value and is " initialization ".The FMM_IDLE register can be write, so that FMM (311) is discharged down from idle pulley.The default value that powers on of this register is " free time ", is used to indicate FMM (311) to be in idle pulley.When FMM_IDLE register value of writing " activation ", the FMM_IDLE register is discharged down from idle pulley, with execution FMM program code, and FMM (311) begins to carry out the task to initialized operation of FMM (311) or the appointment of FMM_COMMAND register.After finishing the work, FMM (311) changes back register value " free time ".The FMM_IDLE register write be used for activating FMM " activation " before, poll (poll) FMM_IDLE register comprises that up to this register " free time " is to guarantee indicating FMM (311) to be in idle pulley.

FMM_P (801) instruction set provides the instruction of the configuration register among the Writing/Reading FLASH_CTLR (310), to operate nand flash memory memory (317) in order to configuration and activation FLASH_CTLR (310), FMM_P (801) instruction set also provides between PAGE_BUFF and FMM_RAM the instruction that transmits data, with in order to transmit data to nand flash memory memory (317) with send data from nand flash memory memory (317).FMM_P (801) instruction set further provides the instruction by MAD (308) and SDRAM_CTLR (319) execution data access SDRAM (318), with in order to transmit data between FMM_RAM and SDRAM.In other words, FMM (311) is the main frame of SDRAM, according to the access permission Handshake Protocol of MAD piece, by MAD access SDRAM (318).The average information that FMM_P (801) produces when using SDRAM (318) to come storage running FMM program code and the thin note record of FMM (311) algorithm are not provided for above-mentioned purpose at FMM_RAM under the situation of enough memory space.Utilize these instructions, FMM (311) can carry out data by FMM_RAM and transmit between nand flash memory and SDRAM (318).

The FMM program code is stored in the non-volatile nand flash memory memory (317), and by BOOT_CTLR (313) this FMM program code is loaded into FMM_RAM in bootup process.But when the FMM program code was read from nand flash memory memory (317) by BOOT_CTLR (313), FMM (311) still can not work.Therefore, the FMM program code is stored in the subregion that is referred to herein as " boot section " of nand flash memory memory (317), does not use the FMM algorithm in this district, and is therefore as broad as long between logical page address and physical page address.In other words, do not need to use FMM (311) algorithm sense data from the boot section of nand flash memory memory (317).In conjunction with the description of BOOT_CTLR (311), the boot section is more described in detail.

After electrification reset was stopped to assert, FMM (313) remained in idle pulley, and just the FMM program code is loaded into FMM_RAM.By " activation " write into the FMM_IDLE register, make FMM (311) activate then, thereby make BOOT_CTLR (311) that FMM (311) is discharged down from idle pulley.Then, FMM_P (801) begins to carry out the FMM program code from FMM_RAM.At this moment, the FMM_INIT register also comprises " no initializtion " indication, causes FMM_P (801) transfer to be carried out like this and indicates FMM_P (801) to carry out the initialized program of FMM in the FMM program code.

FMM is initialized as the part in the FMM function, is user-defined therefore, and wherein terminal installation (as portable phone) manufacturer and/or other appropriate users can define the management algorithm and the program of flash memories.The present invention does not limit task or the task sequence that relates in the FMM initialization.Below describe and showed exemplary several initialization tasks that FMM (311) is used for carrying out.

FMM (311) initialization often comprises that discovery need be used for the thin note of the FMM of flash memory medium management (311) record, as ATT, and it is copied to FMM_RAM or SDRAM (318) from nand flash memory memory (317).Find that the idle component that the thin note record of FMM generally includes a lot of nand flash memory pages is loaded into FMM_RAM, FMM (311) checks the data of the idle component of every page herein, determines whether corresponding N AND flash memory pages comprises the thin note of FMM record.In case comprise the thin note of a part of FMM record in the discovery page, then from nand flash memory memory (317), read the User Part of the page, and this User Part is loaded into FMM_RAM or SDRAM (318).

For data (User Part data, idle component data or both) are copied to FMM_RAM from the nand flash memory page, FMM (311) generates nand flash memory PPA, and configuration FLASH_CTLR (310) reads in the nand flash memory page of PPA addressing the PAGE_BUFF of FLASH_CTRL.FMM (311) is loaded into FMM_RAM with data from PAGE_BUFF then.For data are copied to SDRAM from the nand flash memory page, FMM (311) at first generates nand flash memory PPA and SDRAM address, disposes the PAGE_BUFF that FLASH_CTLR (310) reads in the nand flash memory page of PPA addressing FLASH_CTRL then.FMM (311) reads in FMM_RAM with data from PAGE_BUFF then, and by MAD (308) data among the FMM_RAM is write into SDRAM (318).

After finishing the flash memory medium management initialization, the value that FMM (311) changes the FMM_INIT register is " free time ", and the FMM_IDLE register is " initialization ".From this moment, FMM (311) prepares to be used for actuating logic-physical address translations, therefore is ready to receive the order from DMA_CTLR (312), transmits with the DMA that supports the primary processor request.When idle pulley discharges once more, the value of FMM_INTI register " initialization " indication FMM_P (801) is transferred to the part of FMM program code, carries out the operation of appointment in the FMM_COMMAND register, and does not carry out initialization.

In normal operating process, the thin note record of FMM can be retained among the FMM_RAM, among SDRAM (318) or both.Because in FMM_RAM, therefore thin note record also is easy to be stored in FMM_RAM to the FMM program code.In order to explain the operation of present embodiment, below describe the thin note record of supposition FMM and be retained among the SDRAM (318).When the FMM algorithm need read to be stored in thin note record among the SDRAM (318), (for example to carry out some tasks, read ATT and come actuating logic-physical address translations) time, FMM (311) approaches note record copies to FMM_RAM from SDRAM (318) with a part by MAD (308), and the FMM algorithmic code reads the data of copy in FMM_RAM.When the FMM algorithmic code need upgrade the thin note record of a part among the SDRAM, FMM (311) generates the redaction of the thin note record of a part in FMM_RAM, by MAD (308) data are copied to SDRAM (318) from FMM_RAM then, are stored in the legacy version of SDRAM (318) in order to replacement.

Sometimes, some the thin note records in the nand flash memory memory (317) need be write or upgrade to the FMM algorithm, so often relates to the operation of wiping various nand flash memory pieces and data being copied to nand flash memory memory (317) from SDRAM (318).In order to wipe the nand flash memory piece, FMM (311) generates the block address of waiting to wipe the nand flash memory piece, then this block address is loaded into the PPA register, and configuration FLASH_CTRL (310) is to wipe the nand flash memory piece.For data are copied to the nand flash memory page from the SDRAM address, FMM (311) at first generates nand flash memory PPA and SDRAM address, by MAD (308) data are read into FMM_RAM from SDRAM (318) then, and data are write into the PAGE_BUFF of FLASH_CTRL from FMM_RAM.FMM (311) configuration FLASH_CTRL (310) is in order in the nand flash memory page of the data among the PAGE_BUFF being write into the PPA addressing then.

Should be noted that in normal operations do not need other functional blocks of control circuit or primary processor (314) to activate or get involved, FMM (311) algorithm can initiate to upgrade the thin note record in the nand flash memory memory (317).When FMM (311) needed the spontaneous task of execution to serve the order that is written to the FMM_COMMAND register to stop FMM (311), FMM (311) changed into " activation " with the value of FMM_IDLE register before beginning this task.After finishing this task, the value that FMM (311) changes this register is " free time ".Therefore, the FMM_IDLE register write activate FMM (311) " activation " before, poll (poll) FMM_IDLE register comprises " free time " up to this register, is in idle pulley to guarantee FMM (311).

By using configuration register, DMA_CTLR (312) uses FMM (311) to come the access nand flash memory page based on LPA.Read with the LPA according to nand flash memory in order to dispose FMM (311), DMA_CTLR (312) writes into the LPA register with LPA, and will order " page reads " to write in the FMM_COMMAND register.DMA_CTLR (312) writes into " activation " in the FMM_IDLE register then, activates FMM (311), and beginning poll FMM_IDLE register.In case FMM (311) is activated, actuating logic-physical address translations to convert LPA to PPA, disposes the physics nand flash memory page that FLASH_CTLR (310) reads this PPA then.After FLASH_CTLR (310) finished the page and reads, the value that FMM (311) changes the FMM_IDLE register be " free time ", to indicate the nand flash memory page data now to be in PAGE_BUFF to DMA_CTLR (312).DMA_CTLR (312) reads PAGE_BUFF and obtains page data then.

In order to dispose FMM (311) data are write into the LPA of nand flash memory, DMA_CTLR (312) at first writes into data PAGE_BUFF, LPA is write into the LPA register and will order " page is write " to write into the FMM_COMMAND register.DMA_CTLR (312) will order " activation " to write into the FMM_IDLE register and activate FMM (311) then, and beginning poll FMM_IDLE register.In case FMM (311) is activated, actuating logic-physical address translations converts LPA to PPA, disposes FLASH_CTLR (310) then the data among the PAGE_BUFF are write in the physics nand flash memory page of this PPA.The value of FMM (311) change FMM_IDLE register is " free time " then, finishes to write to DMA_CTLR (312) the indication page.

Alternatively, can dispose the FMM program code and stop the zone that comprises significant data in the nand flash memory memory (317) to be wiped free of or to replace, for example comprise the zone of the significant data of system boot code, FMM program code and important operation system-program code or the like.This measure protection is stored in data in the nand flash memory memory (317) can not changed or be intended to destroy to significant data in the nand flash memory memory (317) by accident malicious application software change.The zone of shielded nand flash memory memory (317) is referred to as the FMM protection zone hereinafter.According to logical address, physical address or both, the FMM protection zone can be designated in the FMM program code.For example when DMA_CTLR (312) configuration FMM (311) came the nand flash memory page of LPA write, FMM (311) at first checked and checks whether LPA belongs to the FMM protection zone.If then FMM (311) does not carry out LPA to PPA conversion or activates FLASH_CTLR (310) corresponding PPA is write.Because the FMM program code self needs protection to provide protection in order to other data to nand flash memory memory (317), so a district that especially needs protection is the zone of FMM program code storage.

In exemplary execution mode; before primary processor (314) discharges under the reset mode; when the FMM program code is read from nand flash memory memory (317) by the hardware of BOOT_CTLR (313); and FMM (311) is when working, and the FMM protection zone of FMM program code definition can not be changed by primary processor (314).If the FMM protection zone comprises the boot section, FMM program code and system boot code can not be changed by primary processor.In other words, FMM (311) can provide protection to the data in being stored in nand flash memory memory (317), the influence of the software program of carrying out with other processors that are not subjected in primary processor or the external electronic device.

When the user initiates the order powered-down when (as promoting the power-off button) to host apparatus (for example portable phone), FMM (311) algorithm need upgrade some the thin note records in the nand flash memory memory (317), so that when portable phone powers on once more, can obtain nearest thin note record.This is called as " power-off processing ".In order to make the thin note record in FMM (311) the renewal nand flash memory memory (317), FMM (311) is activated to carry out the processing of power-off, and preferably keep the power supply that is fed to accumulator system (301) simultaneously, finish power-off up to FMM (311) and handle.

After the power-off order that receives the user, power-off (POWER_OFF) register of primary processor (314) in REGS piece (306) writes " activation ", sends signal to FMM (311) then and comes activating power to close closed procedure.When FMM (311) carried out the power-off process, primary processor (314) began this register of poll then.When FMM (311) finishes the power-off process, FMM (311) sends a signal to the value that the REGS piece changes the POWER_OFF register and is " free time ", thereby makes primary processor (314) externally carry out the power supply of necessary task with closing of portable phone in the electronic equipment.When receiving signal from REGS piece (306) and begin the power-off process, FMM (311) can be the free time, or is in the process of carrying out other operations.The configurable operation to interrupt carrying out before beginning power-off process of FMM program code was perhaps finished the operation of carrying out before beginning power-off process.

Alternatively, this FMM structure allows almost do not having to make accumulator system (301) carry out the flash memory medium management task under the intervention of (or minimum) ppu.The software program that primary processor (314) is carried out is operated the flash data memory space according to " logic " address, so ppu needn't have the expense that manages, safeguards or change the data setting in the physical flash medium.The benefit that this autonomy (autonomous) attribute of FMM (311) brings is to make that it similarly is by hard-wired.Alternatively, because FMM (311) is implemented as the internal processor that operates in user-defined FMM program code in the exemplary execution mode, therefore the user can not make any change to the mounting hardware of control circuit, and the update routine code, in this case, accumulator system hardware or even after cellular phone design is finished and is adjusted, allow simple leak repairing and the FMM program code upgraded.Therefore, also to provide similarly be the benefit that is realized by software to FMM (311).

Referring to Fig. 3, existing with the more detailed exemplary dma controller (DMA_CTLR 312) of description.DMA_CTLR (312) is responsible for being used under primary processor (314) control, and when just being monitored by primary processor (314), carries out the DMA transmission between nand flash memory memory (317) and the SDRAM (318).More specifically, CMD_CTLR (305) activates DMA_CTLR 312 then and carries out the DMA transmission by the DMA transmission command (as " downloading the DMA transmission " or " uploading the DMA transmission ") of PPBS (303) reception from primary processor (314).The DMA transmission command itself has been indicated transmission direction.Order causes the transmission of nand flash memory to SDRAM " to download the DMA transmission "." upload the DMA transmission " and cause the transmission of SDRAM to nand flash memory.DMA_CTLR (312) comprise along with the DMA transmission command from other information in the DMA_CONFFIG register of REGS piece (306), as transmitted data amount (as, fixed with nand flash memory page number gauge), initial nand flash memory logical page address (LPA) and initial SDRAM address.DMA_CTLR (312) generates the initial SDRAM address of LPA and corresponding each nand flash memory page to be transmitted of the nand flash memory page to be transmitted then.

For the DMA that finishes the nand flash memory page transmits DMA_CTLR (312) access nand flash memory memory (317) and SDRAM (318).For access nand flash memory memory (317) rather than directly control FLASH_CTLR (310), DMA_CTLR (312) activates FMM (311) and controls FLASH_CTLR (310), because DMA_CTLR (312) operates in nand flash memory logical address space (as LPA), and need FMM (311) to come the actuating logic physical address translations based on FMM algorithm and/or table.

Transmit in order to begin the nand flash memory page, DMA_CTLR (312) writes LPA and transmission type (as " page is write " of being used to download " page is read " of DMA transmission or being used to upload the DMA transmission) to LPA register and FMM_COMMAND register, writes " activation " to the FMM_IDLE register then.The conversion of FMM (311) executive address obtains PPA then, and configuration FLASH_CTLR (310) reads or writes with the nand flash memory page to this PPA address.For downloading the DMA transmission, configuration FLASH_CTLR (310) carries out page read operation.When FLASH_CTLR (310) finished page read operation, page data was stored among the PAGE_BUFF with the potential error of being proofreaied and correct by the ECC circuit.Then, DMA_CTLR (312) generates next LPA, and activates FMM with from nand flash memory memory (317) the read next page, and DMA_CTLR (312) moves to SDRAM (318) from PAGE_BUFF with data simultaneously.

For uploading the DMA transmission, DMA_CTLR (312) at first moves to PAGE_BUFF with the valuable data of the page from SDRAM (318), activates FMM (311) then and uses FLASH_CTLR (310) to carry out page write operation.Along with FLASH_CTLR (310) moves to nand flash memory memory (317) with data from PAGE_BUFF, DMA_CTLR (312) begins the data of following one page are moved to from SDRAM (318) PAGE_BUFF of FLASH_CTLR.Repeat this process up to finishing the DMA transmission.

For access SDRAM (318), as other SDRAM main frames, DMA_CTLR (312) sends access request to MAD (308), and waits for access permission.When licensed, by using SDRAM_CTLR (309), DMA_CTLR (312) execution pulse train is sent to SDRAM/ and transmits pulse train from SDRAM, and then the transmission access request is carried out next pulse train transmission.DMA_CTLR (312) carries out a plurality of pulse trains and transmits, and the valuable data of finishing the nand flash memory page transmit.Burst length is to be determined by the SDRAM_BURST_LENGTH register in the REGS piece, and before beginning DMA transmitted, primary processor (314) loaded suitable value to the SDRAM_BURST_LENGTH register.

Referring to Fig. 3, existing with the more detailed exemplary guide controller (BOOT_CTLR_313) of discussion.BOOT_CTLR (313) is responsible for being used to carry out after powering on the task of initialization control circuit immediately, for example, system boot code and FMM program code is loaded into BOOT_RAM (307) and FMM_RAM respectively from nand flash memory memory (317); Under the free time, discharge FMM (311), and discharge primary processor (314) down from reset mode.BOOT_CTLR (313) use FLASH_CTLR (310) reads the boot section in the nand flash memory memory (317).Because the FMM algorithm shall not be applied to the boot section, so in one embodiment, for as broad as long between the logic of the data of boot section and the physical address.When reading the boot section, BOOT_CTLR (313) does not carry out logic to physical address translations, and directly generates the PPA of the page in the boot section, uses FLASH_CTLR (310) to read each PPA from the boot section then.

Figure 9 shows that exemplary nand flash memory memory space (901) distributes.In the present embodiment, nand flash memory memory space (901) is divided into boot section (902) and FMM controlled area (903).Alternatively, the boot section (902) of nand flash memory memory (as nand flash memory memory (317) among Fig. 3) does not comprise the FMM algorithm of carrying out average read-write, garbage reclamation, the replacement of bad piece and power fail recovery.Boot section (902) is the zone of system's guidance code and the storage of FMM program code.Preferably, when manufacturer assembles portable phone, these program codes just are written into the boot section (902) of nand flash memory, and except under few relatively situation stored program code wherein being carried out leak repairing or can being wiped free of when upgrading, these program codes can not be wiped free of in the common use of portable phone.

Therefore, boot section (902) can not produce the wearing and tearing that bring as other district's as many wiping-rewrite cycle of nand flash memory memory, therefore defective can not occur in the life cycle of portable phone.Therefore, alternatively, the FMM algorithm shall not be applied to boot section (902).In other words, in the present embodiment,, therefore when access should be distinguished, do not need to carry out the logical physical address transition for as broad as long between the logic of the data in boot section (902) and the physical address.FMM controlled area (903) is used to store other program codes, user data and the thin note record of FMM algorithm.In FMM controlled area (903), in order to the purpose that realizes that average read-write and bad piece are replaced, the data that are stored in wherein move to different physical addresss everywhere, and are kept and followed the tracks of by the FMM algorithm.Therefore, when the data of access FMM controlled area, FMM (FMM as shown in Figure 3 (311)) actuating logic physical address translations (907).

As shown in Figure 9, boot section (902) comprise FMM program code (904) and system boot code (905).Referring to Fig. 3, after power-on reset signal was stopped to assert, BOOT_CTLR (313) became activation automatically, disposed and activated FLASH_CTLR (310) then and obtain data with the boot section (902) from nand flash memory memory (317).Obtain each page or leaf of boot section (902) along with the PAGE_BUFF among the FLASH_CTLR (310), if the page is a part of FMM program code, then BOOT_CTLR (313) is sent to FMM_RAM with page data from PAGE_BUFF, if perhaps the page is a part of system boot code, then be sent to BOOT_RAM (307).Then along with BOOT_CTLR (313) with data when PAGE_BUFF shifts out, BOOT_CTLR (313) activates FLASH_CTLR (310) and obtains the next nand flash memory page among the PAGE_BUFF.Repeat this process, the program code in the boot section (902) of nand flash memory memory (317) is loaded into FMM_RAM and BOOT_RAM (307).

Then, BOOT_CTLR (313) writes into " activation " in the FMM_IDLE register, under idle condition, discharging FMM (311), and beginning poll FMM_IDLE register.FMM_P begins to carry out the FMM program code that is stored in the FMM_IDLE register then, and carries out the initialization of FMM algorithm.After initialization, it is " free time " that FMM (311) changes back the value of FMM_IDLE register, so that BOOT_CTLR (313) stops to assert to the reset signal by PPBS (303) whereabouts primary processor (314).Primary processor (314) becomes activation then, and begins to carry out the system boot code that is stored in BOOT_RAM (307).At this moment, BOOT_CTLR (313) finishes its function, and will keep idle be asserted and then be stopped up to power-on reset signal assert so that BOOT_CTLR (313) repeats said process.

For boot section (902) program code read from nand flash memory memory (317), BOOT_CTLR (313) need know the PPA scope of the nand flash memory of FMM program code and system boot code.Providing the method for this information to BOOT_CTLR (313) is that built-in or hardwired makes BOOT_CTLR (313) always from fix N AND flash memory PPA program code read in the circuit of BOOT_CTLR (313) with this information.Another method is the idle component that " leader label " is stored in the nand flash memory page in the boot section (902), leader label is discerned this page or leaf and is FMM program code part or system boot code part thus, perhaps neither FMM program code part neither the system boot code part, to be built into the knowledge of (902) the PPA scope that has the boot section and to detect leader label when the nand flash memory page of boot section (902) is read into PAGE_BUFF be the function of FMM program code or system boot code to discern content of pages to BOOT_CTLR (313) simultaneously.In case content of pages is discerned, BOOT_CTLR (313) moves to FMM_RAM or BOOT_RAM (307) with the data among the PAGE_BUFF of FLASH_CTLR.

Below the operation of some execution modes will be described referring to flow chart and Fig. 3.

At first, the bootup process behind the description electrification reset.Figure 10 shows the bootup process that exemplary BOOT_CTLR (313) carries out.Asserting of power-on reset signal makes whole accumulator systems and external electronic device be in reset mode.In state (1001), power-on reset signal is stopped to assert.After power-on reset signal stopped to assert, BOOT_CTLR (313) became activation automatically, and began to generate a PPA of boot section at state (1002).Then, dispose and activate the nand flash memory page that FLASH_CTLR (310) reads this PPA at state (1003,1004) BOOT_CTLR (313).

In state (1005), determine whether FLASH_CTLR (310) is idle, determine thus whether FLASH_CTLR (310) has finished page read operation.The potential errors that the nand flash memory page of having read is proofreaied and correct with the ECC circuit is stored among the PAGE_BUFF.Then, whether be system boot code part or FMM program code part referring to state (1006,1007 and 1008) according to this page or leaf, BOOT_CTLR (313) is copied to BOOT_RAM (307) or FMM_RAM with page data from PAGE_BUFF.

In state (1009), judged whether the page how waiting for transmission.If also have the page in the boot section, operation executing state (1010), BOOT_CTLR (313) repeats above-mentioned downloading process and downloads other nand flash memory pages, and all program codes up to the boot section have been read into and have been copied to BOOT_RAM (307) or FMM_RAM.In state (1012), BOOT_CTLR (313) discharges FMM (311) under idle condition then.In case be released, begin to carry out the FMM program code that is stored among the FMM_RAM at state (1013) FMM (311).

In state (1013), FMM program code indication FMM (311) initialization FMM disposes, as reads the ATT in the nand flash memory memory (317), and this conversion table is copied to SDRAM (318).Judge as FMM (311) at state (1014) and to finish initialization, then at state (1015) by the reset signal via PPBS interface whereabouts primary processor (314) is stopped to assert, BOOT_CTLR (313) discharges primary processor down from reset mode.Then, in state (1016), BOOT_CTLR (313) becomes the free time, but primary processor (314) is activated, and begins to carry out the system boot code among the BOOT_RAM (307).In state (1017), accumulator system (301) enters " normal mode of operation ".

" normal mode of operation " refers to the initialization at FMM (311), and can actuating logic to the conversion of physics nand flash memory address, and primary processor (314) discharges situation with the executive system guidance code down from reset mode.In addition, primary processor (314) gives an order transmission pulse data turnover BOOT_RAM (307) and SDRAM (318) by PPBS (303) and CMD_CTLR (305); Register in the write and read REGS piece (306) disposes/operation of supervisory memory system (301); Activate the DMA transmission between nand flash memory memory (317) and the SDRAM (318); And the interrupt signal that receives CMD_CTLR (305) or the generation of one or more auxiliary processor.And in normal mode of operation, auxiliary processor can discharge access SDRAM (318) by primary processor (314) individually, and in case of necessity, sends interrupt signal to primary processor (314).

In case be in normal mode of operation, the DMA transmission is the function of often using.Now incite somebody to action the download of more detailed description control circuit execution and upload the DMA transmission.

Figure 11 shows exemplary execution nand flash memory " downloading the DMA transmission " process to the transmission of SDRAM (318).In state (1101), primary processor (314) is to the relevant information of DMA, programmes as initial nand flash memory LPA, initial SDRAM (318) address and the data volume that transfers to the DMA_CONFIG register.In state (1102), primary processor (314) sends " downloading the DMA transmission " order, makes CMD_CTLR (305) activate DMA_CTLR (312) to carry out the DMA transmission in this order of state (1103).In state (1104), DMA_CTLR (312) obtains the DMA relevant information from the DMA_CONFIG register.In state (1104), based on the DMA_CONFIG register information, DMA_CTLR (312) generates the first nand flash memory LPA and its corresponding SDRAM address, activates FMM (311) to read the nand flash memory page of this LPA at state (1105) then.In state (1106), it is PPA that FMM (311) actuating logic to physical address translations is changed LPA, is configured then and activates FLASH_CTLR (310) to read the nand flash memory page of this PPA at state (1107).

When FLASH_CTLR (310) finished page read operation, determined as state (1108), page data was with being stored among the PAGE_BUFF by the calibrated potential error of ECC circuit.DMA_CTLR (312) need move to SDRAM (318) from PAGE_BUFF with page data now.DMA_CTLR (312) at first is split as page number the pulse data with SDRAM pulse train coupling, for given pulse, in state (1109), sends the SDRAM access request to MAD (308).After state (1110) determines that access has been permitted, by SDRAM_CTLR (309) pulse data is transferred to SDRAM (318) from PAGE_BUFF at state (1111) DMA_CTLR (312).In state (1112), determine whether in the page, to have the pulses that need transmission more.If have, at state (1113) DMA_CTLR (312) repeated access SDRAM (318), the SDRAM access will be repeated until that all page datas have transferred to SDRAM (318).Then, DMA_CTLR (312) duplicate pages transmission course is up to finishing whole DMA transmission (1114,1115).In state (1116), CMD_CTLR (304) interruption primary processor (314) is indicated and is finished the DMA transmission.

Figure 12 shows exemplary execution SDRAM " uploading the DMA transmission " process to the nand flash memory transmission course.Referring to Fig. 3 and 12, in the relevant information of state (1201) primary processor (314) with DMA, for example initial nand flash memory LPA, initial SDRAM (318) address and the data volume that transfers to the DMA_CONFIG register are programmed.Send " uploading the DMA transmission " order at state (1202) primary processor (314).Activate DMA_CTLR (312) at state (1203) this order causing CMD_CTLR (305) and carry out the DMA transmission.In state (1204), DMA_CTLR (312) obtains the information relevant with DMA from the DMA_CONFIG register.In state (1204), based on the information relevant with DMA from the DMA_CONFIG register, the LPA that DMA_CTLR (312) generates first nand flash memory with and corresponding SDRAM address.

DMA_CTLR (312) begins page data is moved to PAGE_BUFF from SDRAM (318).In state (1206), ask in response to DMA_CTLR, determine MAD (308) access that whether secured permission, wherein DMA_CTLR (312) at first is split as pulse train with the page data among the SDRAM (318), and, send SDRAM (318) access request to MAD (308) (state 1205) for each pulse.When licensed access, pulse data is transferred to PAGE_BUFF from SDRAM (318) at state (1207) DMA_CTLR (312).Referring to state (1208,1209), DMA_CTLR (312) repeated access SDRAM (318) has been transferred to PAGE_BUFF up to all page datas.

In state (1210), DMA_CTLR (312) activates the nand flash memory page that FMM (311) writes into page data LPA.In state (1211), FMM (311) at first actuating logic to physical address translations converts LPA to PPA, then configuration and activate FLASH_CTLR (310) to write the nand flash memory page of this PPA at state (1212).In state (1213), determine whether FLASH_CTLR (310) is idle, whether finished page write operation with definite FLASH_CTLR (310), and whether the ECC parity check code of page data and the calculating of ECC circuit has write the nand flash memory page of this PPA.DMA_CTLR (312) repeats identical page transmission up to finishing whole DMA transmission,, interrupts primary processor (314) indication at state (1216) CMD_CTLR (305) and finishes the DMA transmission by having determined whether more multipage face transmission at state (1214).

In exemplary execution mode, because the size of BOOT_RAM (307) is little with respect to all program codes that are stored in nand flash memory memory (317), therefore BOOT_CTLR (313) can only be loaded into a small amount of program code BOOT_RAM (307), in order to carry out immediately at the back primary processor (314) that powers on.Primary processor (314) often needs larger sized more multiprogram code to carry out modern portable phone sophisticated functions.Preferably, in case be in normal mode of operation, primary processor (314) will dispose control circuit and carry out DMA transmission, with all program codes or fundamental system program code such as operating system, file system and device drives are copied to SDRAM (318) at least.Then, primary processor (314) continues to carry out from BOOT_RAM (307), perhaps forwards the execution of SDRAM (318) in case of necessity to.From this moment, portable phone (or other host apparatus) enters " user model ".

" user model " refers to except normal mode of operation, enough software program codes have transferred to the situation of SDRAM (318) from nand flash memory memory (317), therefore be in the illustrative embodiments of portable phone at host apparatus, the user interface of portable phone permission user uses the function on the portable phone.

What Figure 13 had illustrated that primary processor (314) carries out enters the exemplary process of user model from normal mode of operation.In state (1302), primary processor (314) identification need be used for the program of user model.Referring to state (1303 to 1308), for each program, primary processor activation DMA transmits program code is copied to SDRAM from nand flash memory, and all program codes that need up to user model are downloaded to SDRAM (318) from nand flash memory.In state (1309), primary processor (314) forwards the user model program implementation then to, and enters user model (1310) at state (1310).

Before entering user model, be not copied under the situation of SDRAM (318) at some program codes (as Application Software Program) from nand flash memory memory (317), when the user begins some application that need carry out these programs, be necessary these application programs are copied to SDRAM (318) from nand flash memory memory (317).

When Figure 14 showed user model, primary processor (314) was carried out the exemplary process that Client-initiated is used.In state (1401), primary processor (314) receives user command to run application.In state (1402), primary processor (314) identification need be used for the program of the application of user's operation, but this program is not copied to SDRAM (318) from nand flash memory memory (317).Referring to state (1403 to 1408), for each program, primary processor activation DMA transmits program code is copied to SDRAM (318) from nand flash memory memory (317).In case the procedure stores that need be used for using in SDRAM (318), forwards the execution of this application at state (1409) primary processor (314).

Alternatively, primary processor (314) further is responsible for: program code is copied to SDRAM (318) from nand flash memory memory (317) carries out in order to one or more auxiliary processors; Resetting of control (control at least in part) auxiliary processor; And the interruption of response auxiliary processor generation.

Figure 15 shows the example process of primary processor (314) control auxiliary processor.In state (1501), primary processor (314) receives user command and activates the application of being carried out by auxiliary processor (as figure or multimedia processor).In order to activate auxiliary processor, in state (1502), primary processor (314) is at first discerned auxiliary processor and is carried out the program that particular task needs.Referring to state (1503 to 1508), for each program, primary processor (314) activates downloads the DMA transmission, thereby corresponding program code is copied to SDRAM (318) from nand flash memory memory (317).In case the required procedure stores of auxiliary processor is in SDRAM (318), in state (1509), primary processor (314) is programmed the SDRAM_PARTITION register, and the zone that correctly is provided with among the SDRAM (318) is used for the auxiliary processor access.This zone comprises the program from nand flash memory memory (317) download that is used for the auxiliary processor execution.In state (1510), primary processor (314) writes suitable value to the RESET register, stops to assert in order to the reset signal to auxiliary processor.In state (1511), auxiliary processor is activated, and carries out the program code from the suitable subregion of SDRAM (318).

Auxiliary processor is because a variety of causes can need to interrupt primary processor (314) (finishing for example to notify the primary processor task).Alternatively, although auxiliary processor in this exemplary process, supposes behind complete operation that because other reasons also can produce interruption auxiliary processor interrupts primary processor.Have no progeny in state (1512) receives, in state (1513), primary processor (314) is read the INT_RECORD register, and definite auxiliary processor has been initiated interruption.In state (1514), primary processor (314) is carried out corresponding program centering stopping pregnancy and is given birth to effect.In this embodiment, in state (1514), primary processor (314) is write the RESET register, makes auxiliary processor recover reset mode.

Under normal mode of operation, primary processor (314) further is responsible for user data is copied to SDRAM (318) from nand flash memory memory (317), perhaps when primary processor needs, perhaps carries out opposite operation for auxiliary processor.

The execution mode that other are exemplary:

The execution mode of other several exemplary now will be described.Below describe and to concentrate the part of describing other execution modes that are different from above-mentioned first execution mode description.

In the second exemplary execution mode, alternatively, control circuit does not have BOOT_RAM.BOOT_CTLR is connected with the MAD circuit, makes BOOT_CTLR can pass through MAD circuit access SDRAM.The bootup process that BOOT_CTLR carries out is different with the described bootup process of above-mentioned first execution mode.After powering on, not that system boot code is copied to BOOT_RAM from the nand flash memory memory, but BOOT_CTLR at random uses SDRAM_CTLR initialization SDRAM, in that primary processor is discharged with before carrying out the code from SDRAM, system boot code is loaded into SDRAM then.

Figure 16 has illustrated second execution mode of accumulator system (1601).The functional block of the control circuit in the present embodiment different with above-mentioned discussion now will be described.

Exemplary execution mode comprises primary processor (1614), one or more auxiliary processor (1604), PI (1602) (it comprises PPBS (1603), and one or more SPBS (1604)) CMD_CTLR (1605), REGS piece (1606), MAD (1608), FMM (1611), DMA_CTLR (1612), SDRAM_CTLR (1609), FLASH_CTLR (1610), BOOT_CTLR (1613), nand flash memory memory (1617) and SDRAM (1618).

As previously discussed, do not have BOOT_RAM in the present embodiment.

Because BOOT_CTLR (1613) moves to system boot code among the SDRAM (1618), rather than system boot code is moved to BOOT_RAM, so the exemplary BOOT_CTLR (1613) of present embodiment is different with first execution mode.The bootup process that BOOT_CTLR (1613) carries out will be described below.

After power-on reset signal (1616) was stopped to assert, BOOT_CTLR (1613) activated automatically.After activation, BOOT_CTLR (1613) disposes FLASH_CTLR (1610), so that obtain data from the boot section of nand flash memory memory (1617), wherein the boot section comprises system boot code and FMM program code.The potential error that every page of ECC circuit in FLASH_CTLR of boot section is proofreaied and correct is loaded into the PAGE_BUFF among the FLASH_CTLR, if the page is a FMM program code part, then BOOT_CTLR (1613) moves to FMM_RAM with page data from PAGE_BUFF, if perhaps the page is the system boot code part, then BOOT_CTLR (1613) moves to SDRAM (1618) with page data from PAGE_BUFF.Alternatively, BOOT_CTLR (1613) activates FLASH_CTLR (1610) simultaneously to obtain the next nand flash memory locked memory pages among the PAGE_BUFF.Repeat this process, be loaded into FMM_RAM, and system boot code is loaded into SDRAM (1618) up to the FMM program code.

For page data is moved to SDRAM (1618) from PAGE_BUFF, provide connection (1619) from BOOT_CTLR (1613) to the MAD (1608), connect BOOT_CTLR (1613) access SDRAM (1618) by this, BOOT_CTLR (1613) is the main frame of SDRAM.For page data is transferred to SDRAM (1618) from PAGE_BUFF, the page data that BOOT_CTLR (1613) splits among the PAGE_BUFF is a plurality of pulse series datas that mate with the SDRAM pulse train, then according to the access permission agreement of MAD (1608), each pulse is transferred to SDRAM (1618) by MAD (1608), up to the full page data being copied to SDRAM (1618).

After the boot section with the nand flash memory memory is loaded among FMM_RAM and the SDRAM (1618), BOOT_CTLR (1613) discharges FMM (1611) with the initialization flash memory medium management, after this, BOOT_CTLR (1613) stops to assert to the reset signal by PPBS (1603) whereabouts primary processor (1614).Primary processor (1614) begins to carry out the system boot code that is stored among the SDRAM (1618) then.At this moment, BOOT_CTLR (1613) finishes its function, and will keep idle being stopped up to power-on reset signal to assert, then is stopped once more and asserts, so that BOOT_CTLR (1613) repeats said process.

The exemplary execution mode of instruction control unit as shown in Figure 16 (CMD_CTLR1605) now will be described.Owing to do not have BOOT_RAM in the present embodiment, so CMD_CTLR 1605 needn't carry out access BOOT_RAM.For primary processor (1614), SDRAM (1618) but be expressed as access RAM storage space.When CMD_CTLR 1605 receives from " RAM reads " or " RAM writes " of primary processor order by PPBS (1603), CMD_CTLR 1605 sends access request to MAD (1608), and the wait access permission, thereby allow primary processor (1614) to carry out burst transmission to SDRAM (1618) or carry out burst transmission from SDRAM (1618).

The illustrative embodiments of the storage access distributor (MAD1608) that goes out as shown in figure 16 now will be described.

In order to allow BOOT_CTLR (1613) that the PAGE_BUFF of data from FLASH_CTLR (1610) moved to SDRAM (1618), configuration MAD (1608) accepts the access request from BOOT_CTLR (1613), and with other SDRAM main frames access request is judged.Therefore, MAD (1608) is used as BOOT_CTLR (1613) as another one SDRAM main frame.

Referring to Figure 17, the operation of second execution mode as shown in figure 16 will be described now.Figure 17 has described the bootup process that BOOT_CTLR (1613) carries out.At state (1701) power-on reset signal is asserted, make accumulator system (1601) and external electronic device be in reset mode.After power-on reset signal is stopped to assert, automatically activate at state (1702) BOOT_CTLR (1613), begin to generate a PPA of boot section, and dispose and activate FLASH_CTLR (1610) so that read the nand flash memory page of this PPA at state (1703,1704).In state (1705), when definite FLASH_CTLR (1610) finished page read operation, any potential error that the nand flash memory page of reading is proofreaied and correct with the ECC circuit of FLASH_CTLR was stored among the PAGE_BUFF.In state (1706), determine whether the page is system boot code part or FMM program code part.In state (1707), if the page is a FMM program code part, then BOOT_CTLR (1613) is copied to FMM_RAM with page data from PAGE_BUFF.If the page is the system boot code part, then will be copied to SDRAM (318) at state (1708) page, as described herein.

Referring to state (1708), if page data is the system boot code part, then BOOT_CTLR (1613) splits into the pulse data that mates with the SDRAM pulse train with page data, then to each pulse, sends the SDRAM access request to MAD (1608).In state (1709), determine whether licensed access of MAD (1608), when licensed access, BOOT_CTLR (1613) transfers to SDRAM (318) with pulse data from PAGE_BUFF by SDRAM_CTLR (1609).In state (1711), determine whether page pulse in addition.If have, BOOT_CTLR (1613) generates the SDRAM address of next pulse at state (1712).BOOT_CTLR (1613) repeats burst transmissions to SDRAM (318), up to the full page transfer of data among the PAGE_BUFF to SDRAM (318).

In state (1713), determine in the boot section whether to also have the page.If also have the page, generate next PPA at state (1714) BOOT_CTLR (1613).BOOT_CTLR (1613) repeats the read operation of the nand flash memory page, and FMM_RAM or SDRAM (318) are read and copied to all program codes in the boot section from nand flash memory.In state (1715), BOOT_CTLR (1613) discharges FMM (1611).In case be released, then in state (1716), FMM (1611) begins to carry out the FMM program code that is stored among the FMM_RAM.FMM program code indication FMM carries out the task of initialization FMM configuration, as reads the ATT in the nand flash memory memory (1617), then it is copied to SDRAM (318).

In case FMM (1611) finishes initialization (1717), in state (1718), by the reset signal through PPBS interface (1603) whereabouts primary processor (1614) is stopped to assert, BOOT_CTLR (1613) discharges primary processor (1614) down from resetting.In state (1719), BOOT_CTLR (1613) becomes the free time, and primary processor (1614) is activated, and begins to carry out system boot code among the SDRAM (318) by transmission pulse data turnover SDRAM (318).In state (1720), accumulator system (1601) enters " normal mode of operation " (1720).

Figure 18 shows the 3rd execution mode of accumulator system (1801).Compare with first execution mode shown in Figure 3, in this embodiment, do not have BOOT_RAM in the control circuit.Therefore, it is described that bootup process is different from first execution mode.

The 3rd illustrative embodiments comprises: primary processor (1814), one or more auxiliary processor (1815), PI (1802) (it comprises PPBS (1803) and one or more SPBS (1804)), CMD_CTLR (1805), REGS piece (1806), MAD (1808), FMM (1811), DMACTLR (1813), nand flash memory memory (1817) and SDRAM (1818).

By with the initialize routine of FMM program code a part, be implemented in the system boot code transmission course that wherein guidance code is transferred to SDRAM (318) from nand flash memory memory (1817) as the FMM initialization procedure.Therefore, except the thin note record of FMM that will be used for the FMM algorithm transfers to the SDRAM (1818) from nand flash memory memory (1817), when operation FMM initialize routine, FMM (1811) is further programmed so that system boot code is loaded into SDRAM (1818) from nand flash memory memory (1817).Do not need BOOT_RAM, and BOOT_CTLR (1813) needn't load the system boot code from nand flash memory memory (1817).BOOT_CTLR (1813) is loaded into FMM_RAM with the FMM program code from nand flash memory memory (1817), then FMM (1811) is discharged down from idle pulley, and primary processor (1814) is discharged down from reset mode.When primary processor (1814) was discharged under reset mode by BOOT_CTLR (1813), primary processor (1814) was carried out the system boot code among the SDRAM (318), rather than carried out the system boot code among the BOOT_RAM.

Functional module with the different control circuit as shown in figure 18 shown in Fig. 3 first execution mode will be described below:

As mentioned above, do not have BOOT_RAM in this embodiment, the BOOT_CTLR of present embodiment (1813) is that with the difference of first execution mode BOOT_CTLR (1813) does not carry out the processing that system boot code is loaded onto BOOT_RAM from the nand flash memory memory device.

After power-on reset signal was stopped to assert, BOOT_CTLR (1813) activated automatically.After being activated, BOOT_CTLR (1813) configuration FLASH_CTLR (1810) is so that obtain the FMM program code from the boot section of nand flash memory memory (1817).When the potential error of proofreading and correct with the ECC circuit when every page FMM program code was packed PAGE_BUFF into, BOOT_CTLR (1813) moved to FMM_RAM with page data from the PAGE_BUFF of FLASH_CTLR.Simultaneously, BOOT_CTLR (1813) activates FLASH_CTLR (1810) to obtain the next nand flash memory locked memory pages among the PAGE_BUFF.Repeat this process, be loaded into FMM_RAM up to the FMM program code.

After the FMM program code was loaded into FMM_RAM, BOOT_CTLR (1813) discharged FMM (1811) to carry out the FMM initialization.Implement as the initialize routine of FMM program code, the FMM initialization both was loaded into SDRAM (1818) with the thin note record of FMM from nand flash memory memory (1817), also system boot code was loaded into SDRAM (1818).After FMM (1811) finished initialization, BOOT_CTLR (1813) stopped to assert to the reset signal by PPBS (1803) whereabouts primary processor (1814).Primary processor (1814) begins to carry out the system boot code that is stored among the SDRAM (1818) then.At this moment, BOOT_CTLR (1813) finishes its function, and keeps idle, is asserted once more up to replying a signal by cable, then is stopped and asserts, thereby make BOOT_CTLR (1813) repeat said process.

CMD_CTRL (1805) is similar with above-mentioned described CMD_CTRL (1605) operation.

Referring to Figure 19, the operation of the 3rd execution mode shown in Figure 180 will be described now.Figure 19 shows the exemplary bootup process that BOOT_CTLR (1813) as shown in figure 18 carries out.In state (1901), power-on reset signal is asserted, so that accumulator system (1801) and external electronic device are in reset mode.After power-on reset signal is stopped to assert, activate automatically at state (1902) BOOT_CTLR (1813), and begin to generate the PPA of the boot section that comprises the FMM program code.In state (1903,1904), BOOT_CTLR (1813) configuration and activation FLASH_CTLR (1810) are in order to read nand flash memory memory (1817) page of this PPA.

In state (1905), whether by detecting FLASH_CTLR (1810) is idle, determine whether FLASH_CTLR (1810) has finished page read operation, and whether nand flash memory memory (1817) page read is stored among the PAGE_BUFF with the potential errors that the ECC circuit is proofreaied and correct.In state (1906), BOOT_CTLR (1813) is copied to FMM_RAM with the PAGE_BUFF of page data from FLASH_CTLR.Based on whether the boot section being gone back determining of the page at state (1907), pass through to generate next PPA at state (1908), BOOT_CTLR (1813) repeats nand flash memory memory (1817) page read operation, up to reading the FMM program code and it is copied to FMM_RAM from nand flash memory memory (1817).

In state (1909), BOOT_CTLR (1813) discharges FMM (1811) down from idle pulley.In case FMM is no longer idle, and has been released, FMM (1811) begins to carry out the FMM program code that is stored among the FMM_RAM.FMM program code indication FMM (1811) carries out the task of initialization FMM (1811), comprises system boot code is copied to SDRAM (1818) from nand flash memory memory (1817).As FMM (1811) when finishing initialization, in state (1910), by the reset signal through PPBS interface (1911) whereabouts primary processor (1814) is stopped to assert, BOOT_CTLR discharges primary processor (1814) down from idle pulley.In state (1912), BOOT_CTLR (1813) becomes the free time, but primary processor (1814) is activated, and by pulse data transmission turnover SDRAM (1818) being begun to carry out the system boot code among the SDRAM (1818).In state (1913), accumulator system (1801) enters " normal mode of operation ".

If the FMM initialize routine is configured to make the FMM algorithm at FMM system boot code to be worked before nand flash memory memory (1817) is read, then because when FMM (1811) read apparatus guidance code, nand flash memory memory logic to physical address translations works, so system boot code needn't leave in the boot section of nand flash memory memory (1817).In other words, in case the FMM algorithm works, the zone of the FMM control of FMM (1811) energy access nand flash memory memory (1817), and the system boot code in the zone that is stored in FMM control can also be set, even the position of system boot code is that the logical address according to the nand flash memory memory defines in the FMM program code.Similarly, except system boot code, dispose the FMM program code alternatively so that other program codes or data are loaded into SDRAM (1818) from nand flash memory memory (1817).Alternatively, whole nand flash memory memory data image can be copied into SDRAM (1818), perhaps copies the as many data image that can hold with SDRAM (1818).

In some installed as portable phone, external electronic device can comprise nonvolatile memory, as was used for storing the flash memory and the read-only memory (ROM) of the system boot code that is used for primary processor (1814).In this case, system boot code can not be stored in the nand flash memory memory (1817) in the accumulator system (1801), and when primary processor (1814) discharges, externally provide system boot code by other mechanism to primary processor (1814) in the electronic equipment under reset mode.Therefore, do not need BOOT_RAM, and BOOT_CTLR (1813) needn't be from nand flash memory memory (1817) the Load System guidance code, but still can from nand flash memory memory (1817), the FMM program code be loaded into FMM_RAM, and FMM and primary processor (1814) are discharged down from reset mode.

When primary processor (1814) was discharged under reset mode by BOOT_CTLR (1813), primary processor (1814) passed through from external electronic device, rather than from accumulator system (1801), obtains instruction, comes the executive system guidance code.And in some electronic installations such as portable phone, external electronic device is further directly controlled resetting of primary processor (1814).In this case, when BOOT_CTLR (1813) stopped to assert to the reset signal of whereabouts primary processor (1814), primary processor (1814) can be or also not discharged down from reset mode by external electronic device.Therefore, the reset signal that BOOT_CTLR (1813) sends to primary processor (1814) can be used to indicate whether accumulator system initialization by primary processor (1814), and the service of being ready to is from the signal of the order of primary processor (1814).

FMM (1811) carries out except before being discharged down from reset mode by BOOT_CTLR (1813) at primary processor (1814), and the ability that system boot code is loaded into the task outside the SDRAM (1818) is used in a lot of application.For example, alternatively, primary processor (1814) needs to satisfy: when primary processor discharged under reset mode, primary processor (1814) can obtain whole software or its subclass, thereby carries out read operation with random access mode.As embodiment, when primary processor (1814) is to use under the situation about implementing based on the microprocessor of ROM, then there is this demand, before the wherein actual executive software, this microprocessor based on ROM is just discharging under reset mode, just can carry out the whole software and the subclass of the software of choosing are carried out safety verification, will cause being stored in the rogue program code that the data in the nand flash memory memory (1817) are damaged to guarantee that software does not comprise.In order to adapt to this demand, alternatively, configuration FMM initialize routine, made before BOOT_CTLR (1813) discharges primary processor (1814) under the reset mode, whole portable telephone system software or the subclass chosen are loaded into SDRAM (1818) from nand flash memory memory (1817).

Alternatively, if primary processor (1814) is this safety verification of executive software not, then safety verification can be implemented in the FMM program code, make to be loaded into SDRAM (1818) afterwards from nand flash memory memory (1817) safety verification of FMM (1811) executive software in SDRAM (1818) at software.Alternatively, configuration FMM program code is to carry out encryption/decryption algorithm.In this case, software program code by the ppu execution, but do not comprise the FMM program code, can be stored in the nand flash memory memory (1817) with encryption format, be loaded into SDRAM (1818) afterwards at software program code, the form that FMM (1811) can carry out the program code deciphering for ppu.Energy uses routine, unconventional and still has various safety verification algorithms and encryption/decryption algorithm to be performed, and is not limited to specific algorithm in accumulator system.

Owing to have above-mentioned memory system architecture, a variety of algorithms can be implemented in the FMM program code, thereby make FMM can manage data in nand flash memory memory (1817), between nand flash memory memory (1817) and SDRAM (1818), transmit data, and the data that are stored in are wherein carried out various operations in a different manner.FMM operation described here only is expressed as embodiment, is not the use that is used for limiting FMM in the specific embodiment (1811).

Figure 20 shows that the 4th execution mode of accumulator system (2001).In the present embodiment, control circuit comprises a plurality of identical circuit of FLASH_CTLR and SDRAM_CTLR.Among the embodiment as shown in figure 20, control circuit provides two identical FLASH_CTLR (being called FLASH_CTLR (2011) and FLASH_CTLR (2012) hereinafter) and two identical SDRAM_CTLR (hereinafter being called SDRAM_CTLR (2009) and SDRAM_CTLR (2010)), but the number of FLASH_CTLR and SDRAM_CTLR is not limited to two.In the 4th exemplary execution mode, further comprise primary processor (2016), one or more auxiliary processor (2017), PI (2002) (comprising PPBS (2003) and a plurality of SPBS of fire (2004)), CMD_CTLR (2005), REGS piece (2006), MAD (2008), FMM (2013), DMACTLR (2014), BOOTCTLR (2015), nand flash memory memory (2019,2020) and SDRAM (2021,2022).

As mentioned above, FLASH_CTLR and/or SDRAM_CTLR provide a plurality of chip select signals in order to operate a plurality of nand flash memory devices and a plurality of SDRAM device respectively.But, in exemplary configuration, alternatively, although a plurality of storage arrangement can be under the control of each controller, each controller (FLASH_CTLR or SDRAM_CTLR) is limited in preset time and on one's own initiative an independent storage arrangement is advanced or gone out to (actively) transfer of data.The storage address of each access is used for determining which memory should be activated based on built-in memory table, or which storage arrangement controller should carry out addressing to, is each storage arrangement specified address area in memory table with this.In other words, provide the controller of a plurality of chip select signals the maximum memory space that is provided above the single memory device can be provided total storage space, but rate of data signalling can not be enlarged the maximum data transfer rate that surpasses the single memory device.

By two identical FLASH_CTLR and two identical SDRAM_CTLR are set, not only the memory space of nand flash memory memory and SDRAM is double, and the rate of data signalling of nand flash memory and SDRAM is also double.For given FLASH_CTLR, control circuit provides one group of input and output port that is connected with the nand flash memory device, and wherein Dui Ying FLASH_CTLR operates this nand flash memory device.Similarly, for given SDRAM_CTLR, control circuit provides one group of input and output port that is connected with the SDRAM device, and wherein Dui Ying SDRAM_CTLR operates this SDRAM device.Therefore, in the present embodiment, the sum of the input and output port that can be connected with the SDRAM device with the nand flash memory device is the twice in the first exemplary execution mode.

Present embodiment is not that coordination constraints with the operation of two FLASH_CTLR or two SDRAM_CTLR is in particular technology.By embodiment current execution mode is described, in embodiment as described below, suppose that two FLASH_CTLR (2011,2012) carry out identical operations, and two SDRAM_CTLR (2009,2010) also carries out identical operations.

When the data access carried out nand flash memory, two FLASH_CTLR (2011,2012) carry out identical operations in the essentially identical time.In other words, control circuit is read two pages in the identical time from the nand flash memory memory space, perhaps the nand flash memory memory space is write two pages, and each page or leaf carries out data by one among the FLASH_CTLR (2011,2012) and transmits.In order to adapt to this hardware configuration, the logical page (LPAGE) in the nand flash memory memory space can be for being " interlaced (interleaved) " between two FLASH_CTLR (2011,2012).For example, if the data in the whole nand flash memory memory space are arranged in the page of LPA0,1,2,3.... or the like in logic, then the even number LPA as LPA0,2... etc. is stored in the nand flash memory device (2019) that links to each other with FLASH_CTLR1, and is stored in the nand flash memory device (2020) that links to each other with FLASH_CTLR2 as the odd number LPA of LPA1,3... etc.Therefore, control circuit is access LPA0 and 1 or LPA2 and 3 together always, or the like.Owing to have two FLASH_CTLR (2011,2012), therefore the LPA sum in the nand flash memory memory space is the twice in first execution mode.

In the present embodiment, each FLASH_CTLR has physical address space (as PPA) independently and unique, the logic relation to physics.Based on unique, the logic of the FLASH_CTLR1 relation to physics, even number LPA is stored in the physical address space of FLASH_CTLR1.Based on unique, the logic of the FLASH_CTLR2 relation to physics, odd number LPA is stored in the physical address space of FLASH_CTLR2.

Introduce new data cell here, and be referred to as " logic pair of pages " hereinafter (LDP).Each LDP comprises two nand flash memory pages of continuous LPA, and one of them LPA is an odd number, and another LPA is an even number.Each LDP is distributed in hereinafter the address that is called " LDP address (LDPA) ".For example, LDPA0 addresses two pages of LPA0 and LPA1, and LDPA1 addresses two pages of LPA2 and LPA3, by that analogy.Owing to have two FLASH_CTLR (2011,2012), control circuit is sent to a LDP nand flash memory space or transmits a LDP from the nand flash memory space in single nand flash memory accessing operation mode, and wherein FLASH_CTLR1 transmits even number LPA, and FLASH_CTLR2 transmits odd number LPA.

Similar with FLASH_CTLR (2011,2012), two SDRAM_CTLR (2009,2010) carry out identical data access operation in the identical time.In other words, when the data access carried out the SDRAM storage space, control circuit is read two pulse datas simultaneously or is write two pulse datas, and each pulse data transmits by one among the SDRAM_CTLR (2009,2010).Two SDRAM_CTLR (2009,2010) in identical time operation same commands are set, and to have effect be with the width of data word is double the same.For example, if the size of data of single SDRAM pulse is 8 words, each word is 16 bit widths, and then two SDRAM pulses in the identical time equal 8 words, and each word is 32 bit widths.

Different with the functional block of control circuit in as shown in Figure 3 first execution mode, the functional block of the control circuit of execution mode as shown in figure 20 is described below.

Control circuit comprises two identical FLASH_CTLR, and wherein each FLASH_CTLR has the function identical or similar as first execution mode.Although be only limited at one time a nand flash memory device is carried out access, each FLASH_CTLR exports a plurality of chip select signals and operates a plurality of nand flash memory devices.Two FLASH_CTLR (2011,2012) are subjected to the control of BOOT_CTLR (2015) and FMM (2011), and carry out identical data access at one time.

For BOOT_CTLR (2015),, therefore as broad as long between logical address and the physical address in the boot section because the FMM algorithm is not applied in the boot section of nand flash memory memory space.In the first embodiment, when reading the boot section, BOOT_CTLR (313) need not carry out logic and directly generate the PPA with the value that increases progressively to physical address translations, activates FLASH_CTLR (310) then and comes to read from the boot section each PPA.In the present embodiment, as shown in figure 20, the boot section page is interleaving access between two FLASH_CTLR (2011,2012), occupies the identical PPA in the physical address space of two FLASH_CTLR (2011,2012), and is preferably, all initial from PPA0.In other words, two FLASH_CTLR (2011,2012) have the identical PPA that is appointed as " boot section PPA ".

Therefore, when carrying out read operation from the boot section, BOOT_CTLR (2015) directly generates boot section PPA, activates two FLASH_CTLR (2011,2012) then simultaneously, makes each FLASH_CTLR read the nand flash memory page of identical PPA.When two FLASH_CTLR (2011,2012) finished their read operation, each PAGE_BUFF comprised page data, and BOOT_CTLR (2015) moves to BOOT_RAM or FMM_RAM according to the PPA of two pages with two page datas.

For sdram controller (SDRAM_CTLR), control circuit comprises two identical SDRAM_CTLR, and each SDRAM_CTLR has and the first execution mode identical functions.Two SDRAM_CTLR (2009,2010) carry out identical data access operation at the same time.For each SDRAM main frame, access SDRAM storage space is to be that the twice of the data word width of single SDRAM device is carried out with the pulse data word.

For flash memory medium management device (FMM_2013), akin flash memory medium management task described in FMM (2013) execution and first execution mode, but, further, the PPA that opens based on one group of LPA and two components carries out these tasks, therefore can safeguard the relation (in other embodiments, FMM can be adjusted to handle other flash controllers and sdram controller) of two logics to physical address.Among first embodiment, be the relation between the PPA of odd number LPA and FLASH_CTLR_1, and the relation between the PPA of even number LPA and FLASH_CTLR_2.Alternatively, these two kinds of relations are based on the FMM algorithm identical or similar with first execution mode.When DMA_CTLR (2014) activation FMM (2013) reads to be used for dual numbers LPA and two pages of LDPA that address of odd number LPA, FMM (2013) carries out two address transition and converts even number LPA the PPA of FLASH_CTLR_1 to, and odd number LPA is converted to the PPA of FLASH_CTLR_2.Then, FMM (2013) is configured two FLASH_CTLR (2011,2012), so that the execution page read operation from their corresponding PPA in the substantially the same time.Therefore, the LPA register among the FMM in the first embodiment (2013) replaces with " LDPA " register.

For register (REGS 2006), in the first embodiment, the DMA_CONFIG register comprises about the DMA information transmitted between nand flash memory and the SDRAM, as the number of initial nand flash memory LPA, initial SDRAM address and the nand flash memory page to be transmitted.In the present embodiment, initial nand flash memory LPA is replaced by initial LDPA, and the number of the nand flash memory page to be transmitted is replaced by the number of LDP to be transmitted.Initial SDRAM address finger widths is the data word of twice of the data word width of single SDRAM device.

For dma controller (DMA_CTLR 2014), because two FLASH_CTLR (2011,2012) operate simultaneously, during therefore each access nand flash memory space, by downloading or upload two nand flash memory pages or LDP, DMA_CTLR (2014) carries out DMA and transmits.Because two SDRAM_CTLR (2009,2010) operate simultaneously, the pulse data word of the double-width of the data word by transmitting single SDRAM device, DMA_CTLR (2014) carries out the access to the SDRAM space.

Obtain in the DAM_CONFIG register of DMA_CTLR (2014) from REGS piece (2006) with this DMA and transmit simultaneous other information of order, as transmission data volume, initial logic pair of pages address (LDPA) and the initial SDRAM address of preferably stipulating with the number of logic pair of pages (LDP).DMA_CTLR (2014) generates the LDPA of LDP to be transmitted then, and corresponding to the initial SDRAM address of each LDP.

In order to transmit LDP, DMA_CTLR (2014) sends LDPA and transmission type (reading or LDP writes as LDP) to FMM (2013), the conversion of this FMM (2013) executive address is to obtain two PPA then, a PPA is used for a FLASH_CTLR, then to two FLASH_CTLR (2011,2012) be configured, so that each FLASH_CTLR reads or writes to it from the nand flash memory page of themselves PPA correspondence.Alternatively, DMA transmits the integer that the data volume that moves is equal to LDP, and can not begin or stop the DMA transmission in the centre of LDP.

Instruction control unit (CMD_CTLR 2005) now will be described.To above-mentioned described similar about first execution mode, preferably, CMD_CTLR (2005) comprises the temporary transient storage that data buffer transmits the data between primary processor (2016) and the accumulator system (2001) with work.Not not matching between the rate of data signalling of data buffer permission PPBS interface (2003) and the rate of data signalling of sdram interface.In the present embodiment, the length that transmits in the pulse of sdram interface is still defined by the SDRAM_BURST_LENGTH register, but because the size of data word is the twice in first execution mode, therefore, be used for CMD_CTLR (2005) and correspondingly enlarged, so that adapt with double-length based on sdram interface by the signal that MAD piece (2008) was sent to and transferred out SDRAM_CTLR.In other words, the data transfer rate between CMD_CTLR data buffer and the SDRAM_CTLR is the twice of the transfer rate in first execution mode, and other factors are identical.

Processor interface (PI 2002) now will be described.To above-mentioned described similar about first execution mode, preferably, SPBS comprises the temporary transient storage that data buffer helps the data between processor and the SDRAM to transmit with work to respective secondary.Not not matching between the rate of data signalling of this data buffer permission SPBS interface and the rate of data signalling of sdram interface.In the present embodiment, remain by the SDRAM_BURST_LENGTH register based on the pulse length of sdram interface and to define, but because the size of data word is the twice in first execution mode, therefore, be used for SPBS and correspondingly enlarged, to adapt with double-length based on sdram interface by the signal that MAD piece (2008) was sent to and sent out the data of SDRAM_CTLR.In other words, the data buffer of SPBS and the data transfer rate between the SDRAM_CTLR are the twices of the transfer rate in first execution mode.

Figure 21 shows the block diagram of exemplary portable phone electronic system.In the present embodiment, accumulator system (2101) provides interface to the one or more displays that are connected accumulator system (2101) (as LCD or OLED screen) (2112).In addition, accumulator system (2101) is to the part of external electronic device (2105), as primary processor (2106) and/or auxiliary processor (2107) configuration and activation control circuit (2102), transmit from SDRAM (2104) to the data between the display (2112) so that carry out.Although two displays have been shown among Figure 21, accumulator system (2101) can with still less or more display be connected.

Figure 22 illustrates in greater detail execution mode shown in Figure 21, comprises the 5th execution mode of accumulator system (2201).The functional block that below description is different from control circuit first execution mode, in the present embodiment.

Processor interface (PI 2202) comprises PPBS (2203) and a plurality of SPBS (2204).In this embodiment, SPBS is designated as the interface that can be programmed, this interface is programmed so that have the function of common SPBS when it is connected with the memory bus of auxiliary processor, or has the function of lcd driver interface when it is connected with one or more lcd screen.For convenience, this special SPBS is called as " SPBS_LCD " (2204) rather than " SPBS ".When being programmed to have the function of common SPBS, SPBS_LCD (2204) acts on the memory bus of corresponding auxiliary processor mutually in the identical mode of other SPBS in PI circuit (2202).

When organizeding the function of (as the LCD) driver interface that has display, SPBS_LCD (2204) provides control signal, data-signal and address signal, so that according to the display data transportation protocol the outside one or more displays of accumulator system (2201) are operated.In this case, the data buffer among the SPBS_LCD (2204) is with doing the temporary transient storage to the transmission of the data between the lcd screen (2219) to SDRAM (318).Data buffer allows the rate of data signalling between lcd screen (2219) and the SDRAM (2218) not match.In the REGS piece (2206), can be determined that SPBS_LCD (2204) has SPBS function or LCD interface driver function by the LCD_CONFIG register that primary processor is write.Provide a plurality of chip select signals to a plurality of lcd screens by the output port through accumulator system (2201), SPBS_LCD (2204) can operate a plurality of lcd screens.As exemplary embodiment, in the execution mode of describing, by providing independently chip select signal to each display, SPBS_LCD (2204) can support two lcd screens (2219).

When primary processor (2214) carries out access, except following order: " RAM reads ", " RAM writes ", " register read ", " register is write ", " downloading DMA transmits " and " uploading DMA transmits ", PPBS (2203) can also convert the memory bus control signal to " LCD writes " and order.

For register (REGS 2206), REGS (2206) comprises that the LCD_CONFIG register is to provide the relevant configuration information of operation with lcd screen (or other displays).This register comprises following territory." LCD enables " territory determines that SPBS_LCD (2204) has the SPBS function or has the function of LCD interface driver.This territory can also correspondingly enable (enable) or forbid (disable) LCD_CTLR (2220).If display is not to be connected with accumulator system (2201), then forbid LCD_CTLR (2220), and SPBS_LCD (2204) is configured to operate as SPBS.Alternatively, as the acquiescence register value, after accumulator system powered on, " LCD enables " territory was set to " forbidding ", but alternatively, default value can be " enabling ".If at least one lcd screen is connected with the SPBS_LCD interface in portable phone, then after powering on, primary processor writes " enabling " value to this register field, therefore makes LCD_CTLR (2220) to operate, and SPBS_LCD (2204) is configured to the lcd driver interface.

The LCD_CONFIG register further comprises following territory: " initial LCD address ", " initial SDRAM address " and " sending the data volume of LCD to ", these territories are the data transmission that are used for disposing from SDRAM to lcd screen (2219).When a plurality of lcd screens that are connected accumulator system (2201) or display, " LCD is cut apart the address " territory is used for the initial address of in whole LCD address space each lcd screen of definition.

Referring to instruction control unit (CMD_CTLR 2205), when CMD_CTLR (2205) received order " LCD writes " from primary processor (2214) by PPBS (2203), CMD_CTLR (2205) activated the data that LCD_CTLR (2220) comes to carry out the lcd screen from SDRAM to the accumulator system outside by the SPBS_LCD interface and transmits.When LCD_CTLR (2220) finished the data transmission, CMD_CTLR (2205) sent interrupt signal by PPBS (2203) to primary processor (2214), had finished data in order to indication and had transmitted.

For lcd controller (LCD_CTLR (2220)), LCD_CTLR (2220) is responsible for by SPBS_LCD (2204) interface, will be stored in the lcd screen (2219) that view data among the SDRAM (2218) exports the accumulator system outside to." LCD enables " territory of LCD_CONFIG register starts or forbids LCD_CTLR (2220).When being enabled, LCD_CTLR (2220) is subjected to the control of CMD_CTLR (2205), and CMD_CTLR (2205) is subjected to the control of primary processor (2214) by PPBS (2203).The LCD_CONFIG register comprises that LCD_CTLR (2220) is used for carrying out the information that the data from SDRAM (2218) to suitable lcd screen transmit.

For example, the indication cut apart relevant for the address of the data volume, initial SDRAM address, initial LCD address and two lcd screens that transmit of LCD_CONFIG register-stored.When being activated by CMD_CTLR (2205) " LCD writes " order, LCD_CTLR (2220) obtains and transmits relevant information from the LCD_CONFIG register, the data transmission is split as a plurality of pulses with SDRAM pulse coupling transmits.Cut apart the address with initial LCD based on the LCD address of two lcd screens, LCD_CTLR (2220) determines that further in two lcd screens which is used for receiving data.Transmit for each pulse, LCD_CTLR (2220) sends the access request of access SDRAM (2218) to MAD (2208).When licensed, LCD_CTLR (2220) carries out the pulse read operation of SDRAM (2218), and the data of reading is write in the data buffer of SPBS_LCD (2204), and SPBS_LCD (2204) writes into data the lcd screen of choosing.LCD_CTLR (2220) repetition pulse transmits, and transmits up to finishing whole data.

Referring to Figure 23, the operation of the 5th execution mode shown in Figure 22 will be described now.The embodiment of the process that the view data from SDRAM (2218) to lcd screen that shows Figure 23 transmits.In state (2301), primary processor (2214) is write " LCD enables " territory of LCD_CONFIG register, make LCD_CTLR (2220) start, and dispose SPBS_LCD (2204), and the data of configuration from SDRAM to lcd screen transmit as the LCD driving interface.In state (2302), primary processor (2214) sends " LCD writes " order, thereby makes CMD_CTLR (2205) activate LCD_CTLR (2220) at state (2303), transmits with the data of carrying out from SDRAM (2218) to lcd screen.According to the access permission agreement of MAD (2208), LCD_CTLR (2220) passes through MAD (2208) from SDRAM (2218) sense data, and data are write lcd screen, is sent to lcd screen from SDRAM (2218) up to all corresponding view data.At this moment, CMD_CTLR (2205) makes primary processor (2214) interrupt indicating and finishes data transmission (2310).

Especially, based on the value of LCD_CONFIG register, in state (2304), LCD_CTLR (2220) generates and is used for the SDRAM address that inceptive impulse transmits.In state (2305), LCD_CTLR (2220) is by MAD (2208) request SDRAM access.In state (2306), determine whether licensed SDRAM access of MAD (2208), in state (2307), LCD_CTLR (2220) is sent to lcd screen (2219) with data pulse from SDRAM (2218).In state (2308), determine whether the data pulse that is still waiting to carry out.If the pulse that is still waiting to transmit then generates the SDRAM address that next pulse transmits at state (2309) LCD_CTLR (2220).In case all suitable view data are sent to lcd screen from SDRAM (2218), in state (2310), CMD_CTLR (2205) makes primary processor (2214) interrupt indicating and finishes data transmission (2310).

Alternatively, when being under an embargo, LCD_CTLR (2220) is as unique connection the between SPBS_LCD (2204) and the MAD piece (2208).SPBS_LCD (2204) has the function of common SPBS interface, and does mutually in order to access SDRAM (2218) with MAD piece (2208), just as there not being LCD_CTLR (2220).

In this illustrative embodiments, although LCD_CTLR (2220) moves to lcd screen (2219) with data from SDRAM (2218), but, LCD_CTLR (2220) is moving to view data lcd screen (2219) before, can carry out the complicated more function that the view data among the SDRAM (2218) is treated to the view data of different-format alternatively.Although the detailed image treatment technology is not described at this, and it is required or desired that they may be defined as the user, but accumulator system (2201) can be carried out image processing, and the computing capability that need not exceedingly to use ppu just can be on display display image.

Although SPBS_LCD (2204) can be configured to be subjected to the common SPBS interface of auxiliary processor control by primary processor (2214), perhaps control the LCD interface of lcd screen (2219), but alternatively, in any special portable phone, SPBS_LCD (2204) is only limited to and uses a kind of in these two kinds of configurations.Therefore, alternatively, in case accumulator system (2201) is installed in the special device, as portable phone, SPBS_LCD (2204) or be connected with auxiliary processor muchly, or be connected (perhaps being connected) with any one device with one or more displays, and correspondingly after powering on, be configured by primary processor (2214), thereby when portable phone is in normal mode of operation, need in two kinds are joined, do not switch back and forth.

Figure 24 shows the 6th execution mode of accumulator system (2401).This exemplary accumulator system (2401) provide be used for one or more movably, the interface of the outside storage card (2412) that inserts, and primary processor is disposed and activation control circuit (2402), so that the data of carrying out between SDRAM (2404) and the storage card (2412) transmit.As example but be not limited to, movably storage card can be the card of memory stick card (memory stick card), smart media card (Smart media card), safe digital card (secure digital card), compact flash (CompatFlash card), multimedia card (MultiMedia card) and extended formatting.Although the embodiment that illustrates has described a storage card that is connected with accumulator system (2401), other execution modes can comprise a plurality of memory card interfaces and a plurality of card.

Storage card refers to movably data storage device, and this storage device can insert in the slot of destination apparatus, as portable phone slot or jack, therefore is connected with the destination apparatus electronic system.The data space that portable phone or other destination apparatus energy accessing memory card provide.Term " storage card " is called MC hereinafter.Because portable phone provides and MC machinery and compatible mutually electronically MC interface, portable phone can be accepted the insertion of MC.Accumulator system (2401) provides the electronics compatibility interface that can handle the MC bus protocol to MC, and the shell of portable phone comprises mechanical compatible slot and the connector that is used for MC.

Figure 25 shows the detailed diagram of accumulator system (2501), comprises the control circuit with MC (2519) interfaces.The functional block that below description is different from control circuit functional block in first execution mode, in the present embodiment.

Referring to PI circuit (2502), PI circuit (2502) comprising: PPBS (2503) and a plurality of SPBS (2504).In this embodiment, at least one PPBS (2503) has configurable interface.It can be programmed to play common SPBS effect or when the driver effect that is used for plaing when being connected with removable MC (2519) MC (2519) when being connected with the memory bus of auxiliary processor.This SPBS is called as " SPBS_MC (2504) " (2504).When being programmed to have common SPBS function, as similar to above-mentioned description about other SPBS, SPBS_MC (2504) acts on mutually with the memory bus of corresponding auxiliary processor.When being programmed to have the driver interface function of MC, SPBS_MC (2504) according to the MC data transfer protocol provide control signal, data-signal and address signal with in order to the operation MC (2519).

Data buffer among the SPBS_MC (2504) is as the temporary transient storage of the transmission of the data between SDRAM (2518) and the MC (2519) in this example.Data buffer allows the rate of data signalling between MC (2519) and the SDRAM (2518) not match.MC_CONFIG register in that primary processor (2514) can be write, the REGS piece (2506) determines that SPBS_MC (2504) has the interface driver function that the SPBS function still has MC.

When primary processor (2514) access PPBS (2503), except " RAM reads ", " RAM writes ", " register read ", " register is write ", " downloading DMA transmits " and " uploading DMA transmits " order, PPBS (2503) converts the memory bus control signal to other two orders " MC writes " and " MC reads ".

For REGS piece (2506), comprising in order to the MC_CONFIG register of the configuration information relevant with the operation of MC to be provided.The MC_CONFIG register comprises following territory." MC enables " territory of determining that SPBS_MC (2504) has SPBS function or MC interface driver function is provided.Correspondingly, this territory starts or forbids MC_CTLR (2520).If accumulator system (2501) is not used to provide the MC interface, then forbids MC_CTLR (2520), and SPBS_MC (2504) is configured to have the SPBS function.Alternatively, it is the default value of this register field after accumulator system (2501) has just powered on.If accumulator system (2501) is used to provide the MC interface, then after powering on, primary processor (2514) writes " enabling " value for " MC enables " territory of register, makes MC_CTLR (2520) start and SPBS_MC (2504) is configured to the driver interface of MC.Other territory as one or more " initial MC (2519) address " territory, " initial SDRAM (2518) address " territory and " be sent to/from the data volume of MC " territory, will be used for that transmission is configured to the data between SDRAM (2518) and the MC (2519).

About instruction control unit (CMD_CTLR 2505), when CMD_CTLR (2505) receives from " MC writes " or " MC reads " of primary processor (2514) order by PPBS (2503), CMD_CTLR (2505) activates MC_CTLR (2520), makes it pass through SPBS_MC (2504) interface data are sent to MC (2519) or are sent to SDRAM (2518) from MC (2519) from SDRAM (2518).After MC_CTLR (2520) finished the data transmission, CMD_CTLR (2505) sent inhibit signal to primary processor (2514) by PPBS (2503), had finished data with indication and had transmitted.

For MC controller (MC_CTLR 2520), MC_CTLR (2520) is responsible for being used for transmitting data between SDRAM (2518) and the MC (2519) by SPBS_MC (2504) interface.As previously discussed, " MC enables " territory of MC_CONFIG register makes MC_CTLR (2520) start or forbids.When being activated, MC_CTLR (2520) is subjected to the control of CMD_CTLR (2505), and this CMD_CTLR (2505) is subjected to the control of primary processor (2514) by PPBS (2503).The MC_CONFIG register comprises the information that the data between required SDRAM of execution of MC_CTLR (2520) (2518) and the MC (2519) transmit, as transmitting data volume, initial SDRAM (2518) address and initial MC (2519) address.

When being activated by " MC writes " or " MC reads " order from CMD_CTLR (2505), MC_CTLR (2520) obtains to transmit relevant information from the MC_CONFIG register, and data are transmitted a plurality of pulses that split into SDRAM (2518) pulse transmission coupling transmit, and for each pulse transmission, MC_CTLR (2520) sends the access request of access SDRAM (2518) to MAD.When licensed, for the write order of " MC writes ", MC_CTLR (2520) is the read pulse string data from SDRAM (2518), by the data buffer among the SPBS_MC (2504) this pulse data is write into MC (2519) then.If carry out the read command of " MC reads ", MC_CTLR (2520) is by the data buffer read pulse data from MC (2519) among the SPBS_MC (2504), and MC_CTLR (2520) writes into SDRAM (2518) with this pulse data then.MC_CTLR (2520) repetition pulse transmits, and transmits up to finishing whole data.

Alternatively, the MC interface of discussing except present embodiment and the relevant circuit, the control circuit of accumulator system also comprises the display interface device of discussing as the 5th execution mode and relevant circuit.

Referring to Figure 26, the operation of the 6th execution mode as shown in figure 25 will be described now.Figure 26 shows the embodiment of the data transfer procedure from SDRAM (2518) to MC (2519).In state (2601), primary processor (2514) is write the MC_CONFIG register makes MC_CTLR (2520) start, and configuration SPBS_MC (2504) is the driver interface of MC (2519), and the data between configuration SDRAM (2518) and the MC (2519) transmit.In state (2602), primary processor (2514) sends " MC writes " order, causes at state (2603) CMD_CTLR (2505) and activates MC_CTLR (2520) to carry out the data transmission from SDRAM (2518) to MC (2519).Value based on the MC_CONFIG register, MC_CTLR (2520) is split as the data among the SDRAM (2518) pulse data that mates with SDRAM (2518) pulse, and according to the access permission agreement of MAD piece (2508), each pulse of reading SDRAM (2518) by MAD piece (2508), and pulse write into MC (2519) (2604 to 2607).Particularly, in state (2604), MC_CTLR (2520) transmits first pulse and generates the SDRAM address.In state (2605), MC_CTLR sends access request to MAD piece (2508).In state (2606), determine whether MAD piece (2508) allows access.If MAD piece (2508) grand access, then executing state (2608) determines whether also to leave pulse.If also have pulse to keep, executing state (2609) then, MC_CTLR (2520) transmits to next pulse and generates the SDRAM address, and turns back to state (2605) and carry out.In case no longer leave pulse, then MC_CTLR (2520) has finished the data transmission, interrupts primary processor (2514) at state (2610) MC_CTLR (2520).

If (2519 transfer to SDRAM (2518) from MC with data in the opposite direction, its processing procedure is to above-mentioned similar, difference is, primary processor (2514) sends " MC reads " and orders to CMD_CTLR MC_CTLR (2520), and MC_CTLR (2520) carries out the data transmission of MC (2519) to SDRAM (2518).

When being under an embargo, MC_CTLR (2520) serves as being connected between SPBS_MC (2504) and the MAD piece (2508).SPBS_MC (2504) operates just as common SPBS interface, and does mutually in order to access SDRAM (2518) with MAD piece (2508), just as not having or not needing MC_CTLR (2520).

Further, although SPBS_MC (2504) can be configured to common SPBS interface by auxiliary processor control by primary processor (2514), or be the MC interface of control MC, but SPBS_MC (2504) is used for any concrete portable phone in any mode in these two kinds of configurations.Therefore, in case accumulator system (2520) is installed in the portable phone, SPBS_MC (2504) or for good and all or be fixedly attached on the auxiliary processor, perhaps as MC interface (or not using), and after powering on, correspondingly be configured, and when portable phone was in normal mode of operation, SPBS_MC (2504) can conversion back and forth in two kinds of configurations by primary processor (2514).

The 7th execution mode of accumulator system now will be described.As described in Figure 27, exemplary accumulator system (2702) comprises flash memories (2704) and control circuit (2703), wherein control circuit (2703) provides control signal to operate flash memories (2704), and this is similar to the description of first execution mode.Alternatively, main RAM (205) shown in Figure 2 does not exist in this exemplary accumulator system (2702).And referring to Figure 27, this embodiment shows the ppu of the energy access memory system (2702) in the external electronic device (2706), and wherein, this ppu is appointed as primary processor (2707).Alternatively, comprise that also other processors and relevant interface circuit are (for example, PBS).

Primary processor (2707) is connected with control circuit, as similar with reference to what discussed in first execution mode.Except access memory system (2702), primary processor (2707) can be set up volatile memory (SFRAM, DRAM or the like) and/or the nonvolatile memory (as flash memories, EEPROM, ROM or the like) in the external electronic device.

Figure 28 shows the functional block of the control circuit of present embodiment.The execution mode that illustrates comprise primary processor (2814), PI (2802), PPBS (2803), CMD_CTLR (2805), REGS piece (2806), BOOT_RAM (2807), FLASH_CTLR (2810), FMM (2811), DMA_CTLR (2812), BOOT_TLR (2813), on reply by cable and be signal (2816) and non-volatile N AND flash memories (2817).The functional block that below description is different from the control circuit of first execution mode.

As shown in figure 28, this exemplary execution mode does not comprise MAD piece (for example, shown in Figure 3 MAD (308)) or SDRAM_CTLR piece (for example, shown in Figure 3 SDRAM_CTLR (309)) alternatively.

About processor interface (PI2802), alternatively, PI piece (2802) only comprises a PBS, i.e. PPBS (2803), and do not comprise the SPBS piece alternatively.Difference between the PPBS of the PPBS (2803) of present embodiment and first execution mode is described below.

As in the first embodiment, the memory bus conversion of signals that PPBS (2803) is responsible for being used for primary processor (2814) becomes order, data and address information, then these information is sent to CMD_CTLR (2805).CMD_CTLR (2805) is the suitable part of activation control circuit then, with the relevant operation in the execute store system (2802).But the two kind orders of PPBS (2803) from the order that memory bus control signal conversion comes, promptly " downloading DMA transmits " and " uploading the DMA transmission " quilt " flash memory is read " and " flash memory write " replace or replenish.More specifically, the PPBS of present embodiment (2803) converts the memory bus control signal of primary processor (2814) to one or more following exemplary orders: " RAM reads ", " RAM writes ", " register read ", " register is write ", " flash memory is read " or " flash memory write " (and other orders alternatively), and send these orders to CMD_CTLR (2805).

If PI piece (2802) does not comprise the SPBS piece, then do not need to be provided with the mechanism that primary processor in first execution mode (2814) is controlled the reset signal of whereabouts auxiliary processor.But, still preferably be provided for the mechanism that control circuit is controlled the reset signal of whereabouts primary processor (2814) in the present embodiment.

Execution mode as shown in figure 28 also comprises the MC interface via additional PBS, and/or via the display interface device of additional PBS, to above-mentioned similar about what discussed in other execution modes.

Figure 29 shows the interlock circuit that resets, and alternatively, this interlock circuit that resets is included in the execution mode shown in Figure 28.The circuit that illustrates comprises primary processor (2912), control circuit (2901), BOOT_CTLR (2902), PI (2906), PPBS (2907), connects memory bus (2909), power-on reset signal (2914) and the reset signal (2910) of primary processor (2912) and PPBS (2907).As shown in figure 29, make BOOT_CTLR (2902) enter reset mode, make BOOT_CTLR (2902) keep the reset signal (2910) of the primary processor be asserted with this to asserting of electrification reset (2914).After electrification reset was stopped to assert, the various functions of BOOT_CTLR (2902) beginning initialization control circuit (2901) simultaneously, remained by the reset signal with primary processor (2912) and to assert, and make it remain reset mode.After finishing initialization task, BOOT_CTLR (2902) stops to assert to reset signal, with primary processor (2912) from the release that resets.

Figure 30 shows and interrupts relevant circuit, and alternatively, this circuit can be included in the execution mode shown in Figure 28.The circuit that illustrates comprises primary processor (3012) and CMD_CTLR (3001).Memory bus (3014), interrupt signal (3015), REGS piece (3004) and INT_RECORD register (3005) that control circuit comprises PI (3007), PPBS (3008), is connected with PPBS (3008) with primary processor (3012).

As shown in figure 30.If there is not auxiliary processor, just do not need to be used for the mechanism that auxiliary processor interrupts primary processor (3012), therefore there is not this mechanism alternatively.Still preferably be provided for the mechanism that CMD_CTLR (3002) interrupts primary processor (3012).The interrupt signal (3003) that CMD_CTLR (3002) generates directly sends to primary processor (3012) by PPBS (3008) and signal (3015) alternatively, and be recorded in readable and that remove, in the REGS piece (3004) interruption logging register by primary processor (3012), promptly in the INT_RECORD register (3005).

Referring to Figure 28, instruction control unit (CMD_CTLR 2805) is by the order (being different from first execution mode) of the primary processor (2814) of PPBS (2803) execution reception, and is as described below.

About " RAM reads " and " RAM writes " order, because accumulator system (2801) does not comprise SDRAM, so BOOT_RAM (2807) provides primary processor (2814) accessible accumulator system RAM storage space.When primary processor (2814) sent " RAM reads " or " RAM writes " order, CMD_CTLR (2805) allowed primary processor (2814) to transfer data to BOOT_RAM (2807) or transfer out data from it.

About " register read " and " register is write " order, the mode that CMD_CTLR (2805) is identical with above-mentioned first execution mode is carried out this two orders.

About " flash memory is read " and " flash memory write " order, the flash memory read command makes CMD_CTLR (2805) activate DMA_CTLR (2812) and carries out the data transmission of nand flash memory memory (2817) to BOOT_RAM (2807).The flash memory write order makes CMD_CTLR (2805) activate DMA_CTLR (2812) and carries out the data transmission of BOOT_RAM (2807) to nand flash memory memory (2817).

After being activated by CMD_CTLR (2805), the DMA_CONFIG register of DMA_CTLR (2812) from REGS piece (2806) obtains to transmit relevant data with data, as treats the address realm of mobile data amount (describing with the nand flash memory number of pages alternatively), initial nand flash memory logical page address (LPA) and BOOT_RAM " translator unit ".Therefore, sending " flash memory is read " or " flash memory write " order to CMD_CTLR (2805) before, primary processor (2814) is loaded into the DMA_CONFIG register with suitable value.After finishing order, CMD_CTLR (2805) sends interrupt signal to primary processor (2814) by PPBS (2803) interface.CMD_CTLR (2805) is not included in the data buffer that exists in first execution mode alternatively.

Preferably, the data of carrying out " flash memory is read " and " flash memory write " order transmit, make the data between BOOT_RAM (2807) and FLASH_CTLR (2810) PAGE_BUFF transmit, and the data between BOOT_RAM (2807) and the primary processor (2814) transmit simultaneously and occur, and DMA_CTLR (2812) and CMD_CTLR (2805) are in the side control data transmission separately of BOOT_RAM (2807).When in " flash memory write " operation, BOOT_RAM (2807) " transmitting the district " is full, and also unripe reception is during from the data of primary processor (2814), perhaps when BOOT_RAM (2807) in " flash memory is read " operation " transmit district " when empty, CMD_CTLR (2805) asserts that by PPBS (2803) data that " wait " signal supspends based on memory bus for primary processor (2814) transmit, and gets ready up to BOOT_RAM (2807) and proceeds the data transmission.

Now referring to register (REGS 2806), because accumulator system (2801) does not comprise the outside SDRAM of control circuit, therefore comprise and the register of the relevant information of this SDRAM of access, remove from REGS (2806) alternatively as SDRAM_BURST_LENGTH register and MAD_PRIORITY register.When carrying out " flash memory is read " or " flash memory write " order, rather than carry out as first execution mode in DMA between nand flash memory and the SDRAM when transmitting, the DMA_CONFIG register comprises the information that control circuit shown in Figure 28 uses.

Now referring to guiding RAM (BOOT_RAM 2807), except BOOT_CTLR (2813) and CMD_CTLR (2805), BOOT_RAM (2807) further is under the control of DMA_CTLR (2812) by connecting (2819).Behind electrification reset, BOOT_CTLR (2813) controls BOOT_RAM (2807) acquiescently, and as the initialized part of control circuit, BOOT_CTLR (2813) is loaded into BOOT_RAM (2807) with system boot code from nand flash memory memory (2817).BOOT_CTLR (2813) will transfer CMD_CTLR (2805) and DMA_CTLR (2812) to the control of BOOT_RAM (2807) then.In " RAM reads " or " RAM writes " operation, CMD_CTLR (2805) allow primary processor (2814) carry out from or the data of whereabouts BOOT_RAM (2807) transmit.In " flash memory is read " or " flash memory write " operation, CMD_CTLR (2805) allow primary processor (2814) carry out from or the data of whereabouts BOOT_RAM (2807) transmit, DMA_CTLR (2812) carries out the data transmission between the PAGE_BUFF among BOOT_RAM (2807) and the FLASH_CTLR (2810) simultaneously.

In " flash memory is read " and " flash memory write " operation, the zone of BOOT_RAM (2807) is conceptive " transmitting the district " that is designated as the data that flow between the PAGE_BUFF that is used for temporarily storing among primary processor (2814) and the FLASH_CTLR (2810).The address realm that transmits the district among the BOOT_RAM (2807) is by the DMA_CONFIG register definitions in the REGS piece (2806), and primary processor (2814) gave suitable value with this address realm programming before sending " flash memory is read " or " flash memory write " order.The purpose in the transmission district among the BOOT_RAM (2807) is to create to be used for the appointed area that data transmit, and makes existing data among the BOOT_RAM (2807), not to be capped as system boot code in data transmit.

About flash memories manager (FLASH_CTLR (2810)), FLASH_CTLR (2810) provides " flash memory _ termination " input signal to end the operation of FLASH_CTLR (2810) for DMA_CTLR (2812).When being asserted, " flash memory _ termination " signal makes and still still keeps the current state of operation by FLASH_CTLR (2810) shut-down operation nand flash memory memory.When being stopped when asserting, " flash memory _ termination " signal makes that FLASH_CTLR (2810) continues to operate the nand flash memory memory from the current state of operation.

About flash memory medium management device (FMM 2811), in the present embodiment, because accumulator system (2801) do not comprise SDRAM, so the FMM_P among the FMM (2811) needn't provide instruction to transmit data between FMM_RAM and the SDRAM.Thus, under normal mode of operation, the thin note record of FMM program code among the FMM_RAM and FMM algorithm is retained among the FMM_RAM.

About dma controller (DMA_CTLR (2812)), nand flash memory memory and the DMA between the SDRAM that DMA_CTLR in the present embodiment (2812) does not carry out in first execution mode transmit, but nand flash memory memory (2817) under execution " flash memory is read " or " flash memory write " order and the data transfer operation between the BOOT_RAM (2807).

More specifically, when CMD_CTLR (2805) activation DMA_CTLR (2812) carries out " flash memory is read " or " flash memory write " order, the DMA_CONFIG register of DMA_CTLR (2812) from REGS piece (2806) obtains the information relevant with this order, transmits the regional address scope as transmission data volume, initial nand flash memory logical page address (LPA) and the BOOT_RAM that preferably is described as the nand flash memory number of pages.DMA_CTLR (2812) generates the LPA of the nand flash memory page to be transmitted then, and corresponding to the address of BOOT_RAM each nand flash memory page, initial (2807).

For the DMA that finishes each nand flash memory page transmits DMA_CTLR (2812) access nand flash memory memory (2817) and BOOT_RAM (2807).DMA_CTLR (2812) is with the method access nand flash memory memory (2817) identical with first execution mode.For access BOOT_RAM (2807), DMA_CTLR (2812) directly reads or writes the transmission district of BOOT_RAM (2807).

The data of carrying out " flash memory is read " and " flash memory write " order alternatively transmit, make the data between the PAGE_BUFF among BOOT_RAM (2807) and the FLASH_CTLR (2810) transmit, and the data between BOOT_RAM (2807) and the primary processor (2814) transmit simultaneously and occur, and DMA_CTLR (2812) and CMD_CTLR (2805) are in one side control data transmission separately of BOOT_RAM (2807).When making in " flash memory is read " operation, when BOOT_RAM (2807) receives data for full and also unripe PAGE_BUFF from FLASH_CTLR (2810), DMA_CTLR (2812) stops to transmit from the data of the PAGE_BUFF to BOOT_RAM (2807) of FLASH_CTLR (2810), and assert that " flash memory _ termination " signal is to FLASH_CTLR (2810), to supspend the operation of nand flash memory, up to primary processor (2814) sense data from BOOT_RAM (2807).

When BOOT_RAM (2807) is empty under " flash memory write " operation, data between the PAGE_BUFF DMA_CTLR (2812) stops from BOOT_RAM (2807) to FLASH_CTLR (2810) transmit, and up to primary processor (2814) data are write into BOOT_RAM (2807).

Referring to Figure 31, the operation of the 7th execution mode shown in Figure 28 will be described now.Stop to assert similar to described in first execution mode of bootup process that back BOOT_CTLR (2813) carries out at electrification reset.After BOOT_CTLR (2813) finished bootup process, accumulator system (2801) entered " normal mode of operation ".

In the present embodiment, " normal mode of operation " refer to following situation: FMM (2811) initialization and can actuating logic to the nand flash memory address transition of physics, and primary processor (2814) discharges down from reset mode, with the executive system guidance code, and can give an order by PPBS (2803) and CMD_CTLR (2805), to transfer out pulse to BOOT_RAM (2807) transmission pulse and from it, register in the write and read REGS piece (2806) is with the operation of configuration/monitor storage systems (2801), the data that activate between nand flash memory memory (2817) and the BOOT_RAM (2807) transmit, and the interrupt signal that receives CMD_CTLR (2805) generation.

Under normal mode of operation, data being sent to and sending out primary processor (2814) by BOOT_RAM (2807) is normally used function.Therefore, in the operation of this detailed description " flash memory is read " and " flash memory write " order.

Figure 31 shows response " flash memory is read " order and the embodiment of the flash memory read procedure carried out.In state (3101), primary processor (2814) is to ordering relevant information, transmits the regional address scope and the data volume that is sent in the DMA_CONFIG register is programmed as initial nand flash memory LPA, BOOT_RAM.In state (3102), primary processor (2814) sends " flash memory is read " order, makes and activates DMA_CTLR at state (3103) CMD_CTLR (2805).In state (3103), CMD_CTLR (2805) asserts that the data that " wait " signal is supspended on the main processor memory bus transmit, and begin to be copied into BOOT_RAM (2807) up to the nand flash memory data simultaneously.Based on the value of DMA_CONFIG register, in state (3104), DMA_CTLR (2812) generates the first nand flash memory LPA and BOOT_RAM address, then, activates the nand flash memory page that FMM reads this LPA at state (3105).In state (3106), FMM (2811) at first actuating logic converts LPA to PPA to the conversion of physical address, and in state (3107) configuration with activate the nand flash memory page that FLASH_CTLR (2810) reads this PPA.

In state (3108), determine whether FLASH_CTLR (2810) enters idle condition (indication FLASH_CTLR (2810) finishes page read operation).In state (3109), the potential error that page data is proofreaied and correct with the ECC circuit is stored among the PAGE_BUFF.In state (3109), DMA_CTLR (2812) is sent to BOOT_RAM (2807) with page data from PAGE_BUFF.After the transmission district that determines BOOT_RAM (2807) is not sky, in state (3110), CMD_CTLR (2805) stops to assert to " wait " signal, so that allow primary processor (2814) to read BOOT_RAM (2807), reads BOOT_RAM (2807) at state (3111).

If the transmission Qu Weiman of BOOT_RAM (2807), then DMA_CTLR (2812) data that stop from PAGE_BUFF to BOOT_RAM (2807) transmit, and assert that " flash memory _ termination " signal supspends the read operation to nand flash memory memory (2817).In state (3112), determine whether that the page needs to transmit in addition.If the transmission Qu Weikong of BOOT_RAM (2807) then asserts that at state (3113) CMD_CTLR (2805) " wait " signal reads BOOT_RAM (2807) so that supspend primary processor (2814).DMA_CTLR (2812) generates the address of next LPA and BOOT_RAM.Each nand flash memory page repeats this process, transmits up to finishing " flash memory is read ".In case transmission is finished, executing state (3115), CMD_CTLR (2805) interruption primary processor (2814) is indicated and is finished the DMA transmission.

Figure 32 shows response " flash memory write " order and the embodiment of the flash memory write process carried out.In state (3201), to the order relevant information, the data volume that for example initial nand flash memory LPA, BOOT_RAM transmit the regional address scope and be transferred to the DMA_CONFIG register is programmed.In state (3202), primary processor (2814) sends " flash memory write " order.Respond this order, CMD_CTLR (2805) activates DMA_CTLR (2812) at state (3203).Simultaneously, begin data are write into BOOT_RAM (2807) at state (3204) primary processor (2814).After the transmission district that determines BOOT_RAM (2807) was not sky, in state (3205), DMA_CTLR (2812) began data are sent to PAGE_BUFF the FLASH_CTLR (2810) from BOOT_RAM (2807).

After the data of one page had been write into PAGE_BUFF, in state (3206), DMA_CTLR (2812) generated the first nand flash memory LPA based on the value of DMA_CONFIG register, and activated the nand flash memory page that FMM (2811) writes this LPA at state (3207).In state (3208), FMM (2811) actuating logic to convert LPA to PPA, disposes and activates the nand flash memory page that FLASH_CTLR (2810) writes this PPA at state (3209) to the address transition of physics then.

Simultaneously, primary processor (2814) continues data are write into BOOT_RAM (2807), so that DMA_CTLR (2812) is sent to PAGE_BUFF with data from BOOT_RAM (2807).If the transmission Qu Weiman of BOOT_RAM (2807), then CMD_CTLR (2805) asserts that " wait " signal supspends the write operation of primary processor (2814) to BOOT_RAM (2807).If the transmission Qu Weikong of BOOT_RAM (2807), then DMA_CTLR (2812) stops the data transmission from BOOT_RAM (2807) to PAGE_BUFF.Each nand flash memory page repeats this process, and whole up to finishing " flash memory write " transmits (by determining whether that at state (3211) page need transmit in addition).In state (3212), CMD_CTLR (2805) interrupts primary processor (2814) finishes the DMA transmission with indication.

In case be under the normal mode of operation, the accumulator system shown in Figure 28 (2801) no longer enters as " user model " under the first execution mode situation.Primary processor (2814) can continue or not continue to carry out the system boot code of BOOT_RAM (2807).In some portable phones, external electronic device can comprise primary processor (2814) volatile random access memory of access easily.In this case, in case under the processing normal mode of operation, and carry out the system boot code of BOOT_RAM (2807), primary processor (2814) will be stored in the some or all software program codes that are used for primary processor (2814) in the accumulator system (2801), be sent to the volatile random access memory in the external electronic device, turn to the software program code of carrying out wherein then.

In some portable phones, external electronic device further comprises nonvolatile memory, stores the ROM of the system boot code of primary processor as flash memories and being used to.In this case, system boot code is not stored in the nand flash memory memory of accumulator system alternatively, in case and primary processor discharge down from reset mode, can obtain this system boot code by the external electronic device primary processor.Therefore, BOOT_CTLR needn't be responsible for system boot code is advanced BOOT_RAM from the nand flash memory memory loads, but still the FMM program code is advanced FMM_RAM from the nand flash memory memory loads, and FMM and primary processor are discharged down from reset mode.

In this case, when primary processor was discharged under reset mode by BOOT_CTLR, primary processor was by obtaining the executive system guidance code from external electronic device rather than from accumulator system.And in this portable phone, external electronic device can directly be controlled resetting of primary processor.In this case, when BOOT_CTLR stopped to assert the reset signal of whereabouts primary processor, primary processor can be discharged down or not discharge from reset mode by external electronic device.Therefore, BOOT_CTLR send to primary processor reset signal may by primary processor as the instruction memory system whether initialization and being ready to serve the signal of the order of primary processor.

Although the present invention is open by some execution modes and embodiment, but, one of ordinary skill in the art be to be understood that the present invention extend to other replaceable execution modes of detailed disclosed execution mode, and/or use of the present invention and conspicuous modification or wherein be equal to replacement.In addition, the present invention shown and described a large amount of variants in detail, other modifications that belong to the scope of the invention for one of ordinary skill in the art based on above-mentioned openly be clearly.Can expect equally, can carry out the combination or the secondary combination of various special characteristics and execution mode aspect, but still belong to the scope of the invention.In sum, be to be understood that the various features of various disclosed execution modes and the aspect can make up or replace each other, so that form disclosed changing pattern of the present invention.Therefore the scope of the invention disclosed herein should not limited by above-mentioned disclosed specific implementations.

Claims (63)

1. wireless telephone stores device controller comprises:

The nonvolatile memory controller circuitry is configured to be coupled with nonvolatile memory;

The volatile memory controller circuitry is configured to be coupled with volatile memory;

The guide controller circuit is configured to and described nonvolatile memory controller circuitry coupling, and is used for user-defined boot code is read the into memory of Memory Controller from nonvolatile memory;

The first processor interface that comprises first reset signal, be configured to be coupled with the first radio telephone processor, wherein after described user-defined guidance code was read in the memory of described Memory Controller into, described Memory Controller discharged the described first radio telephone processor down from reset mode; And

Second processor interface that comprises second reset signal is configured to and the coupling of the second radio telephone processor, and wherein said second reset signal is configured at least in part by described first processor control.

2. wireless telephone stores device controller according to claim 1 further comprises:

First display interface device is configured to first display-coupled;

Second display interface device, be configured to second display-coupled, wherein said Memory Controller further is configured to partial response at least in the transmission request that the memory from described first processor receives, and display data is sent to described second display at least from described volatile memory.

3. wireless telephone stores device controller according to claim 1 further comprises: be configured to the interface with the mobile storage means coupling.

4. wireless telephone stores device controller according to claim 1 further comprises: be configured to the interface with the mobile memory card coupling.

5. wireless telephone stores device controller according to claim 1, wherein said user-defined guidance code are loaded in the special-purpose volatibility bootstrap memory.

6. wireless telephone stores device controller according to claim 1, wherein said nonvolatile memory comprises the nand flash memory memory.

7. wireless telephone stores device controller according to claim 1, wherein said nonvolatile memory comprises the AND flash memories.

8. wireless telephone stores device controller according to claim 1, wherein said volatile memory comprises the SDRAM memory.

9. wireless telephone stores device controller according to claim 1 further comprises:

Dma controller is configured to response via the request that the port of described first processor receives, and data are sent to described volatile memory from described nonvolatile memory; And

The ECC circuit is configured to the data of reading from described nonvolatile memory is carried out error-detecting and correction.

10. wireless telephone stores device controller according to claim 1 further comprises: the memory of storing user-defined flash memory medium management code.

11. wireless telephone stores device controller according to claim 1 further comprises: be used to be directed to Nonvolatile data and transmit data cached data buffer.

12. wireless telephone stores device controller according to claim 1, further comprise: error-detecting and correcting circuit, be used for do not have described first or the situation of the intervention of second processor under, detect and proofread and correct at least a portion data error in the data of from nonvolatile memory, reading.

13. wireless telephone stores device controller according to claim 1 further comprises: do not have described first or the situation of the intervention of second processor under, a plurality of page of data are copied to the circuit of volatile memory from nonvolatile memory.

14. wireless telephone stores device controller according to claim 1 further comprises: the second nonvolatile memory controller and the second volatile memory controller.

15. a method that is used for transmitting from wireless nonvolatile memory data comprises:

Behind electrification reset, use steering circuit to generate first address;

In the described wireless telephonic non-volatile flash memory memory of access, comprise the data of the data that are stored in described first address at least;

With access to storage in page-buffer;

Determine access to data be guidance code or flash memories management code;

If access to data are guidance codes, then these data are copied to the guiding random access memory from page-buffer; And

If access to data are flash memories management code, then these data are copied to flash memory storage management random access memory from page-buffer.

16. method according to claim 15, also comprise: when use is stored in the management of the described flash memories of flash memories management code initialization in the described flash memory storage management buffer, first modem processor is remained on reset mode.

17. method according to claim 16 also comprises: described modem processor is discharged down from reset mode.

18, method according to claim 17 also comprises: data channel is provided, carries out the guidance code that is stored in the described guiding random access memory by the described modulated processor of this data channel.

19. a wireless telephone stores device controller comprises:

First interface circuit is configured to be coupled with the radio telephone nonvolatile memory;

Second interface circuit is configured to be coupled with the radio telephone volatile memory;

The first processor interface is configured to and first radio telephone processor coupling, and makes the described first processor can the described radio telephone volatile memory of access;

Second processor interface is configured to be coupled with the second radio telephone processor; And

Controller circuitry is configured under the situation of the intervention that does not have the described first processor or second processor at least a portion data in the described radio telephone nonvolatile memory are copied to described radio telephone volatile memory.

20. wireless telephone stores device controller according to claim 19, wherein said control circuit are configured to data are write into the described radio telephone nonvolatile memory from the described first radio telephone processor.

21. wireless telephone stores device controller according to claim 19, wherein said volatile memory is a flash memories, and further comprises be configured to the circuit of carrying out the processing of flash memory storage management under the situation that does not have described first or second processor to get involved.

22. wireless telephone stores device controller according to claim 19, wherein when the described nonvolatile memory of access, described first telephone processor and described second processor provide logical address to described controller circuitry, and described controller circuitry is configured to the request of the response described first or second telephone processor, and actuating logic is to the address transition of physics when the described nonvolatile memory of access.

23. wireless telephone stores device controller according to claim 19, wherein said controller circuitry is configured to behind the electrification reset and before waking described first processor up, automatically performs user-defined task according to user-defined sequence, comprising:

Behind electrification reset, the flash memory medium management code is loaded into the local storage of flash memories manager circuit from described radio telephone nonvolatile memory; And

The data that are stored in the described radio telephone nonvolatile memory are carried out safety detection.

24. wireless telephone stores device controller according to claim 19, also comprise: be configured to the control circuit that boot code is sent to the volatibility bootstrap memory from described radio telephone nonvolatile memory, wherein said first processor interface also comprises and being configured to when the described boot code of at least a portion is transferred into described volatibility bootstrap memory, described first processor is remained on the reset signal of reset mode.

25. wireless telephone stores device controller according to claim 19, wherein, described radio telephone nonvolatile memory is configured to the page-mode access.

26. wireless telephone stores device controller according to claim 19 also comprises: error correction and testing circuit are configured to the error that detects and proofread and correct the data of reading from described radio telephone nonvolatile memory.

27. wireless telephone stores device controller according to claim 19, also comprise: the radio telephone nonvolatile memory, wherein said Memory Controller and described radio telephone nonvolatile memory are contained in the single equipment packages, be by described Memory Controller control wherein, stop unauthorized access described nonvolatile memory with this for the access of described radio telephone nonvolatile memory.

28. a method that is used for operate wireless phone memory circuit comprises:

Reset signal is stopped to assert;

Generate be stored in the radio telephone nonvolatile memory in the first corresponding address of vectoring information;

In described radio telephone nonvolatile memory, begin to read boot code from described first address;

The error-detecting of described boot code is provided;

If detect first error, then proofread and correct first error at least;

Described guidance code is loaded into volatile random access memory, if there is the guidance code of proofreading and correct, then described guidance code also comprises the guidance code of described correction;

Flash memories hypervisor code is loaded into flash memory storage management volatile memory from described radio telephone nonvolatile memory;

Make described flash memories hypervisor code carry out by the flash memories management circuit;

From the first radio telephone processor of reset mode release with described wireless telephone stores device which couple;

Make the described boot code of the described first radio telephone processor access; And

Make the second radio telephone processor access be stored in the code of described volatile memory.

29. method according to claim 28 also comprises:

Make the described first radio telephone processor that first group of information is loaded into the first memory configuration circuit at least;

Respond order and described first group of information at least in part from the described first radio telephone processor, program code is sent to described volatile memory from described nonvolatile memory, and the wherein said first radio telephone processor is carried out first program that is stored in described volatile memory at least.

30. method according to claim 28 also comprises:

Receive the display write order from the described first radio telephone processor;

Generate first volatile memory address; And

To be copied to the first radio telephone display from the initial data in described first address in the described volatile memory.

31. method according to claim 28 also comprises:

Display data is sent to second display of first telephone displays and second phone from volatile random access memory.

32. one kind is used for comprising being stored in or storing the into data execution method of its error calibration of wireless telephonic nonvolatile memory:

Reception is configured to first page data that is stored in the radio telephone nonvolatile memory, and described first page comprises user data that is stored in User Part and the idle data that is stored in idle component;

Generation is used for the page parity data of described first page data;

Described page parity data is stored in the described radio telephone nonvolatile memory, and wherein said idle data comprises thin numeration certificate and/or the system marks that is used for the nonvolatile memory management;

Generation is used for the parity data of described idle data, and it is stored in the described radio telephone nonvolatile memory;

From described radio telephone nonvolatile memory, read the parity data of described idle data; And

If necessary, use the parity information of described idle data, the idle data in the described radio telephone nonvolatile memory is carried out error-detecting and error correction.

33. method according to claim 32, wherein said parity data use reed-solomon code to calculate.

34. method according to claim 32, wherein said parity data use Hamming code to calculate.

35. a wireless telephone stores device system comprises:

First port is coupled with the radio telephone nonvolatile memory;

Second port circuit is coupled with the radio telephone volatile memory;

The first processor interface with the coupling of the first radio telephone processor, and is configured so that the described radio telephone volatile memory of described first processor access; And

Second processor interface is coupled with the second radio telephone processor;

One in the wherein said first processor and second processor is arranged to the control modulator-demodulator.

36. wireless telephone stores device controller according to claim 35, also comprise control circuit, be used for boot code is sent to the volatibility bootstrap memory from described radio telephone nonvolatile memory, wherein said first processor interface also comprises and being arranged to when the described boot code of at least a portion just is being transferred into described volatibility bootstrap memory, described first processor is placed the reset signal of reset mode.

37. wireless telephone stores device controller according to claim 35 also comprises memory card interface, it is configured to be coupled with mobile memory card.

38. wireless telephone stores device controller according to claim 35, also comprise be configured to memory stick card, smart media card, safe digital card, compact flash or multimedia card in the interface of one or more couplings.

39. wireless telephone stores device controller according to claim 35, also comprise the direct memory access (DMA) circuit, it is arranged to after transmitting beginning, need not described first or the intervention of described second processor, just data can be sent to described radio telephone volatile memory from described radio telephone nonvolatile memory.

40. wireless telephone stores device controller according to claim 35 also comprises memory access circuit, it is configured for optionally a plurality of requestors is permitted storage access.

41. a wireless telephone stores device system comprises:

First port is coupled with the radio telephone nonvolatile memory;

Second port circuit is coupled with the radio telephone volatile memory;

First device interface with the coupling of the first radio telephone processor, and is configured so that the described radio telephone volatile memory of described first processor access; And

Second device interface optionally can be configured to be connected with the second radio telephone processor or radio telephone display.

42. according to the described wireless telephone stores device of claim 41 controller, also comprise control circuit, described control circuit is sent to the volatibility bootstrap memory with boot code from described radio telephone nonvolatile memory, wherein, described first processor interface also comprises and being configured to when the described boot code of at least a portion just is being transferred into described guiding volatile memory, described first processor is remained in the reset signal of reset mode.

43. according to the described wireless telephone stores device of claim 41 controller, also comprise: memory card interface, it is configured to be coupled with mobile memory card.

44. according to the described wireless telephone stores device of claim 41 controller, also comprise the 3rd device interface, it is configured to and at least one radio telephone processor coupling.

45. according to the described wireless telephone stores device of claim 41 controller, also comprise the direct memory access (DMA) circuit, it is configured to after transmitting beginning, need not described first processor and get involved, just data can be sent to described radio telephone volatile memory from described radio telephone nonvolatile memory.

46. according to the described wireless telephone stores device of claim 41 controller, also comprise memory access circuit, it is configured to selectivity a plurality of requestors is permitted storage access.

47. according to the described wireless telephone stores device of claim 41 controller, also comprise memory component, it is used to store initial display address, initial volatile memory address and is used to indicate will have be sent to the indication of display from described volatile memory address for how many data.

48. a wireless telephone stores device control device comprises:

First port is configured to be coupled with the radio telephone nonvolatile memory;

Second port circuit is configured to and wireless telephonic modem processor coupling;

The volatibility bootstrap memory;

Guide controller is configured to guidance code is copied to described volatibility bootstrap memory from described radio telephone nonvolatile memory;

The direct memory access (DMA) controller is configured to the order of response from described modem processor, and data are copied to the volatibility bootstrap memory from described volatile memory;

Provide described modem processor to be used for reading the passage of bootstrap memory data.

49. according to the described wireless telephone stores device of claim 48 controller, wherein said first port further comprises error-detecting and correcting circuit, it is arranged to the error of the data that detection reads from described radio telephone nonvolatile memory, and proofreaies and correct the detected error of at least a portion.

50. according to the described wireless telephone stores device of claim 48 controller, wherein said first port further comprises data buffer, it is used to be in harmonious proportion not matching between the rate of data signalling of the rate of data signalling of described first port and described second port.

51. according to the described wireless telephone stores device of claim 48 controller, also comprise memory card interface, it is configured to be coupled with mobile memory card.

52. according to the described wireless telephone stores device of claim 48 controller, also comprise the 3rd port, it is configured to be connected with at least one radio telephone processor.

53. one kind wireless telephone stores device system operated the method for being made carbon copies with the data that prevent to be stored in the nonvolatile memory that can write, comprising:

At the write order of memorizer control circuit reception from the first radio telephone processor, wherein said write order indication is carried out write operation in wireless telephonic nonvolatile memory;

In first logical address of described memorizer control circuit reception,, will carry out write operation to data corresponding to described first logical address from the described first radio telephone processor;

Convert described first logical address to first physical address at wireless telephone stores device control circuit, wherein select described first physical address to avoid at least the first protection zone of radio telephone nonvolatile memory at least in part, to prevent that described first protection zone from being made carbon copies; And

Partly, the data of described first radio telephone processor indication are write into described first physical address in response to described write order.

54. according to the described method of claim 53, the wherein said first protection zone memory management code.

55. according to the described method of claim 53; wherein said first protection zone is by the code definition that is stored in the described radio telephone nonvolatile memory, and described code defines described first protection zone according to logical address, physical address or logical address and physical address.

56. according to the described method of claim 53, the wherein said first radio telephone processor provides modem feature.

57. a wireless telephone stores device controller comprises:

First interface circuit is configured to be coupled with the radio telephone nonvolatile memory;

The first processor interface is configured to be coupled with the first radio telephone processor;

First controller circuitry, with described first interface circuit and the coupling of first processor interface, and be configured to via described first processor interface and receive the logical address that is used for described radio telephone nonvolatile memory, and described logical address is converted to physical address, so that when access part code or data, the described first radio telephone processor need not to know first physical address that is used for described a part of code or data at least that is stored in the described phone nonvolatile memory, and wherein said physical address is stored in code or data in the described phone nonvolatile memory as access.

58. according to the described wireless telephone stores device of claim 57 controller, also comprise the flash memories management code that is stored in the computer-readable memory, wherein said flash memories management code does not rely on and will be coupled in the type of the first radio telephone processor of described first processor interface coupling.

59. according to the described wireless telephone stores device of claim 57 controller, also comprise the volatile memory interface, itself and described controller circuitry are coupled, and are configured to be coupled with volatile main memory.

60. according to the described wireless telephone stores device of claim 57 controller, also comprise second processor interface, itself and described control circuit are coupled, and are configured to be coupled with the second radio telephone processor.

61., also comprise according to the described wireless telephone stores device of claim 57 controller:

The volatibility bootstrap memory; And

Control circuit, be configured to boot code is sent to described volatile memory from the radio telephone nonvolatile memory, wherein said first processor interface further comprises and being configured to when the described boot code of at least a portion just is being transmitted into described volatibility bootstrap memory, described first processor is remained in the reset signal of reset mode.

62. according to the described wireless telephone stores device of claim 57 controller, also comprise described radio telephone nonvolatile memory, wherein said Memory Controller and described radio telephone nonvolatile memory are contained in the single device encapsulation, access for described radio telephone nonvolatile memory is controlled by described Memory Controller, prevents unauthorized access to described nonvolatile memory with this.

63. according to the described wireless telephone stores device of claim 57 controller, wherein said volatile memory is a flash memories, and comprises and be configured to the circuit that just can carry out the processing that flash memories is managed of going into that need not the described first radio telephone processor.

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