CN101039442A - Image processing method and device - Google Patents
Image processing method and device Download PDFInfo
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- CN101039442A CN101039442A CN 200610067870 CN200610067870A CN101039442A CN 101039442 A CN101039442 A CN 101039442A CN 200610067870 CN200610067870 CN 200610067870 CN 200610067870 A CN200610067870 A CN 200610067870A CN 101039442 A CN101039442 A CN 101039442A
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Abstract
The present invention provides a video processing method and device, wherein, a time signal related to a video signal which is to be inputted into a display is examined to determine the time signal being normal or not. If the time signal is abnormal, the display is prohibited to receive the synchronal signal related to the video signal. And with this invention, the input of the level synchronal signal and the vertical synchronal signal to the display is controlled; and the internal assembly such as electron gun can be avoided to be used in abnormal time point to prolong the service life of the display.
Description
Technical field
The present invention relates to a kind of image treatment method and device, particularly relate to a kind of image treatment method and device, can make display receive image source, and make the image treatment method and the device of the useful life prolongation of display in correct sequential with protection mechanism.
Background technology
Cathode ray tube (CRT, Cathode Ray Tube) display mainly is made up of electron gun, coil (Deflection coils), shielding (Shadow mask), phosphatization phosphor powder layer (phosphor) and glass screen five major parts.Its electron gun has the ability to get 20,000 5 kilovolt high pressure, produces the high energy electron light beam, and utilizes the correct guiding of shielding electron beam to beat phosphorus on glass screen, and produces bright spot.Simultaneously, the intensity by the control electron beam can produce different colors and brightness.When CRT monitor receive by computer display card or by the television signal reflector spread out of come image signal the time, electron gun can begin from the upper left corner of screen to scan to right-hand, from top to bottom strafe in regular turn then, scanning so repeatedly promptly constitutes the image that we see.
Please refer to Fig. 1, Fig. 1 is the schematic diagram of existing cathode-ray tube display.In Fig. 1, the electron gun 100 of cathode-ray tube display (CRT monitor) 100 produces laser beam 103, and laser beam 103 is correctly played representative R, the G on screen glass 107, the fluorescent material 109 of B by shielding 105 guidings, to produce R, G, the B bright spot that constitutes image frame.
Please refer to Fig. 2, Fig. 2 is the schematic diagram of existing cathode-ray tube display reception by image processing end output image signal.Digital image signal 201 exports analog image signal 214,215 and 216 to CRT monitor 202 after doing signal processing via the digital signal processor 203 of image processing end 200 and digital/analog converter 204,205 and 206 in regular turn.
And from the analog image signal 214 that received to CRT monitor 202 of digital image signal 201 of input, in 215 and 216 the process, its time sequence control, then the clock generator 207 by image processing end 200 produces, wherein the input signal of this clock generator 207 is digitized video clock signal 212 and the synchronizing signal 213 that is received according to digitized video end for process 200, and its output signal then provides a clock signal 208 to digital/analog converter respectively, provide a clock signal 210 to digital signal processor 203, provide a horizontal-drive signal (HSYNC) 209 and a vertical synchronizing signal (VSYNC) 211 to give the purposes of CRT monitor 202 as signal Synchronization.
When abnormal conditions take place synchronizing signal 213 or clock signal 212, might cause the output state of horizontal-drive signal 209 and vertical synchronizing signal 211 to remain on the high level or the frequency unsure state of logic always.And the output state of horizontal-drive signal 209 and vertical synchronizing signal 211 remains on the high level or the unsettled situation of frequency of logic always, it will make no matter (Horizontal Blanking Interval between horizontal clear area of Fig. 1 electron gun 101, HBI) or (Vertical Blanking Interval VBI) all continue to produce electron beam 103 in the vertical blank interval.And electron gun 101 continues to produce the consequences of electron beams 103, except electron gun 101 life-span reduction itself, also can make the useful life of fluorescent material 109 shorten.In simple terms, when synchronizing signal 213 or clock signal 212 generation abnormal conditions, just have an opportunity to make the useful life of CRT monitor 202 to shorten.
In addition, when synchronizing signal 213 or clock signal 212 are undesired, also can influence the abnormal clock signal 208 of clock generator 207 outputs to digital/analog converter 204,205 and 206, and the signal imitation image 214,215 and 216 of digital/analog converter 204,205 and 206 representative digital image signal 201 data that can under undesired sequential, export, this situation also can cause CRT monitor 202 to demonstrate unexpected pattern.
In view of this, the present invention proposes a kind of image treatment method and device, and it can make display receive image source in correct sequential, with effective protection display, and the useful life of display is prolonged.
Summary of the invention
Main purpose of the present invention takes place when unusual in synchronizing signal or clock signal for avoiding display, and display still continues running, and acts CRT monitor is an example, and above-mentioned situation promptly can cause the shortening of CRT monitor useful life.For achieving the above object; the present invention proposes a kind of image processing guard method; it comprises whether detection digital image signal relevant time signal, judgement time signal be unusual; and if time signal is unusual, then pinning the display reception synchronizing signal relevant with signal of video signal is the stable state of logical zero.Wherein, above-mentioned time signal can be a clock signal or the synchronizing signal of digitized video, and this clock signal or the synchronizing signal of digitized video are provided by digitized video source end institute.
In preferred embodiment of the present invention, said method also comprises the clock signal that detects long-time and high level, detect long-time and low level clock signal, and if detect between the clock signal of long-time and high level and long-time and low level clock signal both one of, judge that then clock signal is unusual.Whether the present invention also can directly detect synchronizing signal unusual.
In addition, if time signal is unusual, be the stable state of logical zero except that pinning the display reception synchronizing signal relevant with signal of video signal, the analog image signal that display is received is the lowest amplitude state of this analog image signal.And treat the time signal for just often, the synchronizing signal of then removing display and being received is the state of logical zero and recovers the pairing amplitude of analog image signal.
Similarly, for achieving the above object, the present invention also provides a kind of image processor, and it includes clock status checkout gear and output state control device.Wherein, the clock status checkout gear detects the time signal relevant with a signal of video signal, to export the first testing result signal.Whether one output state control device then receives the synchronizing signal relevant with signal of video signal, and unusual according to the first testing result signal judgement time signal, whether exports synchronizing signal to display with decision.
In preferred embodiment of the present invention, this image processor also comprises digital signal processor, clock generator, and digital/analog converter (differing, it is necessary to be decided to be).Wherein, digital signal processor is exported after receiving digital image signal and handling signal of video signal.Digital/analog converter receives the signal of video signal of being exported by digital signal processor, and after digital/analog converter carries out the digital-to-analog conversion to signal of video signal, exports the analog image signal to display.And clock generator receives outside clock signal or image synchronizing signal, to produce required clock signal in each unit and synchronizing signal.
In preferred embodiment of the present invention, the clock status checkout gear also comprises long-time and the low level clock detecting device, reach high level clock detecting device and clock status judgment means for a long time.Wherein, reach the low level clock detecting device for a long time and detect clock signal, after detecting long-time and low level clock signal, export one second testing result signal.Long-time and high level clock detecting device detects clock signal, with output one the 3rd testing result signal after the clock signal that detects long-time and high level.The clock status judgment means is according to the second testing result signal and the 3rd testing result signal, to judge the output first testing result signal.
Description of drawings
Fig. 1 is the schematic diagram of existing cathode-ray tube display.
Fig. 2 is the schematic diagram of existing cathode-ray tube display reception by the computer terminal output image signal.
Fig. 3 is the process step figure of preferred embodiment image treatment method of the present invention.
Fig. 4 is the schematic diagram of the image processor of preferred embodiment of the present invention.
Fig. 5 is the detailed circuit diagram of Fig. 4 clock status checkout gear of preferred embodiment of the present invention
Fig. 6 is the normal sequential chart of each node of Fig. 5 circuit diagram.
Fig. 7 is the detailed circuit diagram of the output state control device of preferred embodiment of the present invention.
The reference numeral explanation
100,441: display
103: laser beam
105: shielding
107: screen glass
109: fluorescent material
200: the image processing end
201,408,409,410,421: digital image signal
214,215,216,411,412,413: the analog image signal
203: digital signal processor
204,205,206,403,404,405: digital/analog converter
207,402: clock generator
208,210,414,418: clock signal
416: the first synchronizing signals
417: the second synchronizing signals
209,419: horizontal-drive signal
211,420: vertical synchronizing signal
212: clock signal
213: synchronizing signal
301～304: step
400: image processor
401: digital signal processor
407: the clock status checkout gear
406: the output state control device
415: the testing result signal
422: clock signal and synchronizing signal
501,504,701,702: with door
502: delayer
503: or door
506: the power initiation device
510: reach the low level clock detecting device for a long time
511～514: current source
520: reach the high level clock detecting device for a long time
521,522: comparator
530: NOR gate
531,533,536:PMOS transistor
532,534,535:NMOS transistor
541,542: resistance
551,552: electric capacity
555: inverter
Node1～6: node
VDD, VSS: voltage source
Embodiment
Please refer to Fig. 3, Fig. 3 is the process step figure of preferred embodiment image treatment method of the present invention.At first, detect the relevant time signal of signal of video signal with the desire input display, this time signal can for example be a clock signal that is provided by the image processing end, or follows the synchronizing signal of signal of video signal, and this is a step 301.
Then, whether the judgement time signal is unusual, wherein, with the time signal is that clock signal is an example, whether can pass through to detect this clock signal of long-time and high level, or detect long-time and low level this clock signal and come the judgement time signal unusual, this is a step 302.
If time signal is normal, then allow display to receive the level and the vertical synchronizing signal of corresponding signal of video signal, this is a step 303.If time signal be unusual, then pin the above-mentioned synchronizing signal of display reception, and this synchronizing signal is made as the state of logical zero, this is a step 304.
And after the step 303,304, the user can set up how long repeat step 301 at interval on their own, and the time signal detects to this with circulation, so that display operates under correct sequential.According to the embodiment of the invention, with the CRT monitor is example, its electron gun can be under the normal condition in the clock signal of following signal of video signal, allow to receive normal level and the vertical synchronizing signal of following signal of video signal, be that electron gun can not issue out light beam in unusual sequential, to increase the useful life of CRT monitor.
Please refer to Fig. 4, Fig. 4 is the schematic diagram of the image processor of preferred embodiment of the present invention.This image processor 400 is by digital signal processor 401, clock generator 402, digital/analog converter 403,404 and 405, clock status checkout gear 407, and output state control device 406 is formed.Wherein, clock status checkout gear 407 and output state control device 406 are the protective device in order to protection display 441.
When after digital image signal 421 is made signal processing via the image processor 400 with protective device, exporting display 441 to; digital image signal 421 is separated into the digital image signal 408,409 and 410 that has R, G, B information respectively by digital signal processor 401; 408,409 and 410 of this digital image signals are respectively by digital/analog converter 403,404,405, export display 441 to after digital image signal 408,409 and 410 is converted to analog image signal 411,412,413 respectively.
And digital signal processor 401, digital/analog converter 403,404 and 405, and the analog image signal 411 that received of display 441,412 and 413 work period, then the clock generator 402 by image processor 400 provides, wherein the input signal of clock generator 402 is for according to following the synchronizing signal 422 of digital image signal 421, and its output signal then provides digital signal processor 401 required clock signal 414 respectively, digital/analog converter 403, the clock signal 418 that 404 and 405 timely mitriform attitude checkout gears 407 are required, first synchronizing signal 416 and second synchronizing signal 417 that output state control device 406 is required.
Whether detect clock signal 418 as for 407 of clock status checkout gears unusual and export testing result signal 415 (clock status checkout gear 407 arbitrary clock signal that also can directly detect image synchronizing signal 422 or be produced by clock generator 402 wherein, in the present embodiment, clock status checkout gear 407 is set at and detects the clock signal 418 of giving digital/analog converter), and clock status checkout gear 407 offers output state control device 406 and digital/analog converter 403,404 and 405 respectively with testing result signal 415.Output state control device 406 and digital/analog converter 403,404 and 405 then are sent to the signal condition of display 441 according to these testing result signal 415 control first synchronizing signal 416, second synchronizing signal 417 and analog image signals 411,412 and 413 that it received.
Therefore; when 400 pairs of digital image signals 421 of image processor are done the signal of video signal processing; have arbitrary clock signal that the image processor 400 of display defencive function can be produced at the synchronizing signal 422 or the clock generator 402 of corresponding digital image signal 421 and (comprise clock signal 414; 418; first synchronizing signal 416 reaches and second synchronizing signal 417 detects; therefore image processor 400 and controlling level synchronizing signal 419 by this; vertical synchronizing signal 420 exports the signal condition of display 441 to, to avoid display 441 in abnormal level synchronizing signal 419; still continue running under vertical synchronizing signal 420 situations.Thus, therefore the useful life of display 441 can prolong.
Please also refer to Fig. 5, Fig. 6, Fig. 5 is the detailed circuit diagram of Fig. 4 clock status checkout gear of preferred embodiment of the present invention, and Fig. 6 is the normal sequential chart of each node of Fig. 5 circuit diagram.In Fig. 5, clock status checkout gear 407 is mainly by long-time and low level clock detecting device 510, reach high level clock detecting device 520 for a long time, and forms as the NOR gate 530 of clock status judgment means.
Wherein, long-time and low level clock detecting device 510 is by current source 511,512, resistance 541, electric capacity 551, comparator 521, and as the P-type mos field-effect transistor (hereinafter to be referred as the PMOS transistor) 531 of electronic switch, N type metal oxide semiconductor field-effect transistor (hereinafter to be referred as nmos pass transistor) 532, form.Wherein the current value of current source 512 is greater than the current value of current source 511.
520 of long-time and high level clock detecting devices are by current source 513,514, resistance 542, electric capacity 552, comparator 522, and as the PMOS transistor 533 of electronic switch, and nmos pass transistor 534 is formed.Wherein, the current value of current source 513 is greater than the current value of current source 514.In preferred embodiment of the present invention, the current value of current source 512,513 is 4 times of current source 511,514 current values.
In addition, clock status checkout gear 407 also includes power initiation device (POWER ON RESET) 506, delayer 502, and equally as electronic switch with door 501,504 or door 503, nmos pass transistor 535, PMOS transistor 536, and inverter 555.
The running of clock detecting device 407 each assembly, it is as follows then to underdraw: power initiation device 506 electric power startings and after after a while, the voltage of node Node1 just can become the high level of logic.And at this section in the period, the current potential of node Node5 can be discharged to the potential minimum of system via the nmos pass transistor 535 of conducting state, and (voltage source V SS provides, can be ground connection), and the current potential of node Node6 can charge to the maximum potential (voltage source V DD provides) of system via the PMOS transistor 536 of conducting state.When the signal level for the treatment of node Node1 was the high level of logic, then 536 in nmos pass transistor 535 and PMOS transistor presented closed condition.Therefore in the power initiation process, the voltage level of node Node5 is the potential minimum of system, and the voltage level of node Node6 is the maximum potential of system.
Because under clock signal 418 normal conditions, in one-period, node Node3 keeps time of high level can be much larger than keeping the low level time, therefore the voltage of node Node5 is when node Node3 is low level, current source 511 can be via PMOS transistor 531, resistance 541 to electric capacity 551 chargings, and when node Node3 was high level, current source 512 can discharge to Node5 via nmos pass transistor 532, resistance 541.Because node Node3 keeps the time of high level can be much larger than keeping the low level time, and the current value of current source 512 can be greater than the current value of current source 511, therefore just often, the current potential of node Node5 can maintain system's potential minimum (VSS) in clock signal 418.
And comparator 521 makes comparisons current potential and the reference voltage VREF1 of node Node5, and when node Node5 current potential during less than reference voltage VREF1 current potential, the output signal of comparator 521 is a low level.
Accordingly, in one-period, node Node4 keeps the low level time can be much larger than the time of keeping high level, and therefore under clock signal 418 normal conditions, node Node6 will maintain system's maximum potential (VDD).And comparator 522 makes comparisons current potential and the reference voltage VREF2 of node Node6, and when node Node6 current potential during less than reference voltage VREF2 current potential, the output signal of comparator 522 is a low level.In preferred embodiment of the present invention, the magnitude of voltage of reference voltage VREF2 and reference voltage VREF1 can be exemplified below all less than the magnitude of voltage of system voltage source VDD: reference voltage VREF1 is that 2.5V, reference voltage VREF2 are 1V, and voltage source V DD is 3.3V.Therefore, under clock signal 418 normal conditions, comparator 521 and 522 output level are all low level.
So the testing result signal 415 that NOR gate 530 is exported is high level.
In clock signal 418 is under the abnormal conditions, and when the voltage level of clock signal 418 continues to be pulled to system's potential minimum, the voltage level of interior nodes Node3 and node Node4 is all the low voltage level of logic during this period of time, so the voltage level of node Node5 can pass through PMOS transistor 531 with the current value of current source 511 and resistance 541 continues to electric capacity 551 chargings, till the voltage of node Node5 reaches system voltage source VDD or clock signal 418 recoveries normally.In charging process, when the voltage of node Node5 surpasses reference voltage VREF1, then the output meeting of comparator 521 changes high-voltage level into by low voltage level, and can become low level state by high level state by the testing result signal 415 that NOR gate 530 is exported.The i.e. representative of this variation detects clock signal 418 and is abnormal state.When clock signal 418 recovers normal and after after a while, the voltage level of node Node5 can return back to the voltage level of system earth end, and testing result signal 415 can become high level state by low level state again.And the voltage level of node Node6 can with power supply flow 513 current value by PMOS transistor 533, resistance 542 to electric capacity 552 chargings, but because the voltage level of Node6 has been the level of system voltage source VDD, so the output state of comparator 522 can not change.
When abnormal conditions takes place clock signal 418, and when clock signal 418 also continues to be lifted to system's maximum potential, the voltage level of interior nodes Node3 and node Node4 is all the high-voltage level of logic during this period of time, so the voltage level of node Node6 can pass through nmos pass transistor 534 with the current value of current source 514 and resistance 542 continues to the discharge of system earth end, till the voltage of node Node6 reaches the voltage or clock signal 418 recoveries normally of system earth end.In discharge process, when the voltage of node Node6 is lower than reference voltage VREF2, then the output meeting of comparator 522 changes high-voltage level into by low voltage level, and can become low level state by high level state by the testing result signal 415 that NOR gate 530 is exported.The i.e. representative of this variation detects clock signal 418 and is abnormal state.When clock signal 418 recovers normal and after after a while, the voltage level of node Node6 can return back to system's ceiling voltage (VDD), and testing result signal 415 can become high level state by low level state again.And the voltage level of node Node5 can flow 512 current value with power supply and discharges to the system earth end by nmos pass transistor 532, resistance 541, but because the voltage level of Node5 has been the voltage level of system earth end, so the output state of comparator 521 can not change.
When so abnormality takes place in clock signal 418, then the output state 415 of clock status checkout gear 407 also can change, when mitriform attitude checkout gear 407 detects clock signal 418 generation abnormal states at that time, its output state 415 changes the reaction time of its output state, can be decided by the current value of current source 511,514 and the capacitance of electric capacity 551 and 552.
Please refer to Fig. 7, Fig. 7 is the detailed circuit diagram of the output state control device of preferred embodiment of the present invention.Please also refer to Fig. 4, output state control device 406 by with door 701,702 as electronic switch.Receive first synchronizing signal 416 and testing result signal 415 respectively with A, the B of door 701 end, then receive the testing result signal 415 and second synchronizing signal 417 respectively with A, the B end of door 702.When clock signal 418 for just often, testing result signal 415 is a high level, then first synchronizing signal 416 and second synchronizing signal 417 respectively via with the computing of door 701,702, its output is respectively horizontal-drive signal 419 and vertical synchronizing signal 420 input to display.Otherwise then the output state of horizontal-drive signal 419 and vertical synchronizing signal 420 is changed to the low level state of logic.
It should be noted that, in limit levels synchronizing signal 419 and vertical synchronizing signal 420 outputs, the testing result signal 415 that clock status checkout gear 407 is exported also can be used for control figure/analog converter 403,404 and 405 and whether exports analog image signal 411,412 and 413.And this action meaning is, when clock signal 418 when being undesired, the display frame of may command display 441 avoids occurring unusual picture.
In sum, the invention provides a kind of image treatment method and device, the function that it has the protection display can be applicable to the image decoding device to display etc., and can limit the output of its horizontal-drive signal and vertical synchronizing signal.Therefore, by the present invention, the horizontal-drive signal of display and vertical synchronizing signal input Be Controlled, display interior assembly such as electron gun can be avoided being used under abnormal time point, so that the useful life of display is prolonged.
Claims (21)
1. image treatment method comprises:
Detect the relevant time signal of a signal of video signal of importing this display with desire;
Judge whether this time signal is unusual; And
If this time signal is unusual, forbid that then this display receives a synchronous signal relevant with this signal of video signal.
2. image treatment method as claimed in claim 1 also comprises:
Detect this time signal of long-time and high level;
Detect long-time and low level this time signal; And
If detect between this time signal of long-time and high level and long-time and low level this time signal both one of, judge that then this time signal is for unusual.
3. image treatment method as claimed in claim 1, wherein the clock signal that is provided by image source end, the synchronizing signal of following this signal of video signal are provided this time signal, and follow between the clock signal of synchronizing signal through being produced after the signal processing of this signal of video signal and select one.
4. image treatment method as claimed in claim 1 also comprises:
If this time signal is unusual,, also forbidding that this display receives this signal of video signal except that forbidding that this display receives this synchronizing signal; And
Treat this time signal for just often, then allow this display to forbid receiving this synchronizing signal.
5. image processor comprises:
Mitriform attitude checkout gear detects one first clock signal, to export one first testing result signal according to the clock status of this first clock signal for the moment; And
One output state control device receives one first synchronizing signal and one second synchronizing signal, and according to this first testing result signal, whether exports a horizontal-drive signal and a vertical synchronizing signal to this display with decision.
6. image processor as claimed in claim 5 also comprises:
One digital signal processor exports this display to after receiving and handle this digital image signal.
7. image processor as claimed in claim 5 also comprises:
One digital signal processor is exported after receiving and handle this digital image signal; And
One digital/analog converter receives this digital image signal of signal of being exported by this digital signal processor, after this digital/analog converter carries out the digital-to-analog conversion to this signal of video signal, to export an analog image signal to this display.
8. image processor as claimed in claim 5 also comprises:
One digital signal processor is exported after receiving and handle this digital image signal;
One digital/analog converter receives this digital image signal of signal of being exported by this digital signal processor, after this digital/analog converter carries out the digital-to-analog conversion to this digital image signal, to export an analog image signal to this display; And
One clock generator receives a second clock signal producing this first clock signal, one the 3rd clock signal, this first synchronizing signal, and this second synchronizing signal.
9. image processor as claimed in claim 5, wherein this clock status checkout gear also comprises:
One long-time and low level clock detecting device detects this first clock signal, with output one second testing result signal behind the long-time and high level state that detects this first clock signal;
One long-time and high level clock detecting device detects this first clock signal, with output one the 3rd testing result signal behind the long-time and low level state that detects this clock signal; And
Mitriform attitude judgment means according to this second testing result signal and the 3rd testing result signal, is exported this first testing result signal to judge for the moment.
10. image processor as claimed in claim 9 wherein should reach the low level clock detecting device for a long time and also comprise:
One first current source has first end and second end, and first end of this first current source couples one first voltage source;
One first electronic switch has grid, source electrode, and drain electrode, and the source electrode of this first electronic switch couples second end of this first current source;
One second electronic switch, have grid, source electrode, and drain electrode, grid and this clock signal of the grid of this second electronic switch and this first electronic switch are coupled to a first node, and the drain electrode of the drain electrode of this second electronic switch and this first electronic switch is coupled to a Section Point;
One second current source, have first end and second end, first end of this second current source couples the source electrode of this second electronic switch, and second end of this second current source and one second voltage source are coupled to one the 3rd node, and the current value of this second current source is greater than the current value of this first current source;
One first resistance has first end and second end, and first end of this first resistance couples this Section Point;
One first electric capacity has first end and second end, and first end of this first electric capacity and second end of this first resistance are coupled to one the 4th node, and second end of this first electric capacity couples the 3rd node; And
One first comparator, have first receiving terminal, second receiving terminal, and output, first receiving terminal of this first comparator couples one first reference voltage, second receiving terminal of this second comparator couples the 4th node, exportable this second testing result signal of the output of this first comparator.
11. image processor as claimed in claim 10 wherein should reach the high level clock detecting device for a long time and also comprise:
One the 3rd current source has first end and second end, and first end of the 3rd current source couples this first voltage source;
One the 3rd electronic switch has grid, source electrode, and drain electrode, and the source electrode of the 3rd electronic switch couples second end of the 3rd current source;
One quadrielectron switch, have grid, source electrode, and drain electrode, the grid of the grid of this quadrielectron switch and the 3rd electronic switch and this clock signal are coupled to one the 5th node, and the drain electrode of the drain electrode of this quadrielectron switch and the 3rd electronic switch is coupled to one the 6th node;
One the 4th current source, have first end and second end, first end of the 4th current source couples the source electrode of this quadrielectron switch, and second end of the 4th current source and one second voltage source are coupled to one the 7th node, and the current value of the 4th current source is less than the current value of the 3rd current source;
One second resistance has first end and second end, and first end of this second resistance couples the 6th node;
One second electric capacity has first end and second end, and first end of this second electric capacity and second end of this second resistance are coupled to one the 8th node, and second end of this second electric capacity couples the 8th node; And
One second comparator, have first receiving terminal, second receiving terminal, and output, first receiving terminal of this second comparator couples one second reference voltage, second receiving terminal of this second comparator couples the 8th node, exportable the 3rd testing result signal of the output of this second comparator.
12. image processor as claimed in claim 9, wherein this clock status judgment means also comprises:
One the 5th electronic switch, have first receiving terminal, second receiving terminal, and an output, first, second receiving terminal of the 5th electronic switch receives this second testing result signal and the 3rd testing result signal respectively, to judge this first testing result signal of output.
13. image processor as claimed in claim 10, wherein this first electronic switch is a P-type mos field-effect transistor, and this second electronic switch is a N type metal oxide semiconductor field-effect transistor, and this second voltage source is a ground connection.
14. image processor as claimed in claim 11, wherein the 3rd electronic switch is a P-type mos field-effect transistor, and this quadrielectron switch is a N type metal oxide semiconductor field-effect transistor, and this second voltage source is a ground connection.
15. image processor as claimed in claim 12, wherein the 5th electronic switch is a NOR gate.
16. image processor as claimed in claim 5, wherein this clock status checkout gear also comprises:
One delayer has first end and second end, and first end of this delayer couples this clock signal in one the 9th node;
One the 6th electronic switch has first receiving terminal, second receiving terminal, and output, and first receiving terminal of the 6th electronic switch couples the 9th node, and second receiving terminal of the 6th electronic switch and second end of this delayer are coupled to this protelum point;
One the 7th electronic switch has first receiving terminal, second receiving terminal, and output, and first receiving terminal of the 7th electronic switch couples this protelum point, and second receiving terminal of the 7th electronic switch couples the 9th node;
One long-time and low level clock detecting device detects the signal that the 6th electronic switch output is exported, and with after detecting long-time and low level this clock signal, exports one second testing result signal;
One long-time and high level clock detecting device detects this clock signal of signal that the 7th electronic switch output is exported, and with after this clock signal that detects long-time and high level, exports one the 3rd testing result signal; And
Mitriform attitude judgment means according to this second testing result signal and the 3rd testing result signal, is exported this first testing result signal to judge for the moment.
17. image processor as claimed in claim 16, wherein the 6th electronic switch be one or the door, the 7th electronic switch be one with the door.
18. image processor as claimed in claim 5, wherein this clock status checkout gear also comprises:
One delayer has first end and second end, and wherein first end of this delayer is one the 9th node;
One the 6th electronic switch has first receiving terminal, second receiving terminal, and output, and first receiving terminal of the 6th electronic switch couples the 9th node, and second receiving terminal of the 6th electronic switch and second end of this delayer are coupled to this protelum point;
One the 7th electronic switch has first receiving terminal, second receiving terminal, and output, and first receiving terminal of the 7th electronic switch couples this protelum point, and second receiving terminal of the 7th electronic switch couples the 9th node;
One the 8th electronic switch has first receiving terminal, second receiving terminal, and output, and first receiving terminal of the 8th electronic switch couples this clock signal, and the output of the 8th electronic switch couples the 9th node;
One power initiation device has an output, and second receiving terminal of the output of this power initiation device and the 8th electronic switch is coupled to 1 the 11 node;
One inverter has input and output, and the input of this inverter couples the 11 node;
One long-time and low level clock detecting device, have first, second, third, fourth end, five terminal, its first, second, third end couples output, one first voltage source, one second voltage source of the 6th electronic switch, the exportable one second testing result signal of its five terminal respectively;
One long-time and high level clock detecting device, detect this clock signal of signal that the 7th electronic switch output is exported, have first, second, third, fourth end, five terminal, its first, second, third end couples output, this first voltage source, this second voltage source of the 7th electronic switch, exportable one the 3rd testing result signal of its five terminal respectively;
Mitriform attitude judgment means according to this second testing result signal and the 3rd testing result signal, is exported this first testing result signal to judge for the moment
One the 9th electronic switch has grid, source electrode, and drain electrode, the grid of the 9th electronic switch, source electrode, drain electrode couple respectively this inverter output, this second voltage source, this reaches the 4th end of low level clock detecting device for a long time; And
The tenth electronic switch has grid, source electrode, and drain electrode, the grid of the tenth electronic switch, source electrode, drain electrode couple respectively this inverter input, this first voltage source, this reaches the 4th end of high level clock detecting device for a long time.
19. image processor as claimed in claim 18, wherein the 6th to the tenth electronic switch be respectively one or the door, one first with the door, one second with the door, a N type metal oxide semiconductor field-effect transistor, and a P-type mos field-effect transistor, this second voltage source is a ground connection.
20. image processor as claimed in claim 5, wherein this output state control device also comprises:
The 11 electronic switch, have first receiving terminal, second receiving terminal, and an output, first, second receiving terminal of the 11 electronic switch receives this horizontal-drive signal and this first testing result signal respectively, to judge this horizontal-drive signal of output; And
The 12 electronic switch, have first receiving terminal, second receiving terminal, and an output, first, second receiving terminal of the 12 electronic switch receives this vertical synchronizing signal and this first testing result signal respectively, to judge this vertical synchronizing signal of output.
21. an image processor comprises:
Mitriform attitude checkout gear detects one first synchronizing signal and one second synchronizing signal, to export one first testing result signal according to the clock status of this first synchronizing signal and this second synchronizing signal for the moment; And
One output state control device receives this first synchronizing signal and this second synchronizing signal, and according to this first testing result signal, whether exports a horizontal-drive signal and vertical synchronizing signal to a display with decision.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200610067870 CN101039442A (en) | 2006-03-13 | 2006-03-13 | Image processing method and device |
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| CN 200610067870 CN101039442A (en) | 2006-03-13 | 2006-03-13 | Image processing method and device |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102439974A (en) * | 2009-05-22 | 2012-05-02 | 株式会社巨晶片 | Video playback system and video playback method |
| CN109194459A (en) * | 2018-10-08 | 2019-01-11 | 惠科股份有限公司 | Data extraction method and device of transmission signal and storage medium |
| WO2019047956A1 (en) * | 2017-09-08 | 2019-03-14 | 中兴通讯股份有限公司 | Method and apparatus for improving image fluency |
-
2006
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102439974A (en) * | 2009-05-22 | 2012-05-02 | 株式会社巨晶片 | Video playback system and video playback method |
| WO2019047956A1 (en) * | 2017-09-08 | 2019-03-14 | 中兴通讯股份有限公司 | Method and apparatus for improving image fluency |
| CN109194459A (en) * | 2018-10-08 | 2019-01-11 | 惠科股份有限公司 | Data extraction method and device of transmission signal and storage medium |
| CN109194459B (en) * | 2018-10-08 | 2020-11-06 | 惠科股份有限公司 | Data extraction method and device of transmission signal and storage medium |
| US11283587B2 (en) | 2018-10-08 | 2022-03-22 | HKC Corporation | Data extraction method for transmission signal, device and computer readable storage medium |
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