CN101005246A - Three level double voltage reducing type semi-bridge converter - Google Patents
Three level double voltage reducing type semi-bridge converter Download PDFInfo
- Publication number
- CN101005246A CN101005246A CNA2007100193146A CN200710019314A CN101005246A CN 101005246 A CN101005246 A CN 101005246A CN A2007100193146 A CNA2007100193146 A CN A2007100193146A CN 200710019314 A CN200710019314 A CN 200710019314A CN 101005246 A CN101005246 A CN 101005246A
- Authority
- CN
- China
- Prior art keywords
- power
- power switch
- level
- diode
- switch pipe
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 230000008901 benefit Effects 0.000 abstract description 7
- 230000009467 reduction Effects 0.000 abstract description 6
- 238000011084 recovery Methods 0.000 abstract description 3
- 239000003990 capacitor Substances 0.000 description 11
- 238000010586 diagram Methods 0.000 description 7
- 230000001939 inductive effect Effects 0.000 description 7
- 230000009977 dual effect Effects 0.000 description 6
- 230000036541 health Effects 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 230000001052 transient effect Effects 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 2
- 238000001914 filtration Methods 0.000 description 2
- 230000003071 parasitic effect Effects 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- 102100029469 WD repeat and HMG-box DNA-binding protein 1 Human genes 0.000 description 1
- 101710097421 WD repeat and HMG-box DNA-binding protein 1 Proteins 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 238000005070 sampling Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
Images
Landscapes
- Inverter Devices (AREA)
Abstract
The invention includes reduction voltage circuit of first and third electrical level, and reduction voltage circuit of second and third electrical level. Un the two circuits, one end of the power switch tube is connected to external electrical source; and the other end is connected to three levels combined switch composed of two power diodes and one power switch connected to each other. Advantages of the invention are: small content of harmonic wave in output voltage, reduced switch frequency and wastage of switch, no need of large capacitance on DC side, applicable to condition of high voltage and large power, no straight through issue of bridge arm, and no issue of backward recovery of diode in switch tube. Moreover, the invention possesses simple structure and control scheme, and good dynamic properties of the invention.
Description
One, technical field
The present invention relates to a kind of inverter, relate in particular to a kind of dual buck half bridge inverter.
Two, background technology
The dual-buck inverter (Dual Buck Inverter---hereinafter to be referred as DBI) be a kind of novel inverter topology that occurs in recent years.Traditional relatively bridge-type inverter, DBI have the high reliability of no bridge arm direct pass and the distinct advantages of no switching tube parasitic diode reverse-recovery problems; The DBI that works under the half cycle pattern does not have the circulation existence, for high frequencyization and the high efficiency that realizes inverter simultaneously provides a kind of succinct approach, is a kind of topological structure that has very much researching value and development prospect.DBI has a lot of similar places with half-bridge inverter, hereinafter both is commonly referred to as the semi-bridge type inverter.The semi-bridge type inverter needs external positive and negative DC bus-bar voltage, and its amplitude surpasses the peaked twice of output voltage, and device voltage stress is big, and the direct voltage utilance is low; Brachium pontis can only export+and 1 and-1 binary states level, work in the bipolarity modulation system, brachium pontis output waveform harmonic content is big, needs high switching frequency and big filter.More than 2 also be the shortcoming of semi-bridge type inverter.
In recent years, multilevel converter obtains people's more concern and research.Because the restriction of device manufacturing technology, power semiconductor withstand voltage has certain limit.In high tension transformer, power tube series connection can be used, but because the inconsistent and switching transient of device parameters asynchronous, be difficult to realize all pressures of stable state and transient process, cause the overvoltage of indivedual power tubes, the reduction circuit reliability.Multilevel converter is to solve of power tube series connection problem than good method, and the voltage stress that its can guaranteed output pipe bears is clamped on the voltage of bus capacitor in stable state and transient process.
Three, summary of the invention
1, technical problem: the technical problem to be solved in the present invention is to improve the output of general DBI circuit, and a kind of dual-buck inverter that adopts multilevel converter is provided.
2, technical scheme:, the invention provides the three-level dual-buck half-bridge inverter of two kinds of technical schemes in order to solve above-mentioned technical problem.
The three-level dual-buck half-bridge inverter of first kind of scheme comprises the first three-level buck circuit and the second three-level buck circuit, in the first three-level buck circuit, the drain electrode of first power switch pipe is connected with the anode of extraneous power supply, the source electrode of first power switch pipe is connected with the negative electrode of first power diode, the anode of first power diode is connected with the negative electrode of the 3rd power diode, the anode of the 3rd power diode is connected with the negative terminal of extraneous power supply, between the source electrode access power diode of the 3rd power switch pipe, the grounded drain of the 3rd power switch pipe, a termination of first inductance are gone between the negative electrode of the source electrode of first power switch pipe and first power diode; In the second three-level buck formula circuit, the source electrode of second power switch pipe is connected with the negative terminal of extraneous power supply, the drain electrode of second power switch pipe is connected with the anode of the 4th power diode, the negative electrode of the 4th power diode is connected with the anode of second power diode, the negative electrode of second power diode is connected with the anode of extraneous power supply, between the drain electrode access power diode of the 4th power switch pipe, the source ground of the 4th power switch pipe, a termination of second inductance are gone between the anode of the drain electrode of second power switch pipe and the 4th power diode; The other end of first inductance links to each other with the other end of second inductance and inserts extraneous load circuit.In the technical program, the 3rd power diode, first power diode and the 3rd power diode constitute the one or three level unit switch, and the 4th power diode, second power diode and the 4th power diode constitute the two or three level unit switch.
The three-level dual-buck half-bridge inverter of second kind of scheme comprises the first three-level buck circuit and the second three-level buck circuit, in the first three-level buck circuit, the drain electrode of first power switch pipe is connected with the anode of extraneous power supply, the source electrode of first power switch pipe is connected with the negative electrode of the 3rd power diode, the anode of the 3rd power diode is connected with the source electrode of the 3rd power switch pipe, the grounded drain of the 3rd power switch pipe, the negative electrode of first power diode inserts between the negative electrode of the source electrode of first power switch pipe and the 3rd power diode, the anode of first power diode is connected with the negative terminal of extraneous power supply, and an end of first inductance is connected with the negative electrode of first power diode; In the second three-level buck formula circuit, the source electrode of second power switch pipe is connected with the negative terminal of extraneous power supply, the drain electrode of second power switch pipe is connected with the drain electrode of the 4th power switch pipe, the source electrode of the 4th power switch pipe is connected with the anode of the 4th power diode, the minus earth of the 4th power diode, the negative electrode of second power diode is connected with the anode of extraneous power supply, and a termination of the anode of second power diode and second inductance is gone between the drain electrode of the drain electrode of second power switch pipe and the 4th power switch pipe; The other end of first inductance links to each other with the other end of second inductance and inserts extraneous load circuit.With in first kind of identical the technical program of technical scheme two three level unit switches are arranged also, just difference to some extent on combining form.
The three-level dual-buck half-bridge inverter that the present invention adopts comprises two three-level buck circuit, its input side joint power circuit unit, its output side joint output filter capacitor and load circuit.This circuit has kept the characteristics of dual buck half bridge inverter: circuit does not have the danger of bridge circuit bridge arm direct pass; Freewheel current is passed through from power diode, and no switching device body diode reverse is recovered problem.By first fly-wheel diode in the dual buck half bridge inverter is replaced with the one or the three level unit switch that first power diode, the 3rd power diode, the 3rd power switch constitute, second fly-wheel diode replaces with the two or the three level unit switch that second power diode, the 4th power diode, the 4th power switch constitute.Because three level unit switches have two kinds of different combining forms, correspondence can obtain two kinds of different three-level dual-buck half-bridge inverter topologys.The brachium pontis output voltage of three-level dual-buck half-bridge inverter is the three-level pwm modulating wave, two level brachium pontis of dual buck half bridge inverter output relatively, and harmonic content greatly reduces, and required filter greatly reduces; Though increased device, but because the reduction of device voltage stress, can select the littler device of withstand voltage quota for use, mean the reduction of break-over of device resistance and parasitic capacitance, whole on-state loss not necessarily increases, and the devices switch frequency can reduce, make the devices switch loss to reduce, add the reduction of filtering device loss, inverter efficiency can not reduce, but has realized reducing and more excellent output characteristic of machine volume weight.The entire circuit structure is also uncomplicated.Controlling schemes is also simpler: adopt hysteresis current PWM control, guarantee that inverter circuit does not need any bias current when operate as normal, overcome the voltage distortion that inductive current intermittently causes simultaneously.Hysteresis current control scheme also has series of advantages such as inherent current limliting, dynamic property is fast, realization is simple.Because brachium pontis output becomes two level by three level, also make win three level unit switches or the two or three level unit switch in the afterflow stage of working, the pressure drop that is added on first, second inductance reduces, inductive current change rate diminishes, the switching frequency that the ring modulation that stagnates obtains reduces, keep the sense value that switching frequency can reduce filter inductance, this also helps to reduce inductance.
3, beneficial effect: the present invention has following advantage: (1) has kept the little advantage of the harmonic wave of output voltage content of three-level converter own, helps to reduce filter, can reduce the switching frequency of PWM modulating part simultaneously, reduces switching loss, raises the efficiency; (2) compare with the semi-bridge type inverter, DC side need not all to press big electric capacity, and power device voltage stress is low, makes the switching device of middle low power applicable to high pressure, powerful occasion; (3) inherited the advantage that two buck circuit do not have bridge arm direct pass, no switching tube body diode reverse recovery problem; (4) entire circuit structure and controlling schemes are all comparatively simple, are easy to realize; (5) the PWM modulation circuit unit adopts hysteresis current control scheme, and inverter dynamic performance is good.
Four, description of drawings
Fig. 1 is three-level dual-buck half-bridge inverter topology 1 schematic diagram of the present invention; Label title among Fig. 1: 1. power circuit; 2. the first three-level buck circuit; 3. filter capacitor and load circuit; 4. the second three-level buck circuit; Fig. 2 is three-level dual-buck half-bridge inverter topology 2 schematic diagrames of the present invention; Label title among Fig. 2: 1. power circuit; 2. the first three-level buck circuit; 3. filter capacitor and load circuit; 4. the second three-level buck circuit;
Fig. 3 is the dual buck half bridge inverter electrical block diagram;
Fig. 4 is three-level dual-buck half-bridge inverter topology 1 each switch mode schematic diagram of the present invention;
Fig. 5 is the main waveform schematic diagram of three-level dual-buck half-bridge inverter topology 1 of the present invention;
Fig. 6 is three-level dual-buck half-bridge inverter topology 2 each switch mode schematic diagram of the present invention;
Fig. 7 is the control block diagram that three-level dual-buck half-bridge inverter of the present invention adopts.
Main designation in the above-mentioned accompanying drawing: Cf---output filter capacitor; D1～D2---power diode; D1～d2---the drive waveforms of power switch tube S 1～S4; Ir---Voltage loop output is current reference; Il1---filter inductance L1 current waveform; Il2---filter inductance L2 current waveform; L1～L2---filter inductance; R---load impedance; S1～S4---power switch pipe; Ud---inverter input DC bus-bar voltage; Uo---inverter output voltage.
Five, embodiment
Embodiment 1: as shown in Figure 1, the three-level dual-buck half-bridge inverter of present embodiment comprises the first three-level buck circuit 2 and the second three-level buck circuit 4, in the first three-level buck circuit 2, the drain electrode of first power switch tube S 1 is connected with the anode of extraneous power supply Ud1, the source electrode of first power switch tube S 1 is connected with the negative electrode of the first power diode D1, the anode of the first power diode D1 is connected with the negative electrode of the 3rd power diode D3, the anode of the 3rd power diode D3 is connected with the negative terminal of extraneous power supply Ud2, the source electrode access power diode D1 of the 3rd power switch tube S 3, between the D3, the grounded drain of the 3rd power switch tube S 3, a termination of first inductance L 1 are gone between the negative electrode of the source electrode of first power switch tube S 1 and the first power diode D1; In the second three-level buck formula circuit 4, the source electrode of second power switch tube S 2 is connected with the negative terminal of extraneous power supply Ud2, the drain electrode of second power switch tube S 2 is connected with the anode of the 4th power diode D4, the negative electrode of the 4th power diode D4 is connected with the anode of the second power diode D2, the negative electrode of the second power diode D2 is connected with the anode of extraneous power supply, the drain electrode access power diode D2 of the 4th power switch tube S 4, between the D4, the source ground of the 4th power switch tube S 4, a termination of second inductance L 2 are gone between the anode of the drain electrode of second power switch tube S 2 and the 4th power diode D4; The other end of first inductance L 1 is connected with the other end of second inductance L 2, and is connected to by filter capacitor C
fWith a load R filter capacitor that constitutes in parallel and an end of load circuit 3, filter capacitor C
fConnect simultaneously with the other end of load R " ".Extraneous power supply Ud1, Ud2 is in series and series connection point ground connection.The first three-level buck circuit 2 is nursed one's health work when the half period of inverter output cathode electric current, the second three-level buck formula circuit 4 is nursed one's health work when the half period of inverter output negative pole electric current.
Embodiment 2: as shown in Figure 2, the three-level dual-buck half-bridge inverter of present embodiment, comprise the first three-level buck circuit 2 and the second three-level buck circuit 4, in the first three-level buck circuit 2, the drain electrode of first power switch tube S 1 is connected with the anode of extraneous power supply Ud1, the source electrode of first power switch tube S 1 is connected with the negative electrode of the 3rd power diode D3, the anode of the 3rd power diode D3 is connected with the source electrode of the 3rd power switch tube S 3, the grounded drain of the 3rd power switch tube S 3, the negative electrode of the first power diode D1 inserts between the negative electrode of the source electrode of first power switch tube S 1 and the 3rd power diode D3, the anode of the first power diode D1 is connected with the negative terminal of extraneous power supply Ud2, and an end of first inductance L 1 is connected with the negative electrode of the first power diode D1; In the second three-level buck formula circuit 4, the source electrode of second power switch tube S 2 is connected with the negative terminal of extraneous power supply Ud2, the drain electrode of second power switch tube S 2 is connected with the drain electrode of the 4th power switch tube S 4, the source electrode of the 4th power switch tube S 4 is connected with the anode of the 4th power diode D4, the minus earth of the 4th power diode D4, the negative electrode of the second power diode D2 is connected with the anode of extraneous power supply Ud1, and a termination of the anode of the second power diode D2 and second inductance L 2 is gone between the drain electrode of the drain electrode of second power switch tube S 2 and the 4th power switch tube S 4; The other end of first inductance L 1 is connected with the other end of second inductance L 2, and is connected to by filter capacitor C
fWith a load R filter capacitor that constitutes in parallel and an end of load circuit 3, filter capacitor C
fConnect simultaneously with the other end of load R " ".Extraneous power supply Ud1, Ud2 is in series and series connection point ground connection.The first three-level buck circuit 2 is nursed one's health work when the half period of inverter output cathode electric current, the second three-level buck formula circuit 4 is nursed one's health work when the half period of inverter output negative pole electric current.
The principle of above-mentioned two embodiment is: at output current greater than zero positive half cycle, the almost conducting always of the 3rd power switch tube S 3, the 4th power switch tube S 4 is almost ended always, first power switch tube S, 1 PWM modulation, second power switch tube S 2 is not worked, and this moment, the output level of inverter bridge was+Ud or 0; At the minus negative half period of output current, the 3rd power switch tube S 3 almost always by, almost conducting always of the 4th power switch tube S 4, do not work by first power switch tube S 1, second power switch tube S, 2 PWM modulation, this moment, the output level of inverter bridge was-Ud or 0.Output has comprised+1,0 ,-1 ternary level before three-level dual-buck half-bridge inverter topology 1 and topological 2 filtering, and the part of devices voltage stress is reduced to input voltage.Because hysteresis current control has the advantage of inherent current limliting, high accuracy and fast dynamic response, can guarantee that three- level buck circuit 2,4 does not need any bias current when operate as normal, overcome the voltage distortion that inductive current intermittently causes simultaneously, guarantee that inverter moves under greater efficiency and frequency.Thereby in three-level dual-buck half-bridge inverter employing hysteresis current PWM controlling schemes of the present invention.
Below Figure 1 shows that main circuit structure, narrate the concrete operation principle and the operation mode of three-level dual-buck half-bridge inverter topology 1 of the present invention in conjunction with Fig. 4, corresponding circuit key waveforms is seen accompanying drawing 5:
At output current io greater than zero positive half cycle [t0～t1]:
2 work of the first three-level buck circuit, the second three-level buck circuit 4 is not worked: first power switch tube S 1PWM modulation, the 3rd power switch tube S 3 keeps conducting, and second power switch tube S 2, the 4th power switch tube S 4 are ended.This stage circuit switches between following two operation modes:
Operation mode I: shown in Fig. 4 (a), the S1 conducting, the current i L1 of inductance L 1 is linear to rise, and S3, D1 branch road no current pass through.The inverter bridge output level is Ud.
Operation mode II: shown in Fig. 4 (b), S1 turn-offs, and inductive current iL1 is from S3, the afterflow of D1 branch road, and linearity descends.The inverter bridge output level is 0.
2. output current io is born by forward and switches [t1～t2]:
The first three- level buck circuit 2 and 4 alternations of the second three-level buck circuit comprise operation mode I, II, III and operation mode IV, V, VI.Duration in this stage is shorter.
Operation mode III: shown in Fig. 4 (c), S1, S3 all end, and the current i L1 of inductance L 1 is from D1, the afterflow of D3 branch road, and linearity descends.The inverter bridge output level is-Ud.
3. at the minus negative half period of output current io [t2～t3]:
The first three-level buck circuit 2 is not worked, 4 work of the second three-level buck circuit: second power switch tube S 2PWM modulation, and the 4th power switch tube S 4 keeps conducting, and first power switch tube S 1, the 3rd power switch tube S 3 are ended.This stage circuit switches between following two operation modes:
Operation mode IV: shown in Fig. 4 (d), the S2 conducting, the current i L2 of inductance L 2 is linear to rise, and S4, D4 branch road no current pass through.The inverter bridge output level is-Ud.
Operation mode V: shown in Fig. 4 (e), S2 turn-offs, and inductive current iL2 is from S4, the afterflow of D4 branch road, and linearity descends.The inverter bridge output level is 0.
4. output current io just switches [t3～t4] by negative sense:
The second three- level buck circuit 4 and 2 alternations of the first three-level buck circuit comprise operation mode I, II, III and operation mode IV, V, VI.Duration in this stage is shorter.
Operation mode VI: shown in Fig. 4 (f), S2, S4 all end, and the current i L2 of inductance L 2 is from D2, D4 afterflow, and linearity descends.The inverter bridge output level is Ud.
Figure 2 shows that main circuit structure, narrate the concrete operation principle and the operation mode of three-level dual-buck half-bridge inverter topology 2 of the present invention in conjunction with Fig. 6 below:
At output current io greater than zero positive half cycle:
2 work of the first three-level buck circuit, the second three-level buck circuit 4 is not worked: first power switch tube S 1PWM modulation, the 3rd power switch tube S 3 keeps conducting, and second power switch tube S 2, the 4th power switch tube S 4 are ended.This stage circuit switches between following two operation modes:
Operation mode I: shown in Fig. 6 (a), the S1 conducting, the current i L1 of inductance L 1 is linear to rise, and S3, D3 branch road no current pass through.The inverter bridge output level is Ud.
Operation mode II: shown in Fig. 6 (b), S1 turn-offs, and inductive current iL1 is from S3, the afterflow of D3 branch road, and linearity descends.The inverter bridge output level is 0.
2. output current io switches by forward is negative:
The first three- level buck circuit 2 and 4 alternations of the second three-level buck circuit comprise operation mode I, II, III and operation mode IV, V, VI.Duration in this stage is shorter.
Operation mode III: shown in Fig. 6 (c), S1, S3 all end, and the current i L1 of inductance L 1 is from the afterflow of D1 branch road, and linearity descends.The inverter bridge output level is-Ud.
3. at the minus negative half period of output current io:
The first three-level buck circuit 2 is not worked, 4 work of the second three-level buck circuit: second power switch tube S 2PWM modulation, and the 4th power switch tube S 4 keeps conducting, and first power switch tube S 1, the 3rd power switch tube S 3 are ended.This stage circuit switches between following two operation modes:
Operation mode IV: shown in Fig. 6 (d), the S2 conducting, the current i L2 of inductance L 2 is linear to rise, and S4, D4 branch road no current pass through.The inverter bridge output level is-Ud.
Operation mode V: shown in Fig. 6 (e), S2 turn-offs, and inductive current iL2 is from S4, the afterflow of D4 branch road, and linearity descends.The inverter bridge output level is 0.
4. output current io is just switched by negative sense:
The second three- level buck circuit 4 and 2 alternations of the first three-level buck circuit comprise operation mode I, II, III and operation mode IV, V, VI.Duration in this stage is shorter.
Operation mode VI: shown in Fig. 6 (f), S2, S4 all end, and the current i L2 of inductance L 2 is from the D2 afterflow, and linearity descends.The inverter bridge output level is Ud.
For realizing above operation principle, adopt controlling schemes as shown in Figure 7: among the figure, ir is that Voltage loop output is current reference.The control of power switch tube S 3 and S4 is very simple, employing open loop control, at current reference greater than zero positive half cycle, make the 3rd power switch tube S 3 conducting always, the 4th power switch tube S 4 is ended always, the minus negative half period of voltage reference ends the 3rd power switch tube S 3 always, and the 4th power switch tube S 4 conducting always gets final product.Power switch tube S 3, S4 whole power frequency period all a switch once, the dead band influence can be ignored.First power switch tube S 1 and second power switch tube S 2 adopt hysteresis current PWM control, are the electric currents of two inductance L 1 and L2 of sampling respectively, obtain the driving of first power switch tube S 1 and second power switch tube S, 2 pipes behind two hysteresis comparators respectively.
Claims (2)
1, a kind of three-level dual-buck half-bridge inverter, comprise the first three-level buck circuit (2) and the second three-level buck circuit (4), it is characterized in that, in the first three-level buck circuit (2), the drain electrode of first power switch pipe (S1) is connected with the anode of extraneous power supply, the source electrode of first power switch pipe (S1) is connected with the negative electrode of first power diode (D1), the anode of first power diode (D1) is connected with the negative electrode of the 3rd power diode (D3), the anode of the 3rd power diode (D3) is connected with the negative terminal of extraneous power supply, the source electrode access power diode (D1 of the 3rd power switch pipe (S3), D3) between, the grounded drain of the 3rd power switch pipe (S3), a termination of first inductance (L1) are gone between the negative electrode of the source electrode of first power switch pipe (S1) and first power diode (D1); In the second three-level buck formula circuit (4), the source electrode of second power switch pipe (S2) is connected with the negative terminal of extraneous power supply, the drain electrode of second power switch pipe (S2) is connected with the anode of the 4th power diode (D4), the negative electrode of the 4th power diode (D4) is connected with the anode of second power diode (D2), the negative electrode of second power diode (D2) is connected with the anode of extraneous power supply, the drain electrode access power diode (D2 of the 4th power switch pipe (S4), D4) between, the source ground of the 4th power switch pipe (S4), a termination of second inductance (L2) are gone between the anode of the drain electrode of second power switch pipe (S2) and the 4th power diode (D4); The other end of first inductance (L1) links to each other with the other end of second inductance (L2) and inserts extraneous load circuit (3).
2, a kind of three-level dual-buck half-bridge inverter, comprise the first three-level buck circuit (2) and the second three-level buck circuit (4), it is characterized in that, in the first three-level buck circuit (2), the drain electrode of first power switch pipe (S1) is connected with the anode of extraneous power supply, the source electrode of first power switch pipe (S1) is connected with the negative electrode of the 3rd power diode (D3), the anode of the 3rd power diode (D3) is connected with the source electrode of the 3rd power switch pipe (S3), the grounded drain of the 3rd power switch pipe (S3), the negative electrode of first power diode (D1) inserts between the negative electrode of the source electrode of first power switch pipe (S1) and the 3rd power diode (D3), the anode of first power diode (D1) is connected with the negative terminal of extraneous power supply, and an end of first inductance (L1) is connected with the negative electrode of first power diode (D1); In the second three-level buck formula circuit (4), the source electrode of second power switch pipe (S2) is connected with the negative terminal of extraneous power supply, the drain electrode of second power switch pipe (S2) is connected with the drain electrode of the 4th power switch pipe (S4), the source electrode of the 4th power switch pipe (S4) is connected with the anode of the 4th power diode (D4), the minus earth of the 4th power diode (D4), the negative electrode of second power diode (D2) is connected with the anode of extraneous power supply, and a termination of the anode of second power diode (D2) and second inductance (L2) is gone between the drain electrode of the drain electrode of second power switch pipe (S2) and the 4th power switch pipe (S4); The other end of first inductance (L1) links to each other with the other end of second inductance (L2) and inserts extraneous load circuit (3).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100193146A CN100459402C (en) | 2007-01-15 | 2007-01-15 | Three level double voltage reducing type semi-bridge converter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100193146A CN100459402C (en) | 2007-01-15 | 2007-01-15 | Three level double voltage reducing type semi-bridge converter |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101005246A true CN101005246A (en) | 2007-07-25 |
| CN100459402C CN100459402C (en) | 2009-02-04 |
Family
ID=38704182
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007100193146A Expired - Fee Related CN100459402C (en) | 2007-01-15 | 2007-01-15 | Three level double voltage reducing type semi-bridge converter |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100459402C (en) |
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101860244A (en) * | 2010-04-09 | 2010-10-13 | 南京航空航天大学 | Half-period control method of single-phase diode-clamped five-level half-bridge inverter |
| CN101902143A (en) * | 2010-07-26 | 2010-12-01 | 南京航空航天大学 | Capacitor-clamped three-level dual-buck half-bridge inverter |
| CN101552555B (en) * | 2009-04-30 | 2011-01-26 | 淮海工学院 | Buck voltage balance converter |
| CN101552568B (en) * | 2008-12-17 | 2011-10-19 | 南京航空航天大学 | Half-cycle control tri-level single-inductor dual buck half bridge inverter and control method thereof |
| CN103825455A (en) * | 2014-02-11 | 2014-05-28 | 南京航空航天大学 | Single-inductor dual-buck full-bridge inverter |
| CN104022664A (en) * | 2014-06-24 | 2014-09-03 | 苏州弘鹏新能源有限公司 | Four-level double-Buck inverter |
| CN104935279A (en) * | 2015-06-24 | 2015-09-23 | 许继电源有限公司 | Three-level switch power amplifier |
| CN105978379A (en) * | 2016-05-10 | 2016-09-28 | 福州大学 | Mixed control algorithm of double-buck half-bridge inverter |
| CN106452154A (en) * | 2016-12-06 | 2017-02-22 | 福州大学 | Magnetic integration three-level dual-buck type half-bridge inverter and working mode thereof |
| CN108448925A (en) * | 2018-04-04 | 2018-08-24 | 南京航空航天大学 | The two-way inverter of high reliability high energy efficiency dual input |
| CN110445220A (en) * | 2019-08-22 | 2019-11-12 | 中车青岛四方车辆研究所有限公司 | Charger module and circuit |
| CN114977859A (en) * | 2022-06-27 | 2022-08-30 | 中国矿业大学(北京) | Three-phase N-module cascading type unidirectional energy flow multi-level frequency converter and control method |
| CN115800785A (en) * | 2022-11-09 | 2023-03-14 | 国网湖北省电力有限公司宜昌供电公司 | Single-phase three-level four-port clamping type energy storage inverter |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3851092B2 (en) * | 2001-01-31 | 2006-11-29 | 三洋電機株式会社 | Half-bridge inverter circuit |
| CN1195349C (en) * | 2002-10-21 | 2005-03-30 | 南京航空航天大学 | Lay loop current control type double dropping half bridge convertor |
| US6798676B2 (en) * | 2003-01-24 | 2004-09-28 | Cotek Electronic Industrial Co., Ltd. | Inverter for changing direct current to alternating current |
| CN100431255C (en) * | 2003-05-12 | 2008-11-05 | 南京航空航天大学 | Main circuit topology of tri-electrical-level double-dropping type semi-bridge inverter and control method thereof |
| US6838925B1 (en) * | 2003-10-07 | 2005-01-04 | American Power Conversion Corporation | Three level inverter |
-
2007
- 2007-01-15 CN CNB2007100193146A patent/CN100459402C/en not_active Expired - Fee Related
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101552568B (en) * | 2008-12-17 | 2011-10-19 | 南京航空航天大学 | Half-cycle control tri-level single-inductor dual buck half bridge inverter and control method thereof |
| CN101552555B (en) * | 2009-04-30 | 2011-01-26 | 淮海工学院 | Buck voltage balance converter |
| CN101860244A (en) * | 2010-04-09 | 2010-10-13 | 南京航空航天大学 | Half-period control method of single-phase diode-clamped five-level half-bridge inverter |
| CN101902143A (en) * | 2010-07-26 | 2010-12-01 | 南京航空航天大学 | Capacitor-clamped three-level dual-buck half-bridge inverter |
| CN101902143B (en) * | 2010-07-26 | 2012-05-23 | 南京航空航天大学 | Capacitor-clamped three-level dual-buck half-bridge inverter |
| CN103825455A (en) * | 2014-02-11 | 2014-05-28 | 南京航空航天大学 | Single-inductor dual-buck full-bridge inverter |
| CN103825455B (en) * | 2014-02-11 | 2017-01-04 | 南京航空航天大学 | The double Buck full-bridge inverter of single inductance |
| CN104022664A (en) * | 2014-06-24 | 2014-09-03 | 苏州弘鹏新能源有限公司 | Four-level double-Buck inverter |
| CN104935279B (en) * | 2015-06-24 | 2018-09-14 | 许继电源有限公司 | A kind of tri-level switch power amplifier |
| CN104935279A (en) * | 2015-06-24 | 2015-09-23 | 许继电源有限公司 | Three-level switch power amplifier |
| CN105978379A (en) * | 2016-05-10 | 2016-09-28 | 福州大学 | Mixed control algorithm of double-buck half-bridge inverter |
| CN105978379B (en) * | 2016-05-10 | 2018-07-17 | 福州大学 | A kind of hybrid algo-rithm of double buck half-bridge inverters |
| CN106452154A (en) * | 2016-12-06 | 2017-02-22 | 福州大学 | Magnetic integration three-level dual-buck type half-bridge inverter and working mode thereof |
| CN108448925A (en) * | 2018-04-04 | 2018-08-24 | 南京航空航天大学 | The two-way inverter of high reliability high energy efficiency dual input |
| CN110445220A (en) * | 2019-08-22 | 2019-11-12 | 中车青岛四方车辆研究所有限公司 | Charger module and circuit |
| CN114977859A (en) * | 2022-06-27 | 2022-08-30 | 中国矿业大学(北京) | Three-phase N-module cascading type unidirectional energy flow multi-level frequency converter and control method |
| CN115800785A (en) * | 2022-11-09 | 2023-03-14 | 国网湖北省电力有限公司宜昌供电公司 | Single-phase three-level four-port clamping type energy storage inverter |
| CN115800785B (en) * | 2022-11-09 | 2024-02-13 | 国网湖北省电力有限公司宜昌供电公司 | Single-phase three-level four-port clamp type energy storage inverter |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100459402C (en) | 2009-02-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100459402C (en) | Three level double voltage reducing type semi-bridge converter | |
| CN101902143B (en) | Capacitor-clamped three-level dual-buck half-bridge inverter | |
| CN100596011C (en) | Coupling inductance dual-buck full bridge inverter | |
| CN100433526C (en) | Three-level double step-down full bridge inverter | |
| CN101902142B (en) | Diode clamping five-level dual buck half-bridge inverter | |
| CN100438303C (en) | Five-level double step-down full bridge inverter | |
| CN101515763B (en) | Series-parallel connection output tri-level half-bridge inverter and half period hysteresis control method thereof | |
| CN101483397B (en) | Diode clamping tri-level dual decompression type semi-bridge inverter | |
| CN101667789B (en) | Inverter circuit used for solar energy photovoltaic grid connection and device thereof | |
| CN105281361B (en) | A kind of five-level double step-down combining inverter | |
| CN103001484B (en) | The modulator approach of low auxiliary voltage zero voltage switch Bridgeless Power Factor Corrector | |
| CN103178739B (en) | Zero-voltage transition full-bridge non-isolated photovoltaic grid-connected inverter | |
| CN101980437A (en) | Five-level grid-connected inverter | |
| CN206807288U (en) | A kind of three level boost system with one power | |
| CN105186912B (en) | A kind of non-isolated full-bridge grid-connected inverter of two-stage type | |
| CN100433527C (en) | Double step-down inverter | |
| CN103391001A (en) | High-gain DCDC converter for MPPT link of photovoltaic inverter | |
| CN101662231A (en) | Realization method of zero-current switch of diode neutral point clamped inverting circuit | |
| CN103825455B (en) | The double Buck full-bridge inverter of single inductance | |
| CN101499733B (en) | Z source semi-bridge inverter | |
| CN100488019C (en) | Double smoothing inductance full-bridge inverter main circuit | |
| CN206226317U (en) | The integrated three-level dual-buck half-bridge inverter of magnetic | |
| CN101478230B (en) | Passive soft on-off circuit used for inversion bridge | |
| CN201178380Y (en) | Three-transistor step-up/step-down circuit with wide voltage inputting range for interconnected electricity power | |
| CN201393178Y (en) | Z-source half-bridge inverter |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C17 | Cessation of patent right | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090204 Termination date: 20100222 |