CN101005030A - Preparation method of gate oxide layer - Google Patents

Preparation method of gate oxide layer Download PDF

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CN101005030A
CN101005030A CN 200610001049 CN200610001049A CN101005030A CN 101005030 A CN101005030 A CN 101005030A CN 200610001049 CN200610001049 CN 200610001049 CN 200610001049 A CN200610001049 A CN 200610001049A CN 101005030 A CN101005030 A CN 101005030A
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substrate
oxide layer
active area
dielectric
layer
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CN100431109C (en
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陈中怡
朱志勋
周志文
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Promos Technologies Inc
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Abstract

A method for preparing gate oxide layer includes forming at least two grooves in substrate, forming active region between two grooves. Then, a dielectric block is formed in the trench, and the upper surface of the dielectric block is not aligned with the upper surface of the substrate. Then, a doping process is performed to implant nitrogen-containing dopant into the substrate of the active region, wherein the concentration of the nitrogen-containing dopant in the substrate at the center of the active region is higher than that at the edge of the active region. Then, a thermal oxidation process is performed to form a gate oxide layer on the upper surface of the substrate in the active region. The nitrogen-containing dopant can inhibit the thermal oxidation reaction rate, so as to prevent the gate oxide thickness at the edge of the active region from being smaller than that at the center of the active region.

Description

栅氧化层之制备方法Preparation method of gate oxide layer

技术领域technical field

本发明涉及一种栅氧化层之制备方法，特别涉及一种可避免主动区域边缘之栅氧化层厚度变薄的制备方法。The invention relates to a preparation method of a gate oxide layer, in particular to a preparation method which can avoid thinning of the thickness of the gate oxide layer at the edge of an active region.

背景技术Background technique

公知之半导体工艺为了避免电子元件相互干扰而产生短路现象，一般采用硅局部氧化法(local oxidation of silicon；LOCOS)或浅槽隔离法(shallow trench isolation；STI)电气隔离晶片上之电子元件。由于局部氧化法形成之场氧化层占据晶片较大面积，且会伴随形成鸟嘴现象，因此目前先进半导体工艺多采用浅槽隔离法电气隔离电子元件。In order to avoid short circuits caused by mutual interference of electronic components, the known semiconductor technology generally adopts local oxidation of silicon (LOCOS) or shallow trench isolation (STI) to electrically isolate electronic components on the wafer. Since the field oxide layer formed by the local oxidation method occupies a large area of the wafer and will be accompanied by the formation of a bird's beak phenomenon, the shallow trench isolation method is often used to electrically isolate electronic components in advanced semiconductor processes.

图1表示公知之浅槽隔离10。该浅槽隔离10围绕主动区域20，且栅氧化层14形成于该主动区域20之硅基板12的表面。随着半导体元件不断缩小化，该主动区域20之宽度亦随之缩小，因而该主动区域20之边缘处的应力变大。这样，较大的应力会造成氧化反应速率减缓，以致该栅氧化层14在该主动区域20之边缘处的厚度小于在该主动区域20之中心处的厚度，故容易产生漏电问题。FIG. 1 shows a known shallow trench isolation 10 . The shallow trench isolation 10 surrounds the active region 20 , and the gate oxide layer 14 is formed on the surface of the silicon substrate 12 of the active region 20 . As semiconductor devices continue to shrink, the width of the active region 20 also shrinks, so the stress at the edge of the active region 20 increases. In this way, the greater stress will cause the oxidation reaction rate to slow down, so that the thickness of the gate oxide layer 14 at the edge of the active region 20 is smaller than that at the center of the active region 20 , so leakage problems are likely to occur.

发明内容Contents of the invention

本发明之主要目的是提供一种栅氧化层的制备方法，其利用自我对准之掺杂工艺将含氮掺质植入主动区域之硅基板内，并通过含氮掺质抑制氧化反应之速率，来避免主动区域边缘处之栅氧化层的厚度小于主动区域中心处之栅氧化层的厚度。The main purpose of the present invention is to provide a method for preparing a gate oxide layer, which uses a self-aligned doping process to implant nitrogen-containing dopants into the silicon substrate in the active region, and suppresses the oxidation reaction rate through nitrogen-containing dopants , to prevent the thickness of the gate oxide layer at the edge of the active region from being smaller than the thickness of the gate oxide layer at the center of the active region.

为达到上述目的，本发明提出一种利用含氮掺质抑制氧化反应速率之栅氧化层的制备方法。本发明一实施例之制备方法首先形成具有至少两个开口之遮罩层于基板上，再形成沟槽于该开口下方之基板中，相邻两条沟槽之间形成主动区域。之后，形成介电区块于该沟槽之中，该介电区块之上表面不对齐该基板之上表面。接着，进行掺杂工艺，将含氮掺质植入该主动区域之基板中。然后，进行热氧化工艺以形成栅氧化层于该主动区域之基板的上表面。In order to achieve the above object, the present invention proposes a method for preparing a gate oxide layer that utilizes nitrogen-containing dopants to suppress the oxidation reaction rate. In the manufacturing method of an embodiment of the present invention, a mask layer having at least two openings is firstly formed on a substrate, and then trenches are formed in the substrate below the openings, and an active region is formed between two adjacent trenches. After that, a dielectric block is formed in the trench, and the upper surface of the dielectric block is not aligned with the upper surface of the substrate. Next, a doping process is performed to implant nitrogen-containing dopants into the substrate of the active region. Then, a thermal oxidation process is performed to form a gate oxide layer on the upper surface of the substrate in the active region.

由于该介电区块之上表面不对齐该基板之上表面，因此该主动区域中心处之基板内的含氮掺质浓度高于该主动区域边缘处。此外，该含氮掺质可抑制用以形成该栅氧化层之热氧化反应速率，因此该主动区域中心处的氧化反应速率低于该主动区域边缘处，如此后续之热氧化工艺即可避免该主动区域边缘处之栅氧化层厚度小于主动区域中心处之栅氧化层厚度的情况发生。Since the upper surface of the dielectric block is not aligned with the upper surface of the substrate, the nitrogen-containing dopant concentration in the substrate at the center of the active region is higher than that at the edge of the active region. In addition, the nitrogen-containing dopant can suppress the thermal oxidation reaction rate used to form the gate oxide layer, so the oxidation reaction rate at the center of the active region is lower than that at the edge of the active region, so that the subsequent thermal oxidation process can avoid this It occurs that the gate oxide thickness at the edge of the active region is less than the gate oxide thickness at the center of the active region.

根据上述目的，本发明另一实施例之制备方法首先形成具有至少两个开口之遮罩层于基板上，再形成沟槽于该开口下方之基板中，相邻两条沟槽之间形成主动区域。之后，形成衬氧化层于该沟槽之内壁，其中该衬氧化层在该主动区域之边缘处呈圆弧状，亦即该基板在该主动区域之边缘处呈逐渐变低之轮廓。接着，形成介电区块于该沟槽之中，再进行掺杂工艺以将含氮掺质植入该主动区域之基板中。然后，进行热氧化工艺以形成栅氧化层于该主动区域之基板的上表面。According to the above purpose, the preparation method of another embodiment of the present invention first forms a mask layer with at least two openings on the substrate, and then forms a groove in the substrate below the opening, and forms an active layer between two adjacent grooves. area. Afterwards, a liner oxide layer is formed on the inner wall of the trench, wherein the liner oxide layer is arc-shaped at the edge of the active region, that is, the substrate has a gradually lower profile at the edge of the active region. Next, a dielectric block is formed in the trench, and a doping process is performed to implant nitrogen-containing dopants into the substrate of the active region. Then, a thermal oxidation process is performed to form a gate oxide layer on the upper surface of the substrate in the active region.

由于该基板在该主动区域之边缘处呈逐渐变低之轮廓，因此该含氮掺质在该主动区域边缘处之基板内的植入浓度低于该主动区域中心处的植入浓度。如此，在后续进行热氧化工艺，即可避免该主动区域边缘处之栅氧化层厚度小于主动区域中心处之栅氧化层厚度的情形发生。Since the substrate has a gradually lower profile at the edge of the active region, the implantation concentration of the nitrogen-containing dopant in the substrate at the edge of the active region is lower than that at the center of the active region. In this way, the subsequent thermal oxidation process can avoid the situation that the thickness of the gate oxide layer at the edge of the active region is smaller than the thickness of the gate oxide layer at the center of the active region.

由上述可知，通过改变浅槽隔离与主动区域间之相对高度或主动区域之基板轮廓，可使掺杂工艺自我对准地将含氮掺质植入主动区域之基板内，且主动区域之中心处与边缘处具有不同的浓度分布，而不需通过光刻工艺来界定掺杂区域。另外，通过该含氮掺质抑制氧化反应之速率，可避免后续进行热氧化工艺时，该主动区域边缘处之栅氧化层厚度小于主动区域中心处之栅氧化层厚度的情形发生。It can be seen from the above that by changing the relative height between the shallow trench isolation and the active region or the substrate profile of the active region, the doping process can be self-aligned to implant nitrogen-containing dopants into the substrate of the active region, and the center of the active region There is a different concentration distribution at the edge than at the edge, and there is no need to define the doped region through photolithography. In addition, the rate of oxidation reaction is suppressed by the nitrogen-containing dopant, which can avoid the situation that the thickness of the gate oxide layer at the edge of the active region is smaller than the thickness of the gate oxide layer at the center of the active region during the subsequent thermal oxidation process.

附图说明Description of drawings

图1表示公知之浅槽隔离；Figure 1 shows the known shallow trench isolation;

图2至图6表示本发明第一实施例之栅氧化层之制备方法；2 to 6 show the preparation method of the gate oxide layer of the first embodiment of the present invention;

图7至图10表示本发明第二实施例之栅氧化层之制备方法；以及7 to 10 show the preparation method of the gate oxide layer of the second embodiment of the present invention; and

图11至图14表示本发明第三实施例之栅氧化层之制备方法。11 to 14 show the method for preparing the gate oxide layer according to the third embodiment of the present invention.

主要元件标记说明Description of main component marking

10    浅槽隔离      12    硅基板10 shallow trench isolation 12 silicon substrate

14    栅氧化层      20    主动区域14 gate oxide layer 20 active area

32    硅基板        34    垫氧化层32 Silicon substrate 34 Pad oxide layer

36    遮罩层        37    开口36 mask layer 37 opening

38    沟槽          40    介电层38 Trench 40 Dielectric layer

40′  介电区块      40″  介电区块40′ Dielectric Block 40″ Dielectric Block

42    含氮掺质      44    栅氧化层42 Nitrogen-containing dopant 44 Gate oxide layer

44′  栅氧化层      44″  栅氧化层44′ Gate Oxide 44″ Gate Oxide

50    主动区域      60    衬氧化层50 Active area 60 Lining oxide layer

具体实施方式Detailed ways

图2至图6表示本发明第一实施例之栅氧化层44之制备方法。首先，在硅基板32上依次形成垫氧化层34及一层由氮化硅构成之遮罩层36，该遮罩36具有开口37。接着，利用各向异性蚀刻工艺形成沟槽38于该开口37下方之硅基板32中，其中相邻两条沟槽38之间形成主动区域50。之后，进行化学气相沉积工艺以均匀地形成一层由氧化硅构成之介电层40，其填满该沟槽38，如图3所示。2 to 6 show the preparation method of the gate oxide layer 44 according to the first embodiment of the present invention. First, a pad oxide layer 34 and a mask layer 36 made of silicon nitride are sequentially formed on the silicon substrate 32 , and the mask 36 has an opening 37 . Next, an anisotropic etching process is used to form trenches 38 in the silicon substrate 32 below the openings 37 , wherein an active region 50 is formed between two adjacent trenches 38 . Afterwards, a chemical vapor deposition process is performed to uniformly form a dielectric layer 40 made of silicon oxide, which fills up the trench 38 , as shown in FIG. 3 .

参照图4，进行平坦化工艺(例如化学机械研磨工艺)，去除该遮罩层34上方之介电层40以形成介电区块40′于该沟槽38之中。之后，进行湿蚀刻工艺，利用热磷酸溶液完全去除该遮罩层36，但保留该垫氧化层34及该介电区块40′。如此，该介电区块40′之上表面高于该垫氧化层34之上表面，亦即该介电区块40′之上表面高于该主动区域50之硅基板32的上表面。Referring to FIG. 4 , a planarization process (such as a chemical mechanical polishing process) is performed to remove the dielectric layer 40 above the mask layer 34 to form a dielectric block 40 ′ in the trench 38 . Afterwards, a wet etching process is performed, using hot phosphoric acid solution to completely remove the mask layer 36, but retain the pad oxide layer 34 and the dielectric block 40'. Thus, the upper surface of the dielectric block 40 ′ is higher than the upper surface of the pad oxide layer 34 , that is, the upper surface of the dielectric block 40 ′ is higher than the upper surface of the silicon substrate 32 of the active region 50 .

参照图5，进行掺杂工艺，将含氮掺质42植入该主动区域50之硅基板32中及该介电区块40′中。较佳地，该含氮掺质42选自氮离子、氮气离子、氧化亚氮离子及氧化氮离子组成之群，且该含氮掺质42之植入能量介于10至30千电子伏特。由于该介电区块40′之上表面高于该硅基板32之上表面，因此该介电区块40′内与该硅基板32内之含氮掺质42处于不同高度而无法交互扩散(cross diffusion)，且植入之含氮掺质42之浓度呈高斯分布(Gaussian distribution)。因此，该硅基板32内之含氮掺质42之浓度分布并不均匀，特而言之，该含氮掺质42在该主动区域50中心处之浓度高于该主动区域50边缘处之浓度。Referring to FIG. 5 , a doping process is performed to implant nitrogen-containing dopants 42 into the silicon substrate 32 of the active region 50 and into the dielectric block 40 ′. Preferably, the nitrogen-containing dopant 42 is selected from the group consisting of nitrogen ions, nitrogen gas ions, nitrous oxide ions, and nitrogen oxide ions, and the implantation energy of the nitrogen-containing dopant 42 is between 10 and 30 keV. Since the upper surface of the dielectric block 40' is higher than the upper surface of the silicon substrate 32, the nitrogen-containing dopants 42 in the dielectric block 40' and the silicon substrate 32 are at different heights and cannot be interdiffused ( cross diffusion), and the concentration of the implanted nitrogen-containing dopant 42 is Gaussian distribution. Therefore, the concentration distribution of the nitrogen-containing dopant 42 in the silicon substrate 32 is not uniform, in particular, the concentration of the nitrogen-containing dopant 42 at the center of the active region 50 is higher than that at the edge of the active region 50 .

参照图6，进行另一湿蚀刻工艺，利用氢氟酸溶液完全去除该垫氧化层34以曝露该主动区域50之硅基板32表面。之后，进行热氧化工艺以形成栅氧化层44于该主动区域50之硅基板32表面。由于该含氮掺质42可抑制热氧化工艺之氧化速率，且该含氮掺质42在该主动区域50中心处之浓度高于该主动区域50边缘处之浓度，因此在进行热氧化工艺时，该主动区域50中心处之氧化速率较慢，而该主动区域50边缘处之氧化速率较快。如此，即可补偿因应力导致该主动区域50之中心处与边缘处氧化速率不一之问题，而可避免该栅氧化层44在该主动区域50边缘处的厚度小于在该主动区域50中心处的厚度。Referring to FIG. 6 , another wet etching process is performed, using hydrofluoric acid solution to completely remove the pad oxide layer 34 to expose the surface of the silicon substrate 32 of the active region 50 . Afterwards, a thermal oxidation process is performed to form a gate oxide layer 44 on the surface of the silicon substrate 32 of the active region 50 . Since the nitrogen-containing dopant 42 can suppress the oxidation rate of the thermal oxidation process, and the concentration of the nitrogen-containing dopant 42 at the center of the active region 50 is higher than that at the edge of the active region 50, when performing the thermal oxidation process , the oxidation rate at the center of the active region 50 is relatively slow, while the oxidation rate at the edge of the active region 50 is relatively fast. In this way, the problem of different oxidation rates at the center and edge of the active region 50 due to stress can be compensated, and the thickness of the gate oxide layer 44 at the edge of the active region 50 can be prevented from being smaller than at the center of the active region 50 thickness of.

图7至图10表示本发明第二实施例之栅氧化层44′之制备方法。首先，进行如图2及图3所示之工艺以形成该沟槽38于该硅基板32之中，以及形成一层由氧化硅构成介电层40于该硅基板32之上。之后，进行平坦化工艺(例如化学机械研磨工艺)，去除该遮罩层34上方之介电层40，如此该介电层40之上表面水平对齐该遮罩层36之上表面，如图7所示。7 to 10 show the method for preparing the gate oxide layer 44' according to the second embodiment of the present invention. Firstly, the process shown in FIG. 2 and FIG. 3 is performed to form the trench 38 in the silicon substrate 32 and form a dielectric layer 40 made of silicon oxide on the silicon substrate 32 . Afterwards, a planarization process (such as a chemical mechanical polishing process) is performed to remove the dielectric layer 40 above the mask layer 34, so that the upper surface of the dielectric layer 40 is horizontally aligned with the upper surface of the mask layer 36, as shown in FIG. 7 shown.

参照图8，利用该遮罩层36为蚀刻遮罩，进行蚀刻工艺以去除未被该遮罩层36覆盖之介电层40，直到该介电层40位于该硅基板32内部(亦即该介电层40之上表面低于该硅基板32之上表面)，而形成介电区块40″。特而言之，该介电区块40″之上表面低于该硅基板32之上表面。此外，亦可选择性地在形成该介电层(由氧化硅构成)40之后，直接利用该遮罩层(氮化硅)36为蚀刻遮罩进行回蚀(etching back)工艺，而不进行前述之平坦化工艺。Referring to FIG. 8, using the mask layer 36 as an etching mask, an etching process is performed to remove the dielectric layer 40 not covered by the mask layer 36 until the dielectric layer 40 is located inside the silicon substrate 32 (that is, the The upper surface of the dielectric layer 40 is lower than the upper surface of the silicon substrate 32) to form a dielectric block 40″. In particular, the upper surface of the dielectric block 40″ is lower than the upper surface of the silicon substrate 32 surface. In addition, after forming the dielectric layer (made of silicon oxide) 40, the mask layer (silicon nitride) 36 can be directly used as an etching mask to perform etching back (etching back) process. The aforementioned planarization process.

参照图9，进行湿蚀刻工艺，利用热磷酸溶液完全去除该遮罩层36，但保留该垫氧化层34及该介电区块40″。之后，进行掺杂工艺，将该含氮掺质42植入该主动区域50之硅基板32中及该介电区块40″中。因该介电区块40″之上表面低于该硅基板32之上表面，故该介电区块40″内与该硅基板32内之含氮掺质42处于不同高度而无法交互扩散，且植入之含氮掺质42之浓度呈高斯分布(Gaussian distribution)。因此，该硅基板32内之含氮掺质42之浓度分布并不均匀，特而言之，该含氮掺质42在该主动区域50中心处之浓度高于该主动区域50边缘处之浓度。Referring to FIG. 9, a wet etching process is performed, and the mask layer 36 is completely removed using a hot phosphoric acid solution, but the pad oxide layer 34 and the dielectric block 40″ are retained. Afterwards, a doping process is performed, and the nitrogen-containing dopant 42 implanted in the silicon substrate 32 of the active region 50 and in the dielectric block 40″. Because the upper surface of the dielectric block 40″ is lower than the upper surface of the silicon substrate 32, the nitrogen-containing dopants 42 in the dielectric block 40″ and the silicon substrate 32 are at different heights and cannot be alternately diffused. And the concentration of the implanted nitrogen-containing dopant 42 is Gaussian distribution. Therefore, the concentration distribution of the nitrogen-containing dopant 42 in the silicon substrate 32 is not uniform, in particular, the concentration of the nitrogen-containing dopant 42 at the center of the active region 50 is higher than that at the edge of the active region 50 .

参照图10，进行另一湿蚀刻工艺，利用氢氟酸溶液完全去除该垫氧化层34以曝露该主动区域50之硅基板32表面。之后，进行热氧化工艺，形成栅氧化层44′于该主动区域50之硅基板32表面。由于该硅基板32内部浓度呈高斯分布之含氮掺质42会抑制热氧化工艺之氧化速率，因此在进行热氧化工艺时，可避免该栅氧化层44′在该主动区域50边缘处的厚度小于在该主动区域50中心处的厚度。Referring to FIG. 10 , another wet etching process is performed, using a hydrofluoric acid solution to completely remove the pad oxide layer 34 to expose the surface of the silicon substrate 32 of the active region 50 . Afterwards, a thermal oxidation process is performed to form a gate oxide layer 44 ′ on the surface of the silicon substrate 32 of the active region 50 . Since the nitrogen-containing dopant 42 with a Gaussian distribution inside the silicon substrate 32 will inhibit the oxidation rate of the thermal oxidation process, the thickness of the gate oxide layer 44' at the edge of the active region 50 can be avoided during the thermal oxidation process. less than the thickness at the center of the active region 50 .

图11至图14表示本发明第三实施例之栅氧化层44″之制备方法。首先，进行如图2所示之工艺以形成该沟槽38于该硅基板32之中。之后，进行热氧化工艺以形成衬氧化层60于该沟槽38之内壁，并通过该硅基板32之氧化反应改变该主动区域50与该沟槽38之交界处的硅基板32轮廓。特而言之，该热氧化工艺圆角化(round)该主动区域50边缘处之硅基板32，使该硅基板32在该主动区域50之边缘处呈逐渐变低之轮廓，因此该衬氧化层60在该主动区域50之边缘处呈圆弧状，且其于该主动区域50与该沟槽38之交界处的厚度大于主动区域50上的衬氧化层60厚度，如图11所示。该衬氧化层60可由氧化硅、氮化硅或氮氧化硅构成。Figure 11 to Figure 14 represent the preparation method of the gate oxide layer 44 " of the third embodiment of the present invention. First, carry out the process as shown in Figure 2 to form this groove 38 in this silicon substrate 32. Afterwards, carry out thermal oxidation process to form a liner oxide layer 60 on the inner wall of the trench 38, and change the profile of the silicon substrate 32 at the junction of the active region 50 and the trench 38 through the oxidation reaction of the silicon substrate 32. Specifically, the The thermal oxidation process rounds the silicon substrate 32 at the edge of the active region 50, so that the silicon substrate 32 has a gradually lower profile at the edge of the active region 50, so that the liner oxide layer 60 is in the active region. The edge of 50 is arc-shaped, and its thickness at the junction of the active region 50 and the trench 38 is greater than the thickness of the lining oxide layer 60 on the active region 50, as shown in Figure 11. The lining oxide layer 60 can be formed by Silicon oxide, silicon nitride or silicon oxynitride.

参照图12，进行如图3及图4所示之工艺以形成该介电区块40′于该沟槽38之中(亦可选择性地进行图7及图8所示之工艺以形成该介电区块40″于该沟槽38之中)。之后，进行掺杂工艺，将该含氮掺质42植入该主动区域50之硅基板32中及该介电区块40′中。如图13所示，由于该硅基板32在该主动区域50之边缘处呈逐渐变低之轮廓，致使该衬氧化层60于该主动区域50边缘处的厚度较中心处厚，因此利用该衬氧化层60为掩膜进行掺杂工艺时，可使该含氮掺质42在该主动区域50边缘处之植入浓度低于该主动区域50中心处之植入浓度。Referring to FIG. 12, the process shown in FIG. 3 and FIG. 4 is carried out to form the dielectric block 40' in the trench 38 (the process shown in FIG. 7 and FIG. 8 can also be selectively carried out to form the The dielectric block 40 ″ is in the trench 38 ). Afterwards, a doping process is performed to implant the nitrogen-containing dopant 42 into the silicon substrate 32 of the active region 50 and the dielectric block 40 ′. As shown in FIG. 13 , since the silicon substrate 32 has a gradually lower profile at the edge of the active region 50, the thickness of the liner oxide layer 60 at the edge of the active region 50 is thicker than that at the center. When the oxide layer 60 is used as a mask for the doping process, the implantation concentration of the nitrogen-containing dopant 42 at the edge of the active region 50 can be lower than that at the center of the active region 50 .

参照图14，进行另一湿蚀刻工艺，利用氢氟酸溶液完全去除该垫氧化层34以曝露该主动区域50之硅基板32表面。之后，进行热氧化工艺，形成该栅氧化层44″于该主动区域50之硅基板32表面。由于该含氮掺质42在该主动区域50边缘处之植入浓度低于该主动区域50中心处之植入浓度，亦即在该主动区域50边缘处之硅基板32的浅层内部具有较少可抑制氧化反应之含氮掺质42，而在该主动区域50中心处之硅基板32的浅层内部具有较多可抑制氧化反应之含氮掺质42。因此，在该主动区域50中心处之氧化速率较慢，而该主动区域50边缘处之氧化速率较快。如此进行热氧化工艺时，即可补偿因应力造成该栅氧化层44″于该主动区域50边缘处厚度小于中心处厚度的现象。Referring to FIG. 14 , another wet etching process is performed, using a hydrofluoric acid solution to completely remove the pad oxide layer 34 to expose the surface of the silicon substrate 32 of the active region 50 . Afterwards, a thermal oxidation process is performed to form the gate oxide layer 44″ on the surface of the silicon substrate 32 of the active region 50. Since the implantation concentration of the nitrogen-containing dopant 42 at the edge of the active region 50 is lower than that at the center of the active region 50 The implantation concentration at the place, that is, the shallow interior of the silicon substrate 32 at the edge of the active region 50 has less nitrogen-containing dopants 42 that can inhibit the oxidation reaction, while the silicon substrate 32 at the center of the active region 50 has There are more nitrogen-containing dopants 42 that can inhibit the oxidation reaction inside the shallow layer. Therefore, the oxidation rate at the center of the active region 50 is relatively slow, while the oxidation rate at the edge of the active region 50 is relatively fast. Performing the thermal oxidation process in this way , the phenomenon that the thickness of the gate oxide layer 44″ at the edge of the active region 50 is smaller than that at the center due to stress can be compensated.

与公知技术相比，本发明是利用掺杂工艺将含氮掺质植入主动区域之硅基板内，且该含氮掺质在主动区域中心处之浓度高于该主动区域边缘处之浓度。因此，在进行后续之热氧化工艺时，通过该含氮掺质抑制氧化反应之速率，使该主动区域边缘处之氧化速率大于中心处之氧化速率，如此可避免该主动区域边缘处之栅氧化层厚度小于主动区域中心处之栅氧化层厚度。再者，通过改变该浅槽隔离与该主动区域间之相对高度或该主动区域中硅基板轮廓，掺杂工艺可自动地以不同的浓度分布将含氮掺质植入主动区域之硅基板内，而不需通过光刻工艺来界定掺杂区域，亦即掺杂工艺是以自我对准(self-aligned)之方式将含氮掺质植入主动区域之硅基板内。Compared with the known technology, the present invention uses a doping process to implant nitrogen-containing dopant into the silicon substrate of the active region, and the concentration of the nitrogen-containing dopant at the center of the active region is higher than that at the edge of the active region. Therefore, when performing the subsequent thermal oxidation process, the rate of oxidation reaction is suppressed by the nitrogen-containing dopant, so that the oxidation rate at the edge of the active region is greater than the oxidation rate at the center, so that gate oxidation at the edge of the active region can be avoided The layer thickness is less than the gate oxide thickness at the center of the active area. Furthermore, by changing the relative height between the shallow trench isolation and the active region or the profile of the silicon substrate in the active region, the doping process can automatically implant nitrogen-containing dopants into the silicon substrate in the active region with different concentration distributions , instead of defining the doped region through a photolithography process, that is, the doping process is to implant nitrogen-containing dopants into the silicon substrate in the active region in a self-aligned manner.

本发明之技术内容及技术特点已揭示如上，然而所属技术领域的技术人员仍可能基于本发明之教导及揭示而作种种不背离本发明精神之替换及改进。因此，本发明之保护范围应不限于实施例所揭示者，而应包括各种不背离本发明之替换及改进，并为权利要求所涵盖。The technical content and technical features of the present invention have been disclosed above, but those skilled in the art may still make various replacements and improvements based on the teaching and disclosure of the present invention without departing from the spirit of the present invention. Therefore, the protection scope of the present invention should not be limited to those disclosed in the embodiments, but should include various replacements and improvements that do not deviate from the present invention, and are covered by the claims.

Claims (20)

1. method for producing grid oxide layer is characterized in that comprising the following step:
Form mask layer on substrate, this mask layer has at least two openings;
Form two grooves in the substrate of these two opening belows, form active area between these two grooves;
Form the dielectric block in this groove, the surface does not line up surface on this substrate on this dielectric block;
Carry out doping process, nitrogenous admixture is implanted in the substrate of this active area; And
Carry out thermal oxidation technology to form gate oxide in the upper surface of the substrate of this active area.
2. the method for producing grid oxide layer according to claim 1 is characterized in that forming the dielectric block and comprises among this groove:
Form dielectric layer on this substrate;
Carry out flatening process, remove the above dielectric layer of this mask layer to form this dielectric block; And
Carry out etch process to remove this mask layer, make on this dielectric block the surface be higher than surface on this substrate.
3. the method for producing grid oxide layer according to claim 1 is characterized in that forming the dielectric block and comprises among this groove:
Form dielectric layer on this substrate; And
Remove not by the dielectric layer of this mask layer coverings, be lower than on this substrate surperficial and form this dielectric block up to surface on this dielectric layer.
4. the method for producing grid oxide layer according to claim 1 is characterized in that this nitrogenous admixture is selected from the group of nitrogen ion, nitrogen ion, nitrous oxide ion and nitrogen oxide ion composition.
5. the method for producing grid oxide layer according to claim 1 is characterized in that this nitrogenous admixture is Gaussian Profile in the concentration of this active area.
6. the method for producing grid oxide layer according to claim 1 is characterized in that the concentration of this nitrogenous admixture in this active area center is higher than the concentration of this active area edge.
7. the preparation method of a gate oxide is characterized in that comprising the following step:
Form mask layer on substrate, this mask layer has at least two openings;
Form two grooves in the substrate of these two opening belows, form active area between these two grooves;
Change the substrate profile of this active area and this groove intersection, to present the edge of step-down gradually;
Form the dielectric block among this groove;
Carry out doping process nitrogenous admixture is implanted in the substrate of this active area; And
Carry out first thermal oxidation technology to form gate oxide in the upper surface of base plate of this active area.
8. the method for producing grid oxide layer according to claim 7, the substrate profile that it is characterized in that changing this active area and this groove intersection is to carry out second thermal oxidation technology.
9. described according to Claim 8 method for producing grid oxide layer is characterized in that the substrate profile of this this active area of second thermal oxidation technology corners and this groove intersection.
10. described according to Claim 8 method for producing grid oxide layer it is characterized in that this second thermal oxidation technology forms lining oxide layer wall within this groove, and this lining oxide layer is circular-arc in the edge of this active area.
11. the method for producing grid oxide layer according to claim 7 is characterized in that forming the dielectric block and comprises among this groove:
Form dielectric layer on this substrate;
Carry out flatening process, remove the above dielectric layer of this mask layer to form this dielectric block; And
Carry out etch process to remove this mask layer, make on this dielectric block the surface be higher than surface on this substrate.
12. the method for producing grid oxide layer according to claim 7 is characterized in that forming the dielectric block and comprises among this groove:
Form dielectric layer on this substrate; And
Remove not by the dielectric layer of this mask layer coverings, be lower than on this substrate surperficial and form this dielectric block up to surface on this dielectric layer.
13. the method for producing grid oxide layer according to claim 7 is characterized in that this nitrogenous admixture is selected from the group of nitrogen ion, nitrogen ion, nitrous oxide ion and nitrogen oxide ion composition.
14. the method for producing grid oxide layer according to claim 7 is characterized in that this nitrogenous admixture is lower than the implant concentration of this active area center at the implant concentration of this active area edge.
15. a method for producing grid oxide layer is characterized in that comprising the following step:
Form two dielectric blocks in two grooves of substrate, wherein these two dielectric blocks define active area, and on this dielectric block the surface with this substrate on the surface not contour;
Carry out doping process, nitrogenous admixture is implanted in the substrate of this active area, wherein the concentration of this nitrogenous admixture in this active area center is higher than the concentration of this active area edge; And
Carry out thermal oxidation technology, to form gate oxide in the upper surface of base plate of this active area, wherein the oxidation rate of this active area center is less than the oxidation rate of this active area edge.
16. the method for producing grid oxide layer according to claim 15 is characterized in that forming the method for this dielectric block in this groove and comprises:
Form mask layer on this substrate, this mask layer has at least two openings;
Form these two grooves in this substrate of these two opening belows;
Form dielectric layer on this substrate;
Carry out flatening process, remove this above dielectric layer of this mask layer to form this dielectric block; And
Remove this mask layer, make on this dielectric block the surface be higher than surface on this substrate.
17. the method for producing grid oxide layer according to claim 15 is characterized in that forming the method for this dielectric block in this groove and comprises:
Form mask layer on this substrate, this mask layer has at least two openings;
Form these two grooves in this substrate of these two opening belows;
Form dielectric layer on this substrate;
Remove not by the dielectric layer of this mask layer coverings, be lower than on this substrate surperficial and form this dielectric block up to surface on this dielectric layer; And
Remove this mask layer.
18. the method for producing grid oxide layer according to claim 15 is characterized in that this nitrogenous admixture is selected from the group of nitrogen ion, nitrogen ion, nitrous oxide ion and nitrogen oxide ion composition.
19. the method for producing grid oxide layer according to claim 15 is characterized in that this nitrogenous admixture is Gaussian Profile in the concentration of this active area.
20. the method for producing grid oxide layer according to claim 15, it is characterized in that before these two dielectric blocks of formation are in these two grooves, also comprise and carry out another thermal oxidation technology, with formation lining oxide layer wall within these two grooves, and this lining oxide layer is circular-arc in this active area edge.
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Cited By (3)

* Cited by examiner, † Cited by third party
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CN105655246A (en) * 2016-01-04 2016-06-08 株洲南车时代电气股份有限公司 Manufacturing method of groove-type IGBT grid electrode
CN105845577A (en) * 2015-01-16 2016-08-10 中芯国际集成电路制造(上海)有限公司 Semiconductor device structure and making method thereof

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19939597B4 (en) * 1999-08-20 2006-07-20 Infineon Technologies Ag A method of fabricating a microelectronic structure with improved gate dielectric uniformity
KR20020005851A (en) * 2000-07-10 2002-01-18 윤종용 Shallow trench isolation type semiconductor device and method of forming it
KR100386946B1 (en) * 2000-08-01 2003-06-09 삼성전자주식회사 Shallow trench isolation type semiconductor devices and method of forming it
KR100338783B1 (en) * 2000-10-28 2002-06-01 Samsung Electronics Co Ltd Semiconductor device having expanded effective width of active region and fabricating method thereof
US6495430B1 (en) * 2002-05-21 2002-12-17 Macronix International Co., Ltd. Process for fabricating sharp corner-free shallow trench isolation structure
CN1501468A (en) * 2002-11-15 2004-06-02 上海宏力半导体制造有限公司 Method for reducing ditch isolation falling effect of semiconductor assembly
DE10314504B4 (en) * 2003-03-31 2007-04-26 Advanced Micro Devices, Inc., Sunnyvale Process for producing a nitride-containing insulating layer by compensating for nitrogen nonuniformities

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CN104900594A (en) * 2014-03-04 2015-09-09 中芯国际集成电路制造(上海)有限公司 Nonvolatile memory forming method
CN105845577A (en) * 2015-01-16 2016-08-10 中芯国际集成电路制造(上海)有限公司 Semiconductor device structure and making method thereof
CN105655246A (en) * 2016-01-04 2016-06-08 株洲南车时代电气股份有限公司 Manufacturing method of groove-type IGBT grid electrode

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