CN101005030A - Method for producing grid oxide layer - Google Patents
Method for producing grid oxide layer Download PDFInfo
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- CN101005030A CN101005030A CN 200610001049 CN200610001049A CN101005030A CN 101005030 A CN101005030 A CN 101005030A CN 200610001049 CN200610001049 CN 200610001049 CN 200610001049 A CN200610001049 A CN 200610001049A CN 101005030 A CN101005030 A CN 101005030A
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Abstract
The method for preparing grating oxidation layer includes steps: first, forming at least two grooves on the base plate, and forming an active area between the two grooves; next, forming dielectric block on the grooves, and upper surface of the dielectric block is not aligned to the up surface of the base plate; then, doping procedure embeds the doping material containing nitrogen to the base plate in the active area, thus, concentration of containing doping material of nitrogen in the center of the active area is higher than concentration in fringe of the active area; carrying out thermal oxidation procedure to form grating oxidation layer on up surface of the base plate in the active area. The doping material of containing nitrogen restrains rate of thermal oxidation reaction so as to prevent the condition from occurring that thickness of grating oxidation layer at fringe of the active area is smaller than thickness at the center.
Description
Technical field
The present invention relates to a kind of method for producing grid oxide layer, particularly a kind of preparation method who avoids the gate oxide thickness attenuation at active area edge.
Background technology
Known semiconductor technology produces short circuit phenomenon for fear of the mutual interference of electronic component phase, generally adopts silicon selective oxidation method (local oxidation of silicon; LOCOS) or shallow-trench isolation method (shallow trench isolation; STI) electronic component on the electrical isolation wafer.Because the field oxide of selective oxidation method formation occupies wafer than large tracts of land, and can follow formation beak phenomenon, therefore sophisticated semiconductor technology adopts shallow-trench isolation method electrical isolation electronic component more at present.
Fig. 1 represents known shallow-trench isolation 10.This shallow-trench isolation 10 is around active area 20, and gate oxide 14 is formed at the surface of the silicon substrate 12 of this active area 20.Along with the continuous downsizing of semiconductor element, the width of this active area 20 also dwindles thereupon, thereby the stress of the edge of this active area 20 becomes big.Like this, bigger stress can cause oxidizing reaction rate to slow down, thus this gate oxide 14 at the thickness of the edge of this active area 20 less than thickness, so be easy to generate the electric leakage problem in the center of this active area 20.
Summary of the invention
The present invention's main purpose provides a kind of preparation method of gate oxide, it utilizes the doping process of self-aligned nitrogenous admixture to be implanted in the silicon substrate of active area, and suppressing the speed of oxidation reaction by nitrogenous admixture, the thickness of gate oxide of avoiding active area edge is less than the thickness of the gate oxide of active area center.
For achieving the above object, the present invention proposes a kind of preparation method who utilizes nitrogenous admixture to suppress the gate oxide of oxidizing reaction rate.The preparation method of one embodiment of the invention at first form have at least two openings mask layer on substrate, form groove again in the substrate of this opening below, form active area between adjacent two grooves.Afterwards, form the dielectric block among this groove, the surface does not line up surface on this substrate on this dielectric block.Then, carry out doping process, nitrogenous admixture is implanted in the substrate of this active area.Then, carry out thermal oxidation technology to form gate oxide in the upper surface of the substrate of this active area.
Because the surface does not line up surface on this substrate on this dielectric block, so the nitrogenous dopant concentration in the substrate of this active area center is higher than this active area edge.In addition, this nitrogenous admixture can suppress in order to form the thermal oxidative reaction speed of this gate oxide, therefore the oxidizing reaction rate of this active area center is lower than this active area edge, and so follow-up thermal oxidation technology can be avoided the situation generation of the gate oxide thickness of this active area edge less than the gate oxide thickness of active area center.
According to above-mentioned purpose, the preparation method of another embodiment of the present invention at first form have at least two openings mask layer on substrate, form groove again in the substrate of this opening below, form active area between adjacent two grooves.Afterwards, form lining oxide layer wall within this groove, wherein this lining oxide layer is circular-arc in the edge of this active area, that is this substrate is the profile of step-down gradually in the edge of this active area.Then, form the dielectric block among this groove, carry out doping process again so that nitrogenous admixture is implanted in the substrate of this active area.Then, carry out thermal oxidation technology to form gate oxide in the upper surface of the substrate of this active area.
Because this substrate is the profile of step-down gradually in the edge of this active area, therefore the implant concentration of this nitrogenous admixture in the substrate of this active area edge is lower than the implant concentration of this active area center.So, in the follow-up thermal oxidation technology of carrying out, can avoid of the situation generation of the gate oxide thickness of this active area edge less than the gate oxide thickness of active area center.
From the above, by the relative altitude between change shallow-trench isolation and active area or the substrate profile of active area, can make doping process self-aligned ground nitrogenous admixture be implanted in the substrate of active area, and the center of active area has different CONCENTRATION DISTRIBUTION with edge, and does not need to define doped region by photoetching process.In addition, suppress the speed of oxidation reaction by this nitrogenous admixture, can avoid follow-up when carrying out thermal oxidation technology, the gate oxide thickness of this active area edge takes place less than the situation of the gate oxide thickness of active area center.
Description of drawings
Fig. 1 represents known shallow-trench isolation;
Fig. 2 to Fig. 6 represents the method for producing grid oxide layer of first embodiment of the invention;
Fig. 7 to Figure 10 represents the method for producing grid oxide layer of second embodiment of the invention; And
Figure 11 to Figure 14 represents the method for producing grid oxide layer of third embodiment of the invention.
The main element description of symbols
10 shallow-trench isolation, 12 silicon substrates
14 gate oxides, 20 active area
32 silicon substrates, 34 pad oxides
36 mask layers, 37 openings
38 grooves, 40 dielectric layers
40 ' dielectric block 40 " dielectric block
42 nitrogenous admixture 44 gate oxides
44 ' gate oxide, 44 " gate oxides
50 active area, 60 lining oxide layers
Embodiment
Fig. 2 to Fig. 6 represents the preparation method of the gate oxide 44 of first embodiment of the invention.At first, form the mask layer 36 that pad oxide 34 and one deck are made of silicon nitride successively on silicon substrate 32, this shade 36 has opening 37.Then, utilize anisotropic etching process to form groove 38 in the silicon substrate 32 of these opening 37 belows, form active area 50 between wherein adjacent two grooves 38.Afterwards, carry out chemical vapor deposition method to be formed uniformly the dielectric layer 40 that one deck is made of silica, it fills up this groove 38, as shown in Figure 3.
With reference to Fig. 4, carry out flatening process (for example chemical mechanical milling tech), the dielectric layer 40 of removing these mask layer 34 tops is to form dielectric block 40 ' among this groove 38.Afterwards, carry out wet etching process, utilize hot phosphoric acid solution to remove this mask layer 36 fully, but keep this pad oxide 34 and this dielectric block 40 '.So, this dielectric block 40 ' on the surface be higher than on this pad oxide 34 surface, that is this dielectric block 40 ' on the surface be higher than the upper surface of the silicon substrate 32 of this active area 50.
With reference to Fig. 5, carry out doping process, nitrogenous admixture 42 is implanted in the silicon substrate 32 of these active area 50 and this dielectric block 40 ' in.Preferably, this nitrogenous admixture 42 is selected from the group of nitrogen ion, nitrogen ion, nitrous oxide ion and nitrogen oxide ion composition, and the implantation energy of this nitrogenous admixture 42 is between 10 to 30 kilo electron volts.Because this dielectric block 40 ' on the surface be higher than surface on this silicon substrate 32, therefore this dielectric block 40 ' interior is in differing heights and can't spreads (cross diffusion) alternately with nitrogenous admixture 42 in this silicon substrate 32, and the concentration of the nitrogenous admixture 42 of implantation is Gaussian Profile (Gaussian distribution).Therefore, the CONCENTRATION DISTRIBUTION of the nitrogenous admixture 42 in this silicon substrate 32 is also inhomogeneous, the spy's, the concentration of this nitrogenous admixture 42 in these active area 50 centers is higher than the concentration of these active area 50 edges.
With reference to Fig. 6, carry out another wet etching process, utilize hydrofluoric acid solution to remove silicon substrate 32 surfaces of this pad oxide 34 fully to expose this active area 50 to the open air.Afterwards, carry out thermal oxidation technology to form gate oxide 44 in silicon substrate 32 surfaces of this active area 50.Because this nitrogenous admixture 42 can suppress the oxidation rate of thermal oxidation technology, and the concentration of this nitrogenous admixture 42 in these active area 50 centers is higher than the concentration of these active area 50 edges, therefore when carrying out thermal oxidation technology, the oxidation rate of these active area 50 centers is slower, and the oxidation rate of these active area 50 edges is very fast.So, can compensate stress and cause the center of this active area 50 and the problem that edge's oxidation rate differs, and can avoid this gate oxide 44 at the thickness of these active area 50 edges less than thickness in these active area 50 centers.
Fig. 7 to Figure 10 represent the gate oxide 44 of second embodiment of the invention ' the preparation method.At first, carry out as shown in Figures 2 and 3 technology forming this groove 38 among this silicon substrate 32, and form one deck and constitute dielectric layer 40 on this silicon substrate 32 by silica.Afterwards, carry out flatening process (for example chemical mechanical milling tech), remove the dielectric layer 40 of these mask layer 34 tops, surface level surface on this mask layer 36 of aliging on this dielectric layer 40 like this, as shown in Figure 7.
With reference to Fig. 8, utilize this mask layer 36 to be the etching shade, carry out etch process to remove, be positioned at these silicon substrate 32 inside (that is the surface is lower than surface on this silicon substrate 32 on this dielectric layer 40) up to this dielectric layer 40, and form dielectric block 40 " not by the dielectric layer 40 of these mask layer 36 coverings.The spy's, this dielectric block 40 " on the surface be lower than surface on this silicon substrate 32.In addition, also optionally after forming this dielectric layer (constituting) 40, directly utilize this mask layer (silicon nitride) 36 to eat-back (etching back) technology, and do not carry out aforementioned flatening process for the etching shade by silica.
With reference to Fig. 9, carry out wet etching process, utilize hot phosphoric acid solution to remove this mask layer 36 fully, but keep this pad oxide 34 and this dielectric block 40 ".Afterwards, carry out doping process, should reach this dielectric block 40 in the silicon substrate 32 of nitrogenous admixture 42 these active area 50 of implantation " in.Because of this dielectric block 40 " on the surface be lower than on this silicon substrate 32 surface; so this dielectric block 40 " in this silicon substrate 32 in nitrogenous admixture 42 be in differing heights and can't spread alternately, and the concentration of the nitrogenous admixture 42 of implantation is Gaussian Profile (Gaussian distribution).Therefore, the CONCENTRATION DISTRIBUTION of the nitrogenous admixture 42 in this silicon substrate 32 is also inhomogeneous, the spy's, the concentration of this nitrogenous admixture 42 in these active area 50 centers is higher than the concentration of these active area 50 edges.
With reference to Figure 10, carry out another wet etching process, utilize hydrofluoric acid solution to remove silicon substrate 32 surfaces of this pad oxide 34 fully to expose this active area 50 to the open air.Afterwards, carry out thermal oxidation technology, formation gate oxide 44 ' in silicon substrate 32 surfaces of this active area 50.Because these silicon substrate 32 inner concentration are the oxidation rate that the nitrogenous admixture 42 of Gaussian Profile can suppress thermal oxidation technology, therefore when carrying out thermal oxidation technology, can avoid this gate oxide 44 ' less than thickness in these active area 50 centers at the thickness of these active area 50 edges.
Figure 11 to Figure 14 represents the gate oxide 44 of third embodiment of the invention " the preparation method.At first, carry out as shown in Figure 2 technology to form this groove 38 among this silicon substrate 32.Afterwards, carry out thermal oxidation technology, and change silicon substrate 32 profiles of the intersection of this active area 50 and this groove 38 by the oxidation reaction of this silicon substrate 32 with formation lining oxide layer 60 wall within this groove 38.The spy's, the silicon substrate 32 of these these active area 50 edges of thermal oxidation technology corners (round), make this silicon substrate 32 be the profile of step-down gradually in the edge of this active area 50, therefore this lining oxide layer 60 is circular-arc in the edge of this active area 50, and its in the thickness of this active area 50 and the intersection of this groove 38 greater than 60 thickness of the lining oxide layer on the active area 50, as shown in figure 11.This lining oxide layer 60 can be made of silica, silicon nitride or silicon oxynitride.
With reference to Figure 12, carry out as shown in Figures 3 and 4 technology to form this dielectric block 40 ' in (also optionally carry out Fig. 7 and technology shown in Figure 8 " among this groove 38) among this groove 38 to form this dielectric block 40.Afterwards, carry out doping process, should be nitrogenous admixture 42 implant in the silicon substrate 32 of these active area 50 and this dielectric block 40 ' in.As shown in figure 13, because this silicon substrate 32 is the profile of step-down gradually in the edge of this active area 50, cause this lining oxide layer 60 thick than the center in the thickness of these active area 50 edges, when therefore utilizing this lining oxide layer 60 to carry out doping process, can make this nitrogenous admixture 42 be lower than the implant concentration of these active area 50 centers at the implant concentration of these active area 50 edges for mask.
With reference to Figure 14, carry out another wet etching process, utilize hydrofluoric acid solution to remove silicon substrate 32 surfaces of this pad oxide 34 fully to expose this active area 50 to the open air.Afterwards, carry out thermal oxidation technology, form this gate oxide 44 " in silicon substrate 32 surfaces of this active area 50.Because this nitrogenous admixture 42 is lower than the implant concentration of these active area 50 centers at the implant concentration of these active area 50 edges, that is have the less nitrogenous admixture 42 that suppresses oxidation reaction, and has the more nitrogenous admixture 42 that suppresses oxidation reaction in the shallow-layer inside of the silicon substrate 32 of these active area 50 centers in the shallow-layer inside of the silicon substrate 32 of these active area 50 edges.Therefore, slower in the oxidation rate of these active area 50 centers, and the oxidation rate of these active area 50 edges is very fast.When so carrying out thermal oxidation technology, can compensate stress and cause this gate oxide 44 " in the phenomenon of these active area 50 edge's thickness less than center thickness.
Compare with known technology, the present invention utilizes doping process that nitrogenous admixture is implanted in the silicon substrate of active area, and the concentration of this nitrogenous admixture in the active area center is higher than the concentration of this active area edge.Therefore, when carrying out follow-up thermal oxidation technology, the speed that suppresses oxidation reaction by this nitrogenous admixture, make the oxidation rate of the oxidation rate of this active area edge, so can avoid the gate oxide thickness of the gate oxide thickness of this active area edge less than the active area center greater than the center.Moreover, by changing silicon substrate profile in relative altitude between this shallow-trench isolation and this active area or this active area, doping process can automatically be implanted nitrogenous admixture in the silicon substrate of active area with different CONCENTRATION DISTRIBUTION, and do not need to define doped region by photoetching process, that is doping process is in the mode of self-aligned (self-aligned) nitrogenous admixture to be implanted in the silicon substrate of active area.
The present invention's technology contents and technical characterstic disclose as above, yet the person of ordinary skill in the field still may be based on the present invention's instruction and announcement and done all replacement and improvement that does not deviate from spirit of the present invention.Therefore, the present invention's protection range should be not limited to those disclosed embodiments, and should comprise various replacement and the improvement that do not deviate from the present invention, and is contained by claim.
Claims (20)
1. method for producing grid oxide layer is characterized in that comprising the following step:
Form mask layer on substrate, this mask layer has at least two openings;
Form two grooves in the substrate of these two opening belows, form active area between these two grooves;
Form the dielectric block in this groove, the surface does not line up surface on this substrate on this dielectric block;
Carry out doping process, nitrogenous admixture is implanted in the substrate of this active area; And
Carry out thermal oxidation technology to form gate oxide in the upper surface of the substrate of this active area.
2. the method for producing grid oxide layer according to claim 1 is characterized in that forming the dielectric block and comprises among this groove:
Form dielectric layer on this substrate;
Carry out flatening process, remove the above dielectric layer of this mask layer to form this dielectric block; And
Carry out etch process to remove this mask layer, make on this dielectric block the surface be higher than surface on this substrate.
3. the method for producing grid oxide layer according to claim 1 is characterized in that forming the dielectric block and comprises among this groove:
Form dielectric layer on this substrate; And
Remove not by the dielectric layer of this mask layer coverings, be lower than on this substrate surperficial and form this dielectric block up to surface on this dielectric layer.
4. the method for producing grid oxide layer according to claim 1 is characterized in that this nitrogenous admixture is selected from the group of nitrogen ion, nitrogen ion, nitrous oxide ion and nitrogen oxide ion composition.
5. the method for producing grid oxide layer according to claim 1 is characterized in that this nitrogenous admixture is Gaussian Profile in the concentration of this active area.
6. the method for producing grid oxide layer according to claim 1 is characterized in that the concentration of this nitrogenous admixture in this active area center is higher than the concentration of this active area edge.
7. the preparation method of a gate oxide is characterized in that comprising the following step:
Form mask layer on substrate, this mask layer has at least two openings;
Form two grooves in the substrate of these two opening belows, form active area between these two grooves;
Change the substrate profile of this active area and this groove intersection, to present the edge of step-down gradually;
Form the dielectric block among this groove;
Carry out doping process nitrogenous admixture is implanted in the substrate of this active area; And
Carry out first thermal oxidation technology to form gate oxide in the upper surface of base plate of this active area.
8. the method for producing grid oxide layer according to claim 7, the substrate profile that it is characterized in that changing this active area and this groove intersection is to carry out second thermal oxidation technology.
9. described according to Claim 8 method for producing grid oxide layer is characterized in that the substrate profile of this this active area of second thermal oxidation technology corners and this groove intersection.
10. described according to Claim 8 method for producing grid oxide layer it is characterized in that this second thermal oxidation technology forms lining oxide layer wall within this groove, and this lining oxide layer is circular-arc in the edge of this active area.
11. the method for producing grid oxide layer according to claim 7 is characterized in that forming the dielectric block and comprises among this groove:
Form dielectric layer on this substrate;
Carry out flatening process, remove the above dielectric layer of this mask layer to form this dielectric block; And
Carry out etch process to remove this mask layer, make on this dielectric block the surface be higher than surface on this substrate.
12. the method for producing grid oxide layer according to claim 7 is characterized in that forming the dielectric block and comprises among this groove:
Form dielectric layer on this substrate; And
Remove not by the dielectric layer of this mask layer coverings, be lower than on this substrate surperficial and form this dielectric block up to surface on this dielectric layer.
13. the method for producing grid oxide layer according to claim 7 is characterized in that this nitrogenous admixture is selected from the group of nitrogen ion, nitrogen ion, nitrous oxide ion and nitrogen oxide ion composition.
14. the method for producing grid oxide layer according to claim 7 is characterized in that this nitrogenous admixture is lower than the implant concentration of this active area center at the implant concentration of this active area edge.
15. a method for producing grid oxide layer is characterized in that comprising the following step:
Form two dielectric blocks in two grooves of substrate, wherein these two dielectric blocks define active area, and on this dielectric block the surface with this substrate on the surface not contour;
Carry out doping process, nitrogenous admixture is implanted in the substrate of this active area, wherein the concentration of this nitrogenous admixture in this active area center is higher than the concentration of this active area edge; And
Carry out thermal oxidation technology, to form gate oxide in the upper surface of base plate of this active area, wherein the oxidation rate of this active area center is less than the oxidation rate of this active area edge.
16. the method for producing grid oxide layer according to claim 15 is characterized in that forming the method for this dielectric block in this groove and comprises:
Form mask layer on this substrate, this mask layer has at least two openings;
Form these two grooves in this substrate of these two opening belows;
Form dielectric layer on this substrate;
Carry out flatening process, remove this above dielectric layer of this mask layer to form this dielectric block; And
Remove this mask layer, make on this dielectric block the surface be higher than surface on this substrate.
17. the method for producing grid oxide layer according to claim 15 is characterized in that forming the method for this dielectric block in this groove and comprises:
Form mask layer on this substrate, this mask layer has at least two openings;
Form these two grooves in this substrate of these two opening belows;
Form dielectric layer on this substrate;
Remove not by the dielectric layer of this mask layer coverings, be lower than on this substrate surperficial and form this dielectric block up to surface on this dielectric layer; And
Remove this mask layer.
18. the method for producing grid oxide layer according to claim 15 is characterized in that this nitrogenous admixture is selected from the group of nitrogen ion, nitrogen ion, nitrous oxide ion and nitrogen oxide ion composition.
19. the method for producing grid oxide layer according to claim 15 is characterized in that this nitrogenous admixture is Gaussian Profile in the concentration of this active area.
20. the method for producing grid oxide layer according to claim 15, it is characterized in that before these two dielectric blocks of formation are in these two grooves, also comprise and carry out another thermal oxidation technology, with formation lining oxide layer wall within these two grooves, and this lining oxide layer is circular-arc in this active area edge.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104900594A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Nonvolatile memory forming method |
| CN105655246A (en) * | 2016-01-04 | 2016-06-08 | 株洲南车时代电气股份有限公司 | Manufacturing method of groove-type IGBT grid electrode |
| CN105845577A (en) * | 2015-01-16 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and making method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| DE19939597B4 (en) * | 1999-08-20 | 2006-07-20 | Infineon Technologies Ag | A method of fabricating a microelectronic structure with improved gate dielectric uniformity |
| KR20020005851A (en) * | 2000-07-10 | 2002-01-18 | 윤종용 | Shallow trench isolation type semiconductor device and method of forming it |
| KR100386946B1 (en) * | 2000-08-01 | 2003-06-09 | 삼성전자주식회사 | Shallow trench isolation type semiconductor devices and method of forming it |
| KR100338783B1 (en) * | 2000-10-28 | 2002-06-01 | Samsung Electronics Co Ltd | Semiconductor device having expanded effective width of active region and fabricating method thereof |
| US6495430B1 (en) * | 2002-05-21 | 2002-12-17 | Macronix International Co., Ltd. | Process for fabricating sharp corner-free shallow trench isolation structure |
| CN1501468A (en) * | 2002-11-15 | 2004-06-02 | 上海宏力半导体制造有限公司 | Method for reducing ditch isolation falling effect of semiconductor assembly |
| DE10314504B4 (en) * | 2003-03-31 | 2007-04-26 | Advanced Micro Devices, Inc., Sunnyvale | Process for producing a nitride-containing insulating layer by compensating for nitrogen nonuniformities |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104900594A (en) * | 2014-03-04 | 2015-09-09 | 中芯国际集成电路制造(上海)有限公司 | Nonvolatile memory forming method |
| CN105845577A (en) * | 2015-01-16 | 2016-08-10 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device structure and making method thereof |
| CN105655246A (en) * | 2016-01-04 | 2016-06-08 | 株洲南车时代电气股份有限公司 | Manufacturing method of groove-type IGBT grid electrode |
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