CN101004882A - Method and device for driving gray scale modulation of field emission display - Google Patents
Method and device for driving gray scale modulation of field emission display Download PDFInfo
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- CN101004882A CN101004882A CN 200610005360 CN200610005360A CN101004882A CN 101004882 A CN101004882 A CN 101004882A CN 200610005360 CN200610005360 CN 200610005360 CN 200610005360 A CN200610005360 A CN 200610005360A CN 101004882 A CN101004882 A CN 101004882A
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Abstract
A grey level modulation-driving device of field emission display is prepared for reading in data by column display control module then carrying out pretreatment on data and buffer-storing them, sending treated data in packet mode as per certain order to data shift latch high voltage output unit after display is started up, amplifying and outputting signal by data shift latch high voltage output unit.
Description
Technical field
The invention belongs to the display fabrication techniques field, gray modulation driving method and device thereof that particularly a kind of field emission display device is used.
Background technology
Field-emitter display (FED) is comparatively novel a kind of in the flat-panel monitor, is the flat-panel monitor of new generation that the another kind after LCD (LCD), plasma scope (PDP), electroluminescent display (ELD) etc. has future most.The large tracts of land printing-type FED that our company researched and developed adopts low work function FED cathode material of exclusive low-cost large-area and cathode slurry thereof, has independent intellectual property right.Different with the FED of other kind, large tracts of land printing-type FED cost is low, and technology is simple, and institute's materials used has low work function characteristics, can reduce emission voltage required among the FED, makes external circuit oversimplify.We have developed 25 inches large color screen printing-type field-emitter displays at present, belong to initiative at home and abroad.The application number of being applied for by our company in October, 2004 is 200410103217.1 patent of invention " but integrated drive circuit for filed emission display of a kind of display color video image ", but this patent has been introduced a kind of integrated drive circuit for filed emission display of display color video image, the integrated chip HV632PG that this patent adopts the SUPERTEX company of the U.S. to provide, utilize the method for width modulation to realize the gray modulation of FED display, and be applied among the FED of 25 inches colours 240 * 3 * 320.But the gray modulation chip for driving in above-mentioned FED drive circuit system output has only 32 the tunnel, the ceiling voltage of output only is that 80 volts, maximum output current have only 4mA, and the driving tube switching speed is slower, it is not high to exist the displayed image contrast, the not high shortcoming of circuit level.
Summary of the invention
In order to overcome above-mentioned deficiency, the gray modulation driving method and the device thereof that the purpose of this invention is to provide a kind of field-emitter display (FED), but particularly a kind of field-emitter display gray modulation method and device thereof of display color video image, the present invention will further improve the integrated level of original circuit, improve the voltage pulse output of circuit, the image contrast that the FED display screen is shown improves greatly.
Method of the present invention realizes by following step:
1. the data with each row are divided into experimental process row (a common son display packing is that a frame is divided into the experimental process field), each son row was made of address period and demonstration phase, the address period time of each son row equates, and the ratio of the capable demonstration time span of each height is 1: 2: 4: 8: 16: 32: 64: 128 ... the 0th of gradation data used in the demonstration of each son row respectively, 1,2 ... controlled;
2. FPGA sends video data into shift register in address period, and when showing the phase, data latching also is enlarged into high-voltage pulse output, and in the capable demonstration phase of last height, the addressing that next height is capable is carried out simultaneously.
Apparatus of the present invention comprise the row display control module and data shift latchs the high pressure output unit, when start signal arrives, the row display control module just begins the RGB data-signal that order receiver, video plate was handled under the effect of clock, beginning at each row, the row display control module produces video memory and reads address signal, read in the data of delegation, and data are carried out pre-service and buffer memory; After showing beginning, divide into groups to give data shift in a certain order and latch the high pressure output unit, produce the control signal that data shift latchs the high pressure output unit simultaneously data processed.Data shift latchs exports to the FED display screen after the high pressure output unit amplifies data-signal.
Described row display control module comprises several data buffer unit, and data buffer unit is carried out pre-service and buffer memory to data.
Described data buffer unit is made up of 6 N * 16bit RAM pieces, the data of these RAM storing one row, the data of the 1st pixel are deposited in the address 1 of the 1st block RAM, the data of the 2nd pixel are deposited in the address 1 of the 2nd block RAM, the data of the 3rd pixel are deposited in the address 1 of the 3rd block RAM ... the data of the 6th pixel are deposited in the address 1 of the 6th block RAM; Next, the data of the 7th pixel are deposited in the address 2 of the 1st block RAM, and the data of the 8th pixel are deposited in the address 2 of the 2nd block RAM ... and the like.A data buffer cell can be stored the data of 6 * 16 pixels.And data are when reading, and are that the identical bits of getting the identical address of 6 block RAMs respectively is one group, read successively.
Described data shift latchs the high pressure output unit to be made up of some STV7610 chips, and described some is by calculating according to the resolution that shows.
Described data shift latchs the high pressure output unit to be made up of some μ pd16341 chips, and described some is by calculating according to the resolution that shows.
The software control flow process of described row display control module realizes by following steps:
1. counter O reset.
2. the data with delegation input to buffering, and the time of this process need is by the number of total picture element decision of row.
3. send the first sub data of going to shift register, 16 operating cycles of this process need.
4. the data of the first son row are kept several cycles of demonstration, meanwhile, the data of sending the second son row are to shift register, and the latter needs 16 operating cycles.
5. the data of the second son row are kept several cycles of demonstration, meanwhile, the data of sending the 3rd son row are to shift register, and the latter needs 16 operating cycles.
6. the data of the 3rd son row are kept several cycles of demonstration, meanwhile, the data of sending the 4th son row are to shift register, and the latter needs 16 operating cycles.
So continue.
7. in the end sub-line data is kept the data of importing next line in time of demonstration more successively, and the first sub-line data of next line is delivered to shift register.
8. 4.～7. step of circulation.
The invention has the advantages that 1. selected chip compares with HV632G and have higher integrated level, dwindled the volume of circuit widely, 2. the ceiling voltage of its output is 120 volts, improved the contrast of displayed image, improved image quality, 3. maximum output current reach 30mA or-45MA, can improve the brightness of demonstration effectively, 4. data shift latchs the driving load capacity of the chip that the high pressure output unit adopted greater than HV632PG, and the driving tube switching speed is very fast, can improve the precision that gray scale shows, improve image quality effectively, 5. use FPGA and produce the control signal that the integrated chip of high pressure output is latched in to data displacement, realize gray modulation the FED display, control flexiblely, extensibility is strong.
Description of drawings
To be described in further detail the present invention by specific embodiment below.
Fig. 1 is the block scheme of apparatus of the present invention.
Fig. 2 is the circuit theory diagrams of apparatus of the present invention.
Fig. 3 is a row display control module structured flowchart.
Fig. 4 is a μ PD16341 cut-away view.
Fig. 5 is the main signal timing diagram of μ PD16341.
Fig. 6 is the structural drawing of individual data buffer cell.
Fig. 7 is the fundamental diagram of row display control module.
Fig. 8 is the time distribution map of 8 son row.
Fig. 9 is the workflow diagram of row display control module.
Embodiment
As shown in Figure 1, device of the present invention latchs the high pressure output unit by row display control module and data shift and forms, as Fig. 2, shown in Figure 3, the row display control module comprises several data buffer unit, data shift latchs the high pressure output unit and is made up of some μ pd16341 chips, also can form by the identical chip of other functions, such as μ pd16337, STV7610, be that example describes to adopt μ pd16341 chip below, the input of the corresponding a slice μ of the output of each data buffer unit pd16341, in the time of the START signal comes, the RGB data-signal just begins to pass in proper order the row display control module under the effect of CLK clock.In the beginning of each row, the row display control module produces video memory and reads address signal, reads in the data of delegation, by data buffer unit data is carried out pre-service and buffer memory, and the row display control module produces the control signal to μ PD16341 simultaneously.The data presented that the row display control module will be handled in address period divides into groups to give each μ PD16341 in a certain order, and when showing the phase, data latch and be enlarged into high-voltage pulse output by μ PD16341.
Row display control module of the present invention latchs the high pressure output unit according to data shift and designs, and therefore is necessary to introduce earlier the inner structure of selected chip μ pd16341 here.As shown in Figure 4.μ pd16341 is the PDP special driving chip that NEC Corporation produces, and video data is imported by 6 data bus, and data input buffer comprises 6 16 shift register.Drive following video data at input clock and import each shift register successively, STB signal controlling output latch latchs the input data.The data input of μ pd16341 can be taked connected in series or parallel connection.Lead-in wire connected in series is less, but data must first block transfer arrive last one, and the address period holding time is more.Though the lead-in wire that parallel connection needs is more, the time that takies during the data parallel transmission is shorter.What the present invention adopted is parallel the connection.Shown in Figure 5 is the main signal timing diagram of μ pd16341, and the input data are sampled at rising edge clock, and when the STB level is low, data transfer to output latch by shift register, and when the STB level be a height, the output latch data remain unchanged.
According to the structure of μ pd16341, data buffer unit of the present invention is made up of 6 N * 16bit RAM pieces, and wherein N represents the data bits of each pixel.In the present embodiment, we divide 8 son row to send the data of each row, so each pixel data has 8, N=8.As shown in Figure 6, data buffer unit is made up of the RAM piece of 68 * 16bit, the row pixel data writes 6 block RAMs in order, the data of the 1st pixel are deposited in the address 1 of the 1st block RAM, the data of the 2nd pixel are deposited in the address 1 of the 2nd block RAM, the data of the 3rd pixel are deposited in the address 1 of the 3rd block RAM ... the data of the 6th pixel are deposited in the address 1 of the 6th block RAM; Next, the data of the 7th pixel are deposited in the address 2 of the 1st block RAM, and the data of the 8th pixel are deposited in the address 2 of the 2nd block RAM ... and the like.A data buffer cell can be stored the data of 6 * 16 pixels.In 6 position datawires of the corresponding μ pd16341 of each data buffer unit one, so data are when reading is that the identical bits of getting the identical address of 6 block RAMs respectively is one group, and the data of promptly same son row are read successively.
If the display screen picture resolution is 640 * 480, because every μ PD16341 can support 96 tunnel outputs,, 640 row need 7 μ pd16341 altogether so showing, also need 7 with the corresponding data buffer unit of μ pd16341.
Below we are 640 * 480 with the display screen picture resolution, frame frequency per second 30 frames, staggered scanning, 60 of per seconds are example, specify the principle of work of row display control module in conjunction with Fig. 2, Fig. 3, Fig. 7.If the display screen picture resolution is 640 * 480, frame frequency per second 30 frames, staggered scanning, 60 of per seconds, then corresponding frame length is 33.3ms.Gating time of each row is 69.4us, in order to realize 256 grades of gray scales, divides 8 son row to send data of each row, and the ratio of each sub-line time is 1: 2: 4: 8: 16: 32: 64: 128, the time of then boy's row was 271.267361ns.The high operation speed of the shift register of μ pd16341 inside is 40MHz, for the function (time of the phase of abbreviated addressing just) that makes full use of μ pd16341, the speed of data output preferably and its operating rate approaching.In FPGA, clock frequency is selected 39.3216MHz for use, and then the operating cycle of each line time correspondence was 2730.6667 cycles.The sub-line length of equivalence gets 10,21,42,85,170,340,680,1360 (cycle).Each son row was made of address period and demonstration phase.Fig. 8 is the time distribution map of 8 son row.Beginning at each row, the counter of steering logic clear 0 in the row display control module, simultaneously the control address generator generates column data address, and the packet of reading in deposits data buffer unit in, in 6 position datawires of the corresponding μ pd16341 of each data buffer unit one.In address period, our data that each height is capable write the shift register among the μ pd16341, because the shift register of μ pd16341 inside is 16, so address period needs 16 clock operation cycles.In the demonstration phase, the STB control signal is put height, and the input data are latched.The demonstration phase is exactly the equivalent length of each son row, except the first sub-line time is relatively shorter, all the other each son row time all greater than time of address period, therefore can allow the capable addressing of the capable demonstration of last height and next height carry out simultaneously, and utilize and in last son row demonstration time of lastrow in 1360 cycles, read in the data (needing 640 cycles) of next line and send the data presentation that first son of next line is gone.Divide according to top sub-line time, the fluorescent lifetime of actual loss only has several clock period, and is few to the fluorescent lifetime influence.Guaranteed the demonstration time so to the full extent, brightness and the display quality that improves display screen all played vital role.
According to above-mentioned principle of work, as shown in Figure 9, the software control flow process of row display control module realizes by following steps:
1. at each beginning of going, the counter in the steering logic clear 0.
2. the control address generator generates column data address, and the data of delegation are inputed to buffering, and the time of this process need is by the number of total picture element decision of row.Apparatus of the present invention are 640 operating cycles with the time that the data of delegation input to buffering.
3. send the first sub data of going to shift register, 16 operating cycles of this process need.
4. divide according to the time of front, the STB signal is put height, the data of the first son row are kept 10 cycles of demonstration, meanwhile, the data of sending the second son row are to shift register, and the latter needs 16 operating cycles.
5. the data of the second son row are kept 21 cycles of demonstration, meanwhile, the STB signal is put height, the data of sending the 3rd son row are to shift register, and the latter needs 16 operating cycles.
6. the data of the 3rd son row are kept 42 cycles of demonstration, meanwhile, the STB signal is put height, the data of sending the 4th son row are to shift register, and the latter needs 16 operating cycles.
So continue.
7. last sub-line data is kept and is shown 1360 cycles, during this period of time imports the data of next line more successively, and the first sub-line data of next line is delivered to shift register.
8. 4.～7. step of circulation.
Claims (7)
1, a kind of gray modulation driving method of field emission display device is characterized in that it realizes by following step:
1. the data with each row are divided into experimental process row (a common son display packing is that a frame is divided into the experimental process field), each son row was made of address period and demonstration phase, the address period time of each son row equates, and the ratio of the capable demonstration time span of each height is 1: 2: 4: 8: 16: 32: 64: 128 ... the 0th of gradation data used in the demonstration of each son row respectively, 1,2 ... controlled;
2. FPGA sends video data into shift register in address period, and when showing the phase, data latching also is enlarged into high-voltage pulse output, and in the capable demonstration phase of last height, the addressing that next height is capable is carried out simultaneously.
2, a kind of gray modulation drive unit of field emission display device, it is characterized in that it comprises the row display control module and data shift latchs the high pressure output unit, when start signal arrives, the row display control module just begins the RGB data-signal that order receiver, video plate was handled under the effect of clock, beginning at each row, the row display control module produces video memory and reads address signal, reads in the data of delegation, and data are carried out pre-service and buffer memory; After showing beginning, divide into groups to give data shift in a certain order and latch the high pressure output unit data processed, produce the control signal that data shift latchs the high pressure output unit simultaneously, data shift latchs the high pressure output unit data-signal is amplified back output.
3, the gray modulation drive unit of a kind of field emission display device according to claim 2 is characterized in that described row display control module comprises several data buffer unit, and data buffer unit is carried out pre-service and buffer memory to data.
4, the gray modulation drive unit of a kind of field emission display device according to claim 3, it is characterized in that described data buffer unit is made up of 6 N * 16bit RAM pieces, the data of these RAM storing one row, the data of the 1st pixel are deposited in the address 1 of the 1st block RAM, the data of the 2nd pixel are deposited in the address 1 of the 2nd block RAM, the data of the 3rd pixel are deposited in the address 1 of the 3rd block RAM ... the data of the 6th pixel are deposited in the address 1 of the 6th block RAM; Next, the data of the 7th pixel are deposited in the address 2 of the 1st block RAM, and the data of the 8th pixel are deposited in the address 2 of the 2nd block RAM ... and the like; A data buffer cell can be stored the data of 6 * 16 pixels, and data are when reading, and is that the identical bits of getting the identical address of 6 block RAMs respectively is one group, reads successively.
5, the gray modulation drive unit of a kind of field emission display device according to claim 2, it is characterized in that described data shift latchs the high pressure output unit and is made up of some STV7610 chips, described some is by calculating according to the resolution that shows.
6, the gray modulation drive unit of a kind of field emission display device according to claim 2, it is characterized in that described data shift latchs the high pressure output unit and is made up of some μ pd16341 chips, described some is by calculating according to the resolution that shows.
7, the gray modulation drive unit of a kind of field emission display device according to claim 2 is characterized in that the software control flow process of described row display control module realizes by following steps:
1. counter O reset;
2. the data with delegation input to buffering, and the time of this process need is by the number of total picture element decision of row;
3. send the first sub data of going to shift register, 16 operating cycles of this process need;
4. the data of the first son row are kept several cycles of demonstration, meanwhile, the data of sending the second son row are to shift register, and the latter needs 16 operating cycles;
5. the data of the second son row are kept several cycles of demonstration, meanwhile, the data of sending the 3rd son row are to shift register, and the latter needs 16 operating cycles;
6. the data of the 3rd son row are kept several cycles of demonstration, meanwhile, the data of sending the 4th son row are to shift register, and the latter needs 16 operating cycles;
So continue,
7. in the end sub-line data is kept the data of importing next line in time of demonstration more successively, and the first sub-line data of next line is delivered to shift register;
8. 4.～7. step of circulation.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101345021B (en) * | 2008-08-26 | 2010-12-22 | 福州大学 | Image gray scale modulation method and driving circuit of field-enhanced emission display used for big screen |
| WO2011113350A1 (en) * | 2010-03-17 | 2011-09-22 | 福州大学 | Low grayscale enhancing method for field emission display based on subsidiary driving technique |
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2006
- 2006-01-17 CN CN 200610005360 patent/CN101004882A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101345021B (en) * | 2008-08-26 | 2010-12-22 | 福州大学 | Image gray scale modulation method and driving circuit of field-enhanced emission display used for big screen |
| WO2011113350A1 (en) * | 2010-03-17 | 2011-09-22 | 福州大学 | Low grayscale enhancing method for field emission display based on subsidiary driving technique |
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