CN1008500B - Circuit for restricting transient tremble in exchange duration - Google Patents
Circuit for restricting transient tremble in exchange durationInfo
- Publication number
- CN1008500B CN1008500B CN 85106845 CN85106845A CN1008500B CN 1008500 B CN1008500 B CN 1008500B CN 85106845 CN85106845 CN 85106845 CN 85106845 A CN85106845 A CN 85106845A CN 1008500 B CN1008500 B CN 1008500B
- Authority
- CN
- China
- Prior art keywords
- phase
- input
- output
- operational amplifier
- oscillator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000001052 transient effect Effects 0.000 title claims abstract description 12
- 206010044565 Tremor Diseases 0.000 title abstract description 3
- 239000003990 capacitor Substances 0.000 claims abstract description 8
- 230000005055 memory storage Effects 0.000 claims 7
- 238000006243 chemical reaction Methods 0.000 claims 1
- 101100082028 Arabidopsis thaliana PLL2 gene Proteins 0.000 description 13
- 101100350613 Arabidopsis thaliana PLL1 gene Proteins 0.000 description 11
- 239000013078 crystal Substances 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Images
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- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The present invention relates to a circuit for restricting transient tremble in exchange duration. A phase comparator is connected to each input channel, and the clock phase of an input signal is compared with the phase of a local oscillator. The phase comparator of an inner work unit generates a signal for controlling the oscillator and causes the output of the oscillator to be kept consistent with the phase of the input signal, and generated controlling signals are connected to a memory capacitor of the phase comparator of the relevant channel. When the controlling signals are converted to a receiving channel, initial controlling voltage is provided for the oscillator, and therefore, the incontrollable state of the oscillator in the exchange duration is eliminated.
Description
The present invention relates to the exchange of PCm signal, more particularly, relate to a kind ofly between the commutation period of two digital signals, eliminate the circuit of transient state effect of jitter.
As everyone knows, between the commutation period of the identical digital signal of two features that receive with out of phase, its total transient state shake must remain on by within international recommendation (the G703 suggestion of CCITT) predetermined amplitude and the frequency limitation, to guarantee the total desired quality of digital signal downing code flow of swap operation.
A known solution to this problem is to use the location word of the digital signal that receives before exchange, to be somebody's turn to do the digital signal downing code flow clock signal frequency of exchange synchronously.
In theory, this solution has been avoided the transient state shake of exchange moment digital signal, but this way has been used quite complicated location word testing circuit.
The objective of the invention is to overcome whole shortcomings of non-transient exchange of the prior art.
More specifically, according to purpose of the present invention, the method that is limited in PCm signal transient state shake between commutation period has following feature, promptly before exchanging between two digital signals, a control voltage of voltage-controlled oscillator is added on the circuit, and between commutation period, this control voltage is remained under the control of voltage controlled oscillator, keep its phase place.
The invention still further relates to a kind of circuit of realizing said method.
The characteristics of this circuit are: this circuit comprises a feedback loop, this negative feedback loop route is before exchange, the control voltage of voltage-controlled oscillator is applied to first operational amplifier on its input and keeps from second operational amplifier between commutation period, the memory circuit of this oscillator control voltage was formed before its numerical value equaled to exchange.
Non-transient exchange according to the present invention provides compared with prior art a kind of, has the circuit of fairly simple and economic advantage, and the transient state shake that it is total maintains within the predetermined restriction.
With reference to the single square frame accompanying drawing of circuit according to the present invention, only provide from following in the example mode, there is no in the description of optimum implementation of limited significance, whole advantages of the present invention can become more obvious.
With reference to accompanying drawing, CK1 is illustrated in the clock signal of a digital signal of input 1; CK2 is illustrated in the clock signal of a digital signal of input 2; REECK represents the reference clock signal by the VCXO VCXO generation of a routine, this signal is added to two identical automatic phase control circuit PLL1 and the input of PLL2, and this signal is alternately controlled the phase place of voltage controlled crystal oscillator VCXO in the same way.
I1 and I2 represent two switches, according to a predetermined logic, come to determine the phase place of oscillator VCXO is locked onto by phase-control circuit PLL1 on the clock signal of digital signal of the input 1 that indicates CK1, or lock onto by phase-control circuit PLL2 on the clock signal of digital signal of the input 2 that indicates CK2.
△ φ represents input 1(CK1) or input 2(CK2) the phase place of clock signal of digital signal and a conventional phase comparator circuit comparing of the phase place of reference clock signal REFCK.
Signal VX1 represents on the input of operational amplifier IC3, the proportional direct voltage of phase difference between two input signal CK1 of the △ φ of its amplitude and phase comparator and the REFCK.
Signal V3 represents when switch I 1 closure, when switch I 2 disconnects simultaneously, equals the voltage on the output of operational amplifier IC3 of control voltage VC1 of voltage controlled crystal oscillator VCXO.This identical voltage V3 also is added to first input of the operational amplifier IC2 of first input of operational amplifier IC4 of phase-control circuit PLL1 and phase-control circuit PLL2.
Signal VX2 is illustrated on the non-inverting input of operational amplifier IC1, two input signal CK2 of the phase comparator of its amplitude and phase-control circuit PLL2 and the proportional direct voltage of phase difference between the REFCK.
Signal V1 represents when switch I 2 closures, when switch I 1 disconnects simultaneously, equals the output voltage of operational amplifier IC1 of the control voltage of voltage controlled crystal oscillator VCXO.This identical voltage V1 also is added to second reverse input end of the operational amplifier IC4 of second non-inverting input of operational amplifier IC2 of phase-control circuit PLL2 and phase-control circuit PLL1.
Signal V2 represents the output voltage of the operational amplifier IC2 of phase-control circuit PLL2; I3 represents a switch, when switch I 1 closure and switch I 2 disconnections, and switch I 3 closures.The closure of switch I 3 makes and signal voltage V2 can be added on the memory circuit of the phase-control circuit PLL2 that is made up of resistance R 11, R12 and capacitor C 11.Resistance R 13 is build-out resistors between second reverse input end of the operational amplifier IC1 of the output of memory circuit and phase-control circuit PLL2.
Signal V4 represents the output circuit of the operational amplifier IC4 of phase-control circuit PLL1; I4 represents a switch, when switch I 2 closures, when switch I 1 disconnects, switch I 4 closures, under this condition, signal voltage V4 is added on the memory circuit of the phase-control circuit PLL1 that is made up of resistance R 1, R2 and capacitor C 1, R3 represents a build-out resistor between another reverse input end of operational amplifier IC3 of the output of memory circuit and phase-control circuit PLL1.
With reference to accompanying drawing operation principle is in a circuit according to the invention explained in detail.
Suppose that VCXO VCXO has been phase-locked on the clock signal of the digital signal on first input CK1, then switch I 1 and I3 closure, and switch I 2 and I4 disconnection.
The voltage of V3=VL1 also is added to except the phase place of control VCXO VCXO on the input of operational amplifier IC2 of phase-control circuit PLL2, and be phase-control circuit PLL2 at its output, the memory circuit of being made up of capacitor C 11 and resistance R 11, R12 provides a fair piezoelectric voltage V2; This voltage provides a negative feedback voltage at the input of the operational amplifier IC1 of phase-control circuit PLL2, to keep phase-control circuit PLL
2Operational amplifier IC
4Output signal voltage V1 equal VC1, and and applied signal voltage, the numerical value of VX2 is irrelevant.
When changing between the supplied with digital signal, when just VCXO VCXO was phase-locked on the clock signal of second digital signal on the input CK2, then switch I 1, and I3 disconnects, switch I 3, I4 closure.
The control voltage of VCXO VCXO is V1=VC1 during beginning, and by the fair piezoelectric voltage of capacitor C 1 to maintain on the identical numerical value.
This signal voltage V1 will equal capacitor C 11 trends towards new numerical value VC2 from oscillator VCXO control voltage to the speed of resistance R 12 discharges with one then.
This discharge time constant by the memory circuit that capacitor C 11 and resistance R 12 are formed can be represented with T ≌ C11, R12, and be selected in such a way, the transient state shake that promptly gives signal should be within the restriction by international recommendation (CCITTC703 suggestion) predetermined amplitude and frequency.
After the transient state shake of exchange descended, phase-control circuit PLL2 was to operate as the mode of described phase-control circuit PLL2 in the above.
The voltage of V1=VC2 is except the phase place of control VCXO VCXO, also be added to the input of the operational amplifier IC4 of phase-control circuit PLL1, and be the signal voltage V4 that the memory circuit of phase-control circuit PLL1 is determined a fair electricity at its output, this memory circuit is set up a voltage that successively decreases at the operational amplifier IC3 of PLL1 input then, so that output at the operational amplifier IC3 of PLL1, keep signal voltage V3 and equal VC2, and press numerical value VX1 irrelevant with transmission of electricity.
Claims (5)
1, a kind of being used for carrying out between first channel and the second channel between commutation period, the circuit of restriction transient state shake, and it comprises:
A constant-frequency oscillator that includes an output and a control input end;
One first phase detectors and second phase detectors, each phase detectors has an input that is connected with input channel that it is associated, the another one input is connected to the output of said oscillator, other included devices detect the phase difference between the said input signal, and generation and the proportional control voltage of above-mentioned phase difference;
Be used for said control voltage is added to the jockey of the control end of said oscillator, thereby change the phase place of said oscillator output signal, make it with said phase of input signals unanimity, each said phase detectors also comprises a control voltage memory storage in addition;
Be used for the memory storage of phase detectors in work is added to another jockey on the memory storage of standby phase detectors, therefore said standby phase detectors have a utilizable control voltage and are added on the said oscillator under mode of operation;
It is characterized in that: wherein each said phase detectors also comprises a phase comparator and one first operational amplifier, said phase comparator has an output, first and second inputs, this first and second input is connected respectively to the output of said oscillator and the input channel that is associated, said operational amplifier has first, second input and an output, filter apparatus is connected to the first input end of said operational amplifier to the output of said comparator, includes said control voltage on the output of said operational amplifier;
Also comprise a feedback path that outputs to second input from said first operational amplifier in addition;
In each phase detectors, comprise conversion equipment, to keep when in running order, the output of operational amplifier being separated with said relevant memory storage.
2, circuit as claimed in claim 1 is characterized in that also comprising in the described feedback path resistance.
3, according to the desired circuit of claim 1, wherein said other jockey comprises that having output is connected to second operational amplifier on the said memory storage.
4, according to the desired circuit of claim 1, wherein said memory storage comprises a capacitor.
5,, comprise the resistance device that said memory storage electric capacity is connected to second input of said first operational amplifier according to the desired circuit of claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 85106845 CN1008500B (en) | 1985-09-12 | 1985-09-12 | Circuit for restricting transient tremble in exchange duration |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 85106845 CN1008500B (en) | 1985-09-12 | 1985-09-12 | Circuit for restricting transient tremble in exchange duration |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN85106845A CN85106845A (en) | 1987-03-11 |
| CN1008500B true CN1008500B (en) | 1990-06-20 |
Family
ID=4795316
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 85106845 Expired CN1008500B (en) | 1985-09-12 | 1985-09-12 | Circuit for restricting transient tremble in exchange duration |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1008500B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR970009688B1 (en) * | 1994-10-19 | 1997-06-17 | 엘지정보통신 주식회사 | Circuit for depreesing jitter |
| JP4569572B2 (en) | 2004-12-17 | 2010-10-27 | 三菱電機株式会社 | Clock signal generating apparatus and radio base station |
-
1985
- 1985-09-12 CN CN 85106845 patent/CN1008500B/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| CN85106845A (en) | 1987-03-11 |
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Legal Events
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| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C13 | Decision | ||
| GR02 | Examined patent application | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |