CN1007202B - Chrominance signal processing apparatus - Google Patents
Chrominance signal processing apparatusInfo
- Publication number
- CN1007202B CN1007202B CN 85104911 CN85104911A CN1007202B CN 1007202 B CN1007202 B CN 1007202B CN 85104911 CN85104911 CN 85104911 CN 85104911 A CN85104911 A CN 85104911A CN 1007202 B CN1007202 B CN 1007202B
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- China
- Prior art keywords
- signal
- circuit
- color difference
- chrominance signal
- burst
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Abstract
In the digital processing course of a chrominance signal, after a subcarrier chrominance signal is magnified by a variable-gain amplifier, the subcarrier chrominace signal is converted into a digital chrominance signal by an A/D digital converter. The digital chrominance signal is demodulated by a demodulator, and two color difference signals are obtained. An amplitude value of a color synchronization signal is calculated by an arithmetic circuit during the color synchronization period according to the two color difference signals. The amplitude value of the color synchronization signal passes through a low-pass filter, and the gain of the variable-gain amplifier is controlled. As a result, the electrical level of the color synchronization signal of the input end of the A/D converter is kept invariant.
Description
The present invention relates to a chrominance signal processing apparatus, as an automatic chroma control circuit (hereinafter referred to as the ACC circuit), be used for controlling the burst signal level, make it to remain unchanged, this system is applicable to the equipment of video tape recorder and the like.
In civilian video tape recorder, record and the used method of playback of video signal are: vision signal is resolved into luminance signal and carrier chrominance signal, and for carrier chrominance signal, use the ACC circuit to eliminate the fluctuating of chroma level.In addition, in recent years, handle the research work of this class signal with digital form and carrying out, and for the chroma level that makes carrier chrominance signal A/D converter input remains unchanged, it is important that the ACC circuit more and more seems.
Below, with reference to accompanying drawing conventional ACC circuit is described.Fig. 1 is the block diagram of the ACC circuit of routine.Among the figure, the subcarrier chrominance signal from input terminal 1 is sent into after variable-gain amplifier 2 amplifications, is sent to lead-out terminal 3 and synchro detection circuit 4.The carrier signal that synchro detection circuit 4 utilizes automatic phase control circuit (hereinafter referred to as the APC circuit) to be produced, synchronously detect subcarrier chrominance signal, wherein, the APC circuit produces a carrier wave, it is coaxial with the burst signal of subcarrier chrominance signal, and is sent to colour burst storbing gate 5.In the colour burst cycle, colour burst storbing gate 5 kept the level of input signal constant before the next colour burst cycle arrives.In subtracter 6, burst signal level with the subcarrier chrominance signal that has obtained deducts the reference level of importing with terminal 9, the difference signal of trying to achieve is by behind the low pass filter 7, control variable-gain amplifier 2 makes the burst signal level of subcarrier chrominance signal at output 3 places equate with above-mentioned reference level.
Yet, in above-mentioned formation, in case at sound intensity bust (for example, in video tape recorder, when generation is arrived the variation of colour signal with black-and-white signal, or when slow regeneration or fast playback time) after, subcarrier chrominance signal has appearred, and the APC circuit needs the regular hour could produce carrier signal with the burst signal homophase once more, during this, synchro detection circuit, circuit 2 misoperations, so that the ACC circuit can not be worked.
One object of the present invention is to provide a chrominance signal processing apparatus that the ACC circuit is such, is characterized in: even undesired and when failing to obtain carrier wave with the burst signal homophase at the APC circuit working, this system also can normally work.
The present invention also has another purpose.Subcarrier chrominance signal process A/D(analog/digital in signal processing) after the conversion, be demodulated to two color difference signals, and can obtain the amplitude of burst signal with these two color difference signals, in this process, the present invention simplifies circuit by reducing the figure place of a color difference signal to greatest extent.
In addition, the present invention also wants to provide a chrominance signal processing apparatus that circuit structure is simplified, in this system, to carrying out Digital Signal Processing through the subcarrier chrominance signal of A/D conversion, just can make the effective dynamic range of A/D converter input be best suited for standard manner of playback and slow-motion replay mode, prevent the decline of signal to noise ratio, and make that to change the fluctuating of subcarrier chrominance signal level of the A/D converter input that causes less owing to temperature or device property.
Chrominance signal processing apparatus of the present invention comprises: the variable-gain amplifier that can carry out gain controlling is used to amplify subcarrier chrominance signal; An A/D converter is used for the A/D conversion is carried out in the output of above-mentioned variable-gain amplifier, and a demodulator is used for demodulating two color difference signals from the output signal of A/D converter; A computing circuit, its function is calculated the amplitude of the burst signal level of subcarrier chrominance signal for according to two color difference signals that obtain above; A control circuit, it produces a control signal with the control variable gain amplifier according to the output of above-mentioned computing circuit.Like this, though the demodulation axis of demodulator not with the phase coincidence of burst signal, gain controlling also is unlikely to misoperation.
Can be clear that by above-mentioned explanation, in the present invention, after subcarrier chrominance signal is through the A/D conversion, be demodulated to two color difference signals, obtain the amplitude of burst signal to realize the control operation of ACC circuit by these two color difference signals again, even if such course of work makes that the ACC circuit still can operate as normal when the APC circuit erroneous action.In addition, because computing circuit is an amplitude of calculating burst signal according to the mode of digital signal, so, for instance,, computing circuit is simplified if adopt special connected storage.In addition, because computing circuit provides reference level with the digital quantity form, so system has a kind of inhibitory action, it reduces to the subcarrier chrominance signal fluctuation that temperature or components and parts change the A/D converter input that is caused than low degree.
Secondly, the present invention has a kind of good effect, and the figure place that promptly only reduces the R-y signal just can make circuit reduction, and the influence of the suffered quantization effect of ACC circuit there is no increase.
In addition, the present invention can prevent that the signal to noise ratio of carrier chrominance signal from descending, because change the chroma level of A/D converter input between standard mode and slow motion mode, just can utilize the effective dynamic range of A/D converter input to greatest extent.
Fig. 1 is conventional ACC circuit structure block diagram.
Fig. 2 is the block diagram of a preferable embodiment of the present invention.
Fig. 3 (a) and Fig. 3 (b) are two polar plots, in order to the vector correlation between expression demodulation coordinate and the burst signal.
Fig. 4 is the block diagram of another embodiment of the invention.
Fig. 5 (a) and figure (b) are a block diagram and working waveform figure, in order to the concrete demodulator that is adopted in key diagram 2 and two embodiments of Fig. 4.
Fig. 6 has provided the structure chart of the comb filter of reality that is used for Fig. 4 embodiment.
Fig. 7 is the structure chart of the computing circuit of a reality, is used in two embodiments among Fig. 2 and Fig. 4.
Below, preferable embodiment of the present invention is described with reference to the accompanying drawings.
Fig. 2 is a used ACC circuit block diagram in the scheme of the present invention.In the drawings, after subcarrier chrominance signal process variable-gain amplifier 11 amplifications with input terminal 10 inputs, convert digital signal to by A/D converter 12, then, demodulator 13 carries out demodulation to this signal, for example, and Jie's furnishing R-y signal and B-y signal.At this moment, APC circuit 18 produce required clock and the required carrier wave of demodulation of A/D conversion, and this carrier wave make it and the burst signal homophase, and the APC circuit is given A/D converter 12 and demodulator 13 respectively with these two signals by synchronously.R-y signal after the demodulation and B-y signal are given signal processing unit 14 and computing circuit 15.14 pairs of carrier chrominance signals of signal processing unit are handled, and make it to satisfy the requirement of video tape recorder.In computing circuit 15, control the synchronizing cycle of checking colors as follows, promptly in a colour burst cycle, computing circuit calculates square also addition of R-y signal and B-y signal respectively, calculate root sum square then, before the next colour burst cycle arrived, this square root remained unchanged.Ask these the two kinds of computings of quadratic sum extraction of square root to carry out in advance, for example, can weave into table to the result in advance, write read-only memory.
Owing to adopt above-mentioned operating state, so, even carrier signal that APC circuit 18 produces and burst signal is corresponding asynchronous, also can obtain the burst signal level at the output of computing circuit 15.To this, we are explained with reference to Fig. 3: Fig. 3 (a) is a polar plot, the relation between expression R-y axle, B-y axle and the burst signal three.At this moment, the carrier wave of demodulator 13 inputs is made it and the burst signal homophase by synchronously.The polar plot of Fig. 3 (b) shown in being is then undesired corresponding to 18 work of APC circuit, i.e. the situation of the carrier signal of demodulator 13 inputs and the different phase times of burst signal.
Find out that by Fig. 3 when APC circuit operate as normal, the burst signal component only appears on the B-y axle.Equally, by also seeing when the APC circuit working is undesired the appearance of burst signal component on R-y axle and B-y axle among Fig. 3 (b).Yet, by these two polar plots as can be seen no matter any situation, because the burst signal level is R-y component and the synthetic result of B-y component vector, therefore, as mentioned above, by the computing that computing circuit carried out, cause the demodulation reference axis to be offset to some extent even the APC circuit working is undesired, also can obtain the burst signal level.
The burst signal level that obtains with said method is sent to control circuit 21, and this control circuit is by subtracter shown in Figure 2 17, D/A(digital quantity/analog quantity) transducer 16 and low pass filter 20 form, in order to control variable-gain amplifier 11.The working method of control circuit 21 is as described below.The burst signal level of D/A converter 16 output is deducted reference level from input 19 by subtracter 17, and its difference is by behind the low pass filter 20, control variable-gain amplifier 11.As a result, the burst signal level of A/D converter 12 inputs just equals the reference level from input terminal 19.
Below, consider the quantization error effect problem in the present embodiment.The appearance of this quantization error is the result who burst signal is handled owing to digital form.When synchronizing signal is carried out digital processing, wish with many figure places.
On the other hand, as seen from Figure 3, when APC circuit operate as normal, only can obtain the burst signal level, and not need the component on the R-y axle with the component on the B-y axle.When the APC circuit erroneous action, by the explanation of front as can be known, when asking the burst signal level, also to use the component on the R-y axle, still, because the misoperation of APC circuit occurs over just the moment that colour signal is imported suddenly, therefore, the mistake probability of occurrence is very little, therefore, when APC circuit operate as normal, only reduce the figure place of R-y signal, can simplify circuit, and quantization error does not increase, in addition, even the APC misoperation, the ACC circuit also is unlikely misoperation.
In above-mentioned explanation, as an example, get R-y signal and B-y signal as color difference signal, yet, when one-component parallel (homophase) in another component, and the latter and burst signal be when being mutually right angle (quadrature), equally also can reduce the figure place of the component of that and burst signal quadrature.
Below, with reference to accompanying drawing another embodiment of the invention is described.
Fig. 4 is a chrominance signal processing apparatus block diagram in another embodiment of the invention.A subcarrier chrominance signal that is transformed into low frequency is with terminal 30 inputs, and the control signal of gain-controlled amplifier 31 is carried out level adjustment to it, and, A/D converter 32, conversion of signals after regulating is become digital signal, demodulate two color difference signals, B-y and R-y through demodulator then.Clock and carrier signal that A/D converter 32 and demodulator 33 are required are separately provided by APC circuit 37, then, demodulated B-y signal and R-y signal filter when video tape recorder works in slow regeneration by comb filter 46, are mixed in the crosstalk components of the adjacent track part in the replay signal.Filtered signal is given signal processing unit 34 and computing circuit 35.Computing circuit 35 detects the level of burst signal, its process is identical with first embodiment, the output signal of computing circuit deducts the reference level that is produced by reference level generator 39 through subtracter, and its difference is sent into D/A converter, is transformed into analog signal.Analog signal is by low pass filter 38 back control variable-gain amplifiers 31.As a result, the incoming level of A/D converter 32 is suitably controlled, and makes that the burst signal level after the filtering crosstalk components equals the reference level that reference level generator 39 produces.Therefore, putting slowly in the mode, the crosstalk components because the input of A/D conversion 32 has superposeed, at this moment the incoming level when making its incoming level overgauge working method so need to change the reference level value.In this embodiment, two kinds of reference levels are arranged, i.e. level 42 and level 43 in the reference level generator 39.When the design basis level generator, utilize inverter 44 and change over switch 40 and 41, the control criterion level makes it to be proportional to the control signal of delivering to terminal 45.
Structure according to above-mentioned this embodiment, the incoming level of optional A/D converter 32 is proportional to the control signal of delivering to terminal 45, so, when working in mode at a slow speed, when the neighboring trace track part brings crosstalk components, can adjusting knob, change level, make the unlikely dynamic range that surpasses A/D converter too much of the input of A/D converter 32, its difference otherwise greater than crosstalk components.For this reason, when system works is reset and during slow regeneration, be made full use of the effective dynamic range of A/D rotating speed device 32 inputs in standard, to prevent because the influence of quantizing noise makes signal to noise ratio decline.Top explanation is only at the playback occasion, but this system also can be used for writing down occasion.
Secondly, we are with reference to Fig. 5, and Fig. 6 and Fig. 7 illustrate demodulator 33 in the present embodiment respectively, the main composition of comb filter 46 and computing circuit 35.
Fig. 5 (a) is the concrete structure of demodulator.When this was illustrated, establishing the quantization number was 6, and sample frequency is four times of carrier chrominance signal frequency, and Fig. 5 (b) illustrates the situation that subcarrier chrominance signal is sampled, and wherein, sign O and sign X represent sampled point.When latch 90 when a sampled point latchs a sampled value, just obtain the signal among Fig. 5 (c).The each point that indicates " 0 " among the figure is sampled, just belong to this situation.Produce a clock signal by voltage controlled oscillator, behind 1/2 frequency divider, 97 frequency divisions, just obtain the latch signal of latch.Utilize a different OR circuit 91-96, every a clock cycle that the output signal of latch 90 is once anti-phase, just obtain understanding and transfer output, shown in Fig. 3 (d).In this case, we suppose that demodulation output is the B-y signal, utilize the same circuit shown in Fig. 5 (a) to latch with anti-phase and also can obtain the R-y signal, and its demodulation axis is led over the B-y signal with 90 °.Corresponding sampled point is marked among Fig. 5 (b) with sign " X ", so it can obtain the R-y signal in this way, this is because in this embodiment, selects sample frequency to equal four times of subcarrier frequency, so the spacing of two adjacent sampled points is corresponding to 90 °.
Fig. 6 illustrates, the basic structure of comb filter 46.The current signal and the signal plus of lastrow, can realize this comb filter, in the present embodiment, utilize shift register 100 as delegation's delay circuit, finishing operation, and this inhibit signal and current signal plus are got up with adder 101 to signal delay delegation.Handle R-y signal and B-y signal and use two filters.Also to use a memory for delegation's delay circuit.
Fig. 7 has provided an example of computing circuit.As previously mentioned, at the ROM(read-only memory) in 110, write a table in advance, can find respectively with this table the R-y signal quadratic sum B-y signal square, ask sum of the two then, with and square root.Suppose that R-y signal and B-y signal are respectively 6, the data that then have 12 bit address can deposit ROM110 in, and the data of exporting from ROM110 can obtain operation result.Be used to be kept at above-mentioned operation result in the latch cicuit 111, for a horizontal synchronizing cycle from the latch pulse of input terminal 112.
The structure of above-mentioned demodulator, comb filter and computing circuit is not limited to above-mentioned form, according to prior art, can also be modified as other various versions certainly.
Claims (1)
1, a kind of chrominance signal processing apparatus, it comprises:
A variable-gain amplifier can carry out automatic gain control to the amplification of subcarrier chrominance signal;
An A/D converter carries out mould/number conversion in order to the output signal to above-mentioned variable-gain amplifier;
A demodulator becomes two carrier chrominance signals in order to the output signal demodulation with A/D converter;
A computing circuit is in order to calculate the amplitude of the burst signal of described subcarrier chrominance signal according to above-mentioned two color difference signals;
A control circuit produces the gain that a signal removes to control described variable-gain amplifier in order to the output according to described computing circuit;
It is characterized in that, described demodulator has two different demodulation axis, to obtain phase difference is two color difference signals of 90 °, one of them demodulation axis and burst signal vector quadrature, and the figure place that will input to two color difference signals of described computing circuit is to distribute like this, promptly with the demodulation axis of burst signal vector quadrature on the figure place of color difference signal of demodulation less than the figure place of another color difference signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 85104911 CN1007202B (en) | 1985-06-27 | 1985-06-27 | Chrominance signal processing apparatus |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 85104911 CN1007202B (en) | 1985-06-27 | 1985-06-27 | Chrominance signal processing apparatus |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN85104911A CN85104911A (en) | 1987-02-18 |
| CN1007202B true CN1007202B (en) | 1990-03-14 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 85104911 Expired CN1007202B (en) | 1985-06-27 | 1985-06-27 | Chrominance signal processing apparatus |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1007202B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7948501B2 (en) * | 2004-03-09 | 2011-05-24 | Olympus Corporation | Display control apparatus and method under plural different color spaces |
-
1985
- 1985-06-27 CN CN 85104911 patent/CN1007202B/en not_active Expired
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| Publication number | Publication date |
|---|---|
| CN85104911A (en) | 1987-02-18 |
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