CN1007113B - Digital data converting method and apparatus thereof - Google Patents
Digital data converting method and apparatus thereofInfo
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- CN1007113B CN1007113B CN 85101048 CN85101048A CN1007113B CN 1007113 B CN1007113 B CN 1007113B CN 85101048 CN85101048 CN 85101048 CN 85101048 A CN85101048 A CN 85101048A CN 1007113 B CN1007113 B CN 1007113B
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Abstract
A digital signal is divided into a series of base words, and each base word has m bit data; then, each base word is converted to a conversion word having n bit data, wherein each n and each m are both integers, and n is larger than m; the conversion words have maximum numbers of a predetermined continuous number zero. The value of each odd bit of the conversion words is detected, and the conversion words are controlled according to the detection result. The conversion words are modulated in a form of an NRZI (non-return-to-zero and reversed phase) of encoding digital signals with a zero DC component.
Description
The present invention relates to a kind of method and equipment thereof of digital data conversion, relate more specifically to be applicable to sound signal or similar sound signal are carried out pulse code modulation (pcm), the digital data conversion method that writes down then and equipment thereof.
Resembling thisly becomes the PCM sound signal to an analog signal conversion such as sound signal or similar sound signal, need not to form a guard interval by adopting a rotating magnet head to carry out magnetic recording again, with high fidelity duplicating the equipment of this sound signal then, has been technique known.Among such known equipment, except difference output characteristic with magnetic recording and the low frequency cross-talk composition that from adjacent track, produces, owing to by resolver low-frequency component has been ended to fall, therefore the low-frequency component of sound signal with high fidelity can not have been duplicated out.
In above-mentioned equipment, require to have a very narrow recording playback frequency band and low-frequency component seldom; Therefore a tracer signal by a modulating system with a small amount of spectrum component, be modulated at low-frequency component and DC(direct current) zone of composition is effectively.We with so-called be the NRZI(non-return-to-reference, and anti-phase) a kind of modulating system describe as an example of such modulating system.In this NRZI system, when its data-signal is in level"1", carry out signal anti-phase; And it is not anti-phase when being in level "0".
Yet, not anti-phase in during this when continuous digital zero occurring in this NRZI modulating system this modulation signal, thereby the frequencies go lower of its signal.So, such shortcoming has just appearred, and promptly improved the DC(direct current) composition and low-frequency component.
Therefore, suggestion is divided into the figure place of some desired numbers with PCM digital information, and then corresponding of institute is converted to a more figure place of big figure; Thus, avoid the more appearance of the continuous number zero of big figure.
The applicant once proposed following information transition system in the past:
In this converting system, with eight position (B of digital information in the basic digital signal
1, B
2, B
3, B
4, B
5, B
6, B
7, B
8) convert ten position (P to
1, P
2, P
3, P
4, P
5, P
6, P
7, P
8, P
9, P
10).Can be these eight position (B
1, B
2, B
3, B
4, B
5, B
6, B
7, B
8) use 256(2
8) plant different modes and combine.
Because ten position (P are arranged
1, P
2, P
3, P
4, P
5, P
6, P
7, P
8, P
9, P
10), therefore in order to exclude this DC(direct current) composition, among the signal after its NRZI modulation, in these 10 positions, it is just " 1 " that 5 positions are arranged, 5 positions are negative " 0 ", and are just enough.In order to set up Tmax/Tmin=4(at this, Tmax is the maximum time interval between the level transition, and Tmin is the per hour interbody spacer between the level transition), in the middle of its NRZI-coding, require the number of continuous number zero to be less than 3, perhaps in the middle of the signal of having changed, require same level continue to be less than 4 such conditions.
Because restriction has as above been arranged, following table 1 has just illustrated the some possible combination of 10 digit order numbers in this NRZI code; For its DC(direct current) composition is zero, but wherein in delegation, do not have number of combinations more than three digital zeros (perhaps in the inside of per ten words, perhaps the intersection between two this ten words) again,
The table I
……1 ……10 ……100 1000……
1…… 69 34 14 4
01…… 40 20 8 1
001…… 20 10 3 1
0001…… 8 3 2 1
The explanation of table I has many possible combinations, is to satisfy above restriction.For example, if, allow three digital zeros at most, at the end of any one word, just any digital zero can not have been allowed so in beginning place of each word.In this case, the table I illustrates that its possible combination sum is:
137＝69+40+20+8
All possible number of combinations be it seems from the table I, if at the section start of ten hand-over words, does not allow more than two-digit zero, and does not allow at its end just to have reached the sum of a maximum more than a digital zero.In this case, this sum is exactly:
193＝69+40+20+34+20+10
Therefore, for its DC(direct current) composition is zero, can obtain 193 ten bit combinations.
These are referred to as meaning " elementary combination ".
Owing to the eight bit word of 256 possible initial data is arranged,, just requires 63 ten additional bit combinations therefore in order to represent all initial data.Thus, its DC(direct current) ten non-vanishing bit combinations of composition are necessary.
Below explanation of tables at the no more than two-digit of beginning place zero, and locate a no more than digital zero endways, and when being used as the NRZI-coding, have 0 ,-2 and+the 2DC(direct current) the possible combined number of ten bit combinations of composition.See Table II
It seems that from the table II very clear, its DC direct current is-2 possible combined number, can be expressed as:
52+43+30＝125
Equally also very clear, have+the galvanic possibility of 2DC combined number, can be expressed as:
100+40+11＝151
For the DC(direct current in the computational chart II) composition, last that suppose ten bit combinations formerly of its next one is on the low level " 0 " of signal, as shown in Figure 1A to 1C.If by suppose its formerly last level of word be high level " 1 ", will as shown in Fig. 2 A and Fig. 2 B, to do exchange mutually to " 2 " row and "+2 " row so.
In addition, if compared with having zero DC(direct current) combination of electricity comes, more be adopt alternately with have+2 and-the 2DC(direct current) combination of electricity, then the low-frequency spectra of its modulating wave will trend towards more minimizing.Therefore, adopt 125 have a pair of+2 and-the 2DC(direct current) combination of electricity, and for 256 combinations of 8, remaining will adopt 131 and have one zero DC(direct current) electric combination.Thus, make these 125 to make up and these 131 combinations, corresponding to 256 combinations of 8, then elect again one by one.
Because these combinations all have+and 2 and-2 paired DC(direct currents) electricity, so can select in pairs; So, only, just can control its DC(direct current by changing its first) electricity (in these a pair of combinations second and thereafter with, all constitute as same level).Therefore, for example have in those the possible combinations on the his-and-hers watches II+2 and-the 2DC(direct current) electricity and with the primary combination that " 0 " starts, can be represented by the formula:
40+11+43+30＝124
Therefore, in this case, just might make its 124 combinations and 132 have zero DC(direct current) combination of electricity, one by one corresponding to 256 combinations of eight.So, occur having ± the 2DC(direct current at every turn) and during the combination of electricity, with the DC(direct current) electrical alternations ground becomes is the mode of positive electricity and negative electricity, change its combination first.
Here it is as shown in Fig. 3 A and Fig. 3 B, when appearing at ± the 2DC(direct current) during the combination of electricity, just will count from second level transition number (i.e. digital 1 number).Count down to wherein always and have ± the 2DC(direct current) till the next one combination of electricity.If the number of level transition is an even number, just its first (representing it) with inverted triangle convert to the numeral 1, as shown in Figure 3A it, and if the number of level transition is an odd number, then its first, shown in Fig. 3 B, remain digital zero.So, even occurred ± the 2DC(direct current) electricity, they also can be by successive combination ± 2DC(direct current) electricity balances out; Therefore, the digital composition that comes with any connection is irrelevant, the DC(direct current) composition becomes is zero.
Incidentally, usually the DC(direct current of each) electricity is referred to as DSV(numeral summation variable), it is a kind of method of evaluation.Consider that formed combination is for example to resemble the zero DC(direct current of the band shown in Fig. 4 A) a kind of combination of electric ten bit patterns.When the transition of DSV is with DSV=1 at first, then the DSV transition of this combination is according to such variation the shown in the solid line among Fig. 4 B.
If the amplitude between the greatest measure of this DSV and the minimum value is very little, this DSV also just has very little DC(direct current so) the composition section, so its low-frequency component just has been reduced.As a kind of evaluation technique, also has a parameter that is referred to as to call the DSV variance usually.This DSV variance can be by means of asking the DSV numerical value of each square and ask on average and obtain, and wish that this DSV variance is as much as possible little.When the level of DSV=0 definition as to mean value of each DSV numerical value the time, the DSV level of relevant combination (code) waveform of encoding through NRZI-with regard to definable as DSVmax=-DSVmin.Therefore, under this situation, the DSV of intersection between each corresponding combination is got as+1 or-1, and the definition of the median between DSVmax and the DSVmin is still very suitable as DSV=0.
For this reason, let us is considered the above-mentioned conversion method of doing by means of the evaluation technique that adopts the DSV variance.For example in the middle of the combination shown in Fig. 4 A, when the evaluation of DSV variance, with DSV=+1 at first, then the transition of DSV is to change along that solid line shown in Fig. 4 B, and at this moment the DSV variance to become be 1.7.But when the evaluation of DSV variance, with DSV=-1 at first, then the transition of DSV is according to such change the shown in the dotted line among Fig. 4 B, and during this time, it is 6.9 that the DSV variance becomes.In other words, make each combination of same bit pattern have different DC(direct currents) characteristic, then will depend on the initial setting of this DSV.Specifically, in this case, when the evaluation of DSV variance with DSV=-1 at first, it is big that this DSV variance becomes, this is the situation that people do not expect to have.
Fig. 5 has illustrated the equipment example that can change according to above converting system.In Fig. 5, reference numbers 1 is indicated an input terminal; 2 is 8 bit shift register that can accept 8 information; 3 is conversion logic circuits, such as is a programmable logic array (PLA); And 4, be a clock terminal.So, by shift register 2, in response to eight eight ground transmit and are added to the information that input 1 gets on being added to a kind of pulse that clock terminal 4 gets on of bit-rate; And then these eight information (B
1, B
2, B
3, B
4, B
5, B
6, B
7, B
8) be provided to conversion logic circuit 3.
Reference numbers 5 is indicated a discriminator circuit, and this circuit can differentiate that its first is variable, or fixing, that is to say under this situation, the DC(direct current of this combination actually) electricity be " 0 " or ± 2.This discriminator circuit 5, such as, be by exclusive OR (being designated hereinafter simply as EOR) circuit 5a or 5c, and exclusive OR non-(being designated hereinafter simply as ENOR) circuit 5d form.In this discriminator circuit 5, circuit 5a to 5d realizes the modulus addition of the even bit of output from conversion logic circuit 3.In other words.This discriminator circuit 5 detects the number of the digital zero of these even bits, actually or even number odd number.If it is the 0(even number), this discriminator circuit 5 just thinks that this combination has ± the 2DC(direct current) electricity, and, promptly on the output of its ENOR circuit 5d, produce high level " 1 " at its output.That is to say that this discriminator circuit 5 is realized from all EOR logical operations of conversion logic circuit 3 output even bit outputs.In this case, when even bit is " 1 ", then realize the level transition among in this section; Thereby, this DC(direct current) electricity and last one the DC(direct current that is right after) electricity just becomes is 0.Yet when even bit was " 0 ", it just had ± the 2DC(direct current).In addition, when the time that has two-digit zero, then this DC(direct current) electricity just become be 0 or ± 4.In a similar fashion, when having three digital zeros, this DC(direct current then) electricity just become ± 2 or ± 6, in other words,, this DC(direct current then if the number of digital zero is an even number) electricity becomes is 0, ± 4, ± 8 And if the number of digital zero is an odd number, this DC(direct current then) electricity just becomes and is ± 2, ± 6, ± 10 ....On the other hand, the whole DC(direct current of these 10 positions) electricity, just be limited to 0 or-2.Therefore, actually the number even number of the digital zero by detecting above even bit, or odd number; Just might differentiate its DC(direct current) actually electricity 0, Hai Shi ± 2
With the output of this discriminator circuit 5, add to (AND) input of circuit 6; And with this and (AND) another input of circuit, receive again in the output of testing circuit 8.This testing circuit 8 is to receive the DC(direct current that is used for detecting each combination) output of shift register 7 of electricity (DSV) gets on.Up to the DC(of previous combination direct current) electric DSV, such as, be-1, this testing circuit 8 just provides high level output to this and (AND) input of circuit 6.
To be somebody's turn to do with the output of (AND) circuit 6 and supply with on the input of the EOR circuit 11 that makes the upset of first bit level.To change in the logical circuit 3 another input that first P in 10 positions coming supplies with this EOR circuit 11 certainly.Therefore, when this when (AND) circuit 6 is output as " 0 ", this first P level do not overturn, and presents same as before to shift register 7 again; And in the time should being output as " 1 " with (AND) circuit 6, this first P polarity upset presented to shift register 7 again.
In addition, in Fig. 5, EOR circuit 9 and D flip-flop circuit 10 constitute a NRZI modulation circuit.
Have again, in this testing circuit 8, adopt and (AND) circuit 8b and 8e, and or non-(NOR) circuit 8f, with its DC(direct current) electric DSV is initial be set to-1 or+1 on.When by means of counter 8a, on each one or two, in the time of to the DSV of its NRLI-modulating wave counting, if within the scope of DSV, the state of its DSV got as | DSV|≤3, will have many DC(direct currents so) electricity, as if-3 ,-2 ,-1,0 ,+1 ,+2 and+3.Therefore, by with (AND) circuit 8d and 8e, and or non-(NOR) circuit 8f, this DSV is initial be set to-1 or+1 on.
Like this, just can detect this DC(direct current) positive and negative electrode, then, be fed to and (AND) circuit 6 this detected signal and from the signal of discriminator circuit 5 again.Then, produce a control signal that is used for controlling the primary level of being exported with (AND) circuit 6.
As for, have zero DC(direct current) electricity and ± the 2DC(direct current) combination of electricity; Its conversion logic circuit 3 is to be suitable for producing any one combination in these combinations of unified standardization.In this respect, produce a kind of so unified output when this conversion logic circuit 3 and make its DC(direct current) when electricity is-2; If this combination of having changed has-the 2DC(direct current), and the evaluation of DSV variance is with the words of-1 beginning, pass through EOR circuit 11, just the primary level that draws has thus been overturn (during this time, being output as high level) so with (AND) circuit 6; Then, produce as having+the 2DC(direct current) an electric combination.Since, for having one zero DC(direct current) and electric combination, and this discriminator circuit 5 is output as low level, and should also be low level with the output of (AND) circuit 6; Therefore, need not on level, to overturn, just can directly produce this and make up by EOR circuit 11 first with it.
In addition, with the bit rate of its data, sync detection circuit 12 detects the impulsive synchronization of receiving clock terminal 4, and per 8 bit data ground will add to the load end LD of shift register 7 from the synchronizing signal of this sync detection circuit 12.
As mentioned above, convert 10 bit data forms and the interior perhaps data that are latched in the shift register 7 to, according to one be the clock signal of 5/4 overtones band of clock frequency that is added to input signal there from clock end 13, from this shift register, sequentially read.So the signal that will read from shift register 7 adds to the NRZI-modulation circuit again; By the NRZI-modulation circuit that EOR circuit 9 and flip-flop circuit 10 are formed, make the NRZI-coding by this, then be fed to output 14 again.
By the way, under the situation of sort circuit device,, adopted PLA as mentioned above wherein for conversion logic circuit 3.This circuit is used to detect its combination and has zero DC(direct current actually) electricity or have ± the 2DC(direct current) electricity, and similar requirement; Thereby this circuit arrangement is rather complicated.At this, we propose, if adopt the ROM(read-only memory) make conversion logic circuit 3, then without any problem.But ROM can cause this circuit arrangement to become big, and when with the IC(integrated circuit) form when making this ROM, this ROM will take a big pattern section, and will consume more power.In addition, in order to make its DSV variance little, require to have zero DC(direct current with two) electric combination antithesis as much as possible; Thereby according to DSV be+1, still-1 and use this to having any one in the less DSV variance.In this case, need such testing circuit, so that detect this to having identical zero DC(direct current) whether in electric two combinations first be variable.This just makes this circuit arrangement complicated more.
Moreover, if two a pair of combinations, all be not limited to such situation, be that the later some positions of second on its relaying all are to equate and all be situation about choosing from the value with little DSV variance, though its DSV variance can be accomplished smaller, but inevitably, this circuit arrangement can become and become increasingly complex.
Therefore, will consider not use the converting system of testing circuit.
In this converting system, when using wherein DC(direct current) when electricity is zero combination, that it is all first, be similar to direct current to DC() electricity is the conversion of ± 2 combination.So even when anti-phase the time, also constituting possible combination to first in 2 * 2 different modes, in other words, this 8/10-transition form must have 2 * 256 possible combinations.Therefore, suppose Tmax=5T ' (T '=the window limit of Tmin=Tw(detection window)).So the number of its available combination is more than 512 or 512.
Below the table III number that may make up that can satisfy condition to 10 information of Tmax=5T ' has been described.In this case, in order to satisfy the condition of Tmax=5T ', phase digital zero in succession must not be above four in nrzi encoding; Perhaps, all be that the digital signal of same level must not be above 5 in succession after modulating.Therefore, the position of beginning can only have two digital zeros at most; Equally, at most also can only there be two digital zeros the position of ending.See Table III
In the table III, with " 100 ... " the beginning information or word, if its first is anti-phase, then become for " 000 ... " Therefore, in its beginning place, just allowed three phases digital zero in succession.So, the intersection between combination in succession, probably the phase digital zero in succession that just has more than 4 or 4 has occurred; Thereby, in this conversion method, can not use such combination.As a result,, remove this 55(3+18+34 if among all possible combination) individual combination, in this table, just stayed 512 so and made up; This number is exactly the twice of the possible combined number of 2=256 just.
Therefore, may make up corresponding to 256 of 8 bit data, just can constitute 256 may make up, its each constitute have different primary a pair of.In this respect, table III explanation has 102 may make up, and wherein each may constitute and have zero DC(direct current) electric a pair of, and have different first; And have 154 may make up, and wherein each may constitute to be had ± the 2DC(direct current) electricity a pair of, and have different first.
In when conversion, by detecting which combination among the DSV=+1 and-1, make the less method of this DSV variance ratio select to make up right, as above-mentioned about Fig. 4, when this DC(direct current) electric when being-2, then the evaluation of this DSV variance begins with DSV=+1; And when this DS(direct current) when electricity was+2, then the evaluation of this DSV variance began with DSV=-1.
Fig. 6 (being made of Fig. 6 A to Fig. 6 E) expresses these possible combinations of 256 examples that may make up (code) and is based on the table III and chooses.Wherein, these possible combined codes and do not correspond to data.Fig. 6 explanation can only be passed through control, such as, control first antithesis of selecting two combinations.In Fig. 6, reference symbol Q ' indicated before changing, the DC(direct current of this code (combination)) electrical information (corresponding to previous DSV=DSV '); Reference character D V indicates the variance of its DSV; Reference symbol P indicates the number (even number is 0, and odd number is 1) of level transition in each code; And reference symbol Q indicate just change after, the DC(direct current of this code) electrical information (after just changing, the DSV of this code).When the circuit arrangement shown in Fig. 5 for example uses combined code among Fig. 6, use individually from 1 to 102 to have zero DC(direct current) electric code is right.
Fig. 7 schematically illustrates the example of realizing a device of its conversion according to this conversion method.In Fig. 7, with corresponding same part among those and Fig. 5, mark with identical reference symbol, therefore will be not described in detail.
In the example shown in Fig. 7, when conversion, first that these may be made up is variable; Therefore, it is variable being used to detect this first actually, or changeless circuit, its combination of i.e. detection as shown in Figure 5 is to have zero DC(direct current actually) electric combination (first is changeless), still have+the 2DC(direct current) electric combination (first is variable), or suchlike circuit 5 is just unnecessary.
So, in this example, will detect its DC(direct current) and the output of testing circuit 8 of electricity (DSV) input directly being added to EOR circuit 11 gets on.Other structure is all similar with Fig. 5.
This conversion logic circuit 3 produces it and has unified primary output, so just make this previous DSV ' become-1 or+1.Thus, suppose DSV '=+ 1 pair first work unified standardization.Then, when its combination of having changed during with DSV '=-1 beginning, as long as it is just enough that the output of the high level of this testing circuit 8 is added to EOR circuit 11; In this EOR circuit 11, make level with its first and overturn, then add to shift register 7 again.
So, with last similar, content and data in response to reading this shift register from the clock signal of clock end 13 from shift register then add to flip-flop circuit 10 to it by EOR circuit 9 again, just form the NRZI-encoded signals then on its output 14.
As above mentioned, do not adopt as shown in Figure 5 testing circuit 5(and with (AND) circuit 6) situation under, also can realize 8/10-conversion.
Yet, under the situation of the previous circuit of as above being mentioned, because the waveform that will adopt NRZI-coding in each combination is to this DC(direct current) and electricity counts; Therefore, detect this DC(direct current) electric testing circuit 8, structurally just become complicated, and on production cost, also become expensive.
An object of the present invention is to provide a kind of improved digital data conversion method and equipment thereof.
Another object of the present invention provides a kind of digital data conversion method and equipment thereof; Wherein, structurally can be the DC(direct current) power detection circuit simplifies.
A further object of the present invention provides one and has minimum low-frequency component, the DC(direct current) composition is substantially equal to zero NRZI(non-return-to-reference, and anti-phase)-code signal.
A further object of the invention provides and a kind ofly is used for a kind of basic digital conversion of signals become to have being substantially equal to zero DC(direct current) composition, and the method and apparatus that the NRZI-code conversion digital signal of a predetermined maximum time is arranged between the level transition.
According to an aspect of the present invention, provide a kind of method that is used for a digital conversion of signals is become a NRZI-code signal; This method includes following steps:
With a basic digital division of signal become a succession of each the primary word of m bit data is all arranged;
By the word that will change and the pairing of each above-mentioned primary word, this basic digital conversion of signals is become a digital signal of having changed; The word that each is above-mentioned has changed all has the n bit data, and wherein n is greater than m; And this digital signal of having changed has the phase digital zero in succession of a predetermined maximum number;
Whether detect the value of each odd bits of the above-mentioned word of having changed, digital zero;
According to above-mentioned testing result, produce a detection signal;
According to above-mentioned detection signal, the above-mentioned word of having changed is controlled; And
The above-mentioned digital signal of having changed is modulated the form that becomes the NRZI-coded digital signal.
According to another aspect of the present invention, provide a kind of equipment that is used for digital signal is converted into the NRZI-code signal; This equipment includes:
Be used for basic digital division of signal become a succession of each the classification apparatus of the primary word of m bit data is all arranged;
Be used for above-mentioned basic digital signal by the word of having changed and the pairing of above-mentioned primary word, be converted into the conversion equipment of the digital signal of having changed; The word that each is above-mentioned has changed all has the n bit data; Wherein, n is greater than m; And the above-mentioned digital signal of having changed has the phase digital zero in succession of predetermined maximum number;
The value that is used to detect each odd bits of the above-mentioned word of having changed is the checkout gear of digital zero;
Be used for producing the generation device of detection signal according to above-mentioned testing result;
Be used for controlling the control device of the above-mentioned word of having changed according to above-mentioned detection signal; And
Be used for the above-mentioned digital signal of having changed is become the generating means of NRZI-coded digital signal.
Other purposes of the present invention, feature and advantage all will be understood clearly from below in conjunction with the description of the drawings.Among institute's drawings attached, all indicate same element and parts with identical reference symbol.
Figure 1A to Fig. 1 C illustrates NRZI-coded digital signal presumable ten bit combinations of having changed respectively;
Ten bit combinations of the NRZI-coded digital signal that one of Fig. 2 A explanation has been changed;
Ten bit combinations shown in Fig. 2 B key diagram 2A; Its first by from digital zero anti-phase be the numeral one;
Fig. 3 A and Fig. 3 B illustrate the digital signal of having changed respectively;
Fig. 4 A and Fig. 4 B illustrate a digital signal of having changed respectively, and the DSV of this digital signal of having changed changes;
Fig. 5 schematically illustrates an equipment that is used for becoming from a basic digital signal in m position a n position NRZI-code conversion digital signal;
Fig. 6 (being made of Fig. 6 A to Fig. 6 E) is the chart of ten variant bit patterns of explanation;
Fig. 7 schematically illustrates an equipment that is used for producing from a basic digital signal in m position a n position nrzi encoding conversion digital signal;
Fig. 8 schematically illustrates the embodiment according to a kind of MSF of the present invention; And
Fig. 9 schematically illustrates according to another kind of the present invention, the embodiment of its MSF.
Below, we explain an embodiment of the method and apparatus that is used to change a digital signal according to the present invention with reference to the accompanying drawings.
What Fig. 8 illustrated is one embodiment of the invention.In this embodiment, circuit arrangement corresponding to according to the table II for the example of Tmax=4T ' conversion, i.e. circuit example shown in Fig. 5.Therefore, in Fig. 8,, and will no longer elaborate to them with corresponding those parts identical of same reference symbol mark with Fig. 5.
As mentioned above, under the situation of Tmax=4T ', have zero DC(direct current) electricity (first is changeless), and ± the 2DC(direct current) combination of electricity (first is variable); Therefore, must be distinguished from each other these two kinds of combinations and come.So this embodiment will be used used discriminator circuit in the example as shown in fig. 5, perhaps testing circuit 5.In this case, for example will use the toggle flip-flop circuit, make flip-flop circuit 10.
In the present invention, will be to not using the NRZI-coding waveforms, and the only odd number of the odd bits by checking this combination and/or the parity of even number just can be calculated the DC(direct current of this combination (for the combination of coming one after the other)) electric situation provides an explanation.
As mentioned above, in order to detect the DC(direct current of this combination) actually electricity 0, Hai Shi ± 2, consider the even bit of this combination.Subsequently, if the number of its digital zero is an even number, this DC(direct current so) electricity is exactly 0(DC=0), and if the number of its digital zero is an odd number, this DC(direct current then) electricity just is considered to ± 2(DC=± 2).In this case, suppose that its detection information is Pe.Therefore, if Pe=0, then DC(direct current) electricity is exactly 0; And if Pe=1, then DC(direct current) electricity is exactly ± 2.So, if conversion logic circuit 3, produce till that time have the DC(direct current) output of the sort of combination of electric DSV '=+ 1, so when Pe=1, just can be as to having-the 2DC(direct current) limit to electric combination this combination.Therefore, when Pe=1 and DSV '=-1, first bit level of this combination is turned into have+the 2DC(direct current) combination of electricity.
And then, it seems from the n bit combination of doing level upset as requested, promptly is 10 bit combinations in this case, its DC(direct current) electricity is the combination that is suitable for coming one after the other.We suppose that the odd number of this n bit combination and/or the parity of even number are P.So, for zero DC(direct current) and electricity, if P=0 then forms DSV=DSV '; And if P=1 then forms DSV=-DSV '.On the other hand, the DC(direct current for ± 2) electricity, if P=0, then DSV=-DSV '; And if P=1, then DSV=DSV '.Its reason is such, when the DC(direct current) when electricity was 0, this DSV was constant, so form DSV=DSV '.Yet, because in the combination of P=1, the level of the last position of its NRZI-coding is opposite with the level of last position in the previous combination, so, if this DSV is the level of the last position of hypothesis in its previous combination is low level and stipulate that last level in this combination is exactly a high level so; Cause such level for its combination of coming one after the other, just become low level.Therefore, to this DC(direct current) to carry out anti-phase be necessary for the code of electrical information.
DC(direct current for ± 2) if electricity is P=0, then its DC(direct current) state of electricity changes, and this DC(direct current) scope of electricity variation is limited in from+1 to-1, or from-1 to+1; Thereby, form DSV=-DSV ' at last.On the other hand, when forming P=1, level of this last position is the level that is different from last position in the previous combination; Therefore, form DSV=DSV ' at last.
In sum, have only when this DC(direct current) electricity is 0, and P=1, and this DC(direct current) electricity is ± 2, and P=0 the time, for this DC(direct current) electrical information, with the DC(direct current in its previous combination) electrical information does anti-phase just enough.Following table IV, the in a word fact of clear the above summary.
The table IV
DSV′ CD P DSV Pe Po
0 0 0 0 0
0 1 1 0 1
（-1） 0 1 1 1
+2 1 0 1 0
0 1 0 0
0 1 0 0 1
1
0 0 1 1
-2 1 1 1 0
In the table IV, reference symbol Po indicates the parity of odd number and/or even number for P and Pe.When the information Pe that detects is 0, DC(direct current then) electricity is 0; And when the information Pe that detects is 1, DC(direct current then) electricity is ± 2.So, be shown Po(Po=P+Pe at modulus addition table with P and Pe) condition under, when Po is 1, just with the DC(direct current) electricity level DSV anti-phase.
In addition, Pe represents signifying the parity of number " 0 ", though P represents signifying the parity of number " 1 ", makes even number if the n in m/n one conversion got, and P just may signify the parity of number " 0 " so.Therefore, we can say expression Pe and the odd number of P and/or the P of even parity, is the parity that is signifying number " 0 ".In other words, with this DC(direct current) electricity transmission information do anti-phase; Then, if on the odd bits of this combination, the parity that is signifying the odd number of number " 0 " and/or even number is that 1 words then send again.
For this reason, in this embodiment, in order to detect this DC(direct current) electricity, provide a testing circuit 20, this testing circuit 20 comprises: receive first and tertiary EOR circuit 20a in 10 positions in each combination; Receive its 5th and the 7th 's EOR circuit 20b; Receive the output of its EOR circuit 20b and the 9th EOR circuit 20c thereof; Receive the ENOR circuit 20d of the output of the output of its EOR circuit 20a and EOR circuit 20c thereof; And the D flip-flop 20f of the output of EOR circuit 20e and reception EOR circuit 20e.The input that the output of this ENOR circuit 20d is added to EOR circuit 20e gets on.Another input that the Q output of this D flip-flop 20f is received EOR circuit 20e gets on; And the output of this EOR circuit 20e is received the D-input of this D flip-flop 20f and is got on.Another input that the Q of this flip-flop circuit 20f output is added to this EOR circuit 20e gets on, and simultaneously, the reversed-phase output Q of this flip-flop circuit 20f is added to (AND) another input of circuit 6.
EOR circuit 20a to 20c gets the parity of its odd bits.In this case, if the number of n is got work 10, because the number of this odd bits is 5, so last such parity is become the number that parity is signifying " 0 " by ENOR circuit 20d paraphase.When the value of this parity is 1, then on next stage,, that the output of flip-flop circuit 20f is anti-phase by EOR circuit 20e.In other words, previous DC(direct current) upset of electrical information level, then be added to flip-flop circuit 20f again and get on.Subsequently, for when the DSV '=-1, when promptly signal level is " 0 ", send signal level " 1 "; Just produce anti-phase output Q among the slave flipflop circuit 20f; Then, again it is fed to (AND) another input of circuit 6.
So, when the DC(direct current) and when electric DSV ' was-1, this testing circuit 20 produced high level output.
On the other hand, as mentioned above, when this DC(direct current) when electricity was-2, this discriminator circuit 5 produced high level output; So, when the output of this discriminator circuit 5 and this testing circuit 20 is all high level, should produce signal " 1 " with (AND) circuit 6.Then, an input that again output with (AND) circuit 6 is added to EOR circuit 11 gets on.At this moment, first among this EOR circuit 11 another input that is added to this EOR circuit 11 from conversion logic circuit 3 is got on 10 is anti-phase, then again it is added to shift register 7.
As mentioned above, in this embodiment, need not to use the NRZI-coding waveforms, only, just can calculate the DC(direct current of the combination that is used to come one after the other) by the odd number of the odd bits in each combination of inspection and/or the parity of even number; Therefore, can simplify this circuit arrangement.
Owing to have-the IDC(direct current) electric reaching+the IDC(direct current) electricity these two states (being exactly that " 0 " reaches " 1 " on signal level) so in the process that begins to modulate, DSV ' can be 1, also can be-1.Therefore, as shown in Fig. 5 and Fig. 7, for when beginning the DC(direct current) electric DSV is set to+1 or-1 do not go and adopt with (AND) circuit 8d and 8e and or the circuit of non-(NOR) circuit 8f, be unwanted.
Fig. 9 schematically illustrates another embodiment of the invention.This embodiment is corresponding to the example about Tmax=5T ' conversion according to the table III, i.e. circuit example shown in Fig. 7.Therefore, in Fig. 9, with same reference symbol mark those corresponding to part identical among Fig. 7, and will no longer elaborate.
As mentioned above, under the situation of Tmax=5T ', all first is being done have the DC(direct current under the state of conversion) combination of electricity has by similarly using ± the 2DC(direct current) combination of electricity.As a result, use that used testing circuit 5 is unnecessary among the figure such as Fig. 8.In this case, therefore, only need to be used for inspection and become the DC(direct current) electric testing circuit, thereby used used testing circuit 20 among Fig. 8.In this case, the output of this testing circuit 20, i.e. the reversed-phase output Q of this flip-flop circuit 20f, an input that directly is added to this EOR circuit 11 gets on.
Also have, in this case, if having, such as, in the combination of DSV=+1, carry out under the standardization, produce words from the output of conversion logic circuit 3; When this combination of having changed is with DSV=-1 at first, then, add to EOR circuit 11 from this testing circuit 20 with its high level output; At this EOR
The table II
The DC(direct current)-2 0+2
First
11…… 40 60 43
1…… 101 52 11 103 30 100 30
100 1 13 27
01…… 43 60 40
001…… 30 30 11
The table III
The DC(direct current)-2 0+2
First
11…… 51 68 52
1…… 101…… 71 17 120 34 120 34
1001…… 3 18 34
01…… 52 68 51
0…… 86 102 68
001…… 34 34 17
Among the road 11, first that adds to it anti-phase, then again it is fed to shift register 7 and gets on.
As mentioned above, according to this embodiment, in fact may reach effect and the effect similar fully with first embodiment.Specifically, compare with first embodiment, this embodiment does not need other circuit 5 that reflects; Therefore, can simplify its circuit arrangement more.
In the present invention, by means of a satisfactory demodulator circuit, just can be according to as mentioned above demodulation being carried out in the combination of having changed.
Simultaneously, in the embodiment under described Tmax=4T ' and the Tmax=5T ' situation, the present invention is not limited to above situation, and the combination that can be applied to other is got on.These combinations include wherein at least the DC(direct current) electric control is to less than ± 2 combination, for example, can be controlled to so that have zero DC(direct current with one) the mutually compound combination of combination of electricity, and its DC(direct current) electricity is changeless, or the like.
Above explanation optimum implementation according to the present invention provides; but; obviously; professional in this professional domain just can realize many modifications and variation not breaking away under spirit of the present invention or the new design scope; therefore, protection scope of the present invention should only be determined by appended claim.
Claims (5)
1, a kind of being used for is converted into NRZI (non-return-to-reference with digital signal; And anti-phase)-method of code signal; It is characterized in that this method includes the following step:
With a basic digital division of signal become a succession of each the primary word of m bit data is all arranged;
By the word that will change and the pairing of each above-mentioned primary word, this basic digital conversion of signals is become a digital signal of having changed; The word that each is above-mentioned has changed all has the n bit data, and wherein n is greater than m; And this digital signal of having changed has the phase digital zero in succession of a predetermined maximum number;
The value that detects each odd bits of the above-mentioned word of having changed is a digital zero;
According to above-mentioned testing result, produce a detection signal;
According to above detection signal, the above-mentioned word of having changed is controlled; And
The above-mentioned digital signal modulation of having changed is become the NRZI-coded digital signal.
2, a kind of method that is used for digital signal is converted into a kind of NRZI-code signal; It is characterized in that this method includes following step:
With a basic digital division of signal become a succession of each the primary word of eight bit data is all arranged;
With each above-mentioned primary word be converted into a conversion with ten bit data word;
Whether detect the value of each odd bits of the above-mentioned word of having changed, digital zero;
Parity according to the above-mentioned digital value among each odd bits of the above-mentioned word of having changed produces a detection signal;
According to above-mentioned detection signal, control the above-mentioned word of having changed first; And
With the above-mentioned word of having changed, modulation becomes the NRZI-code.
3, a kind of equipment that is used for digital signal is converted into a kind of NRZI-code signal; It is characterized in that this equipment includes:
Be used for basic digital division of signal become a succession of each the classification apparatus of the primary word of m bit data is all arranged;
Be used for above-mentioned basic digital conversion of signals being become the conversion equipment of the digital signal of having changed by word of having changed and above-mentioned primary word matched; The word that each is above-mentioned has changed all has the n bit data; Wherein, n is greater than m; And the above-mentioned digital signal of having changed has the phase digital zero in succession of predetermined maximum number;
The value that is used to detect each odd bits of the above-mentioned word of having changed is the checkout gear of digital zero;
Be used for producing the generation device of detection signal according to above-mentioned testing result;
Be used for control device according to the above-mentioned word of having changed of above-mentioned detection signal control; And
Be used for the above-mentioned digital signal of having changed is become the generating means of NRZI-coded digital signal.
4, a kind of be used for basic digital conversion of signals become have a kind of DC(direct current) composition is substantially equal to zero, and has the equipment of the NRZI-code signal of a predetermined maximum time between the level transition; It is characterized in that this equipment includes:
Be used for basic digital division of signal become a succession of each the classification apparatus of the primary word of m bit data is all arranged;
Be used for above-mentioned primary word be converted into conversion with n bit data the storage arrangement of word; Wherein n is greater than m; And the above-mentioned word of having changed has the phase digital zero in succession of predetermined maximum number;
The digital value that is used to detect each odd bits of the above-mentioned word of having changed is digital zero, and is used for the parity according to above-mentioned digital value among each odd bits of the above-mentioned word of having changed, produces the checkout gear of a detection signal;
Be used for according to above-mentioned detection signal, first of the above-mentioned word of having changed carried out anti-phase control device; And
Be used for the above-mentioned tone of Chinese characters of having changed is made for a kind of modulating device of NRZI-code.
5, a kind of according to the equipment in the claim 4, it is characterized in that above-mentioned detection device wherein includes the logic device that is used for producing according to the parity of the above-mentioned digital value among each odd bits of the above-mentioned word of having changed above-mentioned detection signal; And a kind of being used for keeps the memory circuit of above detection signal in each change-over period.
6, a kind of according to the equipment in the claim 5, it is characterized in that wherein above-mentioned logic device includes different one or circuit, and above-mentioned memory circuit includes flip-flop circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 85101048 CN1007113B (en) | 1985-04-01 | 1985-04-01 | Digital data converting method and apparatus thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 85101048 CN1007113B (en) | 1985-04-01 | 1985-04-01 | Digital data converting method and apparatus thereof |
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| Publication Number | Publication Date |
|---|---|
| CN85101048A CN85101048A (en) | 1987-01-10 |
| CN1007113B true CN1007113B (en) | 1990-03-07 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 85101048 Expired CN1007113B (en) | 1985-04-01 | 1985-04-01 | Digital data converting method and apparatus thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100361896C (en) * | 2006-03-01 | 2008-01-16 | 杜文新 | Method for recycling energy in borax production process by carbon-alkali method |
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| CN103679857A (en) * | 2012-08-31 | 2014-03-26 | 深圳光启创新技术有限公司 | Mobile phone photon client coding method |
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1985
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100361896C (en) * | 2006-03-01 | 2008-01-16 | 杜文新 | Method for recycling energy in borax production process by carbon-alkali method |
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| Publication number | Publication date |
|---|---|
| CN85101048A (en) | 1987-01-10 |
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