CN100590889C - Semiconductor device and producing method thereof - Google Patents
Semiconductor device and producing method thereof Download PDFInfo
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- CN100590889C CN100590889C CN200610148250A CN200610148250A CN100590889C CN 100590889 C CN100590889 C CN 100590889C CN 200610148250 A CN200610148250 A CN 200610148250A CN 200610148250 A CN200610148250 A CN 200610148250A CN 100590889 C CN100590889 C CN 100590889C
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Abstract
The invention relates to a semiconductor apparatus and a manufacturing method thereof. The semiconductor apparatus comprises a semiconductor substrate, a gate dielectric layer positioned on the semiconductor substrate, a gate positioned on the gate dielectric layer and a gap wall positioned on the two sides of the gate on the gate dielectric layer, as well as a source cathode and a drain between the two sides of the dielectric layer in the semiconductor layer. The semiconductor apparatus also comprises a joint interface layer extending along the surface of the source cathode and drain and thejoint interface layer extending along the gate surface. The joint interface layers insulate and isolate with the gate dielectric layer. The joint interface layers of the semiconductor apparatus contain doping interface providing a continuous electronic states, which can complete the electron transmission under low effect of an electric field, thus reducing the contact desistence between the semiconductor and the joint metal of the contact hole. And the invented manufacturing method of the semiconductor apparatus can be used in the process in the wide range heavy doping source leakage area, thus increasing the flexibility of the manufacturing process and reducing the process cost.
Description
Technical field
The present invention relates to semiconductor device and preparation method thereof, interconnect structure and preparation method thereof between particularly a kind of semiconductor device.
Background technology
The device architecture of traditional semiconductor memory is the memory construction that provides for 03145409 Chinese patent of application number for example, as shown in Figure 1, be formed with gate dielectric 2 and grid 3 on the Semiconductor substrate 1 successively, described gate dielectric 2 is silicon dioxide or silica-silicon-nitride and silicon oxide layer etc., and described grid 3 is a polysilicon layer.The both sides of gate dielectric 2 and grid 3 have clearance wall (spacer) 5, and the material of clearance wall 5 is silicon dioxide, silicon nitride or silicon oxynitride etc., is formed with source-drain electrode 6 in the Semiconductor substrate 1 of clearance wall 5 both sides.
In the application and manufacture craft of reality, because considering of the engineering design of source-drain electrode for fear of the ionization by collision effect that hot current-carrying ion causes, adopted lightly-doped source/drain electrode (lightly dopedsource/drain, LDD) structure usually.As shown in Figure 2, have gate dielectric 12 and grid 13 on the Semiconductor substrate 11 successively, in the Semiconductor substrate 11 of gate dielectric 12 both sides, be formed with low doping source drain region 14, the both sides of gate dielectric 12 and grid 13 have clearance wall 15, are formed with heavy-doped source drain region 16 in the Semiconductor substrate 11 of clearance wall 15 both sides.An effect in heavy-doped source drain region 16 is: be connected Metal Contact in the contact hole, form the ohmic contact (Ohmic Contact) of low contact resistance.When carrying out metal line, 17 expressions,, require metal is infiltrated the heavy-doped source drain region in order to reach lower contact resistance with the interior ohmic contact regions that is connected Metal Contact of contact hole.Ohmic contact regions has the suitable degree of depth.
Above-mentioned semiconductor component structure with clearance wall becomes the motive force of semiconductor technology evolves.Along with the develop rapidly of semiconductor fabrication, semiconductor chip develops towards higher device density, high integration direction.Therefore, the size of semiconductor element is also done littler and littler; The channel length of element is more and more short, and the doped source of requirement/drain electrode degree of depth is also more and more shallow.
Manufacture craft development for ohmic contact regions can be with reference to SiliconMaterial and Device Characterization 2nd Edition 1998 John Wiley and Sons with the method for measurement of contact resistance, byDieter K.Schroder, the the 133rd to 142 page, when the heavy doping ion concentration range is increased to 5E20/cm by 2E17
3The time, the contact resistance value scope of n type silicon and ohmic contact that metal forms reduces to 3E-8 Ω/cm by 1E-3
2, when the heavy doping ion concentration range is increased to 5E20/cm by 1E16
3The time, p type silicon and metal form an ohm contact resistance value that connects and reduce to 1.5E-8 Ω/cm from 6E-3
2The dopant ion concentration of this technology changes 4 rank, and the variation of contact resistance value reaches rank 5 times, and the variation of contact resistance is by regulating doped region dopant ion concentration and regulating electronic barrier, and dopant ion concentration is higher, and potential barrier reduces.Therefore, this technology strictness relies on the concentration of dopant ion, has limited the degree of depth of source-drain area.
According to the achievement in research (1996 IEEE Symposium on VLSI TechnologyDigest, 14-15 page or leaf) of Texas Instrument, the source-drain area that utilizes Titanium silicide to form, the degree of depth of source-drain area can drop to 500 dusts.The research paper of Toshiba (1994 IEEE Transaction on ElectronDevices, Vol.41, No.12,2305-2317 page or leaf) for example again, the source-drain area that utilizes titanium or nickel silicide to form, wherein the degree of depth of Titanium silicide can reach near 300 dusts.
Along with constantly reducing of semiconductor element supply power voltage, the tunnel degree of depth and junction depth, the dopant ion density in low doping source drain region is near the dopant ion density in heavy-doped source drain region, to satisfy the needs that reduce contact resistance.Therefore, again by the interior Metal Contact that is connected of heavy-doped source drain region and contact hole, the technology that forms the ohmic contact of low contact resistance has seemed and has not been very needs, and the technology cost that forms the heavy-doped source drain region is also higher.
Summary of the invention
The problem that the present invention solves provides a kind of semiconductor device and preparation method thereof, reduces device doped region and the interior contact resistance that is connected metal of contact hole, and helps reducing the technology cost.
For addressing the above problem, the invention provides a kind of semiconductor device, comprise Semiconductor substrate, be positioned at gate dielectric on the Semiconductor substrate, be positioned at the grid on the gate dielectric and be positioned at the clearance wall of the grid both sides on the gate dielectric, and the source electrode and the drain electrode that are positioned at the gate dielectric both sides in the Semiconductor substrate, also comprise linkage interface layer that is positioned at source electrode and drain surface extension and the linkage interface layer that extends along gate surface, described linkage interface layer and gate dielectric layer insulation are isolated.
Wherein, described linkage interface layer is the metal reaction alloy, described alloy is any one in oxygen, nitrogen, hydrogen, boron, arsenic or the phosphorus, the reaction alloy of the reaction alloy that described metal reaction alloy is a cobalt, the reaction alloy of nickel, molybdenum, the reaction alloy of titanium, the reaction alloy of copper or the reaction alloy of niobium.
Perhaps, described linkage interface layer be cobalt metal silicide, the metal silicide of nickel, the metal silicide of molybdenum, the metal silicide of titanium, the metal silicide of copper or the metal silicide of niobium.Contain any one alloy in aerobic, nitrogen, hydrogen, boron, arsenic or the phosphorus in the described metal silicide.
The thickness of the thickness linkage interface layer of described linkage interface layer is 10 to 50 dusts greater than 0 smaller or equal to 100 dusts preferably.
The present invention also provides a kind of manufacture method of semiconductor device, comprises the steps:
Provide Semiconductor substrate, the source electrode and the drain electrode that are formed with gate dielectric on the Semiconductor substrate, are positioned at the grid on the gate dielectric and are positioned at the clearance wall of the grid both sides on the gate dielectric and are positioned at the Semiconductor substrate of gate dielectric both sides;
On described Semiconductor substrate, form mask, the Semiconductor substrate outside leak in the sidewall of cover gate and clearance wall and source;
Formation is along the linkage interface layer of source electrode and drain surface extension and the linkage interface layer that extends along gate surface;
Remove described mask.
Compared with prior art, the present invention has the following advantages:
1, semiconductor device provided by the invention has the linkage interface layer in source electrode and drain electrode and gate surface extension, described linkage interface layer contains available electronic state continuously, under very low electric field action, can finish electric transmission, reduce the contact resistance between the metal of being connected with contact hole.
2, semiconductor device provided by the invention can make the dopant ion concentration of source electrode and drain electrode change in the larger context, the continuous electronic state that utilizes the linkage interface layer to be provided, even under lower dopant ion concentration conditions, also can reach the low resistance ohmic contact.
3, semiconductor device provided by the invention can use the dopant ion concentration of different source electrodes and drain electrode, to distinguish core and output/input element.Utilize lower dopant ion concentration output/input element, can improve chip reliability.
But therefore the technology in the heavy-doped source drain region that 4, the present invention scope of application is wider reduced the technology cost.
Description of drawings
Fig. 1 is the structural representation of prior art semiconductor device;
Fig. 2 is the structural representation that prior art comprises the semiconductor memory of ohmic contact regions;
Fig. 3 is the semiconductor device structure schematic diagram that the present invention forms;
Fig. 4 A to Fig. 4 E is a manufacturing method of semiconductor device process structure schematic diagram of the present invention.
Embodiment
Essence of the present invention is to be formed with along the linkage interface layer of source electrode and drain surface extension at source electrode and the corresponding zone of drain electrode, described linkage interface layer is the metal reaction alloy, described alloy is an oxygen, nitrogen, hydrogen, boron, in arsenic or the phosphorus any one, the reaction alloy that described metal reaction alloy is a cobalt, the reaction alloy of nickel, the reaction alloy of molybdenum, the reaction alloy of titanium, the reaction alloy of copper or the reaction alloy of niobium, perhaps contain oxonium ion, the nitrogen ion, hydrogen ion, the boron ion, arsenic ion, the perhaps metal silicide of any one ion in the phosphonium ion, described metal reaction alloy or metal silicide contain available electronic state continuously, under very low electric field action, can finish electric transmission, reduce the contact resistance between the metal of being connected with contact hole.
Semiconductor device of the present invention, with reference to the accompanying drawings shown in 3, comprise Semiconductor substrate 100, be positioned at gate dielectric 110 on the Semiconductor substrate 100, be positioned at the grid 120 on the gate dielectric 110 and be positioned at the clearance wall 130 of grid 120 both sides on the gate dielectric 110, and the source electrode 140 and the drain electrode 150 that are positioned at gate dielectric 110 both sides in the Semiconductor substrate 100, also comprise along the linkage interface layer 180 of source electrode 140 and drain electrode 150 surface extensions and the linkage interface layers 180 that extend along grid 120 surfaces described linkage interface layer 180 and gate dielectric layer 110 insulation isolation.
Described Semiconductor substrate 100 can comprise the silicon or the SiGe (SiGe) of monocrystalline or polycrystalline structure, can also be to contain for example silicon or the SiGe that mix of N type or P type of dopant ion, the semiconductor structure that also can comprise mixing, for example carborundum, indium antimonide, lead telluride, indium arsenide, indium phosphide, GaAs or gallium antimonide, alloy semiconductor or its combination; It also can be silicon-on-insulator (SOI).
Described gate dielectric 110 can be silica (SiO
2) or silicon oxynitride (SiNO).At the following process node of 65nm, the characteristic size of grid is very little, gate dielectric 110 preferred high-k (high K) materials.Described hafnium comprises hafnium oxide, hafnium silicon oxide, nitrogen hafnium silicon oxide, lanthana, zirconia, zirconium silicon oxide, titanium oxide, tantalum oxide, strontium barium oxide titanium, barium monoxide titanium, strontium oxide strontia titanium, aluminium oxide etc.Particularly preferably be hafnium oxide, zirconia and aluminium oxide.
Described grid 120 can be the sandwich construction that comprises semi-conducting material, for example silicon, germanium, metal or its combination.
The material of described clearance wall 130 is silica-silicon-nitride and silicon oxide (ONO).
Described source electrode 140 and drain electrode 150 are positioned at the Semiconductor substrate 100 of gate dielectric layer 110 both sides, the position of source electrode 140 and drain electrode 150 can exchange in the accompanying drawing 3, and its dopant ion can be one or several in phosphonium ion, arsenic ion, boron ion or the indium ion.
Described linkage interface layer 180 extends along the surface of source electrode 140 and drain electrode 150 and grid 120, in the accompanying drawing 3, linkage interface layer 150 extends downwards along the surface of source electrode 140 and drain electrode 150 and grid 120, form the difference of technology according to linkage interface layer 180, linkage interface layer 180 also may or extend upward at the surperficial downward simultaneously of source electrode 140 and drain electrode 150 and grid 120, that is to say, linkage interface layer 180 may be to extending in the inside of source electrode 140 and drain electrode 150 and grid 120 on the surface of source electrode 140 and drain electrode 150 and grid 120, and also possibility is simultaneously to extending in the outside of source electrode 140 and drain electrode 150 and grid 120.Of the present invention upwards is downwards according to the location expression in the accompanying drawing 3.
Should avoid contacting along the linkage interface layer 180 that extend on source electrode 140 and drain electrode 150 surfaces with gate dielectric layer 110, this is because the effect of linkage interface layer 180 is to be used for interlayer wiring, need be connected with the conducting metal in the interlayer contact hole, in case linkage interface layer 180 is connected with gate dielectric layer 110, the conducting metal that then causes being connected with linkage interface layer 180 contacts the formation short circuit with grid 120, cause device to be scrapped.Generally speaking, the distance between linkage interface layer 180 and the gate dielectric layer 110 is 30 to 80 nanometers, is preferably 20 to 60 nanometers.
Perhaps, described linkage interface layer be cobalt metal silicide, the metal silicide of nickel, the metal silicide of molybdenum, the metal silicide of titanium, the metal silicide of copper or the metal silicide of niobium.Contain any one alloy in aerobic, nitrogen, hydrogen, boron, arsenic or the phosphorus in the described metal silicide.
The formation technology of described linkage interface layer 180 is for to contain argon and oxygen, nitrogen, hydrogen, borane, arsenic hydride, perhaps under the plasma atmosphere of any one in the hydrogen phosphide, splash-proofing sputtering metal is cobalt, nickel, molybdenum, titanium, copper or niobium for example, form infiltration oxonium ion, nitrogen ion, hydrogen ion, boron ion are arranged, arsenic ion, perhaps the linkage interface layer 180 of any one ion in the phosphonium ion.The thickness of described linkage interface layer 180 is 10 to 50 dusts greater than 0 smaller or equal to 100 dusts preferably.The existence of described linkage interface layer 180 makes the dopant ion density of source electrode and drain region have bigger excursion, and for example, the dopant ion concentration range is that 1E18 is to 6E20/cm
3And in above-mentioned dopant ion concentration range, the conducting metal that all has in the interlayer contact hole has less contact resistance.
Because described metal reaction alloy contains oxonium ion, nitrogen ion, hydrogen ion, boron ion, arsenic ion, therefore perhaps any one in the phosphonium ion, provide continuous electronic energy rank at the linkage interface layer of silicon and metal; Directly, make it be in continuous available electronic state with electronics fermi level (Fermi Level) overlaid of metal.Under very low electric field action, can finish electric transmission, reduce the contact resistance between the metal of being connected with contact hole.And can under the situation of the dopant ion concentration of bigger source electrode of scope and drain region, realize low-resistancely electrically contacting.
The present invention also provides a kind of manufacture method of semiconductor device, comprise the steps: to provide Semiconductor substrate, the source electrode and the drain electrode that are formed with gate dielectric on the Semiconductor substrate, are positioned at the grid on the gate dielectric and are positioned at the clearance wall of the grid both sides on the gate dielectric and are positioned at the Semiconductor substrate of gate dielectric both sides; On described Semiconductor substrate, form mask, the Semiconductor substrate outside leak in the sidewall of cover gate and gate dielectric and source; Splash-proofing sputtering metal under plasma environment forms along the linkage interface layer of source electrode and drain surface extension and the linkage interface layer that extends along gate surface; Remove described mask.
Below in conjunction with accompanying drawing 4A to 4E described manufacturing method of semiconductor device is done detailed description.Shown in the 4A, provide Semiconductor substrate 100 with reference to the accompanying drawings, be formed with the clearance wall 130 of gate dielectric layer 110 and grid 120 and grid 120 both sides on the Semiconductor substrate 100.The formation technology of gate dielectric 120 can adopt any prior art well known to those skilled in the art, comparative optimization be chemical vapour deposition technique, the thickness of gate dielectric layer 110 is 15 to 60 dusts.The formation technology of described grid 120 can adopt any prior art well known to those skilled in the art, comparative optimization be chemical vapour deposition technique, for example low-voltage plasma body chemical vapor phase growing or plasma enhanced chemical vapor deposition technology.The thickness of grid 120 is 800 to 3000 dusts.The formation technology of described clearance wall 130 can adopt any prior art well known to those skilled in the art.With grid 120 and gate dielectric 110 is mask, can in the Semiconductor substrate 100 of gate dielectric 110 both sides, form source electrode 140 and drain electrode 150, the dopant ion concentration of described source electrode 140 and drain electrode 150 can change in the larger context, and dopant ion concentration is that 1E18 is to 6E20/cm
3The degree of depth of described source electrode 140 and drain electrode 150 is 600 to 2000 dusts.
With reference to the accompanying drawings shown in the 4B, on the Semiconductor substrate 100 and on the grid 120 and the sidewall of clearance wall 130 form etching barrier layer 160, for example photoresist layer, silicon nitride layer etc., the formation technology of described etching barrier layer 160 can adopt any prior art.
With reference to the accompanying drawings shown in the 4C, remove the etching barrier layer 160 of correspondence position on the etching barrier layer 160 of correspondence position in source electrode 140 and the drain electrode 150 and the grid 120, simultaneously, the etching barrier layer 160 of the sidewall of retention gap wall 130, and form opening 170.
With reference to the accompanying drawings shown in the 4D, with etching barrier layer 160 is mask, under plasma ambient, carry out metal sputtering, form downwards or downward and upwardly extending linkage interface layer 180 of while at the source electrode 140 of opening 170 correspondences and the surface of drain electrode 130 and grid 120.Described plasma comprises argon ion and oxonium ion, nitrogen ion, hydrogen ion, boron ion, arsenic ion, perhaps any one in the phosphonium ion.
Described metal is cobalt, nickel, molybdenum, titanium, copper or niobium.The thickness of described linkage interface layer 180 is less than 100 dusts, is about 10 to 50 dusts preferably.
The pressure of splash-proofing sputtering metal is 0.5 to 1.5 millitorr (mT) under plasma environment.In the process of sputter, form the thin layer of metal and metal reaction alloy, described metal reaction alloy refers to contain the metal of described dopant ion.By pressure is controlled, when forming thin layer, also remove the partial reaction alloy, the dynamic equilibrium that reaches deposition and remove makes the thickness of thin layer reach desired value, realizes lower contact resistance.The characteristic contact resistance of the linkage interface layer that the present invention forms is that 3E-8 is to 2E-9 Ω/cm
2
Shown in the 4E, remove etching barrier layer 160 with reference to the accompanying drawings, form the structure of the semiconductor device of the present invention's formation.The semiconductor device that adopts the present invention to form can be transistors such as memory, logical device.
Because the linkage interface layer of the semiconductor device that the present invention forms contains the doped interface that continuous electronic state is provided, and can finish electric transmission under very low electric field action, reduced the contact resistance between the metal of being connected of semiconductor and contact hole.
In sum, semiconductor device of the present invention and preparation method thereof provides continuous electronic energy rank by being formed with along the linkage interface layer of source electrode and drain surface extension at source electrode and the corresponding zone of drain electrode between silicon and metal; Directly, make it be in continuous available electronic state with the electronics fermi level overlaid of metal.Under very low electric field action, can finish electric transmission, reduce the contact resistance between the metal of being connected with contact hole.And can under the situation of the dopant ion concentration of bigger source electrode of scope and drain region, realize low-resistancely electrically contacting.
Claims (10)
1. semiconductor device, comprise Semiconductor substrate, be positioned at the gate dielectric on the Semiconductor substrate, be positioned at grid and the clearance wall that is positioned at the grid both sides on the gate dielectric on the gate dielectric, and the source electrode and the drain electrode that are positioned at the gate dielectric both sides in the Semiconductor substrate, it is characterized in that, also comprise linkage interface layer that is positioned at source electrode and drain surface extension and the linkage interface layer that extends along gate surface, described linkage interface layer is silicon and intermetallic boundary layer, described linkage interface layer and gate dielectric layer insulation are isolated, described linkage interface layer is the metal that contains dopant ion, and described dopant ion is oxonium ion or hydrogen ion.
2. semiconductor device according to claim 1, it is characterized in that the copper of titanium, doped with oxygen or the hydrogen of molybdenum, doped with oxygen or the hydrogen of nickel, doped with oxygen or the hydrogen of cobalt, doped with oxygen or hydrogen that the described metal that contains dopant ion is doped with oxygen or hydrogen or the niobium of doped with oxygen or hydrogen.
3. semiconductor device according to claim 1 is characterized in that, the thickness of described linkage interface layer greater than 0 smaller or equal to 100 dusts.
4. semiconductor device according to claim 3 is characterized in that, the thickness of described linkage interface layer is 10 to 50 dusts.
5. the manufacture method of a semiconductor device is characterized in that, comprises the steps:
Provide Semiconductor substrate, the source electrode and the drain electrode that are formed with gate dielectric on the Semiconductor substrate, are positioned at the grid on the gate dielectric and are positioned at the clearance wall of the grid both sides on the gate dielectric and are positioned at the Semiconductor substrate of gate dielectric both sides;
Form mask on described Semiconductor substrate, the Semiconductor substrate outside leak in the sidewall of described mask cover gate and clearance wall and source also covers the grid of a part, whole clearance wall and part source-drain areas;
Containing splash-proofing sputtering metal under the plasma environment of dopant ion, formation is along the linkage interface layer of source electrode and drain surface extension and the linkage interface layer that extends along gate surface, described linkage interface layer is silicon and intermetallic boundary layer, described linkage interface layer is the metal that contains dopant ion, and described dopant ion is oxonium ion or hydrogen ion;
Remove described mask.
6. according to the manufacture method of the described semiconductor device of claim 5, it is characterized in that described metal is cobalt, nickel, molybdenum, titanium, copper or niobium.
7. according to the manufacture method of the described semiconductor device of claim 5, it is characterized in that the described plasma that contains dopant ion comprises any one in argon ion and oxonium ion, the hydrogen ion.
8. the manufacture method of semiconductor device according to claim 5 is characterized in that, the thickness of described linkage interface layer greater than 0 smaller or equal to 100 dusts.
9. the manufacture method of semiconductor device according to claim 8 is characterized in that, the thickness of described linkage interface layer is 10 to 50 dusts.
10. according to the manufacture method of the described semiconductor device of claim 5, it is characterized in that the pressure of splash-proofing sputtering metal is 0.5 to 1.5 millitorr under plasma environment.
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| CN200610148250A CN100590889C (en) | 2006-12-28 | 2006-12-28 | Semiconductor device and producing method thereof |
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| CN200610148250A CN100590889C (en) | 2006-12-28 | 2006-12-28 | Semiconductor device and producing method thereof |
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| CN111834456A (en) * | 2019-04-18 | 2020-10-27 | 芯恩（青岛）集成电路有限公司 | Semiconductor element and preparation method thereof |
| CN110600369A (en) * | 2019-08-09 | 2019-12-20 | 长江存储科技有限责任公司 | Preparation method of semiconductor device and semiconductor device |
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Effective date of registration: 20111118 Address after: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Co-patentee after: Semiconductor Manufacturing International (Beijing) Corporation Patentee after: Semiconductor Manufacturing International (Shanghai) Corporation Address before: 201203 Shanghai City, Pudong New Area Zhangjiang Road No. 18 Patentee before: Semiconductor Manufacturing International (Shanghai) Corporation |