Embodiment
Feedforward linear power amplifying circuit of the present invention, its circuit diagram can comprise carrier cancellation loop, error cancellation loop, power-sensing circuit and control circuit referring to shown in Figure 2,
Described carrier cancellation loop comprises signal conditioner, main ring power amplifier and carrier cancellation loop delay unit, described signal conditioner comprises amplitude regulator and phase regulator, the priority position relation of described amplitude regulator and described phase regulator can be arbitrarily, be divided into two-way behind the signal process coupler C1 of input, one the tunnel passes through described signal conditioner and main ring power amplifier successively, another road is by described carrier cancellation loop delay unit, the signal of described main ring power amplifier output, take out a part through coupler C2, with through the carrier signal that does not have distortion of described carrier cancellation loop delay unit in coupler C3 place vector addition; Described carrier cancellation loop also comprises simulated pre-distortion circuit, and described simulated pre-distortion circuit is arranged at before the described main ring power amplifier, and the priority position of described simulated pre-distortion circuit and described signal conditioner relation can be arbitrarily;
Described error cancellation loop comprises signal conditioner, error loop power amplifier and error cancellation loop delay unit, described signal conditioner comprises amplitude regulator and phase regulator, the priority position relation of described amplitude regulator and described phase regulator can be arbitrarily, signal after described coupler C3 place vector addition, pass through described signal conditioner and error loop power amplifier successively, another part signal that described coupler C2 does not take out is through described error cancellation loop delay unit, and the signal of the signal of described error loop power amplifier output and the output of described error cancellation loop delay unit is by coupler C4 vector addition and output; Described error cancellation loop also comprises simulated pre-distortion circuit, and described simulated pre-distortion circuit is arranged at before the described error loop power amplifier, and the priority position of described simulated pre-distortion circuit and described signal conditioner relation can be arbitrarily;
Described power-sensing circuit one end is connected on described carrier cancellation loop or the described error cancellation loop, the other end is connected on the described control circuit, the power at described carrier cancellation loop or the described error cancellation loop place of drawing is converted into voltage signal, is input in the described control circuit; Described power-sensing circuit comprises attenuator, carrier signal detector and A/D converter, described attenuator, carrier signal detector and A/D converter are connected successively, described attenuator is connected on described carrier cancellation loop or the described error cancellation loop, and described A/D converter is connected on the described control circuit; Described power-sensing circuit comprises first power-sensing circuit, second power-sensing circuit and the 3rd power-sensing circuit, the signal of coupler C31 after with described coupler C3 vector addition drawn, be connected to described first power-sensing circuit, the load end of described coupler C4 is connected to described second power-sensing circuit, coupler C5 draws the signal of described coupler C4 vector addition and output, is connected to described the 3rd power-sensing circuit;
Described control circuit can adopt single-chip microcomputer (MCU) system, comprise processor, described processor is handled the signal of described power-sensing circuit input, output signal is connected to the amplitude regulator and the phase regulator of described carrier cancellation loop afterwards, and the amplitude regulator of described error cancellation loop and phase regulator, to the amplitude regulator and the phase regulator of described carrier cancellation loop, and the amplitude regulator of described error cancellation loop and phase regulator are controlled; In the described control circuit, the output of processor is connected to the amplitude regulator and the phase regulator of described carrier cancellation loop and the amplitude regulator of described error cancellation loop and phase regulator by D/A converter; As shown in fig. 1,4 signals of described processor output are by after the D/A converter, be respectively MA, MP, EA and EP, the amplitude regulator of the described carrier cancellation loop of described MA signal controlling, the phase regulator of the described carrier cancellation loop of described MP signal controlling, the amplitude regulator of the described error cancellation loop of described EA signal controlling, the phase regulator of the described error cancellation loop of described EP signal controlling.
The major function of described carrier cancellation loop is to extract carrier signal to amplify the distortion component that produces by the main ring power amplifier; While reserve part carrier signal, the major function of error cancellation loop is to amplify distortion component and the part carrier component that carrier cancellation loop produces, offset the distortion component that main power amplifier produces by amplitude of accommodation adjuster and phase regulator then, carrier signal addition simultaneously, make the signal power maximum of final output, reach the linearity of improving amplifier and the purpose of raising the efficiency.
Input carrier signal is divided into two paths of signals by coupler C1, one road signal is sent into the delay unit branch road, other one the tunnel sends into described carrier cancellation loop, because the main ring power amplifier is non-linear, through in the described carrier cancellation loop amplified output signal distortion component has been arranged just, take out the carrier wave that does not have distortion of a part of signal and process delay unit in coupler C3 place vector addition through coupler C2, by amplitude controller and the phase controller of regulating described carrier cancellation loop, make the two-way carrier signal amplitude equal phase that arrives coupler C3 opposite, by only containing distortion component on the signal theory of carrier cancellation loop, this is the initial closed loop of main ring like this.In error cancellation loop, the pure distortion component of carrier cancellation loop output by the error loop power amplifier after again with being superposeed by coupler C4 that main power amplifier is exported by the carrier wave of non-linear amplification (having distortion component), by adjusting the amplitude controller and the phase controller of error loop, detect at C5, export the high-power carrier signal of a undistorted substantially component at last, and then change the amplitude controller and the phase controller of main ring again, make the load end power level of C4 minimum, thereby reach the effect of optimizing linear and efficient.Coupler C31 is the initial closed power test point of main ring; The load end of C4 is that the power of the final closed loop of main ring is offset test point, and C5 is system's final distortions test point.Amplitude and phase regulator by continuous adjustment main ring in the work of reality make the power level of C4 load end minimum, the power maximum of system output this moment just, the amplitude of continuous adjustment error loop and the distorted signal power level that phase regulator makes C5 are minimum, and just Ci Shi distortion cancellation is best.Amplitude regulator is made up of electric adjustable attenuator, and phase regulator is formed with phase shifter.
Use the analog predistortion technology among the present invention, in described carrier cancellation loop and error cancellation loop, all included simulated pre-distortion circuit.The amplifier nonlinearity characteristic generally adopts AM/AM and AM/PM to represent.AM/AM refers to output level with the characteristic that incoming level changes, and represents the amplifier amplitude non-linearity; AM/PM refers to the characteristic of the phase difference of input and output with the incoming level variation, the principle of predistortion is according to amplifier nonlinearity characteristic (amplitude and phase distortion), signal to input amplifier carries out opposite distortion processing, two nonlinear distortion functions combine, and just can realize highly linear, undistorted system.Application simulation pre-distortion technology among the present invention, improve the linearity of power amplifier greatly, suppress spectral re-growth better, not only improved the linearity of main ring power amplifier and error loop power amplifier, main ring power amplifier and error loop power amplifier are worked under rollback power seldom, improve the linearity of main ring and error loop power amplifier respectively, finally also improved system linearity and efficient.
Main ring power amplifier and error loop power amplifier can adopt the Doherty amplifier among the present invention.Described Doherty amplifier comprises two parts: a carrier amplifier C (Carrier), a peak amplifier P (Peak).Carrier amplifier can be operated near saturated state, thereby obtains greater efficiency, and most of signal amplifies by this amplifier; Peak amplifier is only just worked when peak value arrives, and the most of the time is consumed power not.The linear zone of their synthetic input-output characteristic has expansion significantly than the linear zone of single amplifier, thereby has obtained very high efficient guaranteeing that signal drops under the prerequisite of linear zone.
The invention also discloses a kind of feedforward linear power amplification control method of utilizing above-mentioned circuit to realize, its flow process comprises the steps: as shown in Figure 3
(1) circuit powers on, and described control circuit is gathered the signal of described first power-sensing circuit, and the amplitude regulator and the phase regulator of described carrier cancellation loop are regulated, and makes the signal value minimum of described first power-sensing circuit;
(2) described control circuit is gathered the signal of described the 3rd power-sensing circuit, and the amplitude regulator and the phase regulator of described error cancellation loop are regulated, and makes the signal value minimum of described the 3rd power-sensing circuit;
(3) described control circuit is gathered the signal of described second power-sensing circuit, and the amplitude regulator and the phase regulator of described carrier cancellation loop are regulated, and makes the signal value minimum of described second power-sensing circuit;
(4) cycling jump is to step (2).
In the feedforward linear power amplification control method of the present invention, in the time of the signal minimum of described power-sensing circuit, the two paths of signals amplitude that the coupler that just described power-sensing circuit is connected with described carrier cancellation loop or error cancellation loop is imported equates that phase place is opposite.
Feedforward linear power amplification control method of the present invention is by the continuous circulation of above-mentioned steps (2), (3), (4), finally search out the amplitude control voltage and the phase control voltage MA of this high efficiency feedforward linear power amplifier, MP, EA, the optimal working point of EP, and make it stable fast, realize the optimum of distorted signal is offseted, keep the magnitude of voltage of signal V3 of the signal V2 of second power-sensing circuit and the 3rd power-sensing circuit minimum all the time, make the efficient of system and linearity reach the highest.
The flow process of described step (1) specifically comprises the steps:
(a) after circuit powers on, the circuit initialization, described control circuit is gathered the signal V1 of described first power-sensing circuit;
(b) the signal MA of described control circuit regulates described amplitude regulator to a direction;
(c) described control circuit is gathered the signal V1 of described first power-sensing circuit again;
(d) if with compare before, the signal V1 of described first power-sensing circuit diminishes, then signal MA continues to regulate described amplitude regulator according to this direction, jumps to step (c) afterwards; If with compare before, it is big that the signal V1 of described first power-sensing circuit becomes, then signal MA regulates described amplitude regulator in the opposite direction;
(e) described control circuit is gathered the signal V1 of described first power-sensing circuit again;
(f) if with compare before, the signal V1 of described first power-sensing circuit diminishes, then signal MA continues to regulate described amplitude regulator according to this direction, jumps to step (e) afterwards; If with compare before, it is big that the signal V1 of described first power-sensing circuit becomes, then signal MP regulates described phase regulator to a direction;
(g) described control circuit is gathered the signal V1 of described first power-sensing circuit again;
(h) if with compare before, the signal V1 of described first power-sensing circuit diminishes, then signal MP continues to regulate described phase regulator according to this direction, jumps to step (g) afterwards; If with compare before, it is big that the signal V1 of described first power-sensing circuit becomes, then signal MP regulates described phase regulator in the opposite direction;
(i) described control circuit is gathered the signal V1 of described first power-sensing circuit again;
(j) if with compare before, the signal V1 of described first power-sensing circuit diminishes, then signal MP continues to regulate described phase regulator according to this direction, jumps to step (i) afterwards; If with compare before, it is big that the signal V1 of described first power-sensing circuit becomes, then step (1) finishes.
In the described step (1), also can regulate described phase regulator earlier, afterwards described amplitude regulator be regulated,, specifically comprise the steps: referring to shown in Figure 4
(a) after circuit powers on, described control circuit is gathered the signal V1 of described first power-sensing circuit;
(b) the signal MP of described control circuit regulates described phase regulator to a direction;
(c) described control circuit is gathered the signal V1 of described first power-sensing circuit again;
(d) if with compare before, the signal V1 of described first power-sensing circuit diminishes, then signal MP continues to regulate described phase regulator according to this direction, jumps to step (c) afterwards; If with compare before, it is big that the signal V1 of described first power-sensing circuit becomes, then signal MP regulates described phase regulator in the opposite direction;
(e) described control circuit is gathered the signal V1 of described first power-sensing circuit again;
(f) if with compare before, the signal V1 of described first power-sensing circuit diminishes, then signal MP continues to regulate described phase regulator according to this direction, jumps to step (e) afterwards; If with compare before, it is big that the signal V1 of described first power-sensing circuit becomes, then signal MA regulates described amplitude regulator to a direction;
(g) described control circuit is gathered the signal V1 of described first power-sensing circuit again;
(h) if with compare before, the signal V1 of described first power-sensing circuit diminishes, then signal MA continues to regulate described amplitude regulator according to this direction, jumps to step (g) afterwards; If with compare before, it is big that the signal V1 of described first power-sensing circuit becomes, then signal MA regulates described amplitude regulator in the opposite direction;
(i) described control circuit is gathered the signal V1 of described first power-sensing circuit again;
(j) if with compare before, the signal V1 of described first power-sensing circuit diminishes, then signal MA continues to regulate described amplitude regulator according to this direction, jumps to step (i) afterwards; If with compare before, it is big that the signal V1 of described first power-sensing circuit becomes, then step (1) finishes.
The flow process of described step (2) specifically comprises the steps:
(a) described control circuit is gathered the signal V3 of described the 3rd power-sensing circuit;
(b) the signal EP of described control circuit regulates described amplitude regulator to a direction;
(c) described control circuit is gathered the signal V3 of described the 3rd power-sensing circuit again;
(d) if with compare before, the signal V3 of described the 3rd power-sensing circuit diminishes, then signal EP continues to regulate described amplitude controller according to this direction, jumps to step (c) afterwards; If with compare before, it is big that the signal V3 of described the 3rd power-sensing circuit becomes, then signal EP regulates described amplitude regulator in the opposite direction;
(e) described control circuit is gathered the signal V3 of described the 3rd power-sensing circuit again;
(f) if with compare before, the signal V3 of described the 3rd power-sensing circuit diminishes, then signal EP continues to regulate described amplitude controller according to this direction, jumps to step (e) afterwards; If with compare before, it is big that the signal V3 of described the 3rd power-sensing circuit becomes, then signal EA regulates described phase regulator to a direction;
(g) described control circuit is gathered the signal V3 of described the 3rd power-sensing circuit again;
(h) if with compare before, the signal V3 of described the 3rd power-sensing circuit diminishes, then signal EA continues to regulate described phase controller according to this direction, jumps to step (g) afterwards; If with compare before, it is big that the signal V3 of described the 3rd power-sensing circuit becomes, then signal EA regulates described phase regulator in the opposite direction;
(i) described control circuit is gathered the signal V3 of described the 3rd power-sensing circuit again;
(j) if with compare before, the signal V3 of described the 3rd power-sensing circuit diminishes, then signal EA continues to regulate described phase controller according to this direction, jumps to step (i) afterwards; If with compare before, it is big that the signal V3 of described the 3rd power-sensing circuit becomes, then step (2) finishes.
In the described step (2), also can regulate described phase regulator earlier, afterwards described amplitude regulator be regulated,, specifically comprise the steps: referring to shown in Figure 5
(a) described control circuit is gathered the signal V3 of described the 3rd power-sensing circuit;
(b) the signal EA of described control circuit regulates described phase regulator to a direction;
(c) described control circuit is gathered the signal V3 of described the 3rd power-sensing circuit again;
(d) if with compare before, the signal V3 of described the 3rd power-sensing circuit diminishes, then signal EA continues to regulate described phase regulator according to this direction, jumps to step (c) afterwards; If with compare before, it is big that the signal V3 of described the 3rd power-sensing circuit becomes, then signal EA regulates described phase regulator in the opposite direction;
(e) described control circuit is gathered the signal V3 of described the 3rd power-sensing circuit again;
(f) if with compare before, the signal V3 of described the 3rd power-sensing circuit diminishes, then signal EA continues to regulate described phase regulator according to this direction, jumps to step (e) afterwards; If with compare before, it is big that the signal V3 of described the 3rd power-sensing circuit becomes, then signal EP regulates described amplitude regulator to a direction;
(g) described control circuit is gathered the signal V3 of described the 3rd power-sensing circuit again;
(h) if with compare before, the signal V3 of described the 3rd power-sensing circuit diminishes, then signal EP continues to regulate described amplitude regulator according to this direction, jumps to step (g) afterwards; If with compare before, it is big that the signal V3 of described the 3rd power-sensing circuit becomes, then signal EP regulates described amplitude regulator in the opposite direction;
(i) described control circuit is gathered the signal V3 of described the 3rd power-sensing circuit again;
(j) if with compare before, the signal V3 of described the 3rd power-sensing circuit diminishes, then signal EP continues to regulate described amplitude regulator according to this direction, jumps to step (i) afterwards; If with compare before, it is big that the signal V3 of described the 3rd power-sensing circuit becomes, then step (2) finishes.
The flow process of described step (3) specifically comprises the steps:
(a) described control circuit is gathered the signal V2 of described second power-sensing circuit;
(b) the signal MP of described control circuit regulates described amplitude regulator to a direction;
(c) described control circuit is gathered the signal V2 of described second power-sensing circuit again;
(d) if with compare before, the signal V2 of described second power-sensing circuit diminishes, then signal MP continues to regulate described amplitude controller according to this direction, jumps to step (c) afterwards; If with compare before, it is big that the signal V2 of described second power-sensing circuit becomes, then signal MP regulates described amplitude regulator in the opposite direction;
(e) described control circuit is gathered the signal V2 of described second power-sensing circuit again;
(f) if with compare before, the signal V2 of described second power-sensing circuit diminishes, then signal MP continues to regulate described amplitude controller according to this direction, jumps to step (e) afterwards; If with compare before, it is big that the signal V2 of described second power-sensing circuit becomes, then signal MA regulates described phase regulator to a direction;
(g) described control circuit is gathered the signal V2 of described second power-sensing circuit again;
(h) if with compare before, the signal V2 of described second power-sensing circuit diminishes, then signal MA continues to regulate described phase controller according to this direction, jumps to step (g) afterwards; If with compare before, it is big that the signal V2 of described second power-sensing circuit becomes, then signal MA regulates described phase regulator in the opposite direction;
(i) described control circuit is gathered the signal V2 of described second power-sensing circuit again;
(j) if with compare before, the signal V2 of described second power-sensing circuit diminishes, then signal MA continues to regulate described phase controller according to this direction, jumps to step (i) afterwards; If with compare before, it is big that the signal V2 of described second power-sensing circuit becomes, then step (3) finishes.
In the described step (3), also can regulate described phase regulator earlier, afterwards described amplitude regulator be regulated,, specifically comprise the steps: referring to shown in Figure 6
(a) described control circuit is gathered the signal V2 of described second power-sensing circuit;
(b) the signal MA of described control circuit regulates described phase regulator to a direction;
(c) described control circuit is gathered the signal V2 of described second power-sensing circuit again;
(d) if with compare before, the signal V2 of described second power-sensing circuit diminishes, then signal MA continues to regulate described phase regulator according to this direction, jumps to step (c) afterwards; If with compare before, it is big that the signal V2 of described second power-sensing circuit becomes, then signal MA regulates described phase regulator in the opposite direction;
(e) described control circuit is gathered the signal V2 of described second power-sensing circuit again;
(f) if with compare before, the signal V2 of described second power-sensing circuit diminishes, then signal MA continues to regulate described phase regulator according to this direction, jumps to step (e) afterwards; If with compare before, it is big that the signal V2 of described second power-sensing circuit becomes, then signal MP regulates described amplitude regulator to a direction;
(g) described control circuit is gathered the signal V2 of described second power-sensing circuit again;
(h) if with compare before, the signal V2 of described second power-sensing circuit diminishes, then signal MP continues to regulate described amplitude regulator according to this direction, jumps to step (g) afterwards; If with compare before, it is big that the signal V2 of described second power-sensing circuit becomes, then signal MP regulates described amplitude regulator in the opposite direction;
(i) described control circuit is gathered the signal V2 of described second power-sensing circuit again;
(j) if with compare before, the signal V2 of described second power-sensing circuit diminishes, then signal MP continues to regulate described amplitude regulator according to this direction, jumps to step (i) afterwards; If with compare before, it is big that the signal V2 of described second power-sensing circuit becomes, then step (3) finishes.
Described step (1), step (2) or step (3) self circulates repeatedly, till the signal of described power-sensing circuit no longer diminishes.For example, in described step (1), regulate for described phase regulator, make the V1 signal diminish to greatest extent, more described amplitude regulator is regulated afterwards, make the V1 signal diminish to greatest extent again, if at this moment re-execute step (1) again, promptly more described phase regulator is regulated, might make the V1 signal can reduce again, therefore such circulation execution in step (1) makes the signal of described signal deteching circuit become minimum to greatest extent.And this circulation can endlessly not go on, because the signal of described signal deteching circuit always reaches a minimum value.
The present invention adopts directly the distortion cancellation to error loop to detect, and has simplified error loop control principle and control method greatly, design difficulty of Jian Shaoing and debugging difficulty simultaneously, the integrated level of the system of increase; Feedforward linear power amplification control method provided by the present invention has improved the efficient of feed forward power amplifier; Through facts have proved, on original feedforward linear power amplification control method basis, can effectively raise the efficiency 3~5 percentage points at least; Feedforward linear power amplifying circuit of the present invention simple in structure do not have complicated hardware circuit and software requirement, and be very convenient for the upgrading of existing system, reduced the cost of system upgrade, is very significant to exploitation, debugging and the production of system; Adopt the analog predistortion technology in the feedforward linear power amplifying circuit of the present invention, improved the linear properties of main ring power amplifier and error loop power amplifier, thereby improved system linear and efficient.The power amplifier of main ring and error loop adopts the Doherty amplifier, makes the efficient of system improve 8~10 percentage points.
In a word, feedforward linear power amplifying circuit of the present invention and method, feedforward linear power amplifier efficient and linearity have been improved greatly, system hardware is constituted to be simplified, shortened the R﹠D cycle, exploitation and production cost also significantly reduce, and production technology standardization, simplification help large-scale mass production.