CN100585684C - Light emission device - Google Patents
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- CN100585684C CN100585684C CN200710154289A CN200710154289A CN100585684C CN 100585684 C CN100585684 C CN 100585684C CN 200710154289 A CN200710154289 A CN 200710154289A CN 200710154289 A CN200710154289 A CN 200710154289A CN 100585684 C CN100585684 C CN 100585684C
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Abstract
A pixel having a structure in which low voltage drive is possible is provided by a simple process. A digital image signal input from a source signal line is input to the pixel through a switching TFT. At this point, a voltage compensation circuit amplifies the voltage amplitude of the digital image signal or transforms the amplitude, and applies the result to a gate electrode of a driver TFT. On-off control of TFTs within the pixel can thus be performed normally even if the voltage of a power source for driving gate signal lines becomes lower.
Description
Invention field
The present invention relates to light-emitting device.Particularly, the present invention relates to have the structure of the active matrix light-emitting device of the thin film transistor (TFT) of on insulator, making (hereinafter being called TFT) such as glass or plastics.The invention still further relates to the electronic equipment that uses light-emitting device in the display part.
Background of invention
The development of display device is very active recently, wherein uses the self-emission device such as electroluminescence (EL) element.Term EL element or comprise the element that is used to from luminous (fluorescence) of singlet state exciton perhaps comprises the luminous element that is used to from triplet exciton (phosphorescence).A kind of EL display device here provides as an example of light-emitting device, but is to use the display device of other self-emission device to be also included within the classification of light-emitting device.
EL element is made up of the luminescent layer that is clipped between the pair of electrodes (anode and negative electrode), normally rhythmo structure.Can typically provide the proposition such as Tang of Eastman Kodak company and rhythmo structure with hole transport layer, luminescent layer and electron transport layer.This structure has very high luminous efficiency, and this structure is used for present most of EL element after deliberation.
In addition, also there is other structure, be layered in a kind of structure on the anode in order such as wherein hole injection layer, hole transport layer, luminescent layer and electron transport layer, and wherein hole injection layer, hole transport layer, luminescent layer, electron transport layer and electron injecting layer are layered in a kind of structure on the anode in order.Any can being used in these structures as EL element structure of the present invention.Can also carry out the doping in luminescent layer such as fluorescent dye.
All layers that form between anode and negative electrode generally are called the EL layer here.Aforementioned hole injection layer, hole transport layer, luminescent layer, electron transport layer and electron injecting layer thereby all be included in the EL layer.Light-emitting component by anode, EL layer and cathode structure is called EL element.
Illustrating in Fig. 3 A of light-emitting device.Pixel portion 301 is arranged in the core of substrate 300.The gate signal line driver circuit 303 that is used for the source line driver circuit 302 of Controlling Source signal wire and is used to drive the gate signal line be arranged in pixel portion 301 around.Gate signal line driver circuit 303 is arranged in the both sides of pixel portion 301 symmetrically among Fig. 3 A, but in them one can only be placed on a side.Yet, consider factor, preferably at two side arrangement gate signal line driver circuits 303 such as reliability and circuit running efficiency.
Signal such as clock signal, initial pulse and picture signal is input to source line driver circuit 302 and gate signal line driver circuit 303 by flexible printed circuit board (FPC) etc.
The operation of drive circuit is described.In the gate signal line driver circuit, be used to select the pulse of gate signal line to export one by one by shift register 321 according to clock signal and initial pulse.Then, the voltage of signals amplitude is with level shifter 322 conversion, and outputs on the gate signal line by impact damper 323, and certain delegation of gate signal line places selected state.
In the source line driver circuit, sampling pulse is exported by shift register 311 one by one according to clock signal and initial pulse.In first latch cicuit 312, carry out the storage of data image signal according to the sequential of sampling pulse.When having finished the operation of a horizontal cycle part, latch pulse was imported in the restore cycle, was stored in disposable second latch cicuit 313 that all passes to of delegation's part data image signal in first latch cicuit 312.The delegation of data image signal part is write the pixel to the row that pulse outputed to of selecting the gate signal line simultaneously then.
Next pixels illustrated part 301.By the corresponding pixel of the part shown in the Ref. No. in the pixel portion 301 310, the circuit structure of pixel is shown in Fig. 3 B.The TFT that Ref. No. 351 fingers among Fig. 3 B work as on-off element (hereinafter being called switching TFT) in the process that picture signal is write in pixel.Not that to have n raceway groove polarity be exactly that the TFT with p raceway groove polarity can be used as switching TFT 351.Ref. No. 352 refers to offer as control the TFT (hereinafter being called driver TFT) of elements act of the electric current of EL element 354.If driver TFT352 is the n channel TFT, EL element 354 electrode 355 is used as negative electrode so, and is connected on the output electrode of driver TFT 352.Another electrode 356 of EL element 354 thereby become anode.On the other hand, if the p channel TFT is used as driver TFT 352, EL element 354 electrode 355 is used as anode so, and is connected on the output electrode of driver TFT 352.Another electrode 356 of EL element 354 thereby become negative electrode.Ref. No. 353 refers to formed so that store the holding capacitor (Cs) of the electromotive force of the gate electrode that is applied to driver TFT 352.Although holding capacitor (Cs) provides as capacitive device independently, can also utilize the electric capacity between the gate electrode of source region and electric capacity between the gate electrode that appears at driver TFT 352 or the drain region that appears at driver TFT 352 here.
With reference to figure 5A and 5B, provide the simple declaration that concerns between the structure of the polarity of driver TFT 352 and EL element 354.Fig. 5 A illustrates the structure of EL element pixel portion, and Fig. 5 B schematically illustrates the connection between switching TFT 501, driver TFT 502 and the EL element 504.
In addition, in the present technique explanation, the TFT operation is discussed when the explanation circuit operation.Term " TFT opens " refers to that the absolute value of voltage between TFT source and the grid surpasses the absolute value of TFT threshold voltage, and the drain region of TFT and source region place conduction state by channel formation region like this.Term " TFT pass " refers to that the absolute value of voltage between the source of TFT and the grid is lower than the absolute value of TFT threshold voltage, and the drain region of TFT and source region are in nonconducting state.
In addition, when explanation TFT connects, use term " gate electrode, input electrode, output electrode " and gate electrode, source electrode, drain electrode respectively ".This is because of the voltage of often considering when explanation TFT operates between grid and the source, still is difficult in drain region and the source region of the clear regional TFT of branch on the structural level.Thereby these two districts are called input electrode and output electrode when explanation signal input and output, and when concerning between the electromotive force of explanation TFT electrode, one of input electrode and output electrode are called the source region, and another is called the drain region.
At first, consider that Ref. No. 505 refers to that anode, Ref. No. 506 refer to the situation of negative electrode in EL element 504.If getting, the electromotive force of electrode 505 makes V
505And the electromotive force of electrode 506 is got and is made V
506, be necessary so between anode and negative electrode, to add preposition bias voltage so that EL element 504 is luminous.Thereby satisfy V
505＞V
506If the n channel TFT, in order to open driver TFT 502 reliably, and normally between the electrode of EL element 504, apply voltage, necessary is that the electromotive force that imposes on driver TFT 502 gate electrodes compares V
505At least exceed the amount of TFT 502 threshold voltages.In other words, be necessary to enlarge the amplitude of the signal that writes from source signal line.On the other hand, if p channel TFT and making alive between the electrode of EL element 504 normally then are necessary to compare V for the electromotive force that is added in driver TFT 502 gate electrodes
505The low amount of the threshold value of TFT 502 at least is so that open driver TFT 502 reliably.Thereby the amplitude that there is no need the signal that will write from source signal line enlarges a lot.Like this, be that anode, electrode 506 are situations of negative electrode for electrode 505 in EL element 504, preferably be used for the p channel TFT of driver TFT 502.
In addition, if driver TFT 502 is n raceway grooves in this case, the voltage V between driver TFT502 grid and the source then
GS2Become the voltage between the anode 505 of the gate electrode of driver TFT 502 and EL element 504, be not shown in Fig. 5 B like that.If at this moment owing to the defective on EL element 502 performances or owing to long-term ageing, resistance raises, and has improved V
EL, the electromotive force of driver TFT 502 source electrodes increases so.A kind of possibility is arranged, and promptly the grid of driver TFT 502 and the voltage between the source will make to be dispersed between the pixel and develop owing to the dispersion of EL element 504.Thereby preferably use the p channel TFT here as driver TFT 502.
When Ref. No. in EL element 504 505 refers to negative electrode, when Ref. No. 506 refers to anode,, be necessary on two electrodes, all to add electric potential difference in order to make EL element 504 luminous.In this situation, satisfy V
505＜V
506If the n channel TFT, and normally between the electrode of EL element 504, apply voltage, in order to open driver TFT 502 reliably, the electromotive force that is applied on driver TFT 502 gate electrodes compares V
505Exceed the size of TFT 502 threshold values fully.Thereby the amplitude that there is no need the signal that will write from source signal line enlarges a lot.On the other hand, if the p channel TFT also normally applies voltage between the electrode of EL element 504, the electromotive force that then is added in driver TFT 502 gate electrodes compares V
505The low size of the threshold value of TFT 502 at least is necessary, so that open driver TFT 502 reliably.In other words, the amplitude of the signal that writes from source signal line must enlarge.Like this, be that negative electrode, electrode 506 are situations of anode for electrode 505 in EL element 504, preferably be used for the n channel TFT of driver TFT 502.
In addition, when the electromotive force of the source of considering driver TFT 502 and voltage between the grid and EL element negative electrode, the p channel TFT of using driver TFT 502 in this case also is preferred.
Secondly, illustrate to be transmitted into the photoemissive direction of driver to the polarity of driver TFT 502 and the relation between EL element 504 structures.Fig. 8 A is schematic cross section of EL element 504 structures when driver TFT 502 is the n channel TFT, and Fig. 8 B is schematic cross section of EL element 504 structures when driver TFT 502 is the p channel TFT.
Because electronics need be injected into the ability in the luminescent layer, preferably the negative electrode in EL element 504 uses metal material.Use the electrode of transparency electrode thereby anode normally.The negative electrode that driver TFT among Fig. 8 A thereby be the n channel TFT, electric current supplying wire are connected to the source region of driver TFT 502 and EL element 504 is connected to the drain region of driver TFT 502.Subsequently, launch to the transparency electrode anode-side by the light that luminescent layer produces, thereby photoemissive direction is facing to the top substrate that forms TFT (hereinafter being called the TFT substrate), as shown in the figure.
On the other hand, driver TFT 502 is p channel TFT among Fig. 8 B.Electric current supplying wire is connected to the source region of driver TFT 502, and the anode of EL element 504 is connected to the drain region of driver TFT 502.Subsequently, launch to the transparency electrode anode-side by the light that luminescent layer produces, thereby photoemissive direction is towards the TFT substrate, as shown in the figure.
Here the light emission direction shown in Fig. 8 A is called the upper surface emission, and the light emission direction shown in Fig. 8 B is called the lower surface emission.The occupied zone of the element of structure pixel portion influences the light emitting sheet area in lower surface emission situation.On the other hand, in upper surface emission situation, light can be drawn, and it doesn't matter with zone that the element of structure pixel portion is occupied, and this improve the aperture than on be useful.Yet, shown in Fig. 8 A, when making upper surface emitting structural light-emitting device, be necessary to have the consideration of technological process, after forming, the EL layer forms anode with transparency electrode.By this road technology, easily the EL layer is produced infringement, and such technology is difficult at present carry out.Thereby adopt the lower surface emitting structural shown in Fig. 8 B usually.
Next illustrates the method for driven for emitting lights device.
Simulation stage method and digital stage method can be used as the example of representing the method for many classifications with light-emitting device.The simulation stage method is a kind of method, and the electric current that wherein flows through in EL element is controlled with analog form, controls brightness like this, and obtains classification.Yet small dispersion has a significant impact the dispersion of EL brightness in the TFT performance of structure pixel portion.That is,,, flow through big young pathbreaker's difference of electric current between the source of different driving device TFT and the leakage even so same electromotive force is added on the gate electrode of driver TFT if in the performance of driver TFT102 dispersion is arranged.In other words, because the dispersion of the electric current generation brightness of the different sizes that in EL element, flow through.
The numeral stage method is a kind of method, and the dispersion of wherein constructing in the element function of pixel is not easy to influence picture quality.EL element only drives with two states, an ON state (brightness near 100% state) and an OFF state (brightness is approximately 0% state).That is, we can say that digital stage method is a kind of driving method, though wherein in the source of driver TFT and the size of current that flows through between leaking dispersion is arranged, the dispersion of EL element brightness also is difficult to be distinguished.
Yet, at this state, have only two kinds of classifications to show with digital stage method, proposed by a plurality of technology digital stage method and the multiple classification of another kind of method combination realization.
Can provide with a kind of method that realizes multistage classification is the combination of digital stage method and temporal scalability method.Term temporal scalability method refers to carry out the method that classification is represented by the time sum of control EL element in the luminous time.Particularly, frame period is divided into the period of sub-frame of a plurality of different lengths.Classification is used the difference of fluorescent lifetime length like this by select EL element luminous expression whether in each period of sub-frame in a frame period.
Disclosed method here illustrates as a kind of method with digital stage method and the combination of temporal scalability method among the Japanese Unexamined Patent Publication No 2001-5426.Here the situation that 3 classifications are represented illustrates as an example.
With reference to figure 9A-9C.Be used in frame rate in the display device that shows such as liquid crystal display and EL usually at the order of magnitude of 60Hz.That is, screen drawing carries out with the order of magnitude of per second 60 times, shown in Fig. 9 A.Might show that like this thereby human eye does not think screen flicker.The cycle of carrying out a screen drawing is called a frame period here.
A frame period is divided into a plurality of period of sub-frame in the disclosed temporal scalability method in Japanese Unexamined Patent Publication No 2001-5426.The number that this point is cut apart equals the number of hierarchy bit.That is, here because use 3 classifications, a frame period is divided into three period of sub-frame SF1-SF3.
In addition, each period of sub-frame has addressing (a writing) period T a and lasting (luminous) period T s.Addressing (writing) cycle is the cycle that is used for writing to pixel data image signal, and each period of sub-frame has identical length.The lasting cycle be wherein EL element based on the luminous cycle of data image signal of writing in the cycle in addressing (writing) in the pixel.Continuing (luminous) period T s1-Ts3 has and satisfies Ts1: Ts2: Ts3=4: 2: 1 length ratio.That is, represent that lasting (luminous) cycle of n has 2 for the classification of n position
N-1: 2
N-2: ..: 2
1: 2
0The length ratio.The light period length of each pixel concrete (luminous) cycle that continues decision in cycle luminous in a pixel period by EL element.Carrying out classification like this represents.In other words, by in Fig. 9 B, taking luminance or non-luminance, and utilize the length of total fluorescent lifetime, can represent to have 8 classifications of 0%, 14%, 28%, 43%, 57%, 71% and 100% brightness for lasting (luminous) period T s1-Ts3.If have luminous in Ts1 and do not have luminously in Ts2 and Ts3, brightness is 57%, when brightness is 71%, among luminous Ts1 of occurring in and the Ts3 and do not occur among the Ts2.In order to obtain 71% brightness, use corresponding to the voltage of 71% brightness and control, and keep 71% brightness in the cycle in an entire frame with the simulation stage method.Yet, use the time stage method, same classification is only represented in the luminous of 71% whole light period by the brightness 100%.
Operation describes in detail.Continue with reference to figure 9A-9C, and Fig. 3 B.At first, switching TFT 351 is opened when selecting pulse to be input to the gate signal line.Secondly from source signal line input digital image signal, carry out the control that driver TFT 352 opens or closes according to the electromotive force of data image signal.In addition, corresponding to the charge storage of data image signal in holding capacitor 353.Even open from this point driver TFT 352, voltage also is not added between anode (negative electrode) 355 and the negative electrode (anode) 356, thereby does not launch light.This method is the electromotive force that the electromotive force of setting negative electrode (anode) 356 equals anode (negative electrode) 355, promptly equals the electromotive force of electric current supplying wire (electric current).Negative electrode (anode) 356 is public on all pixels usually, thereby this operation is carried out simultaneously for all pixels.
Operation from first row to the last delegation finish that of write operation, finish addressing (writing) cycle, all pixels move on to lasting (luminous) cycle simultaneously.Voltage is added between anode (negative electrode) 355 and negative electrode (anode) 356 of EL element 354, and electric current flows, and makes light emit.
By in all period of sub-frame, implementing aforementioned operation frame period of structure.In order to increase the number that shows classification in this way, can increase the number of period of sub-frame.In addition, always must not occur from upper to the minimum bit order shown in Fig. 9 B and 9C for period of sub-frame, period of sub-frame can be arranged arbitrarily in the frame period.In addition, order also can change in each frame period.Such driving method is called the display cycle separation and drives (DPS driving).
Low dutycycle (carry out the cycle of classification display, wherein each frame period pixel is luminous) can be used as a problem that drives with DSP and provides.Addressing (writing) cycle and (luminous) cycle of continuing separate, thereby the cycle was present in the frame period that wherein light is not launched under any condition.The result is to feel that the integral body of brightness descends.
In certain period of sub-frame of the pixel that is connected to m row gate signal line, the be written in gate signal line of data image signal in pixel carried out in the selecteed cycle 902, and shown in Fig. 9 D, light is continuing emission in (luminous) cycle 904.Here addressing (writing) cycle is represented whole cycles of Ref. No. 901,902 and 903.Ref. No. 901 refers to be used to carry out the cycle that write of data image signal to 1-(m-1) row, and Ref. No. 903 refers to be used to carry out data image signal walks to last column to (m+1) the cycle that writes.In other words,, become in the 901 and 903 represented cycles of addressing (writing) cycle Ref. No. and to write and the luminous cycle of not carrying out for the pixel that is connected to m row gate signal line, that is, and " wait " cycle.
Addressing (writing) cycle forms in each period of sub-frame, if thereby seek a plurality of classification level, addressing (writing) cycle also increases.In aforementioned " wait " increase was arranged also in the cycle, this just obtains the further minimizing of dutycycle.
Here provide the method that is used to solve these type problems.This method is a kind of method, wherein addressing (writing) cycle with continue not separate between (luminous) cycle, shown in Fig. 9 E, luminously after writing of the pixel that is connected to certain row gate signal line finished, begin immediately at data image signal.The pixel that is connected to m row gate signal line also can allow it luminous in the cycle that writes of carrying out data image signal pixel of gate signal line beyond being connected to m row gate signal line, shown in Fig. 9 F, thereby the problem that dutycycle reduces can solve in this way.
Yet, when considering the increase of branch number of stages, produce other problem in this way again.
Figure 10 A and 10B represent that for driving with above-mentioned DPS the situation of 5 classifications cuts apart the example in a frame period.Addressing (writing) cycle is accompanied by period of sub-frame and separates the increase of number and increase the situation weak point of lasting 3 classifications of period ratio.So just can understand that dutycycle is lower than 3 classification situations.On the other hand, shown in Figure 10 C, some situations have been considered, wherein by driving the minimizing that prevents dutycycle according to addressing (writing) cycle and lasting indiscrete method of (luminous) cycle.The length ratio of the lasting period T s1-Ts5 of each period of sub-frame is Ts1: Ts2: Ts3: Ts4: Ts5=2
4: 2
3: 2
2: 2
1: 2
0=16: 8: 4: 2: 1.
With reference to figure 10B, emphasis is on reference symbol SF5.Can see that in SF5 to continue (luminous) period ratio addressing (writing) cycle long.Thereby, produced the overlapping cycle in the wherein addressing of different period of sub-frame (writing) cycle for according to the situation of wherein addressing (writing) cycle with the driving method driving that continues not have between (luminous) cycle to separate.Before among Figure 10 C SF5 writing of footline being finished, that has finished the 1st row continues (luminous) cycle, and has begun to write next time.In other words, the gate signal line of two different rows is selected at one time, can not carry out normal signal and write.
Display device shown in Fig. 4 A and the 4B proposes to solve this class problem in Japanese patent application 2000-86968 number.Display device shown in display device shown in Fig. 4 A and the prior figures 3A is about the same.Difference between these two is that the display device of Fig. 4 A writes gate signal line driver circuit 403 and erase gate signal line drive circuit 404 on the left side and the right of pixel portion 401.
The circuit structure of a pixel with Ref. No. 401 expressions, is shown among Fig. 4 B in the display device of Fig. 4 A.This structure is different from the pixel part shown in Fig. 3 B and is that it has erase gate signal wire and erasing TFT 457.
Overlapping problem of aforementioned addressing different (writing) cycle is by having solved with this class display device.
Provide explanation about its operation.In order to illustrate, with reference to figure 4B and Figure 10 A-10D.At first select to write the gate signal line, open switching TFT 451.Then from source signal line input digital image signal, the electromotive force Control Driver TFT 452 by input signal opens or closes, in addition, corresponding to the charge storage of input signal in holding capacitor 453.Finish the row that data image signal writes, move on to lasting (luminous) cycle then immediately.
Shown in Figure 10 C and 10D, erase cycle (Tr5) forms after finishing in (luminous) cycle that continues with the period of sub-frame that continues (luminous) cycle shorter than addressing (writing) cycle.Thereby doing next addressing period so can not begin after (luminous) cycle of continuing immediately.EL element 454 is not luminous in erase cycle.In erase cycle (Tr5), erasing TFT 457 is opened by the selection of erase gate signal wire, discharges the electric charge that is stored in the holding capacitor 453.The electric current that flows in driver TFT 452 stops like this, and EL element 454 stops luminous.
In this point, the length of erase cycle becomes the length of finishing up to addressing (writing) cycle of footline after finishing from addressing (writing) cycle of the 1st row.
Like this by forming erase cycle with the raising dutycycle and by preventing the incorrect overlapping multistage classification that realizes of addressing (writing) cycle.Opposite with the DPS driving, such driving method is called wipes turntable driving (SES driving) simultaneously.
Strictly speaking, SES drives and to comprise and write and wipe parallel mode of carrying out.Opposite with the DPS driving that wherein addressing (writing) cycle and (luminous) cycle of continuing separate, there is not the driving method of this separation to be called the SES driving.Wherein there is not the situation of clear and definite erase cycle to be also included within the SES driving method, as Fig. 9 E-9F.
For the display device of making by formation TFT on insulator, manufacturing process is that this complicated fact has caused the minimizing of yield-power and the increase of cost.Thereby the main challenge that reduces cost is that technology is simplified as much as possible.So just consider by only with TFT structure pixel portion with single polarity and drive circuit (such as source line driver circuit and gate signal line driver circuit) on every side.
The operating voltage of considered pixel and drive circuit again.Again with reference to figure 5A and 5B.Fig. 5 A provides the structure of EL element pixel portion, and with schematically illustrating of being connected in the switching TFT 501, driver TFT 502 and EL element 504 are shown among Fig. 5 B.
If driver TFT 502 is p channel TFT, so as mentioned above, preferably the electrode 505 of EL element is that anode, electrode 506 are negative electrodes.Here the polarity of switching TFT 501 is considered according to the polarity of driver TFT 502.At first, are situations of p channel TFT for driver TFT 502, the condition that driver TFT 502 opens is the gate source voltage V of driver TFT 502
GS2Absolute value greater than the absolute value of driver TFT 502 threshold voltages.In other words, hang down size from the L level (supposition EL element when the electromotive force of data image signal is the L level is luminous) of the data image signal of source signal line input than driver TFT 502 source region electromotive forces here more than threshold value.
In this point, if switching TFT 501 and driver TFT 502 have same polarity, if promptly they all are the p channel-types, the condition of TFT 501 unlatchings is switching TFT 501 gate source voltage V so
GS1Absolute value greater than the absolute value of switching TFT 501 threshold voltages.In other words, the gate signal line is placed on the electromotive force low size more than threshold value of the L level (because switching TFT 501 is p channel-types, when the L level is input to the gate signal line gate signal line to be taken as be to be in selecteed state) of the pulse of selected state here than switching TFT 501 source regions.Thereby for the voltage amplitude of gate signal line side, it is necessary enlarging with respect to the voltage amplitude of source signal line.The operating voltage of this expression gate signal line driver circuit is higher.
If switching TFT 501 and driver TFT 502 are the n channel TFT, similarly environment also exists.Thereby when considering power consumption, not only use the n raceway groove and but also use the p channel TFT to become preferably for pixel portion TFT.
From above-mentioned explanation, though realized minimizing on the technology number according to the TFT structure pixel portion and the drive circuit of classic method by having single polarity, but caused the increase of power consumption.
The invention summary
Consider the problems referred to above, the purpose of this invention is to provide a kind of light-emitting device, wherein the number of technology reduces by using TFT structure pixel portion and drive circuit with single polarity, and the minimizing of wherein power consumption realizes by using new circuit structure.
In the pixel of conventional construction, necessary is the signal that is input to the switching TFT gate electrode, promptly selects the signal of gate signal line, has than the signal that is input to the switching TFT source region, promptly outputs to the big voltage amplitude of signal of source signal line.
The voltage amplitude of considering wherein to be input to source signal line equals to be used to select the situation of the voltage of signals amplitude of gate signal line.Again with reference to figure 5A and 5B.
When the signal voltage amplitude that outputs to source signal line equals to be used to select the signal voltage amplitude of gate signal line, import from source signal line if handle the signal of certain electromotive force, so the electromotive force that from electromotive force, deducts of the gate electrode potential of the driver TFT502 electromotive force that will bring up to the threshold voltage of switching TFT 501 wherein by the signal of gate signal line input.The gate electrode potential of driver TFT 502 thereby will become electromotive force than the size of the voltage amplitude low switch TFT threshold value of input signal.
Among the present invention, between switching TFT output electrode and driver TFT gate electrode, form voltage compensating circuit.The corresponding boostrap circuit of voltage compensating circuit, and play the effect of restoring signal voltage amplitude, pass switching TFT and be suppressed to its conventional amplitude.It is possible normally working for pixel like this, even allow the situation that equals to be used for to select the signal voltage amplitude of gate signal line from the signal voltage amplitude of source signal line output therein.Thereby the driving voltage that reduces the gate signal line driver circuit possibility that becomes, this helps to reduce the power consumption of display device.
The problems referred to above are constructed the pixel portion of display device and the TFT structure pixel portion drive circuit solution greatly on every side that has and constitute the same polarity of TFT of pixel portion by use by the pixel that use has voltage compensating circuit of the present invention.
Brief Description Of Drawings
In subsidiary figure:
Figure 1A and 1B are the figure that the embodiment of the present invention pattern is shown;
Fig. 2 A and 2B are the figure that embodiment of the present invention is shown;
Fig. 3 A and 3B are the figure that traditional luminous device structure is shown;
Fig. 4 A and 4B are the figure that traditional luminous device structure is shown;
Fig. 5 A and 5B are respectively the figure of pixels illustrated part TFT and light-emitting component operation;
Fig. 6 A-6D is the figure that the method for making light-emitting device of the present invention is shown;
Fig. 7 A-7C is the figure that the method for making light-emitting device of the present invention is shown;
Fig. 8 A and 8B are the figure that light-emitting device pixel portion xsect is shown for the luminous and luminous situation of lower surface of upper surface respectively;
Fig. 9 A-9F is the figure that the sequential chart that relates to light emitting device drive is shown;
Figure 10 A-10D is the figure that the sequential chart that relates to light emitting device drive is shown;
Figure 11 A-11D is the figure of each node potential when being illustrated in the pixel that drives light-emitting device of the present invention;
Figure 12 A-12E is the figure of each node potential when being illustrated in the pixel that drives light-emitting device of the present invention;
Figure 13 is the structural drawing of the source line driver circuit of structure light-emitting device of the present invention;
Figure 14 A and 14B are the circuit structure diagrams of shift register;
Figure 15 is the figure that the sequential chart that relates to the shift register driving is shown;
Figure 16 A-16C is the circuit structure diagram of impact damper;
Figure 17 A-17D is the circuit structure diagram of shift register;
Figure 18 is the circuit structure diagram of latch cicuit;
Figure 19 is the structural drawing of the gate signal line driver circuit of structure light-emitting device of the present invention;
Figure 20 A and 20B are the synoptic diagram of whole light-emitting device of the present invention;
Figure 21 A-21C illustrates the general figure that latchs the circuit structure example;
Figure 22 A-22C is the figure that the method example of making light-emitting device of the present invention is shown;
Figure 23 A-23G illustrates the figure that can use electronic equipment example of the present invention;
Figure 24 A-24C is the figure that double grid TFT xsect is shown and makes its method;
Figure 25 A and 25B are the figure that embodiment of the present invention pattern is shown; And
Figure 26 A-26C is the figure that embodiment of the present invention pattern is shown.
Detailed description of preferred embodiments
The dot structure of voltage compensating circuit of the present invention is shown in Figure 1A and 1B.Shown in Figure 1A, the parts that are similar to legacy device are used for switching TFT 101, driver TFT 102, EL element 104, source signal line (S), gate signal line (G) and electric current supplying wire (electric current).Pixel of the present invention has voltage compensating circuit 110 between the gate electrode of the output electrode of switching TFT 101 and driver TFT 102.
Figure 1B is the circuit diagram that comprises the structure of voltage compensating circuit 110.Voltage compensating circuit 110 has a TFT 151, the 2nd TFT 152, the 3rd TFT 153, first capacitor 154 and second capacitor 155.In addition, Ref. No. G (m) refers to the gate signal line in the m line scanning, and Ref. No. G (m-1) refers to the gate signal line with (m-1) line scanning.
The gate electrode of the one TFT 151 is connected to gate signal line G (m-1), and the input electrode of a TFT 151 is connected to gate signal line G (m), and the output electrode of a TFT 151 is connected to the output electrode of switching TFT 101.
The gate electrode of the 2nd TFT 152 is connected to gate signal line G (m-1), and the input electrode of the 2nd TFT 152 is connected to gate signal line G (m).The output electrode of the 2nd TFT 152 is connected to second electrode of first capacitor 154 and first electrode of second capacitor 155.
The gate electrode of the 3rd TFT 153 is connected to the output electrode of switching TFT 101, and the input electrode of the 3rd TFT153 is connected to power lead.The output electrode of the 3rd TFT 153 is connected to second electrode of first capacitor 154 and first electrode of second capacitor 155.
Notice that the TFT that all has same polarity is here as the TFT 101,102 and the 151-153 that construct pixel.Polarity can be n channel-type or p channel-type.
Next illustrates circuit operation.Here the TFT with a structure pixel all is the example of n channel TFT.Write the signal of gate signal line and the signal of selective erasing gate signal line for signal, selection from the source signal line input, the amplitude of input signal is made as VDD (H level)-VSS (L level).In addition, as original state, the electromotive force of the electromotive force of source signal line (S) and gate signal line (G) all is made as VSS, and the electromotive force of electric current supplying wire (electric current) and the electromotive force of erase gate signal wire all are made as VDD.
In addition, the threshold voltage of TFT is all got and is made VthN.Figure 11 A-11D is the sequential chart that is used to illustrate circuit operation of the present invention shown in Figure 1A and the 1B.Figure 11 A illustrates the electromotive force of (m-1) row gate signal line (G (m-1)), and Figure 11 B illustrates the electromotive force of m row gate signal line (G (m)), and Figure 11 C illustrates the electromotive force of source signal line (S (n)), and Figure 11 D illustrates the electromotive force of the gate electrode of driver TFT 102.In addition, after m row gate signal line (G (m)) is selected, up to m row gate signal line (G (m)) the selecteed once more cycle 1101 corresponding to the period of sub-frame shown in Fig. 9 F.The cycle of Ref. No. 1102 expressions is horizontal cycles.Figure 1A and 1B, Figure 11 A-11D is used in the explanation of operation.
(m-1) gate signal line (G (m-1)) is selected and become the H level, carries out data image signal writing to (m-1) row pixel.In the capable this point of the m of pixel, the H level is input to the gate electrode of a TFT 151 and the 2nd TFT 152, and it is opened then.Two electrodes of first capacitor 154 all become and equal the electromotive force of m row gate signal line, i.e. VSS.At one time, the electromotive force of the gate electrode of driver TFT 202 also becomes VSS.
(m-1) row gate signal line (G (m-1)) is not selected then, and its electromotive force becomes the L level, and a TFT 151 and the 2nd TFT 152 place off status.M row gate signal line (G (m)) is selected and become the H level, and switching TFT 101 is opened.At the electromotive force of this point source signal line (S (n)), i.e. data image signal is input to the gate electrode of driver TFT 202, and it is unlocked.Data image signal is input to the gate electrode of the 3rd TFT 153 simultaneously, its unlatching.
Electromotive force at the gate electrode of the 3rd TFT 153 and driver TFT 102 becomes on this point of (VDD-VthN), and the source of switching TFT 101 and the voltage between the grid become and equals threshold voltage vt hN, and as a result of switching TFT 101 places the state of pass.The gate electrode of the gate electrode of driver TFT 102 and the 3rd TFT 153 thereby place quick condition provisionally.
On the other hand, the electromotive force of the output electrode side of the 3rd TFT 153 raises when the 3rd TFT 153 opens.In this point, because first capacitor 154, capacitive couplings is present between the gate electrode of the output electrode of the 3rd TFT 153 and driver TFT 102.The gate electrode of driver TFT 102 is in quick condition, thereby the electromotive force of the gate electrode of driver TFT 102 raises along with the electromotive force of the output electrode of the 3rd TFT 153 that rises from (VDD-VthN) again, becomes the electromotive force that is higher than VDD.
The result is to have been weakened data image signal once by VthN and be subjected to amplitude compensation by voltage compensating circuit by switching TFT 101, and imposed on the gate electrode of driver TFT 102.Driver TFT 102 thereby unlatching normally can obtain required leakage current.
The electromotive force that imposes on the gate electrode of driver TFT 102 keeps by capacitor 154 and 155 thus, and electric current flows, and EL element 104 is luminous.In next period of sub-frame, when (m-1) gate signal line (G (m-1)) was selected, a TFT 151 and the 2nd TFT 152 placed out state.The gate electrode potential of driver TFT 102 becomes and equals the electromotive force of m row gate signal line (G (m)), i.e. L level.
Here add the explanation of first capacitor 154 and second capacitor 155.
Second capacitor, 155 additional functions are that it is used as the load that the voltage compensating circuit bootstrapping is suitably worked.If this load does not exist, if the gate electrode potential of the 3rd TFT 153 is owing to the input of digital image signal from source signal line raises so, the electromotive force of the 3rd TFT 153 output electrodes is because capacitive couplings is soaring immediately.If this operation has taken place, so aforementioned bootstrapping can not normally be worked.Because capacitive couplings, the 3rd TFT 153 output electrode earth potentials raise thereby have been delayed with respect to the rising of the 3rd TFT 153 gate electrode potential placement by second capacitor 155.The electromotive force of the 3rd TFT output electrode raises by leakage current control when the 3rd TFT itself is in out state like this, and bootstrapping can normally be worked.
The pulse of gate signal line options usually need be than the voltage amplitude of the digital image signal that is input to source signal line bigger voltage amplitude.According to above-mentioned state, the voltage amplitude that the voltage amplitude of gate signal line options is become the be equal to or less than digital image signal possibility that becomes.Thereby might reduce power consumption in gate signal line driver circuit side.
In addition, the gate electrode potential of driver TFT 102, it belongs to capacitive couplings, becomes according to the present invention to be higher than VDD.This electromotive force is elevated to VDD at least, thereby might make the voltage amplitude of gate signal line options pulse littler by the optimal value of capacitor 154 and 155.
Notice that because operational consideration, preferably the electromotive force of electric current supplying wire keeps higherly, thereby preferably the electrode of EL element 104 is Ref. No. 105 expression anodes, Ref. No. 106 expression negative electrodes for the situation shown in here.This situation is putting upside down of the conventional example discussed.Use the situation of n channel TFT to provide lower surface luminous for structure wherein, use the situation of p channel TFT to provide upper surface luminous for structure wherein.
[embodiment pattern 2]
Figure 25 A and 25B illustrate the structure that wherein partly is different from embodiment pattern 1 structure.Shown in Figure 25 A, the parts that are similar to legacy device are used for switching TFT 2501, driver TFT2502, EL element 2504, voltage compensating circuit 2510, source signal line (S (n)), gate signal line (G (m)) and electric current supplying wire (electric current).
Figure 25 B is the circuit diagram that comprises the structure of voltage compensating circuit 2510.Voltage compensating circuit 2510 has a TFT 2551, the 2nd TFT2552, first capacitive means 2553, a little capacitor 2554.By 3 TFT and 2 capacitor constructions, still in embodiment pattern 2, voltage compensating circuit 2510 is by 2 TFT and 2 capacitor constructions in embodiment pattern 1 for voltage compensating circuit.In addition, in Figure 25 B, Ref. No. G (m) is illustrated in the gate signal line of m line scanning, the gate signal line of Ref. No. G (m-1) expression (m-1) line scanning.
First capacitive means 2553 and second capacitive means, 2554 arranged in series.First electrode of first capacitive means 2553 is connected to the output electrode of switching TFT 2501, and second electrode of first capacitive means 2553 is connected to first electrode of second capacitive means 2554.Second electrode of second capacitive means 2554 is connected to electric current supplying wire.
The gate electrode of the one TFT 2551 is connected to gate signal line G (m-1), and the input electrode of a TFT 2551 is connected to provides the first electrical source voltage (V
1) signal wire, perhaps power lead.The output electrode of the one TFT 2551 is connected to the output electrode of switching TFT 2501.
The gate electrode of the 2nd TFT 2552 is connected to the output electrode of switching TFT 2501 and first electrode of first capacitive means.The input electrode of the 2nd TFT 2552 is connected to provides second source electromotive force (V
2) signal wire, perhaps power lead, the output electrode of the 2nd TFT 2552 is connected to second electrode of first capacitive means and first electrode of second capacitive means.
About two TFT of voltage compensating circuit, be called after the TFT 2551 and refresh TFT, be called compensation TFT after the 2nd TFT 2552.
Notice that the TFT that all has same polarity is here as the TFT 2501,2502,2551 and 2552 that constructs pixel.Polarity can be n channel-type or p channel-type.
Yet, the first electrical source voltage (V
1) and second source electromotive force (V
2) differ from one another according to the polarity of the TFT that constructs pixel.If the TFT of structure pixel is n channel TFT, V so
1＜V
2If the TFT of structure pixel is p channel TFT, V so
1＞V
2
If V
1＜V
2, V
1Electromotive force be made as the electromotive force enough lower, V than the threshold voltage of n channel TFT
2Electromotive force be made as than the sufficiently high electromotive force of the threshold voltage of n channel TFT.For example, V
1Electromotive force be located at the order of magnitude of signal wire L level, V
2Electromotive force be located at the order of magnitude of signal wire H level.Described electromotive force is to V
1＞V
2Situation can put upside down.
Next illustrates circuit operation.Here the TFT with a structure pixel all is the example of n channel TFT.Input signal is not the data image signal that outputs to source signal line, is used to select the signal of gate signal line to be made as VDD for the H level exactly, is made as VSS for the L level.In addition, V1=VSS and V2=VDD here.In addition, the electromotive force of electric current supplying wire (electric current) is made as Vc.
The driving sequential is similar in the embodiment pattern 1 used usually, thereby uses Figure 11 A-11D.Figure 11 A illustrates the electromotive force of (m-1) row gate signal line (G (m-1)), and Figure 11 B illustrates the electromotive force of m row gate signal line (G (m)), and Figure 11 C illustrates the electromotive force of source signal line (S (n)), and Figure 11 D illustrates the electromotive force of the gate electrode of driver TFT 2502.In addition, after m row gate signal line (G (m)) is selected, up to m row gate signal line (G (m)) the selecteed once more cycle 1101 corresponding to the period of sub-frame (SF#) shown in Fig. 9 B.The cycle of Ref. No. 1102 expressions is horizontal cycles.Wherein the pixel of switching TFT 2501 by in the pixel of the gate signal line traffic control of the capable selection of m with Figure 1A and 1B, and Figure 11 A-11D explanation.
At first, in the selecteed cycle, promptly wherein picture intelligence is to the cycle that writes enforcement of (m-1) row at (m-1) row gate signal line (G (m-1)), and (m-1) row signal line becomes the H level, and m row gate signal line becomes the L level.Thereby switching TFT 2501 shutoffs, refresh TFT 2551 and open.In this point, V
1=VSS is input to the gate electrode of driver TFT 2502, its shutoff.
(m-1) horizontal cycle is finished, and gate signal line (G (m-1)) becomes the L level.Refreshing TFT 2551 therefore turn-offs.The m horizontal cycle begins, and gate signal line (G (m)) becomes the H level, and switching TFT 2501 is opened like this.The data image signal that outputs to source signal line writes pixel in this point.When data image signal was the H level, switching TFT was opened, thereby the gate electrode potential of driver TFT 2502 raises.
Yet gate signal line (G (m)) is the H level, and its electromotive force is VDD, and digital picture is the H level, and its electromotive force is the same, VDD.The electromotive force that appears at the switching TFT output electrode is subjected to the influence of threshold value.Thereby when electromotive force became (VDD-VthN), switching TFT was turn-offed, the output electrode of switching TFT, and promptly the gate electrode of driver TFT 2502 places quick condition.
On the other hand, the output electrode electromotive force of switching TFT 2501 is elevated to (VDD-VthN).Thereby compensation TFT 2552 unlatchings, the output electrode electromotive force raises, near VDD.Be present between the gate electrode and output electrode that compensates TFT 2552 owing to first capacitive means 2553 in this capacitive couplings.The gate electrode of compensation TFT 2552 is in quick condition when its electromotive force is (VDD-VthN), thereby the further rising of electromotive force rising causing of the output electrode of compensation TFT 2552.The gate electrode potential of compensation TFT 2552 becomes and is higher than VDD.
The result is to have been weakened data image signal once by VthH and be subjected to amplitude compensation by voltage compensating circuit 2510 by switching TFT 2501, and be input to the gate electrode of driver TFT 2502.Thereby gate source voltage can be added on the driver TFT 2502 normally, can flow through required leakage current.
The electromotive force of gate electrode that imposes on driver TFT 2502 in addition, after finishing in addressing (writing) cycle, keeps by first and second capacitive means 2553 and 2554 after the selection of gate signal line is finished.In next period of sub-frame, selected and become the L level when (m-1) row gate signal line (G (m-1)), and the gate electrode potential of driver TFT 2502 refreshes TFT 2551 and opens when becoming the L level.Driver TFT 2502 turn-offs.Image demonstration on the screen is undertaken by repeating aforesaid operations.
Here add the explanation of first capacitor 2553 and second capacitor 2554.
The electromotive force of 2502 gate electrodes.
Second capacitive means 2554 has the effect of other load, and the bootstrapping operation that is used for voltage compensating circuit 2510 is carried out reliably.If this load does not exist, the gate electrode potential that compensates TFT 2552 so is owing to the input of digital image signal from source signal line begins to rise.Be higher than threshold value if electromotive force becomes, the output electrode electromotive force that compensates TFT 2552 so will rise immediately.If the electromotive force of output electrode is soaring too fast, then bootstrapping can not normally be worked.Subsequently, the electromotive force of compensation TFT2552 output electrode is soaring by using second capacitive means 2554 to be delayed as load, and gate electrode placed unsteady state before the rising of output electrode electromotive force stops.The operation of so just can booting reliably.
The pulse of gate signal line options usually need be than the voltage amplitude of the digital image signal that is input to source signal line bigger voltage amplitude.According to above-mentioned state, the voltage amplitude that the voltage amplitude of gate signal line options is become the be equal to or less than digital image signal possibility that becomes.Thereby might reduce power consumption in gate signal line driver circuit side.
In addition, be used in situation in the side circuit for the structure shown in Figure 25 A and the 25B, Figure 26 A-26C illustrates the structure that is used for required electromotive force is added to each node.It is structurally different with the link position of input electrode of compensation TFT 2552 to refresh TFT 2551, in that they are similar aspect other.
Embodiment
Embodiment of the present invention illustrate below.
[embodiment 1]
Comprise example explanation in embodiment 1 of the SES driving of the erase cycle of using pixel with additional erase mechanism.
Fig. 2 A and 2B illustrate the dot structure of the erase mechanism with embodiment 1.Shown in Fig. 2 A, pixel has switching TFT 201, driver TFT 202, EL element 204, source signal line (S), gate signal line (G) and electric current supplying wire (electric current), it is similar to legacy device, and the voltage compensating circuit 210 of the voltage compensating circuit that is similar to embodiment pattern 1 is arranged.Except gate signal line (G), pixel also has erase gate signal wire (Ge) in the embodiment 1.Note, speak of erase gate signal wire (Ge), conventional gate signal line is called and writes the gate signal line in the embodiment 1.
Fig. 2 B is the circuit diagram that comprises the structure of voltage compensating circuit 210.Voltage compensating circuit 210 has a TFT 251, the 2nd TFT 252, the 3rd TFT 253, first capacitor 254 and second capacitor 255.In addition, what reference symbol G (m) was illustrated in the m line scanning writes the gate signal line, and reference symbol G (m-1) is illustrated in the gate signal line of (m-1) line scanning.Reference symbol Ge (m) is illustrated in the erase gate signal wire of m line scanning.
The gate electrode of the one TFT 251 is connected to writes gate signal line G (m-1), and the input electrode of a TFT 251 is connected to writes gate signal line G (m), and the output electrode of a TFT 251 is connected to the output electrode of switching TFT 201.
The gate electrode of the 2nd TFT 252 is connected to writes gate signal line G (m-1), and the input electrode of the 2nd TFT 252 is connected to writes gate signal line G (m).The output electrode of the 2nd TFT 252 is connected to second electrode of first capacitor 254 and first electrode of second capacitor 255.
The gate electrode of the 3rd TFT 253 is connected to the output electrode of switching TFT 201, and the input electrode of the 3rd TFT253 is connected to erase gate signal wire Ge (m).The output electrode of the 3rd TFT 253 is connected to second electrode of first capacitor 254 and first electrode of second capacitor 255.
The TFT that notes all having same polarity is used to construct the TFT 201,202 and the 251-253 of pixel here.Polarity can be n raceway groove or p channel-type.
Next illustrates circuit operation.Here all be the example of n channel TFT with the TFT that wherein constructs pixel.Write the signal of gate signal line and the signal of selective erasing gate signal line for signal, selection from the source signal line input, the amplitude of input signal is made as VDD (H level)-VSS (L level).In addition, as original state, the electromotive force of the electromotive force of source signal line (S) and gate signal line (G) all is made as VSS, and the electromotive force of electric current supplying wire (electric current) and the electromotive force of erase gate signal wire all are made as VDD.
In addition, the threshold voltage of TFT is all got and is made VthN.Figure 12 A-12E is the sequential chart of the circuit operation of the present invention shown in key diagram 2A and the 2B.Figure 12 A illustrates the electromotive force of (m-1) row gate signal line (G (m-1)), Figure 12 B illustrates the electromotive force of the capable write signal line of m (G (m)), Figure 12 C illustrates the electromotive force of source signal line (S (n)), and Figure 12 D illustrates the electromotive force of the gate electrode of driver TFT 102, and Figure 12 E illustrates the electromotive force of erase gate signal wire.In addition, from m capable write gate signal line (G (m)) selected after, up to the capable write signal line of m (G (m)) the selecteed again cycle 1201 corresponding to the period of sub-frame shown in Fig. 9 F.The cycle of Ref. No. 1202 expressions is horizontal cycles.Fig. 2 A and 2B, Figure 12 A-12E is used in the explanation of operation.
(m-1) row gate signal line (G (m-1)) is selected and become the H level, carries out writing of data image signal to the (m-1) row pixel.In this point of the capable pixel of m, the H level is input to the gate electrode of a TFT 251 and the 2nd TFT 252, its unlatching.Two electrodes of first capacitor 254 become and equal the electromotive force of m row gate signal line, i.e. VSS.Simultaneously, the gate electrode potential of driver TFT 202 also becomes VSS.
Finish (m-1) row gate signal line (G (m-1)) selection cycle then, its electromotive force becomes the L level, and a TFT 251 and the 2nd TFT 252 place off status.M row gate signal line (G (m)) is selected and become the H level, and switching TFT 201 is opened.At the electromotive force of this point source signal line (S (n)), i.e. data image signal is input to the gate electrode of driver TFT 202, its unlatching.Data image signal is input to the gate electrode of the 3rd TFT 253 simultaneously, its unlatching.
The electromotive force of the gate electrode of the 3rd TFT 253 and driver TFT 202 becomes this point of (VDD-VthN) therein, and the grid of switching TFT 201 and the voltage between the source become and equals threshold voltage vt hN, and the result is the state that switching TFT 201 places the pass.The gate electrode of the gate electrode of driver TFT 202 and the 3rd TFT 253 thereby place quick condition provisionally.
On the other hand, when the 3rd TFT 253 opened, the electromotive force of the output electrode side of the 3rd TFT 253 raise.Capacitive couplings in this point since first capacitor 254 be present between the gate electrode of the output electrode of the 3rd TFT253 and driver TFT 202.The gate electrode of driver TFT 202 is in unsteady state, thereby the gate electrode potential of driver TFT 202 becomes the electromotive force that is higher than VDD along with the rising of the output electrode electromotive force of the 3rd TFT 253 raises from (VDD-VthN) again.Strictly speaking, it becomes the electromotive force that is higher than (VDD+VthN).
The result is, weakened data image signal once by VthN and has been subjected to amplitude compensation by switching TFT 201 by voltage compensating circuit, and be applied to the gate electrode of driver TFT 202.Driver TFT 202 thereby unlatching normally can obtain required leakage current.
The electromotive force that is applied to the gate electrode of driver TFT 202 is kept by capacitor 254 and 255 afterwards, and electric current flows, and EL element 204 is luminous.
Have the period of sub-frame of erase cycle, the electromotive force of the capable erase gate signal wire of m (Ge (m)) becomes the L level, and the electromotive force of the input electrode side of the 3rd TFT 253 descends.The gate electrode potential of driver TFT 202 is owing to pass through the capacitive couplings also decline simultaneously of first capacitor 254.The result is, the gate electrode potential of driver TFT 202 is fallen under the threshold voltage, and driver TFT 202 turn-offs, and is cut off to the electric current of EL element 204.EL element is not luminous afterwards.
In next period of sub-frame, when (m-1) row gate signal line (G (m-1)) was selected, a TFT 251 and the 2nd TFT 252 opened, and the gate electrode potential of driver TFT 202 becomes and equals the electromotive force of m row gate signal line (G (m)), i.e. L level.The electromotive force of the capable erase gate signal wire of m (Ge (m)) becomes the H level again, and m row gate signal line is selected, carries out writing of data image signal.The image demonstration is undertaken by repeating these processes in succession.
[embodiment 2]
Manufacturing has example explanation in embodiment 2 of the light-emitting device of the pixel shown in embodiment pattern 1 and 2.
Light-emitting device illustrate A in Figure 20.Pixel portion 2001 places the core of substrate 2000.Although do not illustrate especially among Figure 20 A, the structure of pixel the same with shown in Figure 1A and the 1B.Around pixel portion 2001, be formed for the source line driver circuit 2002 and the gate signal line driver circuit 2007 that is used for the control gate signal wire of Controlling Source signal wire.One of gate signal line driver circuit 2007 can also only be formed at a side of pixel portion 2001 as mentioned above.
Input from the outside is used for the signal of drive source signal line drive circuit 2002 and gate signal line driver circuit 2007 by FPC 2010 inputs.Have little voltage amplitude from the signal of FPC 2010 inputs, thereby carry out the conversion of voltage amplitude by level translator 2006, they are input to source line driver circuit 2002 and the gate signal line driver circuit 2007 in the embodiment 2 then.
Figure 13 is the figure that the source line driver circuit structure is shown.The source line driver circuit has shift register 1303, impact damper 1304, first latch cicuit 1305 and second latch cicuit 1306.Impact damper does not illustrate in Figure 20 A and 20B, but for the big situation in the load downstream of for example shift register, can form impact damper, as shown in figure 13.
Source clock signal (SCLK), source clock designature (SCLKb), source initial pulse (SSP), scan direction switch signal (LR), scan direction switch designature (LRb), data image signal (data 1-3) are input to the source line driver circuit.In these signals, clock signal and initial pulse are imported after carrying out the amplitude conversion by level shifter 1301 and 1302.
The structure of shift register is shown among Figure 14 A and the 14B.The frame of Ref. No. 1400 expressions is the level impulse output circuits partly that are used to export sampling pulse in the block diagram of Figure 14 A.(wherein n is a natural number to the shift register of Figure 14 A, 1＜n) impulse output circuit structure by the n rank.
Figure 14 B is the figure that is shown specifically the structure of impulse output circuit.TFT 1407,1408,1409 and 1410 is the switching TFT that form for the transformation of direction of scanning.Conversion left and right direction of scanning is undertaken by scan direction switch signal (LR) and scan direction switch designature (LRb).
For direction of scanning forward, sampling pulse output be in order the first order, the second level ..., (n-1) level and the n level.For reverse scan, sampling pulse output be in order n level, (n-1) level ..., the second level and the first order.
The impulse output circuit main body is made up of TFT 1401-1406 and capacitor 1411.(wherein k is a natural number in the impulse output circuit of certain k level, 1＜k＜n) is input to the gate electrode of TFT 1401 and 1404 and the gate electrode of TFT 1402 and 1403 respectively from the output pulse of (k-1) level impulse output circuit or from the output pulse of (k+1) level impulse output circuit.Note, when k=1, promptly in the initial level of impulse output circuit, initial pulse (SP) is input to the gate electrode of TFT 1401 and TFT 1404, work as k=n, promptly in the last level of impulse output circuit, initial pulse (SP) is input to the gate electrode of TFT 1402 and 1403.
When scanning direction forward, the H level is input to scan direction switch signal (LR), and the L level is input to direction of scanning conversion designature (LRb). TFT 1407 and 1410 thereby open is input to the gate electrode of TNT 1401 and 1404 from the output signal of (k-1) level impulse output circuit.On the other hand, be input to the gate electrode of TFT 1402 and 1403 from the output pulse of (k+1) level impulse output circuit.
Sao Miao situation is here operated with the explanation detail circuits as example forward.Please refer to sequential chart shown in Figure 15.
In some k level impulse output circuits, from (k-1) level impulse output circuit the output pulse be input to TFT 1401 and 1404 gate electrodes, its become the H level (if k=1, promptly for initial level, the input initial pulse). TFT 1401 and 1404 opens (with reference to Figure 15, Ref. No. 1501).The gate electrode potential of TFT 1405 is pulled to VDD side (with reference to Figure 15, Ref. No. 1502), becomes this point of VDD-VthN at electromotive force, and TFT 1401 turn-offs and also places quick condition.Greater than threshold value, TFT 1405 opens in this point for the source of TFT 1405 and the voltage between the grid.On the other hand, pulse no longer is input to the gate electrode of TFT 1402 and 1403, and it is retained in the L level and thereby is in off status.The gate electrode potential of TFT 1406 thereby be the L level, it is turned off.The electromotive force of the outlet terminal of impulse output circuit (SR out) is pulled to the VDD side according to the clock signal (SCLK or SCLKb) that is input to the input electrode of TFT 1405 like this, becomes H level (with reference to Figure 15, Ref. No. 1503).Yet under this state, the electromotive force of the outlet terminal of impulse output circuit (SR out) is had to the increase of VDD-2 (VthN) with respect to the further threshold value that descends of the electromotive force VDD-VthN of the gate electrode of TFT 1405.
Here capacitor 1411 forms between the output electrode of TFT 1405 and gate electrode, and in addition, the gate electrode of TFT 1405 is in quick condition.The gate electrode potential of TFT 1405 thereby along with the rising of the electromotive force of the outlet terminal (SR out) of impulse output circuit is promptly along with the rising of the output electrode electromotive force of TFT 1405 is mentioned from VDD-VthN by capacitor 1411.According to this operation, the final electromotive force of the gate electrode of TFT 1405 becomes and is higher than VDD+VthN (with reference to Figure 15, Ref. No. 1502).The electromotive force of the outlet terminal of impulse output circuit (SR out) is not subjected to the threshold affects of TFT1405, and normally is increased to VDD (with reference to Figure 15, Ref. No. 1503).
Pulse is exported (with reference to Figure 15, Ref. No. 1504) similarly from (k+1) level impulse output circuit.(k+1) level output pulse is got back to the k level and is input to the gate electrode of TFT 1402 and 1403. TFT 1402 and 1403 gate electrode potential become the H level, and TFT 1402 and 1403 opens.The gate electrode potential of TFTF 1405 is drawn into the VSS side, and TFT 1405 turn-offs.Simultaneously, the gate electrode potential of TFT 1406 becomes the H level, and TFT 1406 opens.The electromotive force of the outlet terminal of k level impulse output circuit (SR out) becomes the L level.
Pulse with amplitude between the VDD-VSS is then one by one by the similar operations output up to final level.For the reverse scan circuit operation also is similar.
In final level, return pulse not from next level input, thereby clock signal continues 1405 outputs (with reference to Figure 15, Ref. No. 1507) by TFT.Thereby the output pulse of final level impulse output circuit can not be used as sampling pulse.Similarly, for the situation of reverse scan, initial level output pulse is last level output pulse, thereby can not be used as sampling pulse.In the circuit shown in the embodiment 2, shift register thereby equal necessary number of stages with number and add two impulse output circuit structure.At the impulse output circuit at two ends as pseudo-level (the corresponding pseudo-level of the impulse output circuit that impact damper 1304 is not connected among Figure 13).Promptly be like this, be necessary before next horizontal cycle begins by stopping final output someway, thus final output the initial pulse of next horizontal cycle by with initial pulse as the initial level input with stop this point that the level cycle imports and stop.
Figure 16 A and 16B illustrate the structure of the impact damper 1304 in the light-emitting device that is used in embodiment 2.Shown in Figure 16 A, this is the structure with four level 1601-1604.Having only first level is single input, single output type.Second level with the back is dual input, lose-lose removing from mould.
The circuit structure of initial level unit 1601 is shown in Figure 16 B.Signal is input to the gate electrode of TFT 1652 and 1654.The gate electrode of TFT 1651 is connected to input electrode.If the H level is input to the gate electrode of TFT 1652 and 1654, with the state that TFT places out, the gate electrode potential of TFT 1653 becomes the L level so, and the result is that outlet terminal (out) becomes the L level.If the L level is input to the gate electrode of TFT 1652 and 1654, TFT turn-offs.The input electrode of TFT 1651 is connected with gate electrode, and TFT 1651 normally opens, thereby the gate electrode potential of TFT 1653 raises.Be similar to the situation of above-mentioned shift register, because capacitor 1655 has capacitive couplings, thereby output becomes the H level.
Notice that TFT 1651 is as follows with the relation of TFT 1652: the input electrode of TFT 1651 is connected with gate electrode, thereby when TFT 1652 opened, TFT 1651 and TFT 1652 were in out state.Gate electrode potential for TFT 1653 is necessary to become the L level at this state, thereby is necessary that channel width with TFT 1651 designs less than the width of TFT 1652.If TFT 1653 has only a gate electrode to have charged ability, thus the channel width of TFT 1651 can be made as minimum value just enough.And, because the increase that runs through the current drain that the path causes when TFT 1652 is opening can be by making the TFT 1651 littler minimum value that reduce among VDD, TFT 1651, TFT 1652 and the VSS.
Figure 16 C illustrates and is used in second and the later structure of the unit circuit of level.Input to the gate electrode of TFT 1652 is similar to initial level, and in addition, the preceding stage input is with accomplishing that the gate electrode of TFT 1651 oppositely imports.Like this, TFT 1651 and 1652 exclusively opens respectively and closes, in the structure of Figure 16 B, and running through the path and can eliminate between VDD, TFT 1651, TFT 1652 and the VSS.
Figure 17 A-17D illustrates the initial pulse level shifter (B) in the light-emitting device that is used in embodiment 2 and the structure of clock signal level shifter (A).Basic structure has four levels, and the level shifter of initial level, second and the later impact damper of level is similar to aforementioned buffer circuit.Input has VDD
L0The signal of the amplitude of-VSS, obtain having the amplitude of VDD-VSS output signal (wherein here | VDD
L0|＜| VDD|).
About the clock signal level shifter, initial level is single input, single output type, and second and follow-up level be dual input, single output type.The clock signal level shifter is used to make mutual input to become reverse input.
The initial pulse level shifter has the structure of the aforementioned buffers of being similar to.
The unit circuit that is used in the initial level of level shifter is shown in Figure 17 C, and be used for second and the unit circuit structure of following stages be shown in Figure 17 D.Circuit structure and operation be similar to respectively shown in Figure 16 B and the 16C like that.Unique different a bit be that the amplitude of initial level signal input is VDD
L0-VSS.
This level shifter structure has a feature, and promptly input signal is not directly inputted to gate electrode when being operatively connected to the TFT 1751 of high potential side (VDD side).Subsequently, no matter how many threshold values of TFT 1751 is, even the amplitude of input signal is very little, the gate electrode potential of TFT 1753 also can be mentioned.Thereby obtain the high amplitude conversion gain.
Figure 18 illustrates first latch cicuit in the light-emitting device that is used in embodiment 2 and the structure of second latch cicuit.Shown in Figure 21 A, form and to comprise that wherein it is universal architecture as traditional cmos latch cicuit example that two phase inverters are connected the structure of storage area of an annular and the switch that is used for the control store sequential.In addition, using the structure of Figure 21 B of D-FF (bistable state) circuit also to can be used as example provides.Figure 21 C is the simplest DRAM structure, and storage area is by phase inverter and capacitor constructions.The electromotive force of signal of phase inverter that is input to first latch cicuit (LAT1) and second latch cicuit (LAT2) is by capacitor stores.The simplest structure is used in the embodiment 2 among Figure 21 C.
To such an extent as to latch cicuit shown in Figure 180 is the analog switch of a n channel TFT replacement of structure Figure 21 C so, by the NMOS phase inverter replaced C MOS phase inverter of four n channel TFT and capacitor bank.
If data image signal is from the input electrode input (data in) of TFT 1850, sampling pulse is input to gate electrode (pulse in), opens TFT 1850, and data image signal is input to the phase inverter of being made up of TFT 1851-1854 and capacitor 1855 then, reversal of poles, signal output.In addition, data image signal is stored with capacitor 1856.
Data image signal also writes and is stored in second latch cicuit by similar operation according to latch pulse (LAT) input timing.
Figure 19 is the figure that the circuit structure of gate signal line driver circuit is shown.The gate signal line driver circuit has shift register 1903 and impact damper 1904.
Grid side clock signal (GCLK), grid side clock designature (GLKb) and grid side trigger pip (GSP) are input to the gate signal line driver circuit.Input signal is imported after carrying out the amplitude conversion with level shifter 1901 and 1902.
Notice that shift register 1903, impact damper 1904, initial pulse level shifter 1901 and clock signal level shifter 1902 are similar in the source line driver circuit used, thereby the explanation of their structure and operation is omitted at this.
Among Figure 19, the gate signal line of the row of being represented by reference symbol α forms as pseudo-level, imports because first row of pixel can not obtain the gate signal line options pulse of front delegation.
Display device that introduce here and that made by pixel shown in embodiment pattern 1 and 2 and drive circuit is only with unipolarity TFT structure, thereby can eliminate the part of doping process in the manufacture process.In addition, the number that the reduces mask possibility that becomes.As mentioned above, also possible is to solve because the problem of the increase of the current sinking that the signal amplitude that provides the circuit of bootstrapping method to enlarge by use causes.
[embodiment 3]
Pixel with erase gate signal wire illustrates that in embodiment 1 still with this class pixel, the selection sequential of writing the gate signal line is different from the selection sequential of erase gate signal wire.Thereby, being placed in one of gate signal line driver circuit on the pixel portion both sides shown in Figure 20 B and can be used as and write gate signal line driver circuit structure, another can be used as erase gate signal line drive circuit structure.Circuit structure can be similar to illustrate in the embodiment 2 such, thereby its detailed explanation is omitted at this.
[embodiment 4]
The present embodiment provide make be used for driving be provided in the pixel portion that forms on the same substrate around and the explanation of the method for the TFT of the circuit of pixel portion.
At first, as shown in Figure 6A, basement membrane 5002 is by such as the silicon oxide film on glass substrate 5001, and the dielectric film of silicon nitride film, silicon oxynitride film forms.Substrate 5001 is that Corning # 7059 glass or Corning#1737 glass (product of Corning company) or alumina borosilicate glass form by barium borosilicate glass, its typical example.Basement membrane 5002 is that for example, (not diagram) is by SiH
4, NH
3, and N
2O forms the silicon oxynitride film of 10-200nm (preferred 50-100nm) thickness by plasma CVD and by SiH
4And N
2O forms the lamination of the hydrogen silicon oxynitride film (silicon oxynitride hydride film) of 50-200nm (preferred 100-150nm) thickness by plasma CVD.
Semiconductor film with non crystalline structure by laser crystallization or known thermal crystallisation method crystallization to form the crystal semiconductor film.The crystal semiconductor film produces island semiconductor layer 5003-5005.Each of island semiconductor layer 5003-5005 has the thickness of 25-80nm (preferred 30-60nm).In the selection of crystal semiconductor membrane material, without limits, still preferably use silicon or germanium silicon (SiGe) alloy.
When the crystal semiconductor film forms by laser crystallization, use impulse hunting type or continuous wave excimer laser, YAG laser instrument or YVO
4Laser instrument.From as above the laser of laser instrument of these laser instruments of providing before the irradiation semiconductor film, be gathered into linear beam by optical system ideally.The condition of crystallization is suitably set by the operator.Yet if use excimer laser, the impulse hunting frequency is made as 30Hz, and laser energy density is made as 100-400mJ/cm
2(200-300mJ/cm typically
2).If use the YAG laser instrument, adopt its second harmonic, the impulse hunting frequency is made as 1-10kHz, and the setting laser energy density is 300-600mJ/cm simultaneously
2(350-500mJ/cm typically
2).Laser is gathered into has 100-1000 μ m, and for example the linear beam of the width of 400 μ m is with the irradiation entire substrate.The linear laser irradiation that substrate overlaps each other with the overlap ratio of 80-98% with light beam.
Secondly, gate insulating film 5006 forms, so that cover island semiconductor layer 5003-5005.Gate insulating film 5006 is formed the thickness of 40-150nm by plasma CVD or sputter by siliceous dielectric film.In the present embodiment, use thickness silicon oxynitride film with 120nm.Needless to say, gate insulating film is not limited to silicon oxynitride film, and can be the individual layer or the lamination of other siliceous dielectric film.For example, if silicon oxide film is used for gate insulating film, film forms by plasma CVD, wherein TEOS (tetraethyl orthosilicate, tetraethyl orthosilicate ester) and O
2Mix, reaction pressure is made as 40Pa, and underlayer temperature is 300-400 ℃, and frequency setting is up to 13.56MHz, and the power density that is used for the electric power discharge is made as 0.5-0.8W/cm
2The silicon oxide film of Xing Chenging can provide the gate insulating film that has premium properties when it is subjected to the thermal treatment at 400-500 ℃ subsequently like this.
On gate insulating film 5006, be formed for forming first conducting film 5007 and second conducting film 5008 of gate electrode.In the present embodiment, have the Ta film of 50-100nm thickness during first conducting film 5007, second conducting film 5009 is the W films (figure A) with 100-300nm thickness.
The Ta film forms by sputter, and wherein Ta is as target Ar sputter.In this situation, an amount of Xe or Kr join the internal stress that alleviates the Ta film among the Ar, prevent peeling off of Ta film like this.The resistivity of α phase Ta film approximately is 20 μ Ω cm, can be used for gate electrode.On the other hand, the resistivity of β phase Ta film approximately is 180 μ Ω cm, is not suitable for gate electrode.When the basis of about 10-50nm thickness (base) when forming, can easily obtain α phase Ta film by the tantalum nitride (TaN) with the crystal structure that is similar to α phase Ta film.
The W film forms by sputter as target with W.In addition, the W film can be used tungsten hexafluoride (WF
6) form by hot CVD.In arbitrary situation, the W film must have low-resistivity so that with the W film as gate electrode.The desirable resistivity of W film is 20 μ Ω cm or lower.The resistivity of W film can reduce by increasing crystallite dimension, if but too many impurity element such as oxygen is arranged in the W film, just hinder crystallization to improve resistivity.Therefore, when the W film forms by sputter, with having the W target of 99.9999% purity, and to give very careful, so that do not allow airborne impurity to be mixed in the W film to be formed.The result is that the W film can have the resistivity of 9-20 μ Ω cm.
Though first conducting film 5007 is Ta films in the present embodiment, second conducting film 5008 is W films, has no particular limits.Conducting film can be formed by the compound-material or the alloy material that are selected from any element in the group that comprises Ta, W, Mo, Al and Cu or mainly comprise column element.Semiconductor film, typically use the polycrystal semiconductor film that mixes such as the impurity element of phosphorus can replace use.The combination of the ideal material of other first and second conducting film comprises except shown in the present embodiment: the W of the tantalum nitride of first conducting film 5007 (TaN) and second conducting film 5008; The Al of the tantalum nitride of first conducting film 5007 (TaN) and second conducting film 5008; The Cu of the tantalum nitride of first conducting film 5007 (TaN) and second conducting film 5008.
Secondly, form Etching mask 5009, to be used to form first etching processing of electrode and wire line.In the present embodiment, adopt ICP (inducing coupled plasma) etching, wherein CF
4And CL
2Mix as etching gas, the RF of 500W (13.56MHz) power gives coil electrode to produce plasma under the pressure of 1Pa.Substrate side (sample stage) also accepts the RF (13.56MHz) of 100W thereby power applies negative basically self-bias.When using CF
4And Cl
2Potpourri the time, W film and Ta film etch into same degree.
Under above-mentioned etching condition, if suitably moulding of Etching mask, acting on around the edge of first conducting film and second conducting film bias voltage by being applied to substrate side is taper.The angle of tapering part is 15 °-45 °.For the etching conductive film, and do not stay any residue in gate insulating film, etching time prolongs 10-20%.The W film is 2-4 (typically 3) to the selection ratio of silicon oxynitride film, thereby the silicon oxynitride film exposed areas is handled the about 20-50nm of etching by over etching.In this way, the first shape conductive layer 5010-5013 that comprises the first conductive layer 5010a-5013a and the second conductive layer 5010b-5013b is formed by first conducting film and second conducting film by first etching processing.In this point, the zone of the gate insulating film 5006 that the first shape conductive layer 5010-5013 of no use covers is etched and the about 20-50nm of attenuate (Fig. 6 B).
At first implement the doping (Fig. 6 B) that first doping treatment is used to provide the impurity element of N type electric conductivity.Adopt ion doping or ion to inject.In ion doping, dosage is made as 1 * 10
13-5 * 10
14Atom/cm
2, accelerating potential is made as 60-100keV.The impurity element that provides N type electric conductivity belongs to 15 families, typically, and phosphorus (P) or arsenic (As).Here use phosphorus (P).In this situation, conductive layer 5010-5013 stops the element that provides N type electric conductivity as mask, and the first impurity range 5014-5016 forms in self aligned mode.The first impurity range 5014-5016 respectively comprise provide N type electric conductivity be in 1 * 10
20-1 * 10
21Atom/cm
3The impurity element of concentration.
Secondly, shown in Fig. 6 C, implement second etching technics.Use the ICP etching method similarly, wherein CF
4, Cl
2And O
2Mix as etching gas, the RF of 500W (13.56MHz) power imposes on the coil form electrode to produce plasma under the pressure of 1Pa.The RF power of 50W imposes on substrate side (sample stage), applies upward compared with self-bias low in first etching technics.According to these conditions, as the W film of second conductive layer etching anisotropically, as the Ta film of first conducting film with the etch rate that is lower than the W film anisotropically etching to form the second shape conductive layer 5017-5020 (the first conductive layer 5017a-5020a and the second conductive layer 5017b-5020b).Ref. No. 5006 refers to gate insulating film, and the zone that is covered by the second shape conductive layer 5017-5020 is not etched into the film thickness of about 20-50nm, to form thin district.
W film and Ta film are for CF
4And Cl
2The reaction of etching of mixed gas can derive out from the free radical that produces or the vapor pressure of ion samples and reaction product.Relatively W and the chloride of Ta and the vapor pressure between the fluoride are as the WF of the fluoride of W
6Have very high vapor pressure, and other, i.e. WCl
5, TaF
5, and TaCl
5Vapor pressure with approximately same degree.Therefore, W film and Ta film are all used CF
4And Cl
4The mixed gas etching.Yet, as an amount of O
2When adding in this mixed gas, CF
4And O
2Interreaction produces a large amount of F free radicals or F ion to become CO and F.The result is that its fluoride has the etch rate etching of W film to improve of high vapor pressure.On the other hand, the etch rate of Ta film does not increase a lot when increasing on the F ion populations.Because Ta is than the easier oxidation of W, O
2Adding cause the oxidation on Ta film surface.The oxide of Ta does not react with fluorine or chlorine, thereby the etch rate of Ta film further reduces.The difference of etch rate is incorporated between W film and the Ta film like this, thereby the etch rate of W film is provided with sooner than the etch rate of Ta film.
Carry out second doping treatment (Fig. 6 D) then.In second doping treatment, film mixes under high accelerating potential with the dosage less than first doping treatment with the impurity element that provides N type electric conductivity.For example, accelerating potential is made as 7-120keV, and dosage is made as 1 * 10
13Atom/cm
2, with the new impurity range of the inner formation of first impurity range in being formed at the island semiconductor layer of Fig. 6 B.When the second conductive layer 5017b-5020b is used as the mask that stops impurity element, also mix with impurity element in the zone under the first conductive layer 5017a-5020a.That form like this is the second impurity range 5021-5023 overlapping with first conductive layer.
Secondly, shown in Fig. 7 A, implement the 3rd etching technics.In the present embodiment, adopt the ICP etching device, Cl
2As etching gas.
Etching was carried out 70 seconds, set Cl
2Flow velocity be 60 (sccm), the RF power of 350W is being applied under the pressure of 1Pa on the coil shape electrode to produce plasma.RF power also is applied to substrate side (sample stage), thereby applies negative basically self-bias.By the 3rd etching technics, etching first conductive layer forms the 3rd shape conductive layer 5024-5027 (the first conductive layer 5024a-5027a and the second conductive layer 5024b-5027b) thus to reduce the zone.The second impurity range 5021-5023 comprises and overlapping second impurity range 5028a-5030a of first conductive layer and the 3rd impurity range 5028b-5030b that do not covered by first conductive layer.
By above-mentioned steps, in dividing other island semiconductor layer, form impurity range.Work as the gate electrode of TFT with the 3rd shape conductive layer 5024-5026 of island semiconductor ply.The 3rd shape conductive layer 5027 works as the island source signal line.
Activation is used to mix the island semiconductor layer to control the impurity element of conduction type.Activating step implements by thermal annealing with annealing furnace.Other activates adoptable method and comprises laser annealing and rapid thermal annealing (RTA).Thermal annealing is at 400-700 ℃, typically 500-600 ℃, in that 1ppm or is still less arranged, preferably carries out in the blanket of nitrogen of 0.1ppm or oxygen concentration still less.In the present embodiment, substrate was 500 ℃ of heat-treated 4 hours.Yet,, activate ideally and after formation interlayer insulating film (mainly siliceous) is with guardwire circuit and other line, carry out if it is thermo-labile to be used for the wire line material of the 3rd shape conductive layer 5024-5027.
Another time thermal treatment in the atmosphere that contains 3-100% hydrogen 300-450 ℃ carried out hydrogenation island semiconductor layer thus 1-12 hour.Step of hydrogenation is with the dangling bonds in the heat activated hydrogen termination semiconductor layer.In addition, can using plasma hydrogenation (using the hydrogen that activates by plasma).
Shown in Fig. 7 B, secondly the silicon oxynitride film by 100-200nm thickness forms first interlayer insulating film 5031.Form second interlayer insulating film 5032 thereon by organic insulation.Afterwards, form contact hole, corresponding first interlayer insulating film 5031, second interlayer insulating film 5032 and gate insulating film 5006.The film that formation is made by the wire line material is thus connected wire line 5033-5037 and connection electrode 5038 and forms by forming figure.Then, form pixel electrode 5039 so that contact by forming figure with connection electrode 5038.
Comprise in the present embodiment that wire line 5033-5037 and connection electrode 5038 and substrate refer to the active matrix substrate.
Second interlayer insulating film 5032 is films that organic resin is made.The example of available organic resin comprises polyimide, polyamide, acryl resin and BCB (benzocyclobutene, benzocyclobutene).Because complanation is the active importance of second interlayer insulating film 5032, the acryl resin of flat surface is preferred especially well.In the present embodiment, acrylic film is enough thick in to eliminate the level difference that TFT causes.The suitable thickness of film is 1-5 μ m (preferably 2-4 μ m).
Contact hole forms by doing to carve or wet to carve, and comprises the contact hole that arrives impurity range 5014-4016, source signal line 5027, gate signal line (not having diagram), power supply supply line (not having to illustrate) and gate electrode 5024-5026 (not having diagram) with N type electric conductivity respectively.
In addition, the stack membrane of three-decker, wherein the thick Ti film of 100nm, the thick Al film of 300nm that contains Ti, the thick Ti film of 150nm form in proper order by sputter e lead 5033-5038.Certainly, also can use other conducting film.
In the present embodiment, pixel electrode (reflecting electrode) 5039 forms the thickness with 200nm by MgAg etc., forms figure then.Forming pixel electrode 5039 contacts with connection electrode 5038.
Secondly, shown in Fig. 7 C, contain the thickness that is formed into 1-3 μ m such as the dielectric film of the organic material of acryl resin, open an aperture on the position corresponding to pixel electrode 5039 positions in film.Form the 3rd interlayer insulating film 5040 like this.When forming the aperture, preferably the etching sidewall is so that become taper.If the sidewall in aperture is smooth inadequately, level difference can make the degeneration of EL layer become serious problem.
EL layer 5041 and opposite electrode (transparency electrode) 5042 form by the vacuum evaporation order.The thickness of EL layer is made as 80-120nm (typically 100-120nm).The thickness of pixel electrode (transparency electrode) 5042 is made as 110nm.
In this step, EL layer and pixel electrode (transparency electrode), form in the blue light pixel then in the green glow pixel then in the ruddiness pixel.The EL layer has low repellence to solution, has stoped photolithographic use.Thereby a kind of EL layer of color and pixel electrode (transparency electrode) can not form together with the EL layer and the pixel electrode (transparency electrode) of other color.EL layer and pixel electrode (transparency electrode) optionally form in a kind of color pixel then, cover other two kinds of color pixel with metal mask simultaneously.
According to R, G and B, what form here is three class EL element.Can use the white luminous EL element that makes up with color filter in addition, with fluorophor (fluorescence color conversion layer: CCM) Zu He blueness and blue-green light-emitting component.
Notice that known material can be used for EL layer 5041.Consider driving voltage, preferred known materials is an organic material.
By above-mentioned steps, the anode that negative electrode that formation MgAg makes and EL layer and nesa coating are made.Then, passivating film forms the thickness with 50-300nm by silicon nitride as diaphragm 5043.Diaphragm 5043 protection EL avoid the influence of moisture etc.
In fact, the device that arrives Fig. 7 C state allows the diaphragm or the printing opacity of gas permeation (dwelling stack membrane or UV aged resin) to pack (encapsulation) with high-seal hardly, so that further avoid being exposed to outside air.The space of sealed inside can be made as inert atmosphere or hygroscopic material (for example baryta) can be placed on there to improve the reliability of EL element.
By packing or after other technology guaranteed sealing, attached connection connector (flexible print circuit: FPC) be used for the terminal that the element that will form on external signal terminal and the substrate or circuit draw and link to each other.But the device that is in travel position in the present technique explanation is called display device.
By following the technology shown in the present embodiment, the number of making the required photomask of active matrix substrate can be reduced to 4 (the island semiconductor layer pattern forms, comprises that the first wire line figure of grid wire line, island source wire line and capacitive lead circuit forms, contact hole graph forms, comprises that the second wire line figure of connection electrode forms).The result is that technological process has been prescinded to reduce manufacturing cost and to improve output.
[embodiment 5]
The example of constructing the situation of peripheral drive circuit and pixel with the n channel TFT illustrates in embodiment 4, but also might realize the present invention with the p channel TFT.
The impurity range that is called the overlay region for the n channel TFT forms to control hot carrier degradation etc. in the zone with gate electrode.On the contrary, almost do not have because the influence that hot carrier degradation causes for the situation of p channel TFT, thereby the not special necessary overlay region that forms.Thereby might make with simple process steps more.
On by the dielectric substrate of making such as the material of glass 6001, form basement membrane 6002, form island semiconductor layer 6003-6005, gate insulating film 6006 and conductive layer 6007 and 6008 as Figure 22 A according to embodiment 4 then.Conductive layer 6007 and 6008 is shown rhythmo structure here, but also can use single layer structure, does not have special problem.
Secondly, shown in Figure 22 B, form mask 6009, carry out first etching technics by resist.The selectivity that anisotropic etching causes by the material property that utilizes the rhythmo structure conductive layer in embodiment 4 is implemented.Yet, be not that necessary especially formation becomes the zone of overlay region here, thereby can implement normal etching.The zone of the total amount that has approached the 20-50nm magnitude owing to becoming in this point etching forms in gate insulating film 6006.
Secondly, implement to be used to add first doping process of the impurity element that gives island semiconductor layer p type electric conductivity.Conductive layer 6010-6012 is as the mask that stops impurity element, and impurity range forms in self aligned mode.Boron (B) etc. are typically as the impurity element that provides p type electric conductivity.Here impurity range is by using borine (B
2H
6) ion doping formation, the impurity concentration in the semiconductor layer is made as 2 * 10
20-2 * 10
21Atom/cm
3
Remove Etching mask then, obtain the state of Figure 22 C.The processing step that makes progress according to Fig. 7 B in the embodiment 4 continues to make then.
Noting, is the p channel TFT because form the TFT of pixel and peripheral drive device circuit, preferably forms a kind of structure in the embodiment 5, and it is the opposite of EL element structure shown in the embodiment 4.That is, the pixel electrode 5032 usefulness transparency electrodes that are used in Fig. 7 B in the embodiment 4 form, and as the EL element anode.In addition, form after the EL layer, form reflecting electrode, and be used as the negative electrode of EL element by material such as MgAg.The light that produces in the EL element thereby formed the substrate emission of TFT towards this structure of top usefulness.
[embodiment 6]
In the technology shown in the embodiment 4, the TFT of structure drive circuit and pixel is the TFT with conventional single grid structure, but the present invention can also be with having the TFT realization that is clipped in a plurality of gate electrode structures in the active layer, as Figure 24 C.The explanation of manufacturing process illustrates below.
By barium borosilicate glass, alumina borosilicate glass etc., typically form conducting film by conductive material on the substrate 7001 that the #7059 of Corning company glass or #1737 glass are made, form down gate electrode 7002 by the figure shown in Figure 24 A.Under being used to form, have no particular limits on the material of gate electrode, as long as it is a conductive material.Typically use material such as Ta and W.
Next forms first dielectric film 7003.First dielectric film, 7003 usefulness silicon oxynitrides form the thickness of 10-50nm.
The surface is caused by following gate electrode 7002 as Figure 24 unevenness that A is shown with when first dielectric film 7003 forms.Consider later manufacturing process, preferably implement the leveling of unevenness.CMP (chemically mechanical polishing) is here as leveling device.CMP is a kind of by polished body surface being carried out chemical treatment, making the surface easily to polishing condition, carry out the method that mechanical buffing obtains densification, smooth surface then.
On first dielectric film 7003, form silicon oxide film or silicon oxynitride film as leveling film 7004 with 0.5-1 μ m thickness.For example, be dispersed in the CMP brilliant polish (slurry) that potpourri in the KOH aqueous solution can be used as leveling film 7004 by the thermal decomposition of silicon chloride gas (fumed) silicon oxide particle of being fuming.0.5-1 the total amount of μ m magnitude is by removing planarization surface with the CMP polishing from the surface of leveling film 7004.
Obtain the surface like this and be flattened the state of having changed, shown in Figure 34 B.Can form TFT according to embodiment 4 then, form peripheral circuit and pixel.
Here the TFT of Zhi Zaoing has overlapping gate electrode and following gate electrode, clamps active layer.For requiring fast corresponding situation, such as on-off circuit, signal can be input to down gate electrode 7002 and gate electrode 7006.By signal being input to two gate electrodes, it is very fast that ground is carried out in the loss of channel region in the active layer, and the field effect mobility increases, and can improve current capacity.Like this can be in advance in respect of fast corresponding performance.
On the other hand, for the situation of homogeneity that requires performance and low current leakage, as pixel part driver TFT, signal can be input to gate electrode and descend gate electrode to remain on a certain fixing electromotive force.The a certain fixed potential of term refers to that when electromotive force is added in the gate electrode of TFT TFT remains on the state of pass reliably.Typically, if n channel TFT during TFT, following gate electrode is connected to the low potential side power supply such as VSS, if TFT is the p channel TFT, then is connected to the high potential power supply such as VDD.In this situation, when comparing with the TFT that does not have following gate electrode structure, the discrete of threshold voltage can reduce.In addition, because also can expect reducing of leakage current, so it is effective.
[embodiment 7]
Semiconductor device of the present invention can be applicable to be used for the manufacturing of the display device of various electronic equipments.This class display device comprises portable data assistance (electronic memo, movable computer, portable phone etc.), video camera, digital camera, personal computer, TV, portable phone etc.Figure 23 A-23G illustrates their example.
Figure 23 A illustrates the OLED display of being made up of support 3001, brace table 3002, display part 3003 etc.Semiconductor device of the present invention can be applicable to the manufacturing of display part 3003.
Figure 23 B illustrates the video camera of being made up of body 3011, display part 3012, sound importation 3013, operating switch 3014, battery 3015, image receiving unit 3016 etc.Semiconductor device of the present invention can be applicable to the manufacturing of display part 3012.
Figure 23 C illustrates the notebook-sized personal computer of being made up of body 3021, support 3022, display part 3023, keyboard 3024 etc.Semiconductor device of the present invention can be applicable to the manufacturing of display part 3023.
Figure 23 D illustrates the portable data assistance of being made up of body 3031, input pen 3032, display part 3033, action button 3034, outer interface 3035 etc.Semiconductor device of the present invention can be applicable to the manufacturing of display part 3033.
Figure 23 E illustrates sound reproduction system, and concrete is stereo set on the machine, and it is made up of body 3041, display part 3042, operating switch 3043 and 3044 etc.Semiconductor device of the present invention can be applicable to the manufacturing of display part 3042.In addition, though stereo set on the machine has been described in this example, the present invention also can be used for portable or the family expenses stereo set.
Figure 23 F illustrates the digital camera of being made up of body 3051, display part (A) 3052, eyeshade part 3053, operating switch 3054, display part (B) 3055, battery 3056 etc.Semiconductor device of the present invention can be applicable to the manufacturing of display part (A) 3052 and display part (B) 3055.
Figure 23 G illustrates the portable phone of being made up of body 3061, voice output part 3062, sound importation 3063, display part 3064, operating switch 3065, antenna 3066 etc.Semiconductor device of the present invention can be applicable to the manufacturing of display part 3064.
Notice that the above-mentioned example that provides only is an example, the invention is not restricted to these application.
In the light-emitting device of the present invention, pixel portion and peripheral drive device circuit are formed integrally as with unipolarity TFT.The part of doping process can be deleted, and in addition, the number of mask can reduce, and it helps the increase of quantum of output and the minimizing of cost.
In addition, light-emitting device of the present invention has the new structure of corresponding bootstrapping method, and the voltage amplitude that is used to drive pixel can be done forr a short time.This helps the minimizing of light-emitting device power consumption.
Claims (21)
1. display device comprises:
Pixel, it comprises:
The first transistor, this first transistor comprises the gate electrode that is electrically connected to first grid signal wire;
Transistor seconds, this transistor seconds comprise the gate electrode that is electrically connected to the second gate signal line and are electrically connected to the input electrode of described first grid signal wire;
The 3rd transistor, the 3rd transistor comprises the gate electrode of the output electrode that is electrically connected to described the first transistor and transistor seconds; With
The 4th transistor, the 4th transistor comprise gate electrode that is electrically connected to described the 3rd transistorized described gate electrode and the output electrode that is electrically connected to EL element,
Wherein said the first transistor, described transistor seconds is described has identical conduction type with the 3rd transistor.
2. display device comprises:
Pixel, it comprises:
The first transistor that comprises the gate electrode that is electrically connected to first grid signal wire;
Comprise gate electrode that is electrically connected to the second gate signal line and the transistor seconds that is electrically connected to the input electrode of described first grid signal wire; With
The 3rd transistor that comprises the gate electrode that is electrically connected to the described first and second transistorized output electrodes,
Comprise gate electrode that is electrically connected to described the 3rd transistorized described gate electrode and the 4th transistor that is electrically connected to the input electrode of electric current supplying wire,
Wherein said the first transistor, described transistor seconds and described the 3rd transistor have identical conduction type.
3. display device comprises:
Pixel, it comprises:
The first transistor that comprises the gate electrode that is electrically connected to first grid signal wire;
Comprise gate electrode that is electrically connected to the second gate signal line and the transistor seconds that is electrically connected to the input electrode of described first grid signal wire; With
Comprise being electrically connected to described first and the 3rd transistor of the gate electrode of the output electrode of described transistor seconds,
The 4th transistor that comprises the gate electrode that is electrically connected to described the 3rd transistorized described gate electrode,
Wherein said the first transistor, described transistor seconds and described the 3rd transistor have identical conduction type.
4. according to the display device of claim 1, further be included in the capacitor between the described the 3rd transistorized described gate electrode and the output electrode.
5. according to the display device of claim 2, further be included in the capacitor between the described the 3rd transistorized described gate electrode and the output electrode.
6. according to the display device of claim 3, further be included in the capacitor between the described the 3rd transistorized described gate electrode and the output electrode.
7. according to the display device of claim 1, further comprise drive circuit, this drive circuit comprises a plurality of transistors with conduction type identical with described first, second, third transistor.
8. according to the display device of claim 2, further comprise drive circuit, this drive circuit comprises a plurality of transistors with conduction type identical with described first, second, third transistor.
9. according to the display device of claim 3, further comprise drive circuit, this drive circuit comprises a plurality of transistors with conduction type identical with described first, second, third transistor.
10. according to the display device of claim 1, wherein data image signal is input to described pixel.
11., wherein data image signal is input to described pixel according to the display device of claim 2.
12., wherein data image signal is input to described pixel according to the display device of claim 3.
13. according to the display device of claim 1, wherein this display device is used for the electronic equipment selected from the group that comprises OLED display, video camera, notebook-sized personal computer, portable data assistance, sound reproduction system, digital camera and portable phone.
14. according to the display device of claim 2, wherein this display device is used for the electronic equipment selected from the group that comprises OLED display, video camera, notebook-sized personal computer, portable data assistance, sound reproduction system, digital camera and portable phone.
15. according to the display device of claim 3, wherein this display device is used for the electronic equipment selected from the group that comprises OLED display, video camera, notebook-sized personal computer, portable data assistance, sound reproduction system, digital camera and portable phone.
16. according to the display device of claim 1, wherein the electromotive force of described the 3rd transistorized described gate electrode is in quick condition when described the first transistor and described transistor seconds are in off state.
17. according to the display device of claim 1, wherein the electromotive force of described the 3rd transistorized described gate electrode rises when described the first transistor and described transistor seconds are in off state.
18. according to the display device of claim 2, wherein the electromotive force of described the 3rd transistorized described gate electrode is in quick condition when described the first transistor and described transistor seconds are in off state.
19. according to the display device of claim 2, wherein the electromotive force of described the 3rd transistorized described gate electrode rises when described the first transistor and described transistor seconds are in off state.
20. according to the display device of claim 3, wherein the electromotive force of described the 3rd transistorized described gate electrode is in quick condition when described the first transistor and described transistor seconds are in off state.
21. according to the display device of claim 3, wherein the electromotive force of described the 3rd transistorized described gate electrode rises when described the first transistor and described transistor seconds are in off state.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2001216029A JP5147150B2 (en) | 2001-07-16 | 2001-07-16 | LIGHT EMITTING DEVICE AND ELECTRONIC DEVICE |
| JP216029/2001 | 2001-07-16 | ||
| JP283998/2001 | 2001-09-18 |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB021261377A Division CN100350446C (en) | 2001-07-16 | 2002-07-16 | Luminaire |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101159117A CN101159117A (en) | 2008-04-09 |
| CN100585684C true CN100585684C (en) | 2010-01-27 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN200710154289A Expired - Fee Related CN100585684C (en) | 2001-07-16 | 2002-07-16 | Light emission device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JP5147150B2 (en) |
| CN (1) | CN100585684C (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4608999B2 (en) * | 2003-08-29 | 2011-01-12 | セイコーエプソン株式会社 | Electronic circuit driving method, electronic circuit, electronic device, electro-optical device, electronic apparatus, and electronic device driving method |
| JP2005099715A (en) | 2003-08-29 | 2005-04-14 | Seiko Epson Corp | Driving method of electronic circuit, electronic circuit, electronic device, electrooptical device, electronic equipment and driving method of electronic device |
| US7405713B2 (en) | 2003-12-25 | 2008-07-29 | Semiconductor Energy Laboratory Co., Ltd. | Light emitting device and electronic equipment using the same |
| JP5142455B2 (en) * | 2003-12-25 | 2013-02-13 | 株式会社半導体エネルギー研究所 | LIGHT EMITTING DEVICE AND ELECTRONIC DEVICE USING THE SAME |
| KR100911969B1 (en) | 2007-12-06 | 2009-08-13 | 삼성모바일디스플레이주식회사 | Pixel and Organic Light Emitting Display Device |
| KR100911981B1 (en) | 2008-03-04 | 2009-08-13 | 삼성모바일디스플레이주식회사 | Pixel and organic light emitting display using the same |
| JP5532301B2 (en) * | 2009-12-25 | 2014-06-25 | ソニー株式会社 | Driving circuit and display device |
| SG10201607278TA (en) * | 2015-09-18 | 2017-04-27 | Semiconductor Energy Lab Co Ltd | Semiconductor device and electronic device |
| JP2022000833A (en) * | 2020-06-19 | 2022-01-04 | 凸版印刷株式会社 | Shift register, and display device |
Family Cites Families (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05173175A (en) * | 1991-12-25 | 1993-07-13 | Toshiba Corp | Liquid crystal display device |
| JP2689916B2 (en) * | 1994-08-09 | 1997-12-10 | 日本電気株式会社 | Active matrix type current control type light emitting element drive circuit |
| JP3467334B2 (en) * | 1994-10-31 | 2003-11-17 | Ｔｄｋ株式会社 | Electroluminescence display device |
| US6229508B1 (en) * | 1997-09-29 | 2001-05-08 | Sarnoff Corporation | Active matrix light emitting diode pixel structure and concomitant method |
| JP3667175B2 (en) * | 1998-11-06 | 2005-07-06 | キヤノン株式会社 | Display device |
-
2001
- 2001-07-16 JP JP2001216029A patent/JP5147150B2/en not_active Expired - Fee Related
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2002
- 2002-07-16 CN CN200710154289A patent/CN100585684C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JP2003029707A (en) | 2003-01-31 |
| CN101159117A (en) | 2008-04-09 |
| JP5147150B2 (en) | 2013-02-20 |
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