CN100578513C - Method for retention and transformation of upper-drawing impedance/lower-drawing impedance/bus of tri-state device - Google Patents

Abstract

The invention relates to method which maintains the conversion of a three state device (a pull-up resistance/a pull-down resistance/a bus) in the system-on-chip integrated software and hardware collaborative simulation. The method reads SoC design source codes in a hardware description language and creates a corresponding line network after a user appoints a DUT and a TB two parts of the SoC design, then the three state device in the SoC design is organized into groups, and a corresponding function equivalent circuit is adopted to modify the line network, thereby realizing the conversion to the three state device which is organized into groups, at last, the obtained conversion circuit carries out the output in the hardware description language, so as to be used in the subsequent procedure of the system-on-chip integrated software and hardware collaborative simulation. The method provided by the invention can effectively improve the efficiency and the accuracy rate of the conversion method of the three state device in the software and hardware collaborative simulation, thereby having better practicability.

Description

Draw impedance/pull-down impedance/bus to keep conversion method on the three state device

Technical field:

The present invention relates to a kind of SoC emulation mode, draw impedance/pull-down impedance/bus to keep conversion method in particularly a kind of SoC software and hardware cooperating simulation on the three state device.Belong to SoC emulation, verification technique field.

Background technology:

Technical term and some important abbreviations

Software and hardware cooperating simulation: be meant that a large-scale analogue system is divided into soft, hardware two parts to be realized, the part that need calculate in a large number adopts the FPGA hardware platform to carry out emulation, is referred to as hardware components; Need the usage behavior level to describe, or be used to encourage the emulation of input and response output partly to use workstation to finish, be referred to as software section.Like this, just can pass through advantage separately, constitute the large artificial system that a function and speed have all improved in conjunction with FPGA hardware platform and workstation software emulation.

FPGA:Field Programmable Gate Array (field programmable gate array)

SoC:System on Chip (system level chip is integrated)

DUT:Design Under Testing (design to be measured)

TB:Test Bench (test benchmark)

Large-scale SoC design is normally begun by the algorithm design of high level, then according to the function of required realization and the difference of complexity thereof, is divided into software design and hardware design two big modules, then progressively refinement until last realization.The main thought of software and hardware cooperating simulation is exactly with the function complexity, need the hardware module of a large amount of simulation calculation to download to test in the FPGA simulation hardware platform and verify, the software module that will adopt senior description such as behavioral scaling to design simultaneously is put into workstation and goes exploitation, thereby has realized that soft, hardware designing two portions carries out simultaneously.Like this, not only can utilize the high speed performance of FPGA hardware platform to come the accelerating hardware modular design, and simultaneously since the software simulator on the workstation in conjunction with work, can also apply pumping signal and the response of observation circuit quickly and easily, improve the design efficiency of SoC greatly, shortened the cycle of design, proving time and launch products.

After whole SoC design was divided into DUT and TB two parts, the DUT part be as can comprehensively partly downloading to the FPGA platform, the TB part as the behavioral scaling part in the workstation simulation run.Because FPGA three state device resource is very limited, and the high-impedance state on the FPGA circuit can't correctly feed back to workstation and carry out emulation, therefore three state device suitably need be changed, and makes software and hardware collaborative simulation correctly.From existing software and hardware cooperating simulation technology, generally to be undertaken before the software and hardware cooperating simulation by the SoC designer, cost certain hour manual modification SoC design is with its existence that is divided into DUT and TB two parts and avoids such problem.

Summary of the invention:

Purpose of the present invention is at the deficiency of the integrated software and hardware cooperating simulation technology of existing systems level chip on the three state device processing mode, provide and draw impedance/pull-down impedance/bus to keep conversion method in the integrated software and hardware cooperating simulation of a kind of system level chip on the three state device, its design is as follows:

Specify the DUT and TB two parts of SoC design the user after, read in the SoC design source code that adopts the hardware description language description and set up corresponding gauze, then the three state device in the SoC design is organized into groups, adopt the function corresponding equivalent circuit, gauze is made amendment, thereby realize the three state device of having organized into groups is changed, at last the change-over circuit that obtains is exported with hardware description language, be used for the follow-up flow process of software and hardware cooperating simulation.

For easy discussion, Fig. 1 represents a kind of to three state device circuit in the integrated software and hardware cooperating simulation of simplifying of system level chip, draws impedance/pull-down impedance/bus to keep conversion method on employing function corresponding equivalent circuit carries out.

Three state device 101,102,103,104 belongs to same marshalling, therefore after carrying out circuit conversion, four three state devices corresponding to door 105,106,107,108, again by or door 109 will with door 105,106,107,108 output terminals mutually or the back export.When the non-high-impedance state of three state device circuit was exported, the circuit output of conversion back was identical with it; When three state device circuit high-impedance state was exported, then conversion back circuit was output as low level, and this conversion is referred to as the Pulldown conversion, deserves to be called again and draws impedance transformation.

Three state device 110,111 belongs to same marshalling, therefore after carrying out circuit conversion, two three state devices corresponding to door 112,113, again by or door 114 will with door 112,113 output terminals mutually or after output to or 116 input end; Rejection gate 115 with enable signal en5, the en6 of two three state devices mutually or output to or the input end of door 116.When the non-high-impedance state of three state device circuit was exported, the circuit output of conversion back was identical with it; When three state device circuit high-impedance state was exported, then conversion back circuit was output as high level, and this conversion is referred to as the Pullup conversion, claimed the pull-down impedance conversion again.

Three state device 117,118 belongs to same marshalling, therefore after carrying out circuit conversion, two three state devices corresponding to door 119,120, again by or door 121 will with door 119,120 output terminals mutually or after output to the data input pin D of latch 123; Door 122 with enable signal en7, the en8 of two three state devices mutually or output to latch 123 enable input end G.When the non-high-impedance state of three state device circuit was exported, the circuit output of conversion back was identical with it; When three state device circuit high-impedance state was exported, then conversion back circuit was output as last non-high-impedance state output valve, and this conversion is referred to as the Busholder conversion, claimed bus to keep conversion again.

According to above-mentioned inventive concept, technical scheme of the present invention is achieved in that the conversion method of drawing impedance/pull-down impedance/bus to keep in the integrated software and hardware cooperating simulation of a kind of system level chip on the three state device, it is characterized in that after the user specifies the DUT and TB two parts of SoC design, read in the SoC design source code that adopts the hardware description language description and set up corresponding gauze, then the three state device in the SoC design is organized into groups, adopt the function corresponding equivalent circuit, gauze is made amendment, thereby realize the three state device of having organized into groups is changed, at last the change-over circuit that obtains is exported with hardware description language, be used for the follow-up flow process of software and hardware cooperating simulation; Its concrete operations step is as follows:

Step 1 is described the SoC design with hardware description language, generates SoC design source code character;

Step 2, SoC design source code character is from left to right read in lexical analysis one by one, the character stream that constitutes source code is scanned and decomposes, thereby identify word one by one;

Step 3, grammatical analysis is resolved into all kinds of grammer phrases with word sequence on basis of lexical analysis, according to the syntax rule of hardware description language, determine whether whole character stream constitutes correct program on the grammer;

Step 4, semantic analysis, the audit source code has or not semantic error on the basis of grammatical analysis, for the intermediate code generation phase is collected type information;

Step 5, intermediate code generates, and on the basis of grammatical analysis and semantic analysis, the SoC design source code is generated intermediate code, represents with the bosom form;

Step 6, tree-shaped hierarchical structure gauze generates, based on the tree-shaped hierarchical structure gauze of intermediate code structure SoC design; The top-level module of whole SoC design is a root module, and it is made of by signal is interconnected the submodule example and the circuit logic unit of stratification, and each submodule inside is connected and composed by signal by port, circuit logic unit, nested submodule;

Step 7 travels through the gauze of tree-shaped hierarchical structure, and revising gauze, to make three state device in the gauze all be converted to one three state device and Enable Pin high level effective.

Step 8, three state device marshalling, clear table T travels through the circuit gauze of tree-shaped hierarchical structure, and all three state devices in the circuit are organized into groups;

Step 9 draws impedance/pull-down impedance/bus to keep conversion on each group three state device of form T storage carried out;

Step 10, output circuit travels through amended gauze, and the change-over circuit that obtains is stored in the circuit description document with hardware description language.

The conversion method of drawing impedance/pull-down impedance/bus to keep in the above-mentioned integrated software and hardware cooperating simulation of a kind of system level chip on the three state device wherein, comprises in described step 7,

7.1 travel through the gauze of tree-shaped hierarchical structure, the multidigit three state device replaced with a plurality of three state devices;

7.2 if three state device Enable Pin low level is effective, then before the three state device Enable Pin, increase phase inverter, it is effective to convert three state device Enable Pin high level to;

7.3 three state device all is that one three state device and Enable Pin high level is effective in the gauze that obtains.The conversion method of drawing impedance/pull-down impedance/bus to keep in the above-mentioned integrated software and hardware cooperating simulation of a kind of system level chip on the three state device wherein, comprises in described step 8,

8.1 clear table T begins to travel through the gauze of tree-shaped hierarchical structure from root module, notes simultaneously from as the routing information Path of front module to root module;

8.2 handle the three state device Tri that finds in the ergodic process successively, and it organized into groups, organized into groups entirely until all three state devices;

8.3 each the signal S that stores in form T, signal S go up by the three state device of additional five-tuple information correspondence and are considered to one group of three state device.Wherein each five-tuple information is corresponding to a three state device.

The conversion method of drawing impedance/pull-down impedance/bus to keep in the above-mentioned integrated software and hardware cooperating simulation of a kind of system level chip on the three state device wherein, comprises in described step 8.2,

8.2.1 note the enable signal En of three state device Tri, data input signal Din, data output signal Dout, the current path information Path of three state device self and three state device place module, i.e. five-tuple information (Tri, En, Din, Dout, Path);

8.2.2, search out as far as possible continuous signal S near root module according to current path information Path to the data output signal Dout of three state device Tri;

8.2.3 in form T, search signal S,, signal S be inserted among the form T if search failure;

8.2.4 (Tri, En, Din, Dout, Path) five-tuple information is attached on the signal S.

The conversion method of drawing impedance/pull-down impedance/bus to keep in the above-mentioned integrated software and hardware cooperating simulation of a kind of system level chip on the three state device wherein, comprises in described step 9,

9.1, read signal S and go up by additional five-tuple information to each signal S of form T storage;

9.2 go up by additional five-tuple information number n n input of module creation or door A according to signal S at signal S place; If signal S goes up by this group three state device of additional five-tuple information correspondence and crosses over DUT and TB, then need DUV and TB transmitted in both directions port are split, and, reach the software simulator that the high-impedance state on the FPGA circuit is correctly fed back to workstation indirectly at TB insertion IOBUF device;

If 9.3 carry out pull-down impedance conversion, then or the output terminal of door A link to each other with signal S; If draw impedance transformation on carrying out, the n input rejection gate B of module creation that then needs at signal S place and one two input or door C, two input ends of door C with or the output terminal of door A, the output terminal of rejection gate B link to each other, or the output terminal of a C links to each other with signal S; Keep conversion if carry out bus, then need n input of module creation or door D and a latch E at signal S place, the data input pin of latch E with or the door A output terminal link to each other, latch E enable input end with or the door D output terminal link to each other, the data output end of latch E links to each other with signal S;

9.4 signal S being gone up the three state device of each five-tuple information (Tri, En, Din, Dout, Path) correspondence of being added changes;

The conversion method of drawing impedance/pull-down impedance/bus to keep in the above-mentioned integrated software and hardware cooperating simulation of a kind of system level chip on the three state device wherein, comprises in described step 9.4,

9.4.1 read five-tuple information (Tri, En, Din, Dout, Path);

9.4.2,, create from three state device Tri place module to signal S place module, with link to each other signal En ', the Din ' of signal En, Din if three state device Tri place module and signal S place module are disparate modules according to Path; If three state device Tri place module and signal S place module are same module, then signal En ' is En, and signal Din ' is Din.

9.4.3, link to each other with signal En ', Din ' with two input ends of door F in two inputs and a door F of the module creation at signal S place corresponding to three state device Tri, with the output terminal of door F with or the input end of an A link to each other; If draw impedance transformation on carrying out, then also need signal En ' is connected to the input end of rejection gate B; Keep conversion if carry out bus, then also need signal En ' is connected to or the input end of door D.

Draw impedance/pull-down impedance/bus to keep conversion method in the integrated software and hardware cooperating simulation of a kind of system level chip of the present invention on the three state device owing to adopted above-mentioned technical scheme, make it compared with prior art, have following conspicuous outstanding substantive distinguishing features and advantage:

1, improved the efficient of conversion method

Draw impedance/pull-down impedance/bus to keep conversion method in the integrated software and hardware cooperating simulation of a kind of system level chip of the present invention on the three state device owing to realized the input of SoC design hardware description language source code, automatically after the conversion and with the output of hardware description language file, thereby improved the efficient of conversion effectively.

2, improved the accuracy of conversion method

Draw impedance/pull-down impedance/bus to keep conversion method in the integrated software and hardware cooperating simulation of a kind of system level chip of the present invention on the three state device, Electronic Design automatch by foundation the present invention realization, automatically realize that three state device is organized into groups and conversion work in the SoC design, thereby wrong generation such as avoided omitting in the manual switch, improved the accuracy of conversion significantly.

3, realized drawing impedance, pull-down impedance, bus to keep three kinds of conversions

Draw impedance/pull-down impedance/bus to keep conversion method in the integrated software and hardware cooperating simulation of a kind of system level chip of the present invention on the three state device, Electronic Design automatch by foundation the present invention realization, realize drawing on the three state device impedance, pull-down impedance, bus to keep three kinds of conversions easily, possess the dirigibility of conversion.

Description of drawings:

To drawing impedance/pull-down impedance/bus to keep of the description of the example of conversion method on the three state device in the integrated software and hardware cooperating simulation of a kind of system level chip of the present invention, can further understand purpose of the present invention, specific structural features and advantage by following in conjunction with its accompanying drawing.Wherein, accompanying drawing is:

Fig. 1 draws impedance/pull-down impedance/bus to keep change-over circuit figure on the three state device in a kind of software and hardware cooperating simulation of simplification.

Fig. 2 draws impedance/pull-down impedance/bus to keep the FB(flow block) of conversion method on the three state device in a kind of software and hardware cooperating simulation of the present invention.

Fig. 3 draws impedance/pull-down impedance/bus to keep one in the conversion method to simplify the three state device circuit diagram on the three state device in the software and hardware cooperating simulation of one embodiment of the invention.

Fig. 4 draws impedance/pull-down impedance/bus to keep in the conversion method Fig. 3 embodiment being carried out circuit diagram after the pull-down impedance conversion on the three state device in a kind of software and hardware cooperating simulation of the present invention.

Fig. 5 is the circuit diagram that draws on the three state device in a kind of software and hardware cooperating simulation of the present invention after impedance/pull-down impedance/bus keeps drawing on Fig. 3 embodiment is carried out in the conversion method impedance transformation.

Fig. 6 draws impedance/pull-down impedance/bus to keep in the conversion method Fig. 3 embodiment being carried out the back circuit diagram that bus keeps conversion on the three state device in a kind of software and hardware cooperating simulation of the present invention.

Fig. 7 draws impedance/pull-down impedance/bus to keep a three state device group embodiment who crosses over DUV and TB in the conversion method to carry out the circuit diagram that bus keeps conversion on the three state device in a kind of software and hardware cooperating simulation of the present invention.

Embodiment:

In order more to be expressly understood the technology contents that draws impedance/pull-down impedance/bus to keep conversion method in the integrated software and hardware cooperating simulation of a kind of system level chip of the present invention on the three state device, especially exemplified by following example in detail.

See also shown in Figure 2ly, describe SoC design 201, obtain SoC design source code 202 with hardware description language; Lexical analysis SoC design source code obtains corresponding word symbol 203; Enterprising lang method is analyzed on the lexical analysis basis, obtains corresponding grammer phrase 204; Enterprising lang justice is analyzed on the grammatical analysis basis, obtains corresponding type information 205; On the semantic analysis basis, the bosom code 206 that structure is corresponding; Based on the bosom code, the corresponding tree-shaped level gauze 207 of structure SoC design; It is effective to pass through the three state device and the Enable Pin high level that are converted to one, obtains amended gauze 208; Call 212 pairs of all three state devices of three state device marshalling program and organize into groups, obtain three state device marshalling information 209; Call three state device converse routine 213 each group three state device is carried out circuit conversion, obtain changing the circuit gauze 210 that revise the back; Travel through amended gauze, the change-over circuit that obtains is stored as circuit description document 211 with hardware description language.

Now with reference to describing the present invention as the represented illustrative embodiment of each accompanying drawing.In the following description, express many concrete details, so that complete understanding of the present invention is provided.But, obviously for the professional and technical personnel, not having under some and the whole situation of these details, the present invention still can implement.Each following accompanying drawing is represented embodiments of the invention, is the simplification circuit that known structure is not described in detail, so that be unlikely to unnecessarily to obscure the present invention, and can understand better each characteristic of the present invention and advantage.

Fig. 3 represents simplification three state device embodiment of circuit of the present invention, and each inside modules is connected and composed by signal by the example of port, circuit logic unit, nested submodule.For example: the supposition M of the superiors module 312 is the root module in the tree-shaped hierarchical structure, and it is made of by signal is interconnected the example of the submodule 304,305,306,307 of stratification.The M1 module 308 at three state device 301 places belongs to the submodule of M1 ' module 310.Module 310 belongs to M1 again in as module 308 father's modules " submodule of module 304.Belong to one group three state device 301,302,303 place modules 308,309,311 relative modules 312 together, all belong to the submodule of tri-layer.Design in the tree-shaped level gauze at the SoC of reality, the nest relation of module can be more complicated under the three state device, and it is indefinite to belong to one group three state device number together.

For drawing impedance/pull-down impedance/bus to keep the step 8 of conversion method on the three state device in the integrated software and hardware cooperating simulation of a kind of system level chip, to carry out the three state device marshalling at the simplification three state device embodiment of circuit of Fig. 3 and handle, step is as follows:

R1: clear table T begins to travel through the circuit gauze of tree-shaped hierarchical structure from M root module 312, notes simultaneously from as the routing information Path of front module to root module 312;

R2: when ergodic discovery TRI1 three state device 301, current path information Path be [M1 → M1 ' → M1 " → M], note three state device 301 five-tuple information (TRI1, EN1, IN1, IO1, [M1 → M1 ' → M1 " → M]);

R3: to the data of three state device 301 output IO1 signal 314, according to current path information [M1 → M1 ' → M1 " → M] search out as far as possible continuous IO signal 313 near root module 312;

R4: in form T, search the IO signal, search failure, the IO signal is inserted form T, and will (TRI1, EN1, IN1, IO1, [M1 → M1 ' → M1 " → M]) five-tuple information is attached on the IO signal 313;

R5: handle the three state device of finding in the ergodic process 302,303 successively, and it is organized into groups, obtain following result: storage IO signal 313 among the form T, and additional three the five-tuple information of IO signal promptly (TRI1, EN1, IN1, IO1, [M1 → M1 ' → M1 " → M]); (TRI2, EN2, IN2, IO2, [M2 → M2 ' → M2 " → M]), (TRI3, EN4, IN4, O4, [M4 → M4 ' → M4 " → M]), expression three state device 301,302,303 belongs to same group of three state device.

For drawing impedance/pull-down impedance/bus to keep the step 9 of conversion method on the three state device in the integrated software and hardware cooperating simulation of a kind of system level chip, at the simplification three state device circuit of Fig. 3 carry out after the conversion of three state device pull-down impedance circuit as shown in Figure 4, step is as follows:

S1:, read on the IO signal by one group of additional five-tuple information to the IO signal of form T storage;

S2:, create one three input or door 416 in the M module 418 at IO signal place according to the additional five-tuple information number 3 of quilt on the IO signal;

S3: or the output terminal of door 416 connects IO signal 417;

S4: read first five-tuple information (TRI1, EN1, IN1, IO1, [M1 → M1 ' → M1 " → M]);

S5: according to [M1 → M1 ' → M1 " → M] path; judge three state device TRI1 place M1 module 419 and IO signal 417 place M modules 418 and be disparate modules; create from module 419 to module 418; the EN1 ' signal 407 that links to each other with EN1 signal 401, the IN1 ' signal 408 that links to each other with IN1 signal 402;

S6: in two inputs and door 409 of IO signal 417 place modules 418 establishments corresponding to three state device TRI1, link to each other with EN1 ' signal 407, IN1 ' signal 408 respectively with two input ends of door 409, with the output terminal of door 409 with or an input end of door 416 link to each other;

S7: on the IO signal by additional five-tuple information (TRI2, EN2, IN2, IO2, [M2 → M2 ' → M2 " → M]) corresponding three state device transforms; create from module 420 to module 418; the EN2 ' signal 410 that links to each other with EN2 signal 403, the IN2 ' signal 411 that links to each other with IN2 signal 404; Create two inputs and door 412 in module 418, link to each other with EN2 ' signal 410, IN2 ' signal 411 respectively with two input ends of door 412 corresponding to three state device TRI2, with the output terminal of door 412 with or an input end of 416 link to each other;

S8: on the IO signal by additional five-tuple information (TRI3, EN4, IN4, O4, [M4 → M4 ' → M4 " → M]) corresponding three state device transforms; create from module 421 to module 418; the EN4 ' signal 413 that links to each other with EN4 signal 405, the IN4 ' signal 414 that links to each other with IN4 signal 406; Create two inputs and door 415 in module 418, link to each other with EN4 ' signal 413, IN4 ' signal 414 respectively with two input ends of door 415 corresponding to three state device TRI3, with the output terminal 415 of door with or an input end of 416 link to each other.

For drawing impedance/pull-down impedance/bus to keep the step 9 of conversion method on the three state device in the integrated software and hardware cooperating simulation of a kind of system level chip, at the simplification three state device circuit of Fig. 3 carry out drawing on the three state device after the impedance transformation circuit as shown in Figure 5, step is as follows:

S1:, read on the IO signal by one group of additional five-tuple information to the IO signal of form T storage;

S2: according on the IO signal by additional five-tuple information number 3, create one three input or door 516, one three inputs rejection gates 519 and one two input or door 520 in the M module 518 at IO signal place;

S3: or door 520 input end with or the output terminal of door 516, the output terminal of rejection gate 519 link to each other or the output terminal of door 520 connection IO signal 517;

S4: read first five-tuple information (TRI1, EN1, IN1, IO1, [M1 → M1 ' → M1 " → M]);

S5: according to [M1 → M1 ' → M1 " → M] path; judge three state device TRI1 place M1 module 521 and IO signal 517 place M modules 518 and be disparate modules; create from module 521 to module 518; the EN1 ' signal 508 that links to each other with EN1 signal 502, the IN1 ' signal 507 that links to each other with IN1 signal 501;

S6 a: input end that EN1 ' signal 508 is connected to rejection gate 519; Create two inputs and door 509 in IO signal 517 place modules 518, link to each other with EN2 ' signal 508, IN1 ' signal 507 respectively with two input ends of door 509 corresponding to three state device TRI1, with the output terminal of door 509 with or an input end of 516 link to each other;

S7: on the IO signal by additional five-tuple information (TRI2, EN2, IN2, IO2, [M2 → M2 ' → M2 " → M]) corresponding three state device transforms; create from module 522 to module 518; the EN2 ' signal 510 that links to each other with EN2 signal 503, the IN2 ' signal 511 that links to each other with IN2 signal 504; EN2 ' signal 510 is connected to an input end of rejection gate 519; Create two inputs and door 512 in module 518, link to each other with EN2 ' signal 510, IN2 ' signal 511 respectively with two input ends of door 512 corresponding to three state device TRI2, with the output terminal of door 512 with or an input end of 516 link to each other;

S8: on the IO signal by additional five-tuple information (TRI3, EN4, IN4, O4, [M4 → M4 ' → M4 " → M]) corresponding three state device transforms; create from module 523 to module 518; the EN4 ' signal 514 that links to each other with EN4 signal 506, the IN4 ' signal 513 that links to each other with IN4 signal 505; EN4 ' signal 514 is connected to an input end of rejection gate 519; Create two inputs and door 515 in module 518, link to each other with EN4 ' signal 514, IN4 ' signal 513 respectively with two input ends of door 515 corresponding to three state device TRI3, with the output terminal of door 515 with or an input end of 516 link to each other.

For drawing impedance/pull-down impedance/bus to keep the step 9 of conversion method on the three state device in the integrated software and hardware cooperating simulation of a kind of system level chip, at the simplification three state device circuit of Fig. 3 carry out the three state device bus keep after the conversion circuit as shown in Figure 6, step is as follows:

S1:, read on the IO signal by one group of additional five-tuple information to the IO signal of form T storage;

S2:, import or 619 and latchs 620 at one three input of M module 618 establishments or 616, one three at the door at IO signal place according to the five-tuple information number 3 that quilt on the IO signal adds;

S3: the G of latch 620 enable input end with or door 619 output terminal link to each other, the D data input pin with or the output terminal of door 616 link to each other the output terminal connection IO signal 617 of latch 620;

S4: read first five-tuple information (TRI1, EN1, IN1, IO1, [M1 → M1 ' → M1 " → M]);

S5: according to [M1 → M1 ' → M1 " → M] path; judge three state device TRI1 place M1 module 621 and IO signal 617 place M modules 618 and be disparate modules; create from module 621 to module 618; the EN1 ' signal 608 that links to each other with EN1 signal 602, the IN1 ' signal 607 that links to each other with IN1 signal 601;

S6: EN1 ' signal 608 is connected to or an input end of door 619; Create two inputs and door 609 in IO signal 617 place modules 618, link to each other with EN1 ' signal 608, IN1 ' signal 607 respectively with two input ends of door 609 corresponding to three state device TRI1, with the output terminal of door 609 with or an input end of 616 link to each other;

S7: on the IO signal by additional five-tuple information (TRI2, EN2, IN2, IO2, [M2 → M2 ' → M2 " → M]) corresponding three state device transforms; create from module 622 to module 618; the EN2 ' signal 610 that links to each other with EN2 signal 603, the IN2 ' signal 611 that links to each other with IN2 signal 604; EN2 ' signal 610 is connected to or an input end of door 619; Create two inputs and door 612 in module 618, link to each other with EN2 ' signal 610, IN2 ' signal 611 respectively with two input ends of door 612 corresponding to three state device TRI2, with the output terminal of door 612 with or an input end of 616 link to each other;

S8: on the IO signal by additional five-tuple information (TRI3, EN4, IN4, O4, [M4 → M4 ' → M4 " → M]) corresponding three state device transforms; create from module 623 to module 618; the EN4 ' signal 614 that links to each other with EN4 signal 606, the IN4 ' signal 613 that links to each other with IN4 signal 605; EN4 ' signal 614 is connected to or an input end of door 619; Create two inputs and door 615 in module 618, link to each other with EN4 ' signal 614, IN4 ' signal 613 respectively with two input ends of door 615 corresponding to three state device TRI3, with the output terminal of door 615 with or an input end of 616 link to each other.

For drawing impedance/pull-down impedance/bus to keep conversion method on the three state device in the integrated software and hardware cooperating simulation of a kind of system level chip, organize into groups and pull-down impedance conversion process details at the leap DUV of Fig. 7 and the embodiment of TB three state device group, step is as follows:

T1: clear table T begins to travel through the circuit gauze of tree-shaped hierarchical structure from SoC root module 706, notes simultaneously from as the routing information Path of front module to root module 706;

T2: when ergodic discovery TRI1 three state device 701, current path information Path is [DUV → SoC], notes three state device 701 five-tuple information (TRI1, EN1, IN1, IO1, [DUV → SoC]);

T3:, search out as far as possible continuous IO3 signal 705 near SoC root module 706 according to current path information [DUV → SoC] to the data of three state device 701 output IO1 signal 704;

T4: in form T, search the IO3 signal, search failure, the IO3 signal is inserted form T, and (TRI1, EN1, IN1, IO1, [DUV → SoC]) five-tuple information is attached on the IO3 signal 705;

T5: handle the three state device of finding in the ergodic process 702,703 successively, and it is organized into groups, obtain following result: storage IO3 signal 705 among the form T, and additional three the five-tuple information of IO3 signal i.e. { (TRI1, EN1, IN1, IO1, [DUV → SoC]), (TRI2, EN2, IN2, IO1, [DUV → SoC]), (TRI3, EN3, IN3, IO2, [TB → SoC]) }, expression three state device 701,702,703 belongs to same group.

T6:, read on the IO3 signal by one group of additional five-tuple information to the IO3 signal of form T storage; Find this group three state device leap DUV and TB, need split DUV and TB bidirectional port, and in operations such as TB insertion IOBUF devices, thereby indirectly the high-impedance state on the FPGA circuit is correctly fed back to the workstation software part;

T7: create OUTX output port 717, INX input port 718, ENX output port 719 in DUV module 725, create INY input ports 720, OUTY output port 721, ENY input port 722 in TB module 726, and in the SoC module, the OUTX output port 717 of DUV module and TB module instance is linked to each other with INY input port 720, INX input port 718 links to each other with OUTY output port 721, ENX output port 719 links to each other with ENY input port 722;

T8: create IOBUF devices 723 in TB module 726, and with the IO port of IOBUF device 723 link to each other with IO2 signal 724, the T port links to each other with ENY input port 722, the I port links to each other with INY input port 720, the O port links to each other with OUTY output port 721;

T9:, add 1 on five-tuple number 2 bases in affiliated DUV module and obtain 3 according to the additional five-tuple information of quilt on the IO3 signal; At one three input of DUV module creation or door 716, a general or door 716 output terminals link to each other with OUTX output port 717;

T10: at DUV module creation or door 713, and will or door 713 input ends link to each other with three state device EN1 enable signal 708, the EN2 enable signal 710 of affiliated DUV module or 713 output terminals link to each other with ENX output port 719; At DUV module creation not gate 714, and with not gate 714 input ends with or the door 713 output terminals link to each other; At DUV module creation two input and door 715, link to each other with INX input port 718, not gate 714 output terminals respectively with two input ends of door 715, with the output terminal of door 715 with or an input end of 716 link to each other;

T11: to being changed by the corresponding three state device of the additional DUV module three state device five-tuple information (TRI1, EN1, IN1, IO1, [DUV → SoC]) that is on the IO3 signal, in of two inputs and door 711 of DUV module creation corresponding to three state device TRI1, link to each other with IN1 signal 707, EN1 signal 708 respectively with two input ends of door 711, with the output terminal of door 711 with or an input end of door 716 link to each other;

T12: to being changed by the corresponding three state device of the additional DUV module three state device five-tuple information (TRI2, EN2, IN2, IO1, [DUV → SoC]) that is on the IO3 signal, in of two inputs and door 712 of DUV module creation corresponding to three state device TRI2, link to each other with IN2 signal 709, EN2 signal 710 respectively with two input ends of door 712, with the output terminal of door 712 with or an input end of door 716 link to each other.

Claims (6)

1. the conversion method of drawing impedance/pull-down impedance/bus to keep on the three state device in the integrated software and hardware cooperating simulation of system level chip, it is characterized in that behind the design DUT to be measured and test benchmark TB two parts of the integrated SoC design of user's appointing system level chip, read in the integrated SoC design source code of system level chip that adopts the hardware description language description and set up corresponding gauze, then the three state device in the integrated SoC design of system level chip is organized into groups, adopt the function corresponding equivalent circuit, gauze is made amendment, thereby realize the three state device of having organized into groups is changed, at last the change-over circuit that obtains is exported with hardware description language, be used for the follow-up flow process of the integrated software and hardware cooperating simulation of system level chip; Its concrete operations step is as follows:

Step 1 is with the integrated SoC design of hardware description language descriptive system level chip, the integrated SoC design source code of generation system level chip character;

Step 2, the integrated SoC design source code of system level chip character is from left to right read in lexical analysis one by one, the character stream that constitutes source code is scanned and decomposes, thereby identify word one by one;

Step 3, grammatical analysis is resolved into all kinds of grammer phrases with word sequence on basis of lexical analysis, according to the syntax rule of hardware description language, determine whether whole character stream constitutes correct program on the grammer;

Step 4, semantic analysis, the audit source code has or not semantic error on the basis of grammatical analysis, for the intermediate code generation phase is collected type information;

Step 5, intermediate code generates, and on the basis of grammatical analysis and semantic analysis, the integrated SoC design source code of system level chip is generated intermediate code, represents with the bosom form;

Step 6, tree-shaped hierarchical structure gauze generates, based on the tree-shaped hierarchical structure gauze of the integrated SoC design of intermediate code tectonic system level chip; The top-level module of the integrated SoC design of total system level chip is a root module, and it is made of by signal is interconnected the submodule and the circuit logic unit of stratification, and each submodule inside is connected and composed by signal by port, circuit logic unit, nested submodule;

Step 7 travels through the gauze of tree-shaped hierarchical structure, and revising gauze, to make three state device in the gauze all be converted to one three state device and Enable Pin high level effective;

Step 8, three state device marshalling, clear table T travels through the gauze of tree-shaped hierarchical structure, handles the three state device Tri that finds in the ergodic process successively, according to the routing information Path of three state device Tri place module to root module; Seek as far as possible near the continuous signal S of root module, in form T, search signal S,, signal S is input among the form T, then three state device Tri information is attached on the signal S, organized into groups entirely up to all three state device Tri if search failure;

Step 9 draws impedance/pull-down impedance/bus to keep conversion on each group three state device of form T storage carried out;

Step 10, output circuit travels through amended gauze, and the change-over circuit that obtains is stored in the circuit description document with hardware description language.

2. by the conversion method of drawing impedance/pull-down impedance/bus to keep on the three state device in the integrated software and hardware cooperating simulation of the described a kind of system level chip of claim 1, it is characterized in that: in described step 7, comprise,

7.1 travel through the gauze of tree-shaped hierarchical structure, the multidigit three state device replaced with a plurality of three state devices;

7.2 if three state device Enable Pin low level is effective, then before the three state device Enable Pin, increase phase inverter, convert the effective equivalent electrical circuit of three state device Enable Pin high level to;

7.3 the three state device and the Enable Pin high level that obtain three state device in the gauze and all be one are effective.

3. by the conversion method of drawing impedance/pull-down impedance/bus to keep on the three state device in the integrated software and hardware cooperating simulation of the described a kind of system level chip of claim 1, it is characterized in that: in described step 8, comprise,

8.1 clear table T begins to travel through the gauze of tree-shaped hierarchical structure from root module, notes simultaneously from as the routing information Path of front module to root module;

8.2 handle the three state device Tri that finds in the ergodic process successively, and it organized into groups, organized into groups entirely until all three state devices;

8.3 each the signal S that stores in form T, signal S go up by the three state device of additional five-tuple information correspondence and be considered to one group of three state device, wherein each five-tuple information is corresponding to a three state device.

4. by the conversion method of drawing impedance/pull-down impedance/bus to keep on the three state device in the integrated software and hardware cooperating simulation of the described a kind of system level chip of claim 1, it is characterized in that: in described step 9, comprise,

9.1, read signal S and go up by additional five-tuple information to each signal S of form T storage;

9.2 go up by additional five-tuple information number n n input of module creation or door A according to signal S at signal S place; If signal S goes up by pairing this group three state device of additional five-tuple information and crosses over design DUT to be measured and test benchmark TB, then need design DUT to be measured and test benchmark TB transmitted in both directions port are split, and, reach the software simulator that the high-impedance state on the FPGA circuit is correctly fed back to workstation indirectly at test benchmark TB insertion IOBUF device;

If 9.3 carry out pull-down impedance conversion, then or the output terminal of door A link to each other with signal S; If draw impedance transformation on carrying out, the n input rejection gate B of module creation that then needs at signal S place and one two input or door C, two input ends of door C with or the output terminal of door A, the output terminal of rejection gate B link to each other, or the output terminal of a C links to each other with signal S; Keep conversion if carry out bus, then need n input of module creation or door D and a latch E at signal S place, the data input pin of latch E with or the door A output terminal link to each other, latch E enable input end with or the door D output terminal link to each other, the data output end of latch E links to each other with signal S;

9.4 signal S is gone up by each additional five-tuple information, and promptly the three state device of three state device Tri, enable signal En, data input signal Din, data output signal Dout, routing information Path correspondence is changed.

5. by the conversion method of drawing impedance/pull-down impedance/bus to keep on the three state device in the integrated software and hardware cooperating simulation of the described a kind of system level chip of claim 3, it is characterized in that: in described step 8.2, comprise,

8.2.1 note the enable signal En of three state device Tri, data input signal Din, data output signal Dout, three state device self and three state device place module arrive the routing information Path of root module, i.e. five-tuple information: three state device Tri, enable signal En, data input signal Din, data output signal Dout, routing information Path;

8.2.2, search out as far as possible continuous signal S to the routing information Path of root module near root module according to three state device place module to the data output signal Dout of three state device Tri;

8.2.3 in form T, search signal S,, signal S be inserted among the form T if search failure;

8.2.4 three state device Tri, enable signal En, data input signal Din, data output signal Dout, routing information Path five-tuple information are attached on the signal S.

6. by the conversion method of drawing impedance/pull-down impedance/bus to keep on the three state device in the integrated software and hardware cooperating simulation of the described a kind of system level chip of claim 4, it is characterized in that: in described step 9.4, comprise,

9.4.1 read five-tuple information: three state device Tri, enable signal En, data input signal Din, data output signal Dout, routing information Path;

9.4.2,, create from three state device Tri place module to signal S place module, with link to each other signal En ', the Din ' of signal En, Din if three state device Tri place module and signal S place module are disparate modules according to routing information Path; If three state device Tri place module and signal S place module are same module, then creating signal En ' is En, and signal Din ' is Din;

9.4.3, link to each other with signal En ', Din ' with two input ends of door F in two inputs and a door F of the module creation at signal S place corresponding to three state device Tri, with the output terminal of door F with or the input end of an A link to each other; If draw impedance transformation on carrying out, then also need signal En ' is connected to the input end of rejection gate B; Keep conversion if carry out bus, then also need signal En ' is connected to or the input end of door D.

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