CN100573909C - Semiconductor device and manufacture method thereof - Google Patents
Semiconductor device and manufacture method thereof Download PDFInfo
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- CN100573909C CN100573909C CNB2006101719012A CN200610171901A CN100573909C CN 100573909 C CN100573909 C CN 100573909C CN B2006101719012 A CNB2006101719012 A CN B2006101719012A CN 200610171901 A CN200610171901 A CN 200610171901A CN 100573909 C CN100573909 C CN 100573909C
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Abstract
A kind of semiconductor device, purpose are the low resistanceizations of seeking semiconductor device, it is characterized in that, have the through hole that forms on semiconductor layer (10) with first metal film (18) butt; The dielectric film that on the side wall portion of described through hole (10), forms (12); First metal film (18) of the bottom of the described through hole (10) that does not form described dielectric film (12) go up and described semiconductor layer on second metal film (13) that forms; Described dielectric film (12) in described through hole (10) and first metal film (18) are gone up barrier metal film (14) that forms and the wiring layer (15) that forms by described barrier metal film (14) in described through hole.
Description
Technical field
The present invention relates to semiconductor device and manufacture method thereof, particularly have the semiconductor device of through electrode.
Background technology
Last drain type MOS transistor with groove structure is the semiconductor device of example explanation prior art.
That is, as shown in figure 14, for example on the Semiconductor substrate 51 that N type silicon is formed, be formed with epitaxial loayer 52, on the top layer of this epitaxial loayer 52, be formed with p type diffused layer 53 (channel region CH).In addition, the prescribed depth position that arrives epitaxial loayer 52 from the top layer of p type diffused layer 53 is formed with ditch 54.Conductive layer in that the poly-silicon fiml of these ditch 54 embedded set dielectric films 55 encirclements is formed constitutes gate electrode (G) 56.
And then at the N type source layer 57 that is formed with on the top layer of epitaxial loayer 52 and in the one of the two side of ditch 54 with dielectric film 55 adjacency.Between adjacent source layer 57, be formed with P type body layer 58 (BD) of cross-over connection.
In addition, constitute the drain electrode layer of forming by N type impurity 59, make it arrive the prescribed depth of Semiconductor substrate 51 from the top layer of epitaxial loayer 52.
And then on epitaxial loayer 52, be formed with the source electrode (S) 60 that aluminium (Al) alloy etc. is formed, make it cover source layer 57.Equally, the drain electrode (D) 61 that formation aluminium (Al) alloy etc. is formed makes it cover drain electrode layer 59.
Be formed with metal film 62 at the back side of Semiconductor substrate 51, thereby form semiconductor device 63.
[patent documentation 1] spy opens the 2004-363302 communique
The last drain type MOS transistor of above-mentioned groove structure, along the direction of arrow shown in Figure 14, electric current I 2 is by in above-mentioned source electrode 60, epitaxial loayer 52, the Semiconductor substrate 51, via described metal film 62, flow through Semiconductor substrate 51, epitaxial loayer 52 once more, drain electrode 61.
At this moment, because twice by not forming high-resistance Semiconductor substrate 51 parts of epitaxial loayer 52, so there is the problem of the resistance value that can not lower semiconductor device.
Summary of the invention
Principal character of the present invention is as follows.Promptly, semiconductor device of the present invention is characterised in that, have the through hole that connects to the back side from its surface, form on described surface first conductivity type of source layer Semiconductor substrate, described through hole is covered, at first metal film that forms on the back side of described Semiconductor substrate, the drain electrode layer that is electrically connected with described first metal film that forms in described through hole, described drain electrode layer is included in second metal film that forms and be connected with the surface of described Semiconductor substrate on the surface of described Semiconductor substrate.
In addition, semiconductor device of the present invention is characterised in that, have the through hole that connects from its surface to the back side, form the Semiconductor substrate of first conductivity type of source layer, the drain electrode that the described through hole of lining forms on the surface of described Semiconductor substrate, the drain electrode layer that is electrically connected with described drain electrode that in described through hole, forms on described surface, second metal film that described drain electrode layer is included in formation on the back side of described Semiconductor substrate and is connected with the back side of described Semiconductor substrate.
In addition, the manufacture method of semiconductor device of the present invention is characterised in that, has the Semiconductor substrate that preparation forms first conductivity type of source layer and drain electrode in its surface, formation arrives the operation of the through hole of described drain electrode from the back side of described Semiconductor substrate, with the operation that forms the drain electrode layer that is electrically connected with described drain electrode in described through hole, the operation of described formation drain electrode layer comprises the operation that forms second metal film that is connected with the back side of described Semiconductor substrate.
According to semiconductor device of the present invention, because without impurity layer but with through electrode structure formation drain electrode layer, so can realize the low resistanceization of semiconductor device.Then,, on semiconductor layer, do not form described dielectric film, in the semiconductor device of the structure of longitudinal direction (film thickness direction of semiconductor layer) upper reaches overcurrent, on current path, do not form electric capacity by forming dielectric film on the side wall portion in through hole.Therefore, improve the device characteristics of semiconductor device.In addition, on Semiconductor substrate, directly do not form the barrier metal film, but form under the situation of barrier metal film, can form to have and wish thickness, membranous barrier metal film by the metal film that uses sputtering method or vapour deposition method to form.
Description of drawings
Fig. 1 is the profile of the semiconductor device of expression first execution mode of the present invention;
Fig. 2 is the plane graph of the semiconductor device of expression first execution mode of the present invention;
Fig. 3 is the profile of manufacture method of the semiconductor device of expression first execution mode of the present invention;
Fig. 4 is the profile of manufacture method of the semiconductor device of expression first execution mode of the present invention;
Fig. 5 is the profile of manufacture method of the semiconductor device of expression first execution mode of the present invention;
Fig. 6 is the profile of manufacture method of the semiconductor device of expression second execution mode of the present invention;
Fig. 7 is the profile of manufacture method of the semiconductor device of expression second execution mode of the present invention;
Fig. 8 is the profile of manufacture method of the semiconductor device of expression second execution mode of the present invention;
Fig. 9 is the profile of manufacture method of the semiconductor device of expression second execution mode of the present invention;
Figure 10 is the profile of manufacture method of the semiconductor device of expression second execution mode of the present invention;
Figure 11 is the profile of manufacture method of the semiconductor device of expression second execution mode of the present invention;
Figure 12 is the profile of manufacture method of the semiconductor device of expression second execution mode of the present invention;
Figure 13 is the profile of the semiconductor device of expression other execution modes of the present invention;
Figure 14 is the profile of the semiconductor device of expression prior art.
Symbol description
1 Semiconductor substrate, 2 epitaxial loayers, 3P type diffusion layer (channel region), 4 ditches, 5 dielectric films, 6 gate electrodes (G), 7 source layers, 7A source electrode (S), 8P type body layer, 10 through holes, 11 drain electrode layers (drain electrode D), 12 dielectric films, 13 second metal films, 14 barrier metal films (the 3rd metal film), 15 wiring layers (the 4th metal film), 18 first metal films, 19 semiconductor devices, 20 drain electrodes, 21 through holes, 22 dielectric films, 23 metal films, 24 barrier metal films, 25 wiring layers, 26 drain electrode layers, 30 semiconductor devices, 51: Semiconductor substrate, 52: epitaxial loayer, 53:P type diffusion layer, 54: ditch, 55: dielectric film, 56: gate electrode (G), 57: source layer, 58:P type body layer, 59 drain electrode layers, 60: source electrode (S), 61: drain electrode (D), 62: metal film
Embodiment
First execution mode of semiconductor device of the present invention and manufacture method thereof is described with reference to the accompanying drawings.
Here, the last drain type MOS transistor with groove structure is that example illustrates semiconductor device of the present invention.
At first, as shown in Figure 1, on by a kind of conductivity type Semiconductor substrate 1 that for example N type silicon is formed, be formed with N type epitaxial loayer 2, on the top layer of this epitaxial loayer 2, be formed with p type diffused layer 3 (channel region CH).In addition, in the present embodiment, the thickness of for example above-mentioned epitaxial loayer 2 is 10 μ m, and the thickness that the thickness of Semiconductor substrate 1 comprises epitaxial loayer 2 is 200 μ m, and the thickness of p type diffused layer 3 is 1～1.5 μ m.
In addition, form the ditch 4 that arrives the prescribed depth position of above-mentioned epitaxial loayer 2 from p type diffused layer 3.Be embedded with the conductive layer that poly-silicon fiml that dielectric film 5 surrounds is formed at this ditch 4, constitute gate electrode (G) 6.In addition, in the present embodiment, for example the degree of depth of ditch 4 is that the opening diameter of the central portion of 2 μ m, ditch 4 is 0.4 μ m.
And then on the top layer of epitaxial loayer 2, in the one of the two side of ditch 4, be formed with N type source layer 7 with described dielectric film 5 adjacency.Between adjacent source layer 7, form P type body layer 8 (BD) of cross-over connection.In addition, on each source layer 7, for example be formed with the source electrode 7A (S) that forms by aluminium (Al) alloy film.
In addition, be equipped with the through hole 10 of the opening diameter that for example has 60 μ m～70 μ m, make its top layer penetrate into the back side of Semiconductor substrate 1 from epitaxial loayer 2.In this through hole 10, constitute the drain electrode layer 11 that becomes the through electrode structure.Here, in the manufacture method of common through electrode, form dielectric film on the Semiconductor substrate in comprising through hole, only remove the dielectric film of the bottom of through hole, expose the metal film of through hole bottom, form through electrode and be electrically connected this metal film thus.
But in the MOS transistor of drain type structure, the source electrode that electric current forms from the surface in Semiconductor substrate flows through the drain electrode that forms on the surface of Semiconductor substrate once more by Semiconductor substrate on described.Therefore, because in through hole and the existence of the dielectric film that forms on the Semiconductor substrate, on this zone, form electric capacity, as prior art so device characteristics are poor.
Therefore, the inventor develops the through electrode operation with described dielectric film.But recognize on Semiconductor substrate, to form dielectric film, different at the barrier metal film that forms on this dielectric film with the barrier metal film that under the state that does not have dielectric film on the Semiconductor substrate, directly forms.Promptly recognize, passing through CVD (Chemical Vapor Deposition) method for example under the situation of the barrier metal film that directly forms TiN film composition on the Semiconductor substrate, compared with on Semiconductor substrate, forming the situation film forming amount of TiN film below half by dielectric films such as silicon oxide layers.
In inventor's checking, on Semiconductor substrate, use the CVD method directly to form in the situation of TiN film, the rotten film that the chemical reaction when being formed with owing to the CVD operation between Semiconductor substrate and TiN film causes.The material of being somebody's turn to do rotten film is unconfirmed.Because existence that should rotten film, can not form and wish thickness, membranous TiN film, can not form semiconductor device as the design load of expectation.Therefore, the semiconductor device of the characteristic that can not obtain expecting.
Therefore, develop the invention of following explanation.Promptly as shown in Figure 3, in through hole 10, form the dielectric film of forming by silicon oxide layer or silicon nitride film 12, by etching dielectric film 12 is carried out anisotropic etching, remove the dielectric film 12 of bottom of through hole 10 and the lip-deep dielectric film 12 of Semiconductor substrate 1.Thus, residual dielectric film 12 on the side wall portion of through hole 10 only.In the present embodiment, when the dielectric film 12 of the bottom of etching through hole 10,, remove the dielectric film 12 of bottom of through hole 10 and the dielectric film 12 on the epitaxial loayer 2 by crossing etching.
Then, as shown in Figure 3, using sputtering method for example to form second metal film of forming by Ti film etc. 13 on first metal film 18 of the bottom of through hole 10 and on the surface of Semiconductor substrate 1.In addition, in the present embodiment, form approximately as second metal film 13
About thin Ti film.This point is because second metal film 13 does not form on the dielectric film 12 that forms on the side wall portion of through hole 10, and the cause that only forms on first metal film 18 of the bottom that is positioned at through hole 10 and on the epitaxial loayer 2.Furtherly, can only on epitaxial loayer 2, form second metal film 13.
In addition, also can for example form as second metal film 13 about 100～
About the Ti film.In this case, also on dielectric film 12 or epitaxial loayer 2, form the Ti film sometimes, therefore also can use diaphragm to remove the Ti film in unnecessary place.
Here, use the Ti film as second metal film 13 in the present embodiment, but also can use chromium (Cr), vanadium refractory metal films such as (V).And then, also can use the material (for example tantalum (Ta) or tungsten (W), zirconium (Zr) etc.) of common usefulness as the barrier metal film.In addition,, except that the CVD method, be not limited to above-mentioned sputtering method, can use various film shaped methods (for example vapour deposition method etc.) as the formation method of second metal film 13.
Then, as shown in Figure 4, the barrier metal film 14 (the 3rd metal film) that uses formation on whole faces of CVD method during comprising through hole 10 to form by Ti film or WN film or TaN film.Barrier metal film 14 has the diffusion of the metal material that prevents afterwards the wiring layer 15 that forms in through hole 10, perhaps prevents the effect that reacts to each other of this metal material and electric conductor (being first metal film 18 in the present embodiment).
Then, as shown in Figure 5, the Seed Layer (not shown) by using film forming methods formation Cu layers such as CVD method or sputtering method to form on barrier metal film 14.Seed Layer is as the conductive layer that is used to electroplate the underlayer electrode that forms wiring layer 15.Then, on Seed Layer, use electrolytic plating method to form the wiring layer 15 (the 4th metal level) that the Cu layer is formed.
Then, after forming the first metal layer 18, the back side of Semiconductor substrate 1 finishes the semiconductor device 19 of formation.In addition, in the present embodiment,, for example use the Ti-Ni-Au alloy-layer as first metal film 18, but so long as low-resistance electric conducting material also can use other materials.
Use the last drain type MOS transistor (semiconductor device 19) of the through electrode technology that constitutes like this, along the direction of arrow shown in Figure 1, electric current I 1 is by flowing to the drain electrode layer 11 (drain electrode D) that becomes the through electrode structure via first metal film 18 in source layer 7 (source electrode S), epitaxial loayer 2, the Semiconductor substrate 1.
Therefore, compare, because the zone of the high-resistance Semiconductor substrate that can flow through electric current reduces by half, so can lower the resistance value of semiconductor device with the semiconductor device 63 (with reference to Figure 14) of prior art.Especially, because between epitaxial loayer 52 and Semiconductor substrate 51 with 200 μ m thickness, so by a side of current path as the metal film of forming by through electrode, the realization current delivery high speed (the resistance value R1 of the resistance value R2 of the semiconductor device 63 of prior art＞semiconductor device 19 of the present invention).
In addition, in the present invention, do not form the drain electrode layer of forming by impurity layer 59, but form the drain electrode layer of forming by the through electrode structure 11.Therefore, compare, can realize low resistanceization with the semiconductor device of prior art.Here, can realize low resistanceization by the volume that enlarges through electrode.In addition, also can form a plurality of through electrodes.
Then, form dielectric film 12 on the side wall portion in through hole 10, because (the regional X of Fig. 1) forms dielectric film 12 not on epitaxial loayer 2, therefore in the semiconductor device 19 of the structure of longitudinal direction (film thickness direction of Semiconductor substrate) upper reaches overcurrent, do not form electric capacity.Therefore, compare, improved the device characteristics of semiconductor device with the structure that on epitaxial loayer 2, forms dielectric film 12.
Have again, in semiconductor device 19, near semiconductor layer through hole 10 (epitaxial loayer 2) is gone up by the method (sputtering method or vapour deposition method in the present embodiment) beyond the CVD and is formed second metal film 13, forms barrier metal film 14 by second metal film 13 thereafter.Therefore, do not take place as use the CVD method the operation that directly forms the barrier metal film on the Semiconductor substrate Semiconductor substrate and the chemical reaction between the barrier metal film, can access the barrier metal film of membranous, the thickness of hope.
The application of the invention can realize low-resistance flip-chip.Fig. 2 is the plane graph that flip-chip of the present invention is adopted in expression, and 40 of Fig. 2 is sticking patch electrodes (G) of gate electrode 6 usefulness, the 41st, and the sticking patch electrode (S) that source electrode 7A uses, the 42nd, the sticking patch electrode of drain electrode (D) usefulness.In addition, in the scope of the flatness that does not hinder flip-chip, also can further constitute a plurality of sticking patch electrodes.
Second execution mode of the present invention is described with reference to the accompanying drawings.In the first above-mentioned execution mode, from face side (equipment component forms the face side) the formation through hole 10 of Semiconductor substrate.To this, in second execution mode, adopt the operation that forms through hole from the rear side of Semiconductor substrate.Below describe in detail.In addition, use prosign, simplify or omit its explanation about the structure identical with first execution mode.
At first as shown in Figure 6, on the surface of N type semiconductor substrate 1, form epitaxial loayer 2.Then, use known semiconductor manufacturing process on the surface of epitaxial loayer 2, to form p type diffused layer 3, ditch 4, dielectric film 5, gate electrode 6, source layer 7, P type body layer 8 respectively.Then, on source layer 7, form source electrode 7A, on the surface of the epitaxial loayer 2 that leaves p type diffused layer 3, form drain electrode 20.
Then on the back side of Semiconductor substrate 1, form protective layer (not shown), this protective layer as mask etching semiconductor substrate 1.By this etching, as shown in Figure 7, form from this back side the through hole 21 of the Semiconductor substrate 1 that connects the position corresponding to the surface with drain electrode 20.
Then, as shown in Figure 8, form dielectric film 22 in through hole 21 and on the back side of Semiconductor substrate 1.Dielectric film 22 is silicon oxide layer or the silicon nitride films that for example form by the CVD method.
Then, the dielectric film 22 on the bottom of selection etching through hole 21 and the back side of Semiconductor substrate 1, as shown in Figure 9, the dielectric film 22 on the side wall portion of only residual through hole 21.By this etching, on the bottom of through hole 21, expose drain electrode 20, expose the back side of Semiconductor substrate 1.
Then use the film forming method (for example sputtering method or vapour deposition method) beyond the CVD method, as shown in figure 10, forming metal film 23 (for example titanium (Ti) film) on the drain electrode 20 of the bottom of through hole 21 and on the back side of Semiconductor substrate 1.This metal film 23 is equivalent to said in the present invention second metal film.In addition, using sputtering method to form under the situation of metal film 23, few for the adhesion amount of the metal film 23 of the side wall portion of through hole 21.Therefore, in Figure 10, be illustrated in the structure that does not form metal film 23 on the side wall portion of through hole 21.In addition, when the formation of metal film 23, do not adopt the CVD method, be because also as described in the explanation of first execution mode, suppose by the CVD method on Semiconductor substrate, directly to form metal film that very difficult precision forms the thickness of hope, the cause of membranous metal film well.
Then, as shown in figure 11, use the CVD method to form barrier metal film 24 (for example TiN film or WN film) in through hole 21 and on the back side of Semiconductor substrate 1.Barrier metal film 24 is equivalent to said the 3rd metal film among the present invention.Barrier metal film 24 does not directly form on the back side of Semiconductor substrate 1, and forms by metal film 23.That is, when forming barrier metal film 24 on the back side of Semiconductor substrate 1, metal film 23 or dielectric film 22 become barrier, and the chemical reaction of the back side of Semiconductor substrate 1 and CVD gas etc. does not take place.Therefore, can form the thickness of hope, membranous barrier metal film 24.Then, form for example Seed Layer (not shown) of copper composition, make all of its covering barrier layer metal film 24.
Then, as shown in figure 12, on the back side of through hole 21 and Semiconductor substrate 1, use, form for example wiring layer 25 of copper composition the electrolytic plating method of Seed Layer as electroplated electrode.Wiring layer 25 is electrically connected with the back side and the drain electrode 20 of Semiconductor substrate 1 by Seed Layer or barrier metal film 24 or metal film 23.In the present embodiment, the electric conducting material integral body (metal film 23, barrier metal film 24, wiring layer 25) that forms in through hole 21 constitutes drain electrode layer 26., as required, source electrode 7A and drain electrode 20 on form as shown in Figure 2 sticking patch electrode, perhaps form the diaphragm of forming by protective material thereafter.
Then, the line of cut cut-out along regulation is divided into each semiconductor device 30.In addition, as the method that is divided into each semiconductor device 30, patterning method, etching method, laser cutting method etc. are arranged.Semiconductor device 30, as using shown in the arrow of Figure 12, electric current I 3 flows to the drain electrode layer 26 of through electrode structure from source layer 7.
In second execution mode,,, also can realize the low resistanceization of current path so compare with prior art constructions (with reference to Figure 14) because have the drain electrode layer 26 that in through hole 21, forms.
In addition, the invention is not restricted to above-mentioned first and second execution mode, in the scope that does not break away from its purport, can change.
For example, can in through hole (10,21), not fill wiring layer (15,25) fully, can not exclusively fill as shown in figure 13 yet.In addition, in the above-described 2nd embodiment, also can be before forming through hole 21 on the surface of Semiconductor substrate 1 support such as sticking glass substrate, carry out the formation of through hole 21 or metal film 23, barrier metal film 24, wiring layer 25 thereafter.Its reason is in the face side (equipment component face side) of protection Semiconductor substrate 1, strengthens Semiconductor substrate 1.Then, also can after forming drain electrode layer 26, take out support as required.
In addition, also go for forming semiconductor device or the semiconductor device of LGA (Land Grid Array) type or the semiconductor device of other CSP (Chip SizePackage) type of BGA (the Ball Grid Array) type of spherical terminal.
Claims (16)
1. semiconductor device is characterized in that having:
Form the Semiconductor substrate of first conductivity type of source layer from the teeth outwards;
The through hole that connects to the back side from the surface of described Semiconductor substrate;
The described through hole that is covered, first metal film that on the back side of described Semiconductor substrate, forms;
The drain electrode layer that is electrically connected with described first metal film that in described through hole, forms;
Described drain electrode layer is included in second metal film that forms and be connected with the surface of described Semiconductor substrate on the surface of described Semiconductor substrate;
On the side wall portion of described through hole, has first dielectric film;
Described drain electrode layer comprises the 3rd metal film of described first dielectric film of lining and described second metal film.
2. semiconductor device according to claim 1 is characterized in that having:
The epitaxial loayer that on the surface of described Semiconductor substrate, forms;
The impurity diffusion layer of second conductivity type that on described epitaxial loayer, forms;
The ditch that forms to the prescribed depth position of described epitaxial loayer from the top layer of described impurity diffusion layer;
The gate electrode that in described ditch, forms by the embedding conductive layer of second dielectric film;
Described source layer forms in abutting connection with described ditch on the top layer of described impurity diffusion layer.
3. semiconductor device according to claim 1 is characterized in that, described drain electrode layer comprises described the 3rd metal film of lining, is filled in wiring layer in the described through hole fully or not exclusively.
4. semiconductor device according to claim 1 is characterized in that, described second metal film is made up of the metal film that forms by sputtering method or vapour deposition method.
5. semiconductor device according to claim 1 is characterized in that, described the 3rd metal film is made up of the barrier metal film.
6. semiconductor device is characterized in that having:
Form the Semiconductor substrate of first conductivity type of source layer from the teeth outwards;
The through hole that connects to the back side from the surface of described Semiconductor substrate;
The described through hole that is covered, the drain electrode that on the surface of described Semiconductor substrate, forms;
The drain electrode layer that is electrically connected with described drain electrode that in described through hole, forms;
Described drain electrode layer is included in second metal film that forms and be connected with the back side of described Semiconductor substrate on the back side of described Semiconductor substrate;
On the side wall portion of described through hole, has first dielectric film;
Described drain electrode layer comprises the 3rd metal film of described first dielectric film of lining and described second metal film.
7. semiconductor device according to claim 6 is characterized in that having:
The epitaxial loayer that on the surface of described Semiconductor substrate, forms;
The impurity diffusion layer of second conductivity type that on described epitaxial loayer, forms;
The ditch that forms to the prescribed depth position of described epitaxial loayer from the top layer of described impurity diffusion layer;
The gate electrode that in described ditch, forms by the embedding conductive layer of second dielectric film;
Described source layer forms in abutting connection with described ditch on the top layer of described impurity diffusion layer.
8. semiconductor device according to claim 6 is characterized in that, described drain electrode layer comprises described the 3rd metal film of lining, is filled in wiring layer in the described through hole fully or not exclusively.
9. semiconductor device according to claim 6 is characterized in that, described second metal film is made up of the metal film that forms by sputtering method or vapour deposition method.
10. semiconductor device according to claim 6 is characterized in that, described the 3rd metal film is made up of the barrier metal film.
11. the manufacture method of a semiconductor device is characterized in that, has:
Preparation forms the Semiconductor substrate of first conductivity type of source layer and drain electrode from the teeth outwards, forms the operation that arrives the through hole of described drain electrode from the back side of described Semiconductor substrate;
In described through hole, form the operation of the drain electrode layer that is electrically connected with described drain electrode;
The operation that forms described drain electrode layer comprises the operation that forms second metal film that is connected with the back side of described Semiconductor substrate;
Operation with first dielectric film of the side wall portion that forms the described through hole of lining;
Has the operation that on first dielectric film of the side wall portion of described second metal film and described through hole, forms the 3rd metal film.
12. the manufacture method of semiconductor device according to claim 11 is characterized in that,
Form the operation of described first dielectric film, it comprises: the operation that forms dielectric film in described through hole and on the back side of described Semiconductor substrate;
Remove the operation of the described dielectric film on the back side of the bottom of described through hole and described Semiconductor substrate.
13. the manufacture method according to claim 11 or 12 described semiconductor devices is characterized in that having:
On the surface of described Semiconductor substrate, form the operation of the epitaxial loayer of first conductivity type;
On the surface of described epitaxial loayer, form the operation of the impurity diffusion layer of second conductivity type;
Form the operation of ditch to the prescribed depth position of described epitaxial loayer from the top layer of described impurity diffusion layer;
In described ditch, form the operation of second dielectric film;
On described second dielectric film, form the operation of gate electrode;
Described source layer is the top layer of described impurity diffusion layer, abuts to form with described ditch.
14. the manufacture method of semiconductor device according to claim 11 is characterized in that, has the operation that forms wiring layer by described the 3rd metal film in described through hole.
15. the manufacture method of semiconductor device according to claim 11 is characterized in that, the operation that forms described second metal film forms second metal film by sputtering method or vapour deposition method.
16. the manufacture method of semiconductor device according to claim 11 is characterized in that, the operation that forms described the 3rd metal film constitutes the 3rd metal film by the barrier metal film.
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| JP2005352424 | 2005-12-06 | ||
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| US8563360B2 (en) * | 2009-06-08 | 2013-10-22 | Alpha And Omega Semiconductor, Inc. | Power semiconductor device package and fabrication method |
| US8487371B2 (en) * | 2011-03-29 | 2013-07-16 | Fairchild Semiconductor Corporation | Vertical MOSFET transistor having source/drain contacts disposed on the same side and method for manufacturing the same |
| CN103390645B (en) * | 2012-05-08 | 2016-08-03 | 上海韦尔半导体股份有限公司 | LDMOS transistor and preparation method thereof |
| CN104218078B (en) * | 2013-06-05 | 2017-11-07 | 帅群微电子股份有限公司 | With drain electrode in the power transistor at top and forming method thereof |
| JP6131114B2 (en) * | 2013-06-13 | 2017-05-17 | ルネサスエレクトロニクス株式会社 | Semiconductor device and manufacturing method thereof |
| CN103996666B (en) * | 2014-06-05 | 2017-01-11 | 无锡新洁能股份有限公司 | Power semiconductor device and manufacturing method thereof |
| JP2016115698A (en) * | 2014-12-11 | 2016-06-23 | トヨタ自動車株式会社 | Semiconductor device and method of manufacturing the same |
| CN105870172A (en) * | 2016-04-28 | 2016-08-17 | 上海格瑞宝电子有限公司 | MOSFET and preparation method therefor |
| CN105845735A (en) * | 2016-04-28 | 2016-08-10 | 上海格瑞宝电子有限公司 | MOSFET and preparation method thereof |
| CN105932061A (en) * | 2016-04-28 | 2016-09-07 | 上海格瑞宝电子有限公司 | MOSFET and preparation method thereof |
| CN105762193A (en) * | 2016-04-28 | 2016-07-13 | 上海格瑞宝电子有限公司 | MOSFET and preparation method thereof |
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