CN100573875C - Memory - Google Patents

Abstract

The invention provides a kind of memory that reduces memory cell size.In this memory, first selects transistorized first grid electrode and second to select transistorized second grid electrode and word line integrated setting, and, overlook and see, the upwardly extending while of side that the bearing of trend of first impurity tilts on the formation zone of relative memory cell, select last first extrinsic region in transistorized formation zone to dispose across with the first selection transistor and second.

Description

Memory

Technical field

The present invention relates to a kind of memory, especially relate to the memory of mask rom etc.

Background technology

In the past, as an example of memory, known had a mask rom.This mask rom for example is disclosed in the spy and opens in the flat 5-275656 communique.

Figure 34 is based on the plane figure of the structure of the mask rom of the way of contact before illustrating.Figure 35 is the sectional view of former mask rom based on the way of contact shown in Figure 34 along the 500-500 line.With reference to Figure 34 and Figure 35, in the former mask rom, on substrate 201, form the extrinsic region 202 of a plurality of diffusion impurities across predetermined distance based on the way of contact.In addition, on corresponding to the substrate 201 between two adjacent extrinsic regions 202, form the word line 204 that is used as gate electrode through dielectric film 203.By this word line 204, gate insulating film 203, form a transistor 205 with corresponding two extrinsic regions 202.In addition, form ground floor interlayer insulating film 206, with the top and word line 204 of covered substrate 201.In the interlayer insulating film 206 of this ground floor, form contact hole 207 corresponding to each extrinsic region 202, simultaneously, in this contact hole 207, connect each extrinsic region 202 ground and imbed ground floor plug-in unit (plug) 208.

In addition, on ground floor interlayer insulating film 206, connect plug-in unit 208 ground source electrode line (GND line) 209 and articulamentum 210 are set.In addition, each memory cell 211 is provided with a transistor 205.In addition, on ground floor interlayer insulating film 206, form second layer interlayer insulating film 212, to cover source electrode line (GND line) 209 and articulamentum 210.Being positioned on the zone on the regulation articulamentum 210 of this second layer interlayer insulating film 212, form contact hole 213, simultaneously, in this contact hole 213, imbed second layer plug-in unit 214.In addition, on second layer interlayer insulating film 212, connect plug-in unit 214 ground and form bit line 215.Thus, the extrinsic region 202 that connects bit line 215 and transistor 205.

In addition, in the former mask rom,, determine whether transistor 205 is connected (contact) on bit line 215 by whether second layer contact hole (contact hole) 213 being set based on the way of contact.In addition, by whether transistor 205 being connected on the bit line 215, will comprising the data that the memory cell 211 of this transistor 205 has and distinguish ' 0 ' or ' 1 '.

But, in existing mask rom shown in Figure 34,, exist memory cell dimensions to become big problem because each memory cell 211 is provided with a transistor 205.

Summary of the invention

The present invention makes in order to address the above problem, and one object of the present invention is to provide a kind of memory that reduces memory cell dimensions.

To achieve these goals, the memory of first aspect present invention possesses: contain the memory cell array region territory that is configured to rectangular memory cell; The total first selection transistor and second of a plurality of memory cells is selected transistor; Play the electrode of the diode of formation memory cell, and play first and select transistor and second to select first extrinsic region of the side effect of transistorized regions and source; Playing first selects transistor and second to select second extrinsic region of the opposing party's effect of transistorized regions and source; With on the memory cell array region territory, along the word line of first extrinsic region setting.In addition, first selects transistor and second to select transistors share second extrinsic region, first selects transistorized first grid electrode and second to select transistorized second grid electrode and word line integrated setting, and overlook and see, extend on the direction that the bearing of trend of first extrinsic region tilts in the formation zone of relative memory cell, select transistor and second to select first extrinsic region in the transistorized formation zone to dispose across with first simultaneously, select transistor AND gate second to select transistor that first extrinsic region is cut apart by first.

The memory of this first aspect as mentioned above, configuration first selects transistorized first grid electrode and second to select transistorized second grid electrode, make it to extend on the direction that the bearing of trend of first extrinsic region in the formation zone of relative memory cell tilts, select transistor and second to select first extrinsic region in the transistorized formation zone to intersect with first simultaneously, the situation that constitutes gate electrode with a part that disposes word line at the bearing of trend to first extrinsic region is orthogonally compared, can make and the formation zone of memory cell on the direction of bearing of trend quadrature of first extrinsic region interval between adjacent word line diminish.Thus, memory cell dimensions is diminished, therefore can seek the miniaturization of memory.In addition, select transistorized first grid electrode and second to select transistorized second grid electrode and word line integrated setting by being arranged on first on each of a plurality of memory cells, owing to can use word line to constitute the selection transistor gate common to a plurality of memory cells, so compare with the situation of using word line on each memory cell, all to constitute a selection transistor gate electrodes, can significantly reduce the load capacity of word line.Can make the word line high speed motion thus.In addition, select transistor that first extrinsic region is cut apart, can suppress to increase the increase of the first extrinsic region impedance that causes by the length of first extrinsic region by the first selection transistor and second.The increase that the current impedance that can suppress to flow through first extrinsic region thus loses.In addition, constituting first in the mode of second extrinsic region of the opposing party's of having shared regions and source effect selects transistor and second to select transistor, with first and second is selected transistor be provided with respectively to compare, can make first and second select transistorized miniaturization as the situation of the opposing party's of regions and source extrinsic region.Can seek the miniaturization of memory thus.

In the memory of above-mentioned first aspect, adjacent two word lines that are provided with along first extrinsic region of having cut apart preferably are connected with the second grid electrode through the first grid electrode respectively.By such structure, owing to can connect into one word line to a plurality of first extrinsic region settings of cutting apart, thus different with the situation that a plurality of first extrinsic regions of cutting apart are provided with word line respectively, can suppress the increase of word line number.

In the memory of above-mentioned first aspect, first extrinsic region and second extrinsic region are preferably constituted mask, are formed by the ion injection on semiconductor substrate by first grid electrode and second grid electrode.By such structure, first extrinsic region and second extrinsic region can inject this one procedure by ion on semiconductor substrate and form simultaneously, so can simplify manufacture process.

In the memory of above-mentioned first aspect, first select first, second extrinsic region on the transistorized formation zone at least with the part of first grid electrode crossing near the zone, preferred disposition become along with the formation zone of memory cell in the bearing of trend of first extrinsic region extend, second select first, second extrinsic region in the transistorized formation zone at least with the part of second grid electrode crossing near the zone, be configured to extend along the bearing of trend of first extrinsic region on the formation zone of memory cell.By such structure, easily extend first of ground configuration for the bearing of trend at upper edge, the formation of memory cell zone first extrinsic region and select transistorized first extrinsic region that forms the zone, the bearing of trend of cross-over configuration first extrinsic region on the formation zone of memory cell is relatively overlooked the first grid electrode that extends the ground configuration on the direction of seeing inclination.In addition, easily extend second of ground configuration and select transistorized second extrinsic region that forms the zone for bearing of trend at upper edge, the formation of memory cell zone first extrinsic region, cross-over configuration with the formation zone of memory cell on overlook the second grid electrode that extends the ground configuration on the direction of seeing inclination on the bearing of trend of first extrinsic region.

In the memory of above-mentioned first aspect, select on the transistorized formation zone first first, second extrinsic region at least with the part of first grid electrode crossing near the zone, overlook and see, preferably on the direction that the first extrinsic region bearing of trend on the formation zone of relative memory cell tilts, extend the ground configuration, select on the transistorized formation zone first second, second extrinsic region at least with the part of second grid electrode crossing near the zone, overlook and see, preferably on the direction that the first extrinsic region bearing of trend on the formation zone of relative memory cell tilts, extend the ground configuration.By such structure, select on the transistorized formation zone first extrinsic region and first grid electrode to overlook to see under the state that incline direction tilts mutually to intersect first, so select first that first extrinsic region and first grid electrode can be with bigger angular cross on the transistorized formation zone.In addition, select on the transistorized formation zone first extrinsic region and second grid electrode to overlook to see under the state that incline direction tilts mutually to intersect second, so select second that first extrinsic region and second grid electrode can be with bigger angular cross on the transistorized formation zone.As mentioned above, select on the transistorized formation zone first extrinsic region and first grid electrode and second grid electrode to intersect at first and second, so select the length of the bearing of trend of the transistorized word line that forms the zone to diminish along first and second with wide-angle more.Therefore, can make and select transistor to diminish, seek the miniaturization of memory thus.In addition, in the case, be configured on the tilted direction on the transistorized formation of first selection zone with first, second extrinsic region at least with the part of first grid electrode crossing near the zone, make it to overlook and see, has angle below 40 ° with the bearing of trend of first extrinsic region on the formation zone of memory cell, simultaneously, also can select on the transistorized formation zone first being configured in second on the tilted direction, near second extrinsic region and part second grid electrode crossing at least zone, make it to overlook and see, have angle below 40 ° with the bearing of trend of first extrinsic region on the formation zone of memory cell.

Select on the transistorized formation zone first above-mentioned first, second extrinsic region at least with the part of first grid electrode crossing near the zone, with select on the transistorized formation zone first second, on second extrinsic region at least with the part of second grid electrode crossing near the zone, overlook and see, on tilted direction, extend the ground configuration, in such formation, be preferably, select on the transistorized formation zone first first, second extrinsic region at least with the part of first grid electrode crossing near the zone, overlook and see, on the opposite incline direction of first grid electrode extension tilted direction, extend the ground configuration, select on the transistorized formation zone first second, second extrinsic region at least with the part of second grid electrode crossing near the zone, overlook and see, in second grid electrode configuration relatively with extending the opposite tilted direction extension of the direction that tilts.By such structure, overlook and see, the first grid electrode and first extrinsic region that extend on mutually opposite tilted direction are intersected, simultaneously, overlook and see, the second grid electrode that extends on mutually opposite tilted direction is intersected with first extrinsic region.

Above-mentioned first selects transistorized formation zone last first, second extrinsic region at least with the part of first grid electrode crossing near the zone, with the transistorized formation of second selection zone last first, second extrinsic region at least with the part of second grid electrode crossing near the zone, overlook and see, on tilted direction, extend configuration, in such formation, be preferably, adjacent first grid electrode is connected by connecting portion with the second grid electrode, the end limit of opposing side with second extrinsic region of connecting portion, with first extrinsic region on the formation zone of memory cell oppose that with word line the end limit actual disposition of a side is on same line, the end limit of opposing a side with connecting portion of second extrinsic region, with the end limit of opposing a side with first extrinsic region of word line on the formation zone of memory cell, actual disposition is on same line.By such structure, on the peripheral part of memory cell array, that can suppress connecting portion opposes that with second extrinsic region end limit first extrinsic region of ratio on the formation zone of memory cell of a side is more outside outstanding, and that can suppress second extrinsic region simultaneously opposes that with connecting portion the end limit word line of ratio on the formation zone of memory cell of a side is more outside outstanding.Thus, can suppress the increase of memory cell array profile.

In this case, first grid electrode, connecting portion and second grid electrode overlooked see the shape that is configured to have the U word, simultaneously also can select transistor and second to select regional last first extrinsic region of transistorized formations and second extrinsic region with first, be configured to overlook the contrary U font of seeing that the U word shape with first grid electrode, connecting portion and second grid electrode intersects.

In the memory of above-mentioned first aspect, along the width on the direction of the actual quadrature of bearing of trend of first extrinsic region in word line and formation memory cell the zone that first extrinsic region is provided with, preferably than near width near the direction of the central portion of first grid electrode and the actual quadrature of the bearing of trend first grid electrode and the second grid electrode central portion with the direction of the actual quadrature of second grid electrode bearing of trend on width little.By such structure, under the situation of word line and first grid electrode and the integrated formation of second grid electrode, can guarantee that also the width on the direction of actual quadrature on the bearing of trend of first grid electrode and second grid electrode is the width of regulation, can make simultaneously along the width on the direction of actual quadrature on the bearing of trend of first extrinsic region in the word line of the first extrinsic region setting and formation memory cell the zone to diminish.Thus, the width that can guarantee first grid electrode and second grid electrode is the width of regulation, and the size on the direction of quadrature on the bearing of trend of first extrinsic region in memory cell array region territory is dwindled.

In the memory of above-mentioned first aspect, width on the direction of the connecting portion of first grid electrode and word line and the actual quadrature of the bearing of trend first grid electrode, preferably little than the width near the direction of the central portion of first grid electrode and the actual quadrature of the bearing of trend first grid electrode, width on the connecting portion of second grid electrode and word line and the bearing of trend second grid electrode on the direction of actual quadrature is littler than the width near the direction of actual quadrature on the central portion of second grid electrode and the bearing of trend second grid electrode.By such structure, width on connecting portion and the direction actual quadrature of first grid electrode bearing of trend on the word line of first grid electrode is diminished, so near the connecting portion on the word line of first grid electrode with the situation of other first grid electrode disposed adjacent, the connecting portion on the word line of also can mutually noninterfere ground configuration width little first grid electrode and other adjacent first grid electrode.In addition, width on connecting portion and the direction actual quadrature of second grid electrode bearing of trend on the word line of second grid electrode is diminished, so near the connecting portion on the word line of second grid electrode will the situation of other second grid electrode disposed adjacent, the connecting portion on the word line of also can mutually noninterfere ground configuration width little second grid electrode and other adjacent second grid electrode.

In the case, the relative both sides of first grid electrode, overlook and see, the bearing of trend that preferably contains first extrinsic region on the formation zone with memory cell has the part of first angle and has the part of second angle littler than first angle, the relative both sides of second grid electrode, overlook and see, contain with the memory cell array region territory on the bearing of trend of first extrinsic region have the part of first angle and have the part of second angle littler than first angle.By such structure, if near the connecting portion side on the word line of first grid electrode (second grid electrode) central portion of first grid electrode (second grid electrode), make width on the direction of the actual quadrature of bearing of trend of relative first grid electrode (second grid electrode) dispose part that the both sides relative with first grid electrode (second grid electrode) have first angle and part with second angle with diminishing, so make the width near the direction of actual quadrature on the connecting portion on the word line of first grid electrode (second grid electrode) and bearing of trend first grid electrode (second grid electrode) easily, also littler than the width near the direction of actual quadrature on the central portion of first grid electrode (second grid electrode) and bearing of trend first grid electrode (second grid electrode).

In the memory of above-mentioned first aspect, preferred a plurality of memory cells contain a diode separately, and first extrinsic region of first conductivity type plays a common electrode of diode of a plurality of memory cells.By such structure, because a plurality of memory cells contain a diode separately respectively, contain a transistor separately respectively with a plurality of memory cells and compare, can reduce the size of memory cell.In addition, first extrinsic region plays a common electrode of the diode of a plurality of memory cells, and diode first extrinsic region for a plurality of memory cells can be used jointly thus.Thus, can simplify the structure and the manufacture process in memory cell array region territory.

The memory of a second aspect of the present invention possesses: contain the memory cell array region territory that is configured to rectangular memory cell, select transistor with the first selection transistor and second that a plurality of memory cells are total, electrode with the diode that plays the formation memory cell, and playing first selects transistor and second to select first extrinsic region of the side effect of transistorized regions and source, with second extrinsic region of the opposing party's effect that plays the first selection transistor and the transistorized regions and source of second selection and the word line that is provided with at upper edge, memory cell array region territory first extrinsic region.In addition, first selects transistor and second to select transistors share second extrinsic region, first selects transistorized first grid electrode and second to select transistorized second grid electrode and word line integrated setting, and overlook and see, the upwardly extending while of side that the first extrinsic region bearing of trend tilts on the formation zone of relative memory cell, select last first extrinsic region in transistorized formation zone to dispose across with the first selection transistor and second, first selects transistor and second to select transistor to cut apart first extrinsic region, select on the transistorized formation zone first first, second extrinsic region at least with the part of first grid electrode crossing near the zone, overlook and see, on the direction that the first extrinsic region bearing of trend on the formation zone of relative memory cell tilts, extend the ground configuration, second selects transistorized formation zone last first, second extrinsic region at least with the part of second grid electrode crossing near the zone, overlook and see, on the direction that the bearing of trend of first extrinsic region on the formation zone of relative memory cell tilts, extend the ground configuration.

In the memory of this second aspect, as mentioned above, first selects transistorized first grid electrode and second to select transistorized second grid electrode, the upwardly extending while of side that the bearing of trend of first extrinsic region tilts on the formation zone of relative memory cell, select last first extrinsic region in transistorized formation zone to dispose across with the first selection transistor and second, dispose the situation of word line part formation gate electrode with the relative first extrinsic region bearing of trend orthogonally and compare, the interval between word line adjacent on the first extrinsic region bearing of trend orthogonal direction on the formation zone of relative memory cell can diminish.Thus, can reduce the size of memory cell.So can seek the miniaturization of memory.In addition, be arranged on first on each of a plurality of memory cells select transistorized first grid electrode and second select transistorized second grid electrode by with the word line integrated setting, can use word line to constitute the transistorized grid of the shared selection of a plurality of memory cells, so, with using word line the situation that each memory cell all constitutes a transistorized gate electrode is compared, can significantly be reduced the load capacity of word line.Thus, can make the word line high speed motion.In addition, select transistor to cut apart first extrinsic region, can suppress to increase the increase of the first extrinsic region impedance that causes by the length of first extrinsic region by the first selection transistor and second.The increase that the current impedance that can suppress to flow through first extrinsic region thus loses.In addition, the structure of second extrinsic region that first the opposing party who selects transistor and second to select transistors share to play regions and source acts on, compare with the situation of extrinsic region of first and second being selected crystal the opposing party's effect of regions and source has been set respectively, can make first and second selection transistor miniaturization.Thus, can seek the miniaturization of memory.

In addition, in the memory of second aspect, first selects transistorized formation zone last first, second extrinsic region at least with the near zone of the part of first grid electrode crossing, overlook and see, on the direction that the first extrinsic region bearing of trend on the formation zone of relative memory cell tilts, extend the ground configuration, first selects transistorized last first extrinsic region in zone and the first grid electrode of forming to overlook and see under the state that incline direction tilts mutually and intersect, so first selects regional last first extrinsic region of transistorized formation and the first grid electrode can be with bigger angular cross.In addition, with second select transistorized form the zone go up first, second extrinsic region at least with the part of second grid electrode crossing near the zone, overlook and see, on the direction that the first extrinsic region bearing of trend on the formation zone of relative memory cell tilts, extend the ground configuration, second selects transistorized last first extrinsic region in zone and the second grid electrode of forming to overlook and see under the state that incline direction tilts mutually and intersect, so second selects regional last first extrinsic region of transistorized formation and the second grid electrode can be with bigger angular cross.As mentioned above, transistorized formation last first extrinsic region in zone of first and second selection and first grid electrode and second grid electrode can be with bigger angular cross, so select the transistorized length that forms the bearing of trend of regional word line to diminish along first and second.Therefore, select transistor to diminish, so can seek the miniaturization of memory.

Description of drawings

Fig. 1 is the circuit diagram of formation that the mask rom of first embodiment of the invention is shown.

Fig. 2 is the plane figure of formation that the mask rom of first execution mode shown in Figure 1 is shown.

Fig. 3 is at the mask rom of first execution mode shown in Figure 2 sectional view along the 100-100 line.

Fig. 4 is the amplification view that amplifies the dashed region A of the mask rom that first execution mode shown in Figure 2 is shown.

Fig. 5 and Fig. 6 are the circuit diagrams of effect of the mask rom of explanation first embodiment of the invention.

Fig. 7～Figure 13 is the sectional view of manufacture process of the mask rom of explanation first embodiment of the invention.

Figure 14 is the sectional view of formation of mask rom of first variation of explanation first embodiment of the invention.

Figure 15～Figure 21 is the sectional view of manufacture process of mask rom of first variation of explanation first embodiment of the invention.

Figure 22 is the sectional view of formation of mask rom of second variation of explanation first embodiment of the invention.

Figure 23 is the circuit diagram of formation that the MRAM of second embodiment of the invention is shown.

Figure 24 and Figure 25 are the ideographs that the TMR element formation of the MRAM that is used for second execution mode shown in Figure 23 is described.

Figure 26 is the sectional view of formation of memory cell array that the MRAM of second execution mode shown in Figure 23 is shown.

Figure 27 is that the memory cell array of MRAM of second execution mode shown in Figure 26 is along the sectional view of 150-150 line.

Figure 28 is that the memory cell array of MRAM of second execution mode shown in Figure 26 is along the sectional view of 200-200 line.

Figure 29 illustrates the sectional view that the memory cell array of MRAM of the variation of second execution mode constitutes.

Figure 30 is that the memory cell array of MRAM of the second execution mode variation shown in Figure 29 is along the sectional view of 250-250 line.

Figure 31 is that the memory cell array of MRAM of the second execution mode variation shown in Figure 29 is along the sectional view of 300-300 line.

Figure 32 is the plane figure of structure that the mask rom of the 3rd execution mode of the present invention is shown.

Figure 33 is the amplification view that amplifies the dashed region D of the mask rom that the 3rd execution mode of the present invention shown in Figure 32 is shown.

Figure 34 is the plane figure that illustrates with the mask rom structure of last example.

Figure 35 is the sectional view of mask rom with last example shown in Figure 34 along the 500-500 line.

Embodiment

Below, with reference to accompanying drawing embodiments of the present invention are described.

(first execution mode)

With reference to Fig. 1～Fig. 4, the formation of the mask rom of first embodiment of the invention is described.

As shown in Figure 1, the mask rom of first execution mode possesses address input circuit 1, row decoder 2, column decoder 3, sense amplifier 4, output circuit 5 and memory cell array 6.In addition, constitute peripheral circuit by address input circuit 1, row decoder 2, column decoder 3, sense amplifier 4 and output circuit 5.Address input circuit 1 is by the address from outside input regulation, to row decoder 2 and column decoder 3 output address datas.In addition, on column decoder 2, connect many word lines (WL) 7.Row decoder 2 is selected the word line 7 corresponding to the address date of input by from address input circuit 1 Input Address data, simultaneously, makes the current potential of selected word line 7 rise to the H level.In addition, on column decoder 3, connect multiple bit lines (BL) 8.Column decoder 3 is selected the bit line 8 corresponding to the address date of input by from address input circuit 1 Input Address data, simultaneously, connects this bit line of choosing 8 and sense amplifier 4.In addition, sense amplifier 4 is under the situation of L level at the current potential of selected bit line 8 after judging and amplifying the current potential of the bit line of being selected by column decoder 38, the signal of output H level, simultaneously, be under the situation of H level at the current potential of selected bit line 8, the signal of output L level.In addition, sense amplifier 4 is included under the situation that the current potential of selected bit line 8 is not the L level, makes the current potential of bit line 8 rise to the load circuit (not shown) of H level.In addition, output circuit 5 comes to external output signal by the output of input sense amplifier 4.

In addition, in memory cell array 6, be configured to a plurality of memory cells 9 rectangular.Each memory cell 9 comprises a diode 10.In addition, in the memory cell array 6, setting comprises anode and is connected in the memory cell 9 of the diode 10 on the bit line 8 and comprises the memory cell 9 that anode is not connected in the diode 10 on the bit line 8.Utilization has unmatchful this bit line 8 to connect the anode of diode 10, is ' 0 ' or ' 1 ' with the data difference that is stored in the memory cell 9.In addition, the negative electrode with diode 10 is connected in the drain electrode of the selection transistor 11 that is made of the n channel transistor.In addition, the source electrode of selecting transistor 11 through source electrode line (GND line) 12 ground connection, simultaneously, is connected in grid on the word line 7.

In addition, in memory cell array 6, as shown in Figures 2 and 3, on p type silicon substrate 13, a plurality of n type extrinsic regions 14 are set across predetermined distance.This p type silicon substrate 13 is examples of ' semiconductor substrate ' of the present invention, and n type extrinsic region 14 is examples of ' first extrinsic region ' of the present invention.In addition, as shown in Figure 3, n type extrinsic region 14 is made of the extrinsic region 14a of n type low concentration and the n type extrinsic region 14b that forms deeplyer than extrinsic region 14a.In addition, extrinsic region 14b has the impurity concentration higher slightly than extrinsic region 14a.

Here, in the first embodiment, in a n type extrinsic region 14, form a plurality of (8) p type extrinsic region 15 across predetermined distance.Afterwards, form diode 10 by a p type extrinsic region 15 and n type extrinsic region 14.Thus, n type extrinsic region 14 plays the common negative electrode of a plurality of diode 10.In addition, p type extrinsic region 15 is as the anode of diode 10.In addition, in n type extrinsic region 14, form a plurality of (8) diode 10.That is, to n type extrinsic region 14 of a plurality of (8) diode 10 common uses.In addition, as shown in Figure 3,, then constitute pnp type bipolar transistor autoeciously if comprise p type silicon substrate 13 in the structure of diode 10.At this moment, as the p type extrinsic region 15 of the anode that is connected in the diode 10 on the bit line 8, the n type extrinsic region 14 that is used as negative electrode and emitter, base stage and the collector electrode that p type silicon substrate 13 is used separately as bipolar transistor.

In addition, in the first embodiment, n type extrinsic region 14 also works to select the drain region of transistor 11 (11a, 11b).The example that in addition, selecting transistor 11a is that the present invention ' first selects transistor ' an example, select transistor 11b of the present invention ' second to select transistor '.In the first embodiment, 8 diodes 10 (memory cell 9) respectively are provided with one and select transistor 11a and 11b.In addition, in the both sides of n type extrinsic region 14, form the source region 17 of selecting transistor 11 (11a, 11b) across predetermined distance.

In addition, the selection transistor 11a that is provided with by 8 memory cells 9 (diode 10) to regulation of source region 17 and selection transistor 11b that other 8 memory cells 9 (diode 10) in abutting connection with 8 memory cells 9 (diode 10) of this regulation are provided with share.In addition, source region 17 comprises n type low concentration impurity zone 17a and n type high concentration impurity 17b.Wherein, an example of source region 17 ' second extrinsic regions ' of the present invention.In addition, n type low concentration impurity zone 17a is formed on more shallow zone, the surface of p type silicon substrate 13, and on the other hand, n type high concentration impurity 17b is formed up to than the also dark zone of 17a, n type low concentration impurity zone.Thus, source region 17 has LDD (the Lightly Doped Drain) structure that is made of n type low concentration impurity zone 17a and n type high concentration impurity 17b.In addition, in source region 17, in n type low concentration impurity zone 17a and n type high concentration impurity 17b, form n type contact area 17c.This n type contact area 17c is set, the contact impedance when ground floor plug-in unit 23 described later being connected in source region 17 with reduction.

In addition, in the first embodiment, the extrinsic region 14a of the n type low concentration impurity of source region 17 zone 17a and n type extrinsic region 14 has identical impurity concentration.In addition, the n type high concentration impurity 17b of source region 17 has the high impurity concentration of impurity concentration than the extrinsic region 14b of n type extrinsic region 14.In addition, in memory cell array 6, as shown in Figure 2, select the common source zone 17 of transistor 11 (11a, 11b) to dispose adjacent n type extrinsic region 14 across predetermined distance respectively from two.That is, cut apart n type extrinsic region 14 by the zone corresponding to two selection transistors 11 (11a, 11b) of p type silicon substrate 13.

In addition, on the n type extrinsic region 14 and the channel region between the source region 17 of p type silicon substrate 13, form gate electrode 19 (19a, 19b) through gate insulating film 18.As shown in Figure 2, this gate electrode 19 (19a, 19b) is integrally formed with the word line 7 that is made of polysilicon film.In addition, gate electrode 19a is an example of ' first grid electrode ' of the present invention, and gate electrode 19b is an example of ' second grid electrode ' of the present invention.In addition, adjacent gate electrode 19a is connected by connecting portion 19c with gate electrode 19b.In addition, configuration gate electrode 19a, connecting portion 19c and gate electrode 19b see to have the U word shape to make it to overlook.

As shown in Figure 2, across predetermined distance a plurality of word lines 7 are set.In addition, gate electrode 19 (19a, 19b) forms by a part of bending of word line 7, simultaneously, overlooks and sees, extends the ground configuration on the direction that the bearing of trend of n type extrinsic region 14 tilts relatively.In addition, the n type extrinsic region 14 on the formation zone of the gate electrode 19a of selection transistor 11a and selection transistor 11a disposes across.In addition, the n type extrinsic region 14 on the formation zone of the gate electrode 19b of selection transistor 11b and selection transistor 11b disposes across.In addition, constitute selection transistor 11a by gate electrode 19a, n type extrinsic region 14 and source region 17.In addition, constitute selection transistor 11b by gate electrode 19b, n type extrinsic region 14 and source region 17.In addition, the relative both sides of gate electrode 19 as shown in Figure 4, are seen by overlooking, have with along the part (the B part among Fig. 4) of the direction angle at 45 approximately of n type extrinsic region 14 with have the part (the C part among Fig. 4) that becomes 40 ° of angles approximately and constitute.Thereby near the width t1 that constitutes the bend of word line 7 is littler than near the width t2 the central portion of gate electrode 19.In addition, with regard to each limit of gate electrode 19, it is shorter than the part with about 40 ° of angles (the C part among Fig. 4) to constitute the part (the B part among Fig. 4) with about 45 degree.By as above constituting, near the part with about 40 ° of angles of the bend of word line 7 (part of width t1) is relative with the part with about 45 degree of other adjacent word line 7, simultaneously, because the interval between two adjacent word lines 7 is wide, so the bend that suppresses word line 7 contacts with adjacent other word line 7.In addition, it is littler than near the width t2 the central portion of gate electrode 19 to constitute the width t3 along the part of n type extrinsic region 14 bearing of trends of word line 7.In addition, the magnitude relationship of the width of word line 7 each several parts (t1, t2, t3) is

In addition, as shown in Figure 3, the sidewall spacer 20 that is made of dielectric film is set in the both sides of gate electrode 19 (19a, 19b).In addition, on p type silicon substrate 13, cover gate electrode 19 (word line 7) and sidewall spacer 20 ground are provided with ground floor interlayer insulating film 21.In the zone corresponding to p type extrinsic region 15 and n type contact area 17c of this ground floor interlayer insulating film 21, contact hole 22 is set.In addition, in this contact hole 22, imbed the ground floor plug-in unit 23 that constitutes by W (tungsten).Thus, plug-in unit 23 is connected on p type extrinsic region 15 and the n type contact area 17c.

In addition, as shown in Figure 3, on ground floor interlayer insulating film 21, connect source electrode line 12 and ground floor articulamentum 24 that the 23 ground settings of ground floor plug-in unit are made of Al.In addition, on ground floor interlayer insulating film 21, cover source electrode line 12 and ground floor articulamentum 24 ground second layer interlayer insulating film 25 is set.In the zone corresponding to ground floor articulamentum 24 of this second layer interlayer insulating film 25, form contact hole 26.In this contact hole 26, imbed the second layer plug-in unit 27 that constitutes by W.

In addition, on second layer interlayer insulating film 25, be connected in the second layer articulamentum 28 that the 27 ground settings of second layer plug-in unit are made of Al.In addition, on second layer interlayer insulating film 25, cover second layer articulamentum 28 ground the 3rd layer interlayer dielectric film 29 is set.In the 3rd layer interlayer dielectric film 29, contact hole 30 is set, simultaneously, in this contact hole 30, imbeds the 3rd layer of plug-in unit 31 that constitutes by W.The 3rd layer of plug-in unit 31 is connected on the second layer articulamentum 28.On the 3rd layer interlayer dielectric film 29, a plurality of bit lines 8 that are made of Al are set across predetermined distance.This bit line 8 is connected on the 3rd layer of plug-in unit 31.In addition, the 3rd layer of plug-in unit 31 be arranged between the second layer articulamentum 28 and bit line 8 on the p type extrinsic region 15 (anode of diode 10) that is connected in regulation, on the other hand, be not arranged between the second layer articulamentum 28 and bit line 8 on the p type extrinsic region 15 (anode of diode 10) that is connected in addition.Thus, constituting anode is connected in diode 10 on the bit line 8 and anode and is not connected in diode 10 on the bit line 8.That is, in the first embodiment, in the 3rd layer interlayer dielectric film 29, store data ' 0 ' or ' 1 ' by whether contact hole 30 being set.

Below, the action of the mask rom of first execution mode is described with reference to Fig. 1.At first, with the address Input Address input circuit of stipulating 1.Thus, will output to row decoder 2 and column decoder 3 respectively from address input circuit 1 corresponding to the address date of this Input Address.Afterwards, by by row decoder 2 decode address data, select regulation word line 7 corresponding to address date.Afterwards, make the current potential of the word line 7 of this selection rise to the H level.Thus, the selection transistor 11 that is connected on this selection word line 7 of grid becomes conducting state.Therefore, owing to will select the drain potential of transistor 11 to drop to GND level (L level), so also be lowered to GND level (L level) with the cathode potential of the diode 10 of the common use of the drain electrode of selecting transistor 11.At this moment, the current potential of non-selected word line 7 keeps the L level.Thus, the selection transistor 11 that is connected on the non-selected word line 7 is maintained at cut-off state.

On the other hand, the regulation bit line 8 from the column decoder 3 of address input circuit 1 Input Address data is selected corresponding to the address date of input simultaneously, should be connected on the sense amplifier 4 by selected bit line 8.Afterwards, under the anode corresponding to the diode 10 of the memory cell 9 of selected word line 7, the selection corresponding with selected bit line 8 is connected in situation on the bit line 8, the current potential of bit line 8 is reduced to the L level through diode 10.Thus, the current potential of the L level of bit line 8 is delivered to sense amplifier 4.At this moment, after sense amplifier 4 is judged the current potential and amplification of bit line 8, the H level signal of the L level current potential opposite polarity of output and bit line 8.Afterwards, output circuit 5 receives the output signal of sense amplifier 4, to the signal of outside output H level.On the other hand, corresponding to selected word line 7, be not connected under the situation on the bit line 8 with the anode of the diode 10 of the selected memory cell 9 of selected bit line 8, the current potential with the L level does not pass to sense amplifier 4.At this moment, by the load circuit (not shown) that is arranged in the sense amplifier 4 current potential of bit line 8 is risen to the H level.Thus, after sense amplifier 4 is judged the current potential and amplification of bit line 8, the L level signal of the H level current potential opposite polarity of output and bit line 8.Afterwards, output circuit 5 receives the output signal of sense amplifier 4, to the signal of outside output L level.

In addition, in the mask rom of first execution mode, by in each memory cell 9 diode 10 being set, the mistake of the data that the current reflux when the inhibition data are read causes is read.Particularly, as shown in Figure 5, when sense data from selected memory cell, under the situation that electric current is crossed along the path flow of arrow D, suppress electric current by the E diode among Fig. 5 and flow through.On the other hand, in memory cell, be not provided with under the situation of diode, as shown in Figure 6, be back to other bit line outside the bit line of selection by path, thereby flow through electric current along arrow F.At this moment, owing to can not judge whether the data of reading through selected bit line are the data of selected memory cell, read so produce the mistake of data.On the contrary, in the mask rom of first execution mode, because the backflow that does not produce electric current, so only read the data of selected memory cell.Thus, the mistake that suppresses data is read.

In addition, in the first embodiment, if in the structure of diode 10, comprise p type silicon substrate 13 (with reference to Fig. 3), then when parasitism constituted pnp type bipolar transistor, p type extrinsic region 15, n type extrinsic region 14 and p type silicon substrate 13 were used separately as emitter, base stage and the collector electrode of bipolar transistor.Thereby, flow through electric current to the clockwise direction of diode 10 and be equivalent to flow through electric current between emitter-base stage at bipolar transistor.At this moment, between emitter (p type the extrinsic region 15)-collector electrode (p type silicon substrate 13) of bipolar transistor, also flow through electric current.Thus, the electric current that flows through bit line 8 is the summation that flows through the electric current between emitter (p type extrinsic region 15)-base stage (n type extrinsic region 14) and flow through the electric current between emitter (p type extrinsic region 15)-collector electrode (p type silicon substrate 13).Because the electric current of emitter-inter-collector produces under the situation that flows through electric current between emitter-base stage, so amplify the cell current that flows through through memory cell 9 (diode 10).Therefore, in the first embodiment, utilization is as the impedance height of the n type extrinsic region 14 of the negative electrode of diode 10, under the situation that the electric current that flows to the extrinsic region 14a of n type extrinsic region 14 from the p type extrinsic region 15 as anode diminishes, by amplifying, suppress to flow through the electric current minimizing of bit line 8 by the electric current that flows to p type silicon substrate 13 from p type extrinsic region 15.

Below, the manufacture process of the mask rom of first execution mode is described with reference to Fig. 2, Fig. 3 and Fig. 7～Figure 13.In addition, in the explanation of following manufacture process, be omitted in the operation that forms potential well (well) and element separated region (LOCOS or STI etc.) in the p type silicon substrate.

At first, as shown in Figure 7, through gate insulating film 18 word line 7 that formation is made of polysilicon on p type silicon substrate 13 (gate electrode 19).As shown in Figure 2, overlook and see, form a plurality of these word lines 7 across predetermined distance.

Then, as shown in Figure 8, gate electrode 19 as mask, on the regulation zone above p type silicon substrate 13, is being injected energy: about 50keV, dosage (injection rate): about 3.0 * 10 ¹³Cm ^-2Condition under, ion injects P (phosphorus).Thus, form by low concentration impurity zone 14a and n type low concentration impurity zone 17a corresponding to the n type extrinsic region 14 of the Region Segmentation of gate electrode 19.

Then, as shown in Figure 9, after covering whole ground formation dielectric film,, on the side of gate electrode 19, form the sidewall spacer 20 that constitutes by dielectric film by this dielectric film of anisotropic etching.Afterwards, after covering n type low concentration impurity zone 17a ground formation resist film 32, as mask, ion injects P (phosphorus) with gate electrode 19, sidewall spacer 20 and resist film 32.The ion implanting conditions of this moment is to inject energy: about 100keV, dosage: about 3.5 * 10 ¹³Cm ^-2Thus, on zone, form n type extrinsic region 14b with impurity concentration higher slightly than the impurity concentration of extrinsic region 14a corresponding to n type low concentration impurity zone 14a.This extrinsic region 14b is formed into the zone darker than extrinsic region 14a.In addition, constitute n type extrinsic region 14 by extrinsic region 14a and extrinsic region 14b.

Then, as shown in figure 10, cover n type extrinsic region 14 ground and form resist film 33.Afterwards, gate electrode 19, sidewall spacer 20 and resist film 33 as mask, are being injected energy: about 70keV, dosage: about 5.0 * 10 ¹⁵Cm ^-2Condition under ion inject As.Thus, on zone, form n type high concentration impurity 17b with impurity concentration also higher than the impurity concentration of n type low concentration impurity zone 17a corresponding to n type low concentration impurity zone 17a.This n type high concentration impurity 17b is formed into than the also dark zone of 17a, n type low concentration impurity zone.In addition, form n type source region 17 by n type low concentration impurity zone 17a and n type high concentration impurity 17b with LDD structure.

Then, as shown in figure 11, cover gate electrode 19 (word line 7) and sidewall spacer 20 ground form ground floor interlayer insulating film 21 on p type silicon substrate 13.Afterwards, use photoetching technique and dry etching technology, on the zone corresponding to source region 17 and n type extrinsic region 14 of ground floor interlayer insulating film 21, form contact hole 22.

Afterwards, as shown in figure 12, cover and to form resist film 34 corresponding to n type extrinsic region 14 on the ground floor interlayer insulating film 21 regionally.Afterwards, injecting energy: about 25keV, dosage: about 3.0 * 10 ¹⁴Cm ^-2Condition under, inject P (phosphorus) through contact hole 22 to source region 17 intermediate ions.Thus, form n type contact area 17c.

Afterwards, as shown in figure 13, what cover ground floor interlayer insulating film 21 forms resist film 35 corresponding to source region 17 regionally.Afterwards, injecting energy: about 40keV, dosage: about 2.0 * 10 ¹⁵Cm ^-2Condition under, inject BF through contact hole 22 to n type extrinsic region 14 intermediate ions ₂Thus, corresponding to contact hole 22, in n type extrinsic region 14, form a plurality of (8) p type extrinsic region 15.In n type extrinsic region 14, form a plurality of (8) diode 10 by this a plurality of (8) p type extrinsic region 15 and n type extrinsic region 14.In addition, p type extrinsic region 15 is formed into darker zone than the extrinsic region 14a of n type extrinsic region 14.

Then, as shown in Figure 3, imbed contact hole 22 ground and form the ground floor plug-in unit 23 that constitutes by W.Thus, ground floor plug-in unit 23 is connected respectively on the n type contact area 17c of p type extrinsic region 15 and source region 17.In addition, plug-in unit 23 ground that are connected on the p type extrinsic region 15 form the ground floor articulamentum 24 that is made of Al on ground floor interlayer insulating film 21, simultaneously, are connected in plug-in unit 23 ground that are connected on the source region 17 and form the source electrode line 12 that is made of Al.In addition, covering ground floor articulamentum 24 and source electrode line 12 ground form second layer interlayer insulating film 25 on ground floor interlayer insulating film 21 after formation contact hole 26 on corresponding to the zone of ground floor articulamentum 24.In addition, in this contact hole 26, imbed the second layer plug-in unit 27 that constitutes by W.Afterwards, be connected in second layer plug-in unit 27 ground and on second layer interlayer insulating film 25, form the second layer articulamentum 28 that constitutes by Al.Afterwards, cover second layer articulamentum 28 ground and on second layer interlayer insulating film 25, form the 3rd layer interlayer dielectric film 29.

In addition, on the zone corresponding to second layer articulamentum 28 of the 3rd layer interlayer dielectric film 29, form contact hole 30, simultaneously, in this contact hole 30, imbed the 3rd layer of plug-in unit 31 that constitutes by W.At this moment, p type extrinsic region 15 is being connected under the situation of bit line 8, contact hole 30 and the 3rd layer of plug-in unit 31 are being set, on the other hand, p type extrinsic region 15 be not connected under the situation of bit line 8, contact hole 30 and the 3rd layer of plug-in unit 31 be not set.At last, on the 3rd layer interlayer dielectric film 29, form the bit line 8 that constitutes by Al.Thus, on the zone that the 3rd layer of plug-in unit 31 is set, owing to second layer articulamentum 28 is connected through the 3rd layer of plug-in unit 31 with bit line 8, so the p type extrinsic region 15 that will be connected on this second layer articulamentum 28 is connected on the bit line 8.On the other hand, on the zone that the 3rd layer of plug-in unit 31 is not set, owing to second layer articulamentum 28 is not connected with bit line 8, so p type extrinsic region 15 is not connected on the bit line 8.Thus, formation is connected in anode (p type extrinsic region 15) corresponding to the diode 10 on the bit line 8 of one of data ' 0 ' or ' 1 ' and anode (p type extrinsic region 15) is not connected in corresponding to the diode 10 on data ' 0 ' or ' 1 ' the opposing party's the bit line 8.As mentioned above, form the memory cell array 6 of the mask rom of first execution mode shown in Figure 3.

In the first embodiment, as mentioned above, select the gate electrode 19a of transistor 11a and the gate electrode 19b of selection transistor 11b, the upwardly extending while of side that the bearing of trend of n type extrinsic region 14 tilts in the formation zone of relative memory cell 9, dispose across with the n type extrinsic region 14 on the formation zone of selecting transistor 11a and 11b, the situation that constitutes gate electrode with a part that bearing of trend at n type extrinsic region 14 disposes word line 7 is orthogonally compared, and the interval of 7 of word lines adjacent on the direction of the bearing of trend quadrature of n type extrinsic region 14 on the formation zone of relative memory cell 9 is diminished.Thus, can make memory cell dimensions littler.So can seek the miniaturization of mask rom.

In addition, in the first embodiment, by gate electrode 19a that will be arranged on the selection transistor 11a on each of a plurality of memory cells 9 and gate electrode 19b and word line 7 integrated setting of selecting transistor 11b, just can use word line 7 to constitute the common transistorized gate electrode of selection of a plurality of memory cell 9, therefore with use word line 7 to each memory cell 9 all the situation of the gate electrode of transistor formed compare, the load capacity of word line 7 can significantly reduce.Thus, word line 7 just can high speed motion.

In addition, in the first embodiment,, can suppress to increase the increase of n type extrinsic region 14 impedances that cause by the length of n type extrinsic region by selecting transistor 11a and selecting transistor 11b that n type extrinsic region 14 is cut apart.Can suppress the increase of the current impedances loss of flowing thus through n type extrinsic region 14.

In addition, in the first embodiment, select transistor 11a and select transistor 11b to constitute the structure of sharing source region 17, and the situation of selecting transistor 11a and 11b that the source region is set is respectively compared, can make and select transistor 11a and 11b miniaturization.

In addition, in the first embodiment, to adjacent two word lines 7 that are provided with along the n type impurity object area of having cut apart 14 respectively, by connecting through gate electrode 19a and 19b, owing to the word line 7 that connects into can be set to a plurality of n type extrinsic regions of having cut apart 14, so that word line 7 is set respectively is different with a plurality of n type extrinsic regions of having cut apart 14, can suppress increasing of word line 7 numbers.

In addition, in the first embodiment, constitute the extrinsic region 14a of n type extrinsic region 14 and the n type low concentration impurity zone 17a of formation source region 17, gate electrode 19a and gate electrode 19b are made mask, on p type silicon substrate 13, form by the ion injection, the extrinsic region 14a that constitutes n type extrinsic region 14 thus can inject this one procedure by ion on p type silicon substrate 13 with the n type low concentration impurity zone 17a that constitutes source region 17 and form simultaneously, so can simplify manufacture process.

Next, with reference to Figure 14, the formation of mask rom in first variation of first execution mode is described.In first variation of first execution mode, the situation of commonization of a part of the n of the anti-low pressure channel transistor, the p of anti-low pressure channel transistor and the high pressure resistant transistorized manufacture process that are provided with on transistorized manufacture process of the selection of memory cell array and the peripheral circuit is described.

Mask rom in first variation of first execution mode as shown in figure 14, add and select transistor 41, possess and have the withstand voltage n of the anti-low pressure channel transistor 42 of regulation in the peripheral circuit and have than the high withstand voltage high pressure resistant transistor 43 of the n of anti-low pressure channel transistor 42 and have the withstand voltage p channel transistor of anti-low pressure 44 of regulation.

In addition, select the n type regions and source 41a of transistor 41 to have the formation the same with the n type extrinsic region 14 of above-mentioned first execution mode.In the drain region of selecting transistor 41, form p type extrinsic region 15.Thus, in the drain region of selecting transistor 41, form the diode that constitutes by n type extrinsic region 14 and p type extrinsic region 15.On the other hand, in the source region of selecting transistor 41, be formed for the n type contact area 41c of the contact impedance of reduction and ground floor plug-in unit 23 (with reference to Fig. 3).In addition, the n type regions and source 42a of the n of anti-low pressure channel transistor 42 has n type low concentration impurity zone 42b that contains P (phosphorus) and the n type high concentration impurity 42c that contains As.In addition, constitute the LDD structure by n type low concentration impurity zone 42b and n type high concentration impurity 42c.In addition, in the n of the n of anti-low pressure channel transistor 42 type regions and source 42a, be provided for the n type contact area 42d of the contact impedance of reduction and ground floor plug-in unit 23 (with reference to Fig. 3).

In addition, the n type regions and source 43a of high pressure resistant transistor 43 has n type low concentration impurity zone 43b that contains P (phosphorus) and the n type high concentration impurity 43c that contains As.In addition, surround n type high concentration impurity 43c ground and form n type low concentration impurity zone 43b.Thus, between n type high concentration impurity 43c and p type silicon substrate 13, owing to sandwich n type low concentration impurity zone 43b, so can be concentrated by the electric field that n type low concentration impurity zone 43b relaxes on the whole borderline region of n type high concentration impurity 43c and p type silicon substrate 13.In addition, in the n of high pressure resistant transistor 43 type regions and source 43a, be provided for the n type contact area 43d of the contact impedance of reduction and ground floor plug-in unit 23 (with reference to Fig. 3).

In addition, the p type regions and source 44a of the p of anti-low pressure channel transistor 44 contains B (boron).In this p type regions and source 44a, be provided for the p type contact area 44c of the contact impedance of reduction and ground floor plug-in unit 23 (with reference to Fig. 3).Have, the p of anti-low pressure channel transistor 44 is formed in the n potential well 44d that forms in p type silicon substrate 13 again.

Here, in first variation of first execution mode, the n type low concentration impurity of high pressure resistant transistor 43 zone 43b has the identical impurity concentration of impurity concentration with the n type extrinsic region 14b that selects transistor 41.In addition, the n type high concentration impurity 43c of high pressure resistant transistor 43 has the identical impurity concentration of impurity concentration with the n type high concentration impurity 42c of the n of anti-low pressure channel transistor 42.In addition, the n type low concentration impurity of the n of anti-low pressure channel transistor 42 zone 42b has the identical impurity concentration of impurity concentration with the regional 14a of the n type low concentration impurity of selecting transistor 41.

In addition, on the formation zone of selecting transistor 41, the n of anti-low pressure channel transistor 42, high pressure resistant transistor 43 and the p of anti-low pressure channel transistor 44, form ground floor interlayer insulating film 21.On the zone of the p type contact area 44c of the n type contact area 43d of the n type contact area 42d corresponding to the p type extrinsic region 15 of selecting transistor 41 and n type contact area 41c, the n of anti-low pressure channel transistor 42 of this ground floor interlayer insulating film 21, high pressure resistant transistor 43 and the p of anti-low pressure channel transistor 44, contact hole 22,42e, 43e and 44e are set respectively.In addition, in contact hole 22,42e, 43e and 44e, imbed plug-in unit 23.

Below, the manufacture process of mask rom of first variation of first execution mode is described with reference to Figure 14-Figure 21.

At first, as shown in figure 15, on the formation zone of the p of the anti-low pressure channel transistor 44 of p type silicon substrate 13, form n potential well 44d.Afterwards, on p type silicon substrate 13, form gate electrode 19 through gate insulating film 18.Then, after the formation that covers high pressure resistant transistor 43 and the p of anti-low pressure channel transistor 44 forms resist film 45 regionally, resist film 45 as mask, is being injected energy: about 50keV, dosage (injection rate): about 3.0 * 10 ¹³Cm ^-2Condition under, ion injects P (phosphorus).Thus, form the n type low concentration impurity zone 42b of the n of anti-low pressure channel transistor 42 and the extrinsic region 14a of the low concentration of selecting transistor 41 simultaneously.

Then, as shown in figure 16, form resist film 46, to cover the formation zone of the n of anti-low pressure channel transistor 42 and the p of anti-low pressure channel transistor 44, cover the wideer zone of width of the ratio gate electrode 19 of selecting transistor 41 simultaneously, afterwards, resist film 46 as mask, is being injected energy: about 100keV, dosage: about 3.5 * 10 ¹³Cm ^-2Condition under, ion injects P (phosphorus).Thus, form the n type low concentration impurity zone 43b of high pressure resistant transistor 43.This n type low concentration impurity zone 43b is formed up to than regional 42b of the n type low concentration impurity of the n of anti-low pressure channel transistor 42 and the also dark zone of 14a, low concentration impurity zone of selecting transistor 41.In addition, on the formation zone of selecting transistor 41, form extrinsic region 14b with impurity concentration higher slightly than the impurity concentration of low concentration impurity zone 14a.Thus, on the formation zone of selecting transistor 41, form the n type regions and source 41a that constitutes by extrinsic region 14a and extrinsic region 14b.

Afterwards, as shown in figure 17, after covering whole ground formation dielectric film,, on the side of gate electrode 19, form the sidewall spacer 20 that constitutes by dielectric film by this dielectric film of anisotropic etching.

Then, as shown in figure 18, after the formation that covers selection transistor 41 and the p of anti-low pressure channel transistor 44 forms resist film 47 regionally, resist film 47 as mask, is being injected energy: about 70keV, dosage: about 5.0 * 10 ¹⁵Cm ^-2Condition under ion inject As.Thus, form the n type high concentration impurity 42c of the n of anti-low pressure channel transistor 42 and the n type high concentration impurity 43c of high pressure resistant transistor 43 simultaneously.Afterwards, on the formation zone of the n of anti-low pressure channel transistor 42, the n type regions and source 42a that formation is made of n type low concentration impurity zone 42b and n type high concentration impurity 42c, on the other hand, on the formation zone of high pressure resistant transistor 43, form the n type regions and source 43a that constitutes by n type low concentration impurity zone 43b and n type high concentration impurity 43c.

Afterwards, as shown in figure 19, cover and select the formation of transistor 41, the n of anti-low pressure channel transistor 42 and high pressure resistant transistor 43 to form resist film 48 regionally, afterwards, resist film 48 as mask, is being injected energy: about 50keV, dosage: about 2.0 * 10 ¹⁵Cm ^-2Condition under, ion injects BF ₂Thus, form the p type regions and source 44a of the p of anti-low pressure channel transistor 44.

Afterwards, as shown in figure 20, by heat-treating the p type impurity among the p type regions and source 44a of the thermal diffusion p of anti-low pressure channel transistor 44.Thus, form the below of p type regions and source 44a to the sidewall spacer 20 of the p of anti-low pressure channel transistor 44.Afterwards, by with the same process of above-mentioned first execution mode, cover to select transistor 41, the n of anti-low pressure channel transistor 42, high pressure resistant transistor 43 and the p of anti-low pressure channel transistor 44 formation separately to form ground floor interlayer insulating film 21 regionally.Afterwards, on the p type regions and source 44a regulation zone separately of the n type regions and source 43a of the n type regions and source 42a corresponding to the n type regions and source 41a that selects transistor 41, the n of anti-low pressure channel transistor 42 of ground floor interlayer insulating film 21, high pressure resistant transistor 43 and the p of anti-low pressure channel transistor 44, form contact hole 22,42e, 43e and 44e respectively.What afterwards, cover ground floor interlayer insulating film 21 forms resist film 49 corresponding to the formation zone of the formation zone of the source region of selecting transistor 41, the n of anti-low pressure channel transistor 42 and high pressure resistant transistor 43 regionally.Afterwards, resist film 49 as mask, is being injected energy: about 40keV, dosage: about 2.0 * 10 ¹⁵Cm ^-2Condition under, ion injects BF ₂Thus, form the p type contact area 44c and the p type extrinsic region 15 of the p of anti-low pressure channel transistor 44 simultaneously.Form diode by this p type extrinsic region 15 and n type extrinsic region 14.

At last, as shown in figure 21, cover ground floor interlayer insulating film 21 corresponding to forming resist film 50 on the zone in the formation zone of the drain region of selecting transistor 41 and the p of anti-low pressure channel transistor 44, afterwards, resist film 50 as mask, is being injected energy: about 25keV, dosage: about 3.0 * 10 ¹⁴Cm ^-2Condition under, ion injects P (phosphorus).Thus, the regions and source 43a of the regions and source 42a of the source region of selecting transistor 41, the n of anti-low pressure channel transistor 42 and high pressure resistant transistor 43 separately in, form n type contact area 41c, 42d and 43d respectively.Afterwards, in contact hole 22,42e, 43e and 44e, imbed plug-in unit 23.As mentioned above, form selection transistor 41, the n of anti-low pressure channel transistor 42, high pressure resistant transistor 43 and the p of anti-low pressure channel transistor 44 shown in Figure 14.

Manufacture process outside first variation of first execution mode above-mentioned is the same with the manufacture process of above-mentioned first execution mode.

In first variation of first execution mode, as mentioned above, constitute the n type low concentration impurity zone 43b of high pressure resistant transistor 43, make it to have the identical impurity concentration of impurity concentration with the n type extrinsic region 14b that selects transistor 41, simultaneously, constitute the n type impurity area with high mercury 43c of high pressure resistant transistor 43, make it to have the identical impurity concentration of impurity concentration with the n type high concentration impurity 42c of the n of anti-low pressure channel transistor 42, constitute the n type low concentration impurity zone 42b of the n of anti-low pressure channel transistor 42 more simultaneously, make it to have the identical impurity concentration of impurity concentration with the n type extrinsic region 14a that selects transistor 41, thus, can form the n type low concentration impurity zone 43b of high pressure resistant transistor 43 by the operation identical with the extrinsic region 14b that selects transistor 41, simultaneously, can form the n type high concentration impurity 43c of high pressure resistant transistor 43 by the operation identical with the n type high concentration impurity 42c of the n of anti-low pressure channel transistor 42.In addition, can form the n type low concentration impurity zone 42b of the n of anti-low pressure channel transistor 42 by the operation identical with the extrinsic region 14a that selects transistor 41.In addition, can form the p type extrinsic region 15 that constitutes diode by the operation identical with the p type contact area 44c of the p of anti-low pressure channel transistor 44.Thus, when in memory cell array, forming under the situation of selecting transistor 41 and diode, because can the local n of anti-low pressure channel transistor 42, high pressure resistant transistor 43 and the p of anti-low pressure channel transistor 44 and the manufacture process of sharing peripheral circuit, even select transistor 41 and diode so be provided with, manufacture process basically can be not complicated yet.

In addition, as second variation of first execution mode, as shown in figure 22, also can constitute the source region 41b (17) that selects transistor 41 with the n type regions and source 42a of the n of anti-low pressure channel transistor 42 the samely.At this moment, as shown in figure 15, in the ion injecting process of P (phosphorus), the extrinsic region 17a of the source region 41b (17) of selection transistor 41 and the low concentration of drain region 41a (14) and 14a (with reference to Figure 22) and the n type low concentration impurity zone 42b of the n type source/drain 42a of the n of anti-low pressure channel transistor 42 similarly form in above-mentioned first variation.Afterwards, as shown in figure 16, in the operation of above-mentioned first variation, the ion of cover selecting at resist film to carry out P (phosphorus) under the state in formation zone of source region 41b (17) (with reference to Figure 22) of transistor 41 injects.Thus, in the formation zone of selecting transistor 41, within regions and source 41b (17) (with reference to Figure 22) and the 41a, form extrinsic region 14b on the 41a of drain region, on the other hand, source electrode 41b does not form extrinsic region 14b on (17).Thereafter, in the operation of above-mentioned first variation as shown in figure 18, when resist film covers the formation zone of the drain region 41a (14) that selects transistor 41, under the state of the formation zone of source region 41b (17) (with reference to Figure 22) opening, As is injected in the formation zone of the formation zone of the source region 41b (17) of selection transistor 41 and the regions and source 42a of the n of anti-low pressure channel transistor 42 similarly ion.Thus, select on the source region 41b (17) of transistor 41 formation and the same dark high concentration impurity 17b (with reference to Figure 22) of the n type high concentration impurity 42c of the n type regions and source 42a of the n of anti-low pressure channel transistor 42.In second variation of first execution mode, above-mentioned manufacture process and above-mentioned first variation in addition similarly carried out, and can form the selection transistor 41 of second variation shown in Figure 22.

(second execution mode)

With reference to Figure 23～Figure 28, the formation of the MRAM (MagneticRandom Access Memory) of second embodiment of the invention is described.In this second execution mode, be example to form the negative electrode of selecting the transistor drain zone and being contained in the diode in the memory cell by common extrinsic region, the MRAM of crosspoint type is described.

In the MRAM of second execution mode, as shown in figure 23, be configured in each memory cell 59 in the memory cell array 56 and possess a diode 60, TMR (TunnelingMagneto Resistance) element 62.In addition, an electrode of TMR element 62 is connected on the anode of diode 50, simultaneously, other electrode is connected on the bit line (BL) 8.It is the same with the circuit formation of the mask rom of above-mentioned first execution mode that circuit outside the MRAM of second execution mode above-mentioned constitutes.

In addition, TMR element 62 is as Figure 24 and shown in Figure 25, has to use pinning (pin) the layer 62b that be made of magnetic and freedom (free) the layer 62c clamping structure by the nonmagnetic layer 62a of oxide-film (aluminium oxide) formation that approaches.Pinning layer 62b is made of the magnetosphere with characteristic that the magnetism direction is difficult to change.In addition, free layer 62c is made of the magnetosphere that the magnetism direction changes easily.In addition, TMR element 62 constitutes under the magnetism direction of pinning layer 62b situation identical with the magnetism direction of free layer 62c and different situation, the size variation of the electric current that flows through through TMR element 62.That is, under the magnetism direction of the pinning layer 62b situation identical with the magnetism direction of free layer 62c, along with the impedance of TMR element 62 diminishes, the electric current I that flows through through TMR element 62 ₀(with reference to Figure 24) becomes big.On the other hand, under the magnetism direction of the pinning layer 62b situation different with the magnetism direction of free layer 62c, along with the impedance of TMR element 62 becomes big, the electric current I that flows through through TMR element 62 ₁(with reference to Figure 25) diminishes.

In addition, in the memory cell array 56 of the MRAM of second execution mode,, on p type silicon substrate 13, form the n type extrinsic region 64 of a plurality of P of containing (phosphorus) across predetermined distance as Figure 26 and shown in Figure 27.This n type extrinsic region 64 is examples of ' first extrinsic region ' of the present invention.In addition, in n type extrinsic region 64, form the p type extrinsic region 65 that contains B (boron).In addition, constitute diode 60 by p type extrinsic region 65 and n type extrinsic region 64.In addition, along the bearing of trend of n type extrinsic region 64,, as shown in figure 27, be provided with and select transistor 61 in the both sides of n type extrinsic region 64.

Here, in second execution mode, n type extrinsic region 64 is by the shared drain region 66 of making the negative electrode of a plurality of (8) diode 60 and selecting transistor 61.In addition, on p type silicon substrate 13, with n type extrinsic region 64 across predetermined distance, the n type source region 67 of selecting transistor 61 is set.In addition, in n type source region 67, be formed for reducing the n type contact area 67c of the contact impedance when ground floor plug-in unit 23 is connected in n type source region 67.In addition, on the channel region between n type extrinsic region 64 and the source region 67,, the gate electrode 69 that is made of polysilicon is set through gate insulating film 68.

In addition, between two n type extrinsic regions 64 of adjacency on the direction of extending, as shown in figure 26, form the element separating insulation film 70 that constitutes by silicon oxide film along bit line BL.On this element separating insulation film 70, the word line 7 that is made of polysilicon is set.Above-mentioned gate electrode 69 is integrally formed with this word line 7.In addition, on the ground floor interlayer insulating film 21 on covering word line 7 ground are arranged on above the p type silicon substrate 13,, the lining wiring 71 of the word line 7 that is made of Al is set corresponding to word line 7 as Figure 26 and shown in Figure 28.This lining wiring 71 is connected with word line 7 through plug-in unit (not shown) on the regulation zone.

In addition, on the second layer interlayer insulating film 25 that is arranged on the ground floor interlayer insulating film 21, the TMR element 62 with above-mentioned formation is set.The pinning layer 62b of this TMR element 62 is connected with p type extrinsic region 65 (anode of diode 60) through ground floor plug-in unit 23, articulamentum 24 and second layer plug-in unit 26.In addition, on the free layer 62c of TMR element 62, form the bit line 8 that constitutes by Al.The edge is formed extended at both sides this bit line 8 with the direction of the bearing of trend quadrature of the lining wiring 71 of word line 7.

Formation outside the MRAM of second execution mode above-mentioned is the same with the formation of the mask rom of above-mentioned first execution mode.

Below, the action of the MRAM of second execution mode is described with reference to Figure 26.

When the MRAM of second execution mode rewrite data, in the lining wiring 71 of bit line 8 and word line 7, flow through orthogonal electric current.Thereby, the data that can only rewrite the TMR element 62 on the intersection point that is positioned at this bit line 8 and lining wiring 71.Particularly, each electric current that flows through lining wiring 71 and bit line 8 produces magnetic field, simultaneously, these two magnetic fields and (resultant magnetic field) act on TMR element 62.By this resultant magnetic field, the counter-rotating of the magnetism direction of the free layer 62c of TMR element 62.Thereby the data that TMR element 62 is kept for example are rewritten into ' 0 ' from ' 1 '.In addition, the action as from the MRAM sense data of second execution mode time is according to the variation of the electric current that flows through along with the impedance variation of TMR element 62, by sense amplifier 4 judgment data ' 0 ' or ' 1 '.In addition to read action the same with the action of the mask rom of above-mentioned first execution mode.

In the MRAM of second execution mode, as mentioned above, with regard to the MRAM that TMR element 62 is set, can reduce memory cell dimensions on diode 10, simultaneously, can simplify the structure and the manufacture process in memory cell array region territory.

Effect outside second execution mode above-mentioned is the same with the effect of above-mentioned first execution mode.

The formation of MRAM of the variation of second execution mode is described with reference to Figure 29-Figure 31.

In the MRAM of the variation of second execution mode, different with the MRAM of above-mentioned second execution mode, constitute by in the pinning layer 92d of TMR element 92, directly flowing through the data that electric current is rewritten TMR element 92.Particularly, as shown in figure 29, TMR element 92 has pinning layer 92b and the 92d that is divided into two.Pinning layer 92b such as Figure 29 and shown in Figure 30 are connected on the p type extrinsic region 65 (anode of diode 60) through plug-in unit 23.Another pinning layer 92d forms the edge and extends with the direction of the bearing of trend quadrature of bit line 8 as shown in figure 31.In addition, pinning layer 92d is connected with plug-in unit (not shown) on being connected in word line 7 in regulation zone.In addition, different with above-mentioned second execution mode in the variation of second execution mode, lining wiring 71 (with reference to Figure 26) of word line 7 are not set.Formation outside the MRAM of the variation of second execution mode above-mentioned is the same with the formation of the MRAM of above-mentioned second execution mode.

Below, the action of MRAM of the variation of second execution mode is described.In the MRAM of the variation of second execution mode, when rewrite data, in a pinning layer 92d of bit line 8 and TMR element 92, flow through orthogonal electric current.Thus, produce magnetic field by flowing through bit line 8 each electric current with pinning layer 92d.By the resultant magnetic field in these two magnetic fields, the counter-rotating of the magnetism direction of free layer 92c.Thereby the data that TMR element 92 is kept for example are rewritten into ' 0 ' from ' 1 '.Action outside the MRAM of the variation of second execution mode above-mentioned is the same with the action of the MRAM of above-mentioned second execution mode.

In the variation of second execution mode, as mentioned above, flow through electric current among the pinning layer 92d at TMR element 92 by constituting when the rewrite data, can in pinning layer 92d, produce magnetic field near free layer 92c.Thus, under the little situation of the electric current that flows through pinning layer 92d, the magnetism direction of free layer 92c is fully reversed, so the data of can little electric current efficiently rewriting TMR element 92.

(the 3rd execution mode)

Figure 32 is the plane figure that the mask rom structure of the 3rd execution mode of the present invention is shown.Figure 33 is the amplification view that amplifies the dashed region D of the mask rom that the 3rd execution mode of the present invention shown in Figure 32 is shown.Next, with reference to Figure 32 and Figure 33, the structure of the mask rom of the 3rd execution mode of the present invention is described.

In the 3rd execution mode in the mask rom, as Figure 32 and shown in Figure 33, different with the mask rom of above-mentioned first execution mode, extend on the tilted direction configuration with the formation zone of the transistor 11a that elects on the near zone of the part of intersecting with gate electrode 19a of the n type extrinsic region 114 of drain region and source region 117, make to overlook and see, have angle θ (about below 40 °) with the bearing of trend of n type extrinsic region 114 on the formation zone of memory cell shown in Figure 19.Moreover n type extrinsic region 114 is examples of " first extrinsic region " of the present invention, and source region 117 is examples of " second extrinsic region " of the present invention.In addition, on the formation zone of selection of configuration transistor 11a as near the zone the part of intersecting with gate electrode 19a of the n type extrinsic region 114 of drain region and source region 117, make to overlook and see, on the opposite tilted direction of the tilted direction of the extension of the gate electrode 19a that selects transistor 11a, extend.Thus, in the mask rom of the 3rd execution mode, compare, constitute n type extrinsic region 114 on the formation zone of selecting transistor 11a, select the gate electrode 19a of transistor 11a with bigger angular cross ground with the mask rom of first execution mode shown in Figure 2.

In addition, select on the formation zone of transistor 11b, in near the zone of extending on the tilted direction part that configuration intersects as the n type impurity 114 of drain region and source region 117 and gate electrode 19b, overlook and see, on the formation zone of memory cell shown in Figure 19 with the angled θ of bearing of trend (about below 40 °) of n type extrinsic region 114.In addition, on the formation zone of selection of configuration transistor 11b as near the zone the part of intersecting with gate electrode 19b of the n type extrinsic region 114 of drain region and source region 117, make to overlook and see, the tilted direction opposite with the tilted direction of the extension of the gate electrode 19b that selects transistor 11b extends.Thus, mask rom in the 3rd execution mode is compared with the mask rom of first execution mode shown in Figure 2, selects on the formation zone of transistor 11b n type extrinsic region 114 and selects the gate electrode 19b of transistor 11b to constitute with bigger angular cross ground.

In addition, in the 3rd execution mode, two limits relative with gate electrode 19, as shown in figure 33, overlook and see, by with constitute into about the part (the E part among Figure 33) of 45 with into about the part (the F part among Figure 33) at 40 ° of angles along n type extrinsic region 114 directions.Thereby, with the wide t11 that forms on the direction of the actual quadrature of bearing of trend of the gate electrode 19 of the connecting portion of the word line 7 of gate electrode 19, than with the central portion of gate electrode 19 near the actual orthogonal direction of bearing of trend of gate electrode 19 on wide t12 narrow.According to aforesaid structure, near the part with about 40 ° of angles of (the wide t11 part) connecting portion of the word line 7 of gate electrode 19, in the time of relative with adjacent other gate electrode 19, interval between two adjacent gate electrodes 19 broadens, and contacts with adjacent other gate electrode 19 so suppressed the connecting portion near zone of the word line 7 of gate electrode 19.In addition, as shown in figure 33, wide t13 on the direction of the actual quadrature of n type extrinsic region 114 bearing of trends of word line 7 on the formation zone of memory cell 9 in that form and first execution mode shown in Figure 1, than with the central portion of gate electrode 19 near the actual orthogonal direction of bearing of trend of gate electrode 19 on wide t12 narrow.

In addition, in the 3rd execution mode, n type extrinsic region 114 and source region 117 on the formation zone of selection of configuration transistor 11a and 11b make it to overlook and see, have the contrary U font that the U font with gate electrode 19a, connecting portion 19c and gate electrode 19b intersects.Then, the end limit opposite with the source region 117 of connecting portion 19c and with the formation zone of as shown in Figure 1 memory cell 9 on the end limit of word line 7 opposition sides of n shape extrinsic region 114, be configured on the actual the same line.In addition, the end limit of the connecting portion 19c opposition side of source region 117, the end limit opposite with the n type extrinsic region 114 of word line 7 on the formation zone of memory cell 9 shown in Figure 1, actual disposition is on the same line.

Structure in the 3rd execution mode beyond mask rom above-mentioned is identical with the structure of mask rom in above-mentioned first execution mode.

In the 3rd execution mode, as mentioned above, select on the formation zone of transistor 11a as near the zone the part of intersecting with gate electrode 19a of the n type extrinsic region 114 of drain region and source region 117, overlook and see, on the direction that the bearing of trend of n type extrinsic region 114 on the formation zone of relatively as shown in Figure 1 memory cell 9 tilts, extend configuration, thus, select on the formation zone of transistor 11a n type extrinsic region 114 and gate electrode 19a to overlook to see under the state that incline direction tilts mutually to intersect, so select that n type extrinsic region 114 and gate electrode 19a can be with bigger angular cross on the formation zone of transistor 11a.In addition, select on the formation zone of transistor 11b as near the zone the part of intersecting with gate electrode 19b of the n type extrinsic region 114 of drain region and source region 117, overlook and see, on the direction that the bearing of trend of n type extrinsic region 114 on the formation zone of relatively as shown in Figure 1 memory cell 9 tilts, extend configuration, thus, select on the formation zone of transistor 11b n type extrinsic region 114 and gate electrode 19b to overlook to see to intersect under tilting state, so select that n type extrinsic region 114 and gate electrode 19b can be with bigger angular cross on the formation zone of transistor 11b at tilted direction mutually.As mentioned above, n type extrinsic region 114 and gate electrode 19a and 19b can be with bigger angular cross, so the length (the long L among Figure 32) of the bearing of trend of the word line 7 in the formation zone of edge selection transistor 11a and 11b can diminish on the formation zone of selection transistor 11a and 11b.Thus, can reduce to select transistor, so can seek the miniaturization of mask rom.

In addition, in the 3rd execution mode, the end limit of reality opposition side of the source region 117 of configuration connecting portion 19c on same straight line, end limit with word line 7 opposition sides of n type extrinsic region 114 on the formation zone of memory cell 9, simultaneously, the end limit of reality opposition side of the connecting portion 19c of configuration source region 117 on same straight line, end limit with n type extrinsic region 114 opposition sides of word line 7 on the formation zone of memory cell 9, thereby on the peripheral part of memory cell array 6, the end limit of opposition side that can suppress the source electrode 117 of connecting portion 19c, more outside more outstanding than n type impurity on the formation zone of memory cell 9 114, the end limit of opposition side of connecting portion 19c that can suppress source region 117 simultaneously is more outside more outstanding than word line on the formation zone of memory cell 97.Thus, increase that can control storage cell array 6 profiles.

Above-mentioned effect in addition is identical with the effect of above-mentioned first execution mode in the 3rd execution mode.

Current disclosed execution mode all should be thought example in all respects and be unrestricted.Scope of the present invention is as the scope of claim but not shown in the explanation of above-mentioned execution mode, and comprises the implication identical with the scope of claim and all changes in the scope.

For example, in the above-described embodiment, for example understand the present invention is applicable in the mask rom and MRAM of crosspoint type, but the invention is not restricted to this, also can be widely used in the memory or the memory outside the type of crosspoint of the crosspoint type outside mask rom or the MRAM.Particularly, in the above-described 2nd embodiment, illustrate the MRAM of TMR element, but the invention is not restricted to this, also the present invention can be applicable in the memory of the element beyond the TMR element as the element of following impedance variation as the element of following impedance variation.For example, also the present invention can be applicable to and use resistance value along with utilizing heat to switch among the OUM (Ovonic Unified Memory) of the element that noncrystalline state changes with crystalline state or the use RRAM (Resistance Random Access Memory) by CMR (the Colossal Magneto Resistive) element that applies potential pulse, resistance value and change significantly etc.

In addition, in the above-described first embodiment, constitute the n type extrinsic region 14 of diode cathode by the extrinsic region 14a of low concentration and extrinsic region 14b with impurity concentration higher slightly than extrinsic region 14a, but the invention is not restricted to this, the extrinsic region 14a that also can constitute n type extrinsic region 14 has identical in fact impurity concentration with extrinsic region 14b.In addition, also can only constitute n type extrinsic region 14 by extrinsic region 14a.At this moment, preferably set ion implanting conditions, in extrinsic region 14a, to form p type extrinsic region 15.In addition, also can change the p type zone of above-mentioned execution mode and variation and the conduction type in n type zone and constitute memory.

Claims (12)

1. memory is characterized in that possessing:

The memory cell array region territory that comprises the memory cell of rectangular configuration;

The total first selection transistor and second of a plurality of described memory cells is selected transistor;

Work to constitute the electrode of the diode in the described memory cell, and play a side first extrinsic region of the source/drain region of described first selection transistor and described transistor seconds;

Playing described first selects transistor and described second to select second extrinsic region of the opposing party's effect of transistorized source/drain region; And

The word line that described first extrinsic region is provided with in upper edge, described memory cell array region territory,

Described first selects transistor and described second to select described second extrinsic region of transistors share,

Described first selects transistorized first grid electrode and described second to select transistorized second grid electrode by same described word line integrated setting each other, and, overlook and see, in the upwardly extending while of side that the bearing of trend of the above first extrinsic region of the formation of described relatively memory cell zone tilts, select transistorized described first extrinsic region that forms the zone to dispose across with the described first selection transistor and described second

Select transistor and described second to select transistor to cut apart described first extrinsic region by described first.

2. memory according to claim 1 is characterized in that:

The two adjacent described word lines that are provided with along described first extrinsic region of having cut apart are connected with described second grid electrode through described first grid electrode respectively.

3. memory according to claim 1 is characterized in that:

Described first extrinsic region and described second extrinsic region be by making described first grid electrode and described second grid electrode as mask, and ion injects and forms on semiconductor substrate.

4. memory according to claim 1 is characterized in that:

Described first select transistorized form the above first extrinsic region of zone at least with the part of described first grid electrode crossing near the zone and described second extrinsic region at least with the part of described first grid electrode crossing near the zone, overlook and see, extending ground on the direction that the bearing of trend of the above first extrinsic region of formation zone of the described relatively memory cell in edge tilts disposes

Described second select transistorized form the above first extrinsic region of zone at least with the part of described second grid electrode crossing near the zone and described second extrinsic region at least with the part of described second grid electrode crossing near the zone, overlook and see, extend ground on the direction that the bearing of trend of the above first extrinsic region of formation zone of the described relatively memory cell in edge tilts and dispose.

5. memory according to claim 4 is characterized in that:

Described first select transistorized form the above first extrinsic region of zone at least with the part of described first grid electrode crossing near the zone and described second extrinsic region at least with the part of described first grid electrode crossing near the zone, overlook and see, have 40 ° with bearing of trend along the above first extrinsic region of the formation of described memory cell zone disposes with lower angle ground with extending on tilted direction

Described second select transistorized form the above first extrinsic region of zone at least with the part of described second grid electrode crossing near the zone and described second extrinsic region at least with the part of described second grid electrode crossing near the zone, overlook and see, have 40 ° with bearing of trend dispose with on tilted direction, extending with lower angle ground along the above first extrinsic region of the formation of described memory cell zone.

6. memory according to claim 4 is characterized in that:

Described first select transistorized form the above first extrinsic region of zone at least with the part of described first grid electrode crossing near the zone and described second extrinsic region at least with the part of described first grid electrode crossing near the zone, overlook and see, on the opposite incline direction of the incline direction of described relatively first grid electrode extension, extend the ground configuration

Described second select transistorized form the above first extrinsic region of zone at least with the part of described second grid electrode crossing near the zone and described second extrinsic region at least with the part of described second grid electrode crossing near the zone, overlook and see, on the opposite incline direction of the incline direction of described relatively second grid electrode extension, extend the ground configuration.

7. memory according to claim 4 is characterized in that:

Adjacent described first grid electrode is connected by connecting portion with described second grid electrode,

Described connecting portion oppose the end limit of opposing a side with described word line of the above first extrinsic region of formation zone of the end limit of a side and described memory cell to be configured on the same line with described second extrinsic region,

Described second extrinsic region oppose the end limit of opposing a side with described first extrinsic region of the above word line of formation zone of the end limit of a side and described memory cell to be configured on the same line with described connecting portion.

8. memory according to claim 7 is characterized in that:

Dispose described first grid electrode, described connecting portion and described second grid electrode, make it to overlook and see, have the U word shape,

Dispose described first and select the transistor and described second described first extrinsic region and described second extrinsic region of selecting on the transistorized formation zone, make it to overlook and see, have the contrary U font that the U font with described first grid electrode, described connecting portion and described second grid electrode intersects.

9. memory according to claim 1 is characterized in that:

Along the width on the direction of the bearing of trend quadrature of the above first extrinsic region of formation described word line and described memory cell zone that described first extrinsic region is provided with, all littler than the width near the direction of the central portion of width near the direction of the central portion of described first grid electrode and bearing of trend quadrature described first grid electrode and described second grid electrode and bearing of trend quadrature described second grid electrode.

10. memory according to claim 1 is characterized in that:

Width on the direction of the connecting portion of described first grid electrode and described word line and bearing of trend quadrature described first grid electrode, littler than the width near the direction of the central portion of described first grid electrode and bearing of trend quadrature described first grid electrode

Width on the direction of the connecting portion of described second grid electrode and described word line and bearing of trend quadrature described second grid electrode is littler than the width near the direction of the central portion of described second grid electrode and bearing of trend quadrature described second grid electrode.

11. memory according to claim 10 is characterized in that:

Two relative limits of described first grid electrode comprise, overlook and see, have the part of first angle with the bearing of trend of the above first extrinsic region of the formation of described memory cell zone and have the part of second angle littler than described first angle,

Two relative limits of described second grid electrode comprise, overlook and see, have the part of described first angle with the bearing of trend of the above first extrinsic region of the formation of described memory cell zone and have the part of described second angle littler than described first angle.

12. memory according to claim 1 is characterized in that:

Described a plurality of memory cell contains a diode respectively,

First extrinsic region of described first conductivity type plays an electrode of sharing of the diode of described a plurality of memory cells.

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