CN100570701C - A kind of image scaling device, method and image display - Google Patents
A kind of image scaling device, method and image display Download PDFInfo
- Publication number
- CN100570701C CN100570701C CNB2007101247016A CN200710124701A CN100570701C CN 100570701 C CN100570701 C CN 100570701C CN B2007101247016 A CNB2007101247016 A CN B2007101247016A CN 200710124701 A CN200710124701 A CN 200710124701A CN 100570701 C CN100570701 C CN 100570701C
- Authority
- CN
- China
- Prior art keywords
- row cache
- channel controller
- data channel
- data
- cache device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000000034 method Methods 0.000 title claims abstract description 11
- 238000013500 data storage Methods 0.000 claims abstract description 16
- 239000000872 buffer Substances 0.000 claims description 42
- 230000015654 memory Effects 0.000 claims description 18
- 238000012545 processing Methods 0.000 claims description 8
- 238000000151 deposition Methods 0.000 claims description 6
- 239000003086 colorant Substances 0.000 abstract description 4
- 238000006243 chemical reaction Methods 0.000 abstract description 3
- DNTFEAHNXKUSKQ-RFZPGFLSSA-N (1r,2r)-2-aminocyclopentane-1-sulfonic acid Chemical compound N[C@@H]1CCC[C@H]1S(O)(=O)=O DNTFEAHNXKUSKQ-RFZPGFLSSA-N 0.000 description 6
- 230000000694 effects Effects 0.000 description 3
- 230000004075 alteration Effects 0.000 description 2
- 230000003111 delayed effect Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000009977 dual effect Effects 0.000 description 1
- 238000001914 filtration Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Images
Landscapes
- Controls And Circuits For Display Device (AREA)
- Image Processing (AREA)
Abstract
The present invention is applicable to that image shows the field, a kind of image scaling device, method and apparatus are provided, described image scaling device comprises vertically scale unit and horizontal scaling unit, described vertically scale unit comprises respectively the data channel controller corresponding with Y, U, three groups of data of V, at least two row cache devices, interpolation arithmetic device, and described vertically scale unit further comprises: configurable row cache device; And configurable row cache device controller, its according to the image pixel data storage mode be provided with described configurable row cache device as the row cache device corresponding with Y data channel controller or with U, row cache device that V data channel controller is corresponding.The present invention is by the use of configurable row cache device, the row cache device structure that can realize under the different colours deposit data pattern each data channel in the vertical unit for scaling symmetry and asymmetric between flexible conversion, thereby under the situation that does not increase hardware cost, eliminated the nonsynchronous problem of each communication channel delay.
Description
Technical field
The invention belongs to image and show the field, relate in particular to a kind of image scaling device, method and image display.
Background technology
The embedded image display device, for example the video playback of computer system, graphic presentation are the extensive and rising directions of current application.Because the size of original image or video is inconsistent with the display resolution of the actual display that uses, how to realize that image zoom just becomes a major issue in the computing machine demonstration.
Image zoom relates to the problem of two-dimentional convergent-divergent, usually way is for successively carrying out the convergent-divergent of two one dimensions on vertical direction and horizontal direction, during vertically scale, because view data all is based on the horizontal scanning mode, have the time-delay of data line in the image up and down in time, therefore when carrying out multitap interpolation arithmetic, correspondingly use some row cache devices that data are carried out buffer memory; During horizontal scaling, have only the time-delay of a clock in time, only need to use several simple registers to carry out buffer memory and get final product with each pixel in the delegation, wherein, vertically, horizontal scaling is separate, can take identical or different interpolation algorithm.
The color space that image shows in the digital and electronic field mainly contains two kinds, promptly according to the red (Red of three primary colours, R), green (Green, G), blue (Blue, B) principle that adds photosystem is described the rgb color space of color and according to the YUV color space of brightness, aberration principles illustrated color, wherein, and the monochrome information of Y component representative image, U and V represent aberration, generally are red and blue relative values.The location mode of yuv data in internal memory mainly contains the YUV piecemeal and deposits and interlock and deposit dual mode, and the RGB data then are generally 565 and 888 two kind of location mode.In the YUV color space, because human eye is the most responsive to the brightness Y-signal, consider image zoom is handled, only to need Y-signal is carried out the complicated filtering interpolation of high tap from aspects such as costs, and U, V signal are adopted the comparatively simply method of bilinear interpolation, promptly the YUV passage is adopted asymmetric structure, be enough to produce gratifying effect.This Y passage and U, when the asymmetry of V passage has determined to carry out vertically scale at Y passage and U, the V passage uses the number difference of row cache device, the Y channel operation of 4 taps for example, the U of 2 taps, the V channel operation, in YUV piecemeal storage mode, because yuv data independently leaves in 3 sections spaces of internal memory, read yuv data with the internal memory pattern of setting out, and three groups of data of YUV can independently be carried out, the influence that not delayed time by the other side each other, but for the staggered storage mode of the YUV of deposit data in the same space section of internal memory, but there is the nonsynchronous problem of each passage, for example when image is exported the 1st row, the Y component is buffer memory the 1st, 2,3 line data also read in the 4th row, to carry out the interpolation arithmetic of 4 taps, and this moment U, V buffer memory the 1st goes and need read in the 2nd row, to carry out the interpolation arithmetic of 2 taps, but since the staggered data of depositing of YUV internal memory set out read in the same time can only read the YUV of the 2nd row or the YUV of the 4th row, and can not read the Y of the 4th row and the U of the 2nd row simultaneously, V, therefore can only read the YUV of an order 2 row, abandon the Y component, obtain the U of the 2nd row, V, read the YUV of an order 4 row again, abandon U, the V component obtains the 4th row Y component, and internal storage access efficient can reduce by half in this case, the efficient of image zoom is lower, the Y passage compares U, the V passage will be delayed time to some extent, if to U, the V passage adopts and the same number of row cache device of Y passage, promptly adopts symmetrical structure, can solve the problem of time-delay, but cost increases to some extent again.
In a word, present image scaling device is not taken into account the problem of cost and image output time-delay simultaneously, adopt dissymmetrical structure to reduce the cost, but internal storage access efficient is low excessively when handling YUV intercrossed data form, the employing symmetrical structure, can guarantee the internal storage access efficient of YUV piecemeal or stagger scheme, but hardware cost raises.
Summary of the invention
The purpose of the embodiment of the invention is to provide a kind of image scaling device, is intended to solve the problem that present image scaling device is not taken into account cost and image output time-delay simultaneously.
The embodiment of the invention is to realize like this, a kind of image scaling device, comprise vertically scale unit and horizontal scaling unit, described vertically scale unit comprises a data channel controller corresponding with the Y data, at least two row cache devices, an interpolation arithmetic device, a data channel controller corresponding, at least two row cache devices, an interpolation arithmetic device with the U data, a data channel controller corresponding, at least two row cache devices, an interpolation arithmetic device with the V data, described vertically scale unit further comprises:
A configurable row cache device is used for carrying out the Y metadata cache according to the control of described Y data channel controller, or carries out U, V metadata cache according to the control of U, V data channel controller; And
A configurable row cache device controller, its according to the image pixel data storage mode be provided with described configurable row cache device as the row cache device corresponding with Y data channel controller or with U, row cache device that V data channel controller is corresponding.
Another purpose of the embodiment of the invention is to provide a kind of image-scaling method, said method comprising the steps of:
According to the yuv data storage mode control that configurable row cache device is accepted corresponding data channel controller is set;
Y, U, V data are read to respectively in the row cache device corresponding with each data channel controller;
Respectively Y, U, V data are carried out vertically scale;
Respectively Y, U, V data are carried out horizontal scaling.
Another purpose of the embodiment of the invention is to provide a kind of image display, comprise central processing unit, image scaling device, internal memory, display, described image scaling device comprises vertically scale unit and horizontal scaling unit, described vertically scale unit comprises a data channel controller corresponding with the Y data, at least two row cache devices, an interpolation arithmetic device, a data channel controller corresponding with the U data, at least two row cache devices, an interpolation arithmetic device, a data channel controller corresponding with the V data, at least two row cache devices, an interpolation arithmetic device, described vertically scale unit further comprises:
A configurable row cache device is used for carrying out the Y metadata cache according to the control of described Y data channel controller, or carries out U, V metadata cache according to the control of U, V data channel controller; And
A configurable row cache device controller, be used for according to the image pixel data storage mode be provided with described configurable row cache device as the row cache device corresponding with Y data channel controller or with U, row cache device that V data channel controller is corresponding.
The embodiment of the invention is by the use of configurable row cache device, realize under the different colours deposit data pattern row cache device structural symmetry and the asymmetric flexible conversion of each data channel in the vertical unit for scaling, thereby eliminated the zooming effect and the asynchronous problem that can not take into account simultaneously of delaying time under the YUV storage mode under the situation that does not increase hardware cost.
Description of drawings
Fig. 1 is image display that the embodiment of the invention the is suitable for structure principle chart between each modular unit when carrying out image zoom;
Fig. 2 is original graph picture point and a target image point location diagram when carrying out the one dimension convergent-divergent;
Fig. 3 is the structure principle chart of vertically scale unit in the image scaling device that provides of the embodiment of the invention;
Fig. 4 is the structure principle chart of the configurable row cache device of vertically scale unit in the image scaling device that provides of the embodiment of the invention when being the Y channel arrangement;
Fig. 5 is the structure principle chart of the configurable row cache device of vertically scale unit in the image scaling device that provides of the embodiment of the invention when being the UV channel arrangement;
Fig. 6 is the realization flow figure of the image-scaling method that provides of the embodiment of the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
In the embodiment of the invention,, under YUV piecemeal storage mode, configurable row cache device is distributed to the Y passage use, realized the asymmetric hardware configuration of YUV by adopting configurable row cache device when the vertically scale; Under the staggered storage mode of YUV, the row cache device is distributed to U, the use of V passage, realized the symmetrical structure of YUV, eliminated the nonsynchronous phenomenon of time-delay.
Structure principle chart when Fig. 1 carries out image zoom for image display between each modular unit for convenience of description, only shows the part relevant with the embodiment of the invention.With reference to Fig. 1, leave in the internal memory through video or view data behind central processing unit or other hardware accelerator decompress(ion)s, its location mode can be with the piecemeal of yuv format or staggered depositing, central processing unit carries out amplification coefficient by system bus to image scaling device, after coefficients such as display size are provided with, starting image scaling device brings into operation, image scaling device sends the read-write operation instruction by system bus or independent bus line to Memory Controller Hub, from internal memory, read yuv data, and after handle through image zoom inside, export display to and shown, wherein comprise vertically scale unit and horizontal scaling unit in the image scaling device, each unit for scaling includes 3 passages, and the convergent-divergent of three signals of corresponding YUV is handled.
Image zoom is divided into the convergent-divergent of vertical direction and two one dimensions of horizontal direction, before image one dimension convergent-divergent carries out interpolation arithmetic, at first try to achieve the position of target pixel points with respect to the original image vegetarian refreshments.If each pixel is spaced apart 1 in the original image, the requirement scaling is N, be that target figure/original graph is N, the position of each pixel is N among the target figure so, as shown in Figure 2, when carrying out horizontal scaling, if scaling is 4/3, then the pixel among the target figure is spaced apart 4/3, wherein the pixel in target figure, near in the corresponding original graph point is called its point of proximity, and the value of target pixel points is calculated by the point of proximity weighted sum, among Fig. 2, concerning target pixel points q1, its nearest point of proximity is p1, p2, inferior near point of proximity is p0, p3, the point of proximity of target pixel points is then for closing on the pixel in the row accordingly in the original graph when carrying out vertically scale.Can use the point of proximity of any amount to carry out computing during interpolation arithmetic, the quantity of point of proximity is called tap number, if be called 2 taps with 2 point processings, 3 point processings are called 3 taps, and the rest may be inferred, and tap number is high more, and interpolation is made an appointment, and principle is not this auspicious stating.
In the YUV color space, relative U, V signal, because human eye is more responsive to the Y-signal of representing monochrome information, therefore consider the interpolation arithmetic that Y-signal is carried out as far as possible higher tap in addition in synchronous taking into account Y, U, V triple channel, below content described with the structural principle of vertically scale unit in 4 taps, 3 taps, the 2 taps image scaling device that to be example provide the embodiment of the invention.
Please refer to Fig. 3, under YUV piecemeal storage mode, because Y, U, three passages of V can be not asymmetric and asynchronous because of structure, the situation of in the embodiment of the invention YUV piecemeal being deposited adopts 4 row cache devices of Y passage, the structure of U, 2 row cache devices of V passage, at this moment, configurable row cache device is accepted the control of Y channel controller, row cache device 4 as the Y passage uses, Y passage and then realized the interpolation arithmetic of 4 taps, and U, V passage are the bilinear interpolation of 2 taps.Under the staggered storage mode of YUV, configurable row cache device is accepted the control of U, V channel controller, row cache device 3 as U, V passage uses, at this moment, Y passage and U, V passage are all 3 row cache devices, realized the interpolation arithmetic of 3 taps of symmetry, frame of broken lines is partly represented the interpolation arithmetic device of Y-signal, U signal and V signal among Fig. 3.
Configurable row cache device in the vertically scale unit that the embodiment of the invention provides by two independently the hemistich buffer form, can adopt the less buffers of two spatial caches to realize during specific implementation.In conjunction with Fig. 1, Fig. 3, Fig. 4 and Fig. 5, when the suitable color space of image display is YUV piecemeal storage mode, central processing unit sends and the corresponding signal of piecemeal storage mode to configurable row cache device controller by system bus, configurable row cache device controller is the Y channel arrangement according to the configurable row cache device of signal triggering that receives, at this moment, the row cache number of Y, U, three passages of V is respectively 4,2,2 in the whole vertically scale unit.The Y channel controller after calculating current output row position to hemistich buffer 1 and hemistich buffer 2 OPADD control signals, in the embodiment of the invention, most significant digit (Most Significant Bit with address control signal, MSB) drive signal as hemistich buffer 1 inputs to its enable port EN1, the inversion signal of MSB inputs to its enable port EN2 as the drive signal of hemistich buffer 2, and all the other address signals as hemistich buffer 1 and hemistich buffer 2 of control signal, input to address port Address1 and Address2 respectively, the Y data that read from internal memory input to two hemistich buffers by input port Dat in1 and Dat in2 respectively, and the output data of two hemistich buffers respectively behind output port Dat out 1 and Dat out 2 to Y data output gate, this gate is by the MSB control of address signal, on the Y passage, just can realize having only one group of input and output, the alternation of two hemistich buffer memorys, for example when height half address is read and write, hemistich buffer 1 is enabled, hemistich buffer 2 is closed, this moment, double row cache device 1 operated, when low half address is read and write, situation is then opposite fully, and only double row cache device 2 operated.After each two row cache device reading of data of 4 row cache devices of Y passage and U, V passage finish, export Y-signal and U to, V signal interpolation arithmetic device carries out vertically scale, export the horizontal scaling unit after computing is finished to and carry out horizontal scaling.
When the color space that is suitable for when image display is the staggered storage mode of YUV, central processing unit sends and the corresponding signal of storage mode that interlocks to configurable row cache device controller by system bus, configurable row cache device controller is U according to the configurable row cache device of signal triggering that receives, the V channel arrangement, at this moment, Y in the whole vertically scale unit, U, the row cache number of three passages of V is 3, because yuv data only has the structure of 4:2:2 under the staggered storage mode, therefore the data of 2 row U or V can be deposited in the space of the Y of delegation row cache device, with hemistich buffer 1 and hemistich buffer 2 respectively as U, the row cache device 3 of V passage, as shown in Figure 5, two hemistich buffers are enabled simultaneously, import U data and V data respectively, two hemistich buffers are worked simultaneously, wherein, enable signal can be by U, the V channel controller provides, and the address port of two hemistich buffers is connected with address wire simultaneously.After each 3 row cache device reading of data of Y, U, V passage finish, export Y-signal and U to, V signal interpolation arithmetic device carries out vertically scale, export the horizontal scaling unit after computing is finished to and carry out horizontal scaling.
Should be appreciated that above content is that example is described the vertically scale unit that the embodiment of the invention provides with 4 taps, 3 taps, 2 taps only, the interpolation algorithm of other number of taps of flexible Application according to circumstances when specifically implementing.
Because when in the horizontal scaling unit, carrying out interpolation arithmetic, neighbor pixel has only the time-delay of 1 clock in time, even Y, U, V passage are adopted the interpolation arithmetic of different tap number, also only have several some time-delays between each passage, can be by inserting several registers with compensation delay, and register cost with respect to the row cache device is much lower, specifically repeats no more.
Fig. 6 shows the realization flow of the image-scaling method that the embodiment of the invention provides, and details are as follows:
In step S601, the control that configurable row cache device is accepted corresponding data channel controller is set according to the yuv data storage mode.
The configurable row cache device that the embodiment of the invention provides by two independently the hemistich buffer form, can adopt two less buffers of spatial cache to realize during specific implementation, when the yuv data storage mode is that piecemeal is when depositing, configurable row cache device is accepted the control of Y data channel controller, row cache device as the Y data channel uses the alternation of two hemistich buffer memorys; And when the yuv data storage mode was deposited for interlocking, configurable row cache device was accepted the control of U, V channel controller, and as the row cache device use of U, V data channel, two hemistich buffers are worked simultaneously.
In step S602, with Y, U, V data read to the row cache device corresponding with each data channel controller.
When configurable row cache device is accepted the control of Y data channel controller, the row cache device of Y data channel controller correspondence also comprises this configurable row cache device, in like manner, when configurable row cache device is accepted the control of U, V data channel controller, the row cache device of U, V data channel controller correspondence also comprises this configurable row cache device, reads Y, U from internal memory, the V data can adopt the pattern of setting out.
In step S603, respectively Y, U, V data are carried out interpolation arithmetic and finish vertically scale.
After each bar row cache device reading of data of Y, U, three passages of V finishes, respectively three groups of data are carried out interpolation arithmetic.
In step S604, respectively Y, U, V data are carried out horizontal scaling.
Further Y, U, V data are carried out horizontal scaling, specifically repeat no more.
The embodiment of the invention is by the use of configurable row cache device, realize under the different colours deposit data pattern structural symmetry and asymmetric flexible conversion in the vertical unit for scaling, thereby eliminated the zooming effect and the asynchronous problem that can not take into account simultaneously of delaying time under the YUV storage mode under the situation that does not increase hardware cost.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (7)
1, a kind of image scaling device, comprise vertically scale unit and horizontal scaling unit, described vertically scale unit comprises a data channel controller corresponding with the Y data, at least two row cache devices, an interpolation arithmetic device, a data channel controller corresponding, at least two row cache devices, an interpolation arithmetic device with the U data, a data channel controller corresponding, at least two row cache devices, an interpolation arithmetic device with the V data, it is characterized in that described vertically scale unit further comprises:
A configurable row cache device is used for carrying out the Y metadata cache according to the control of Y data channel controller, or carries out U, V metadata cache according to the control of U, V data channel controller; And
A configurable row cache device controller, be used for according to the image pixel data storage mode be provided with described configurable row cache device as the row cache device corresponding with Y data channel controller or with U, row cache device that V data channel controller is corresponding;
When described image pixel data storage mode is a piecemeal when depositing, configurable row cache device is accepted the control of Y data channel controller; When described image pixel data storage mode was deposited for interlocking, configurable row cache device was accepted the control of U, V channel controller.
2, image scaling device as claimed in claim 1 is characterized in that, described configurable row cache device further comprises the first hemistich buffer and the second hemistich buffer;
The described first hemistich buffer and the described second hemistich buffer Y metadata cache that hockets during as the row cache device corresponding with Y data channel controller;
The described first hemistich buffer and the described second hemistich buffer carry out U metadata cache and V metadata cache during as the row cache device corresponding with U, V data channel controller simultaneously.
3, image scaling device as claimed in claim 2 is characterized in that, when described first hemistich buffer and the described second hemistich buffer hocket metadata cache, is enabled to drive by the most significant digit of address control signal and the inversion signal of most significant digit respectively.
4, a kind of image-scaling method is characterized in that, said method comprising the steps of:
According to the yuv data storage mode control that configurable row cache device is accepted corresponding data channel controller is set;
When described yuv data storage mode is a piecemeal when depositing, configurable row cache device is accepted the control of Y data channel controller; When described yuv data storage mode was deposited for interlocking, configurable row cache device was accepted the control of U, V channel controller;
Y, U, V data are read to respectively in the row cache device corresponding with each data channel controller;
Respectively Y, U, V data are carried out vertically scale;
Respectively Y, U, V data are carried out horizontal scaling.
5, a kind of image display, comprise central processing unit, image scaling device, internal memory, display, described image scaling device comprises vertically scale unit and horizontal scaling unit, described vertically scale unit comprises a data channel controller corresponding with the Y data, at least two row cache devices, an interpolation arithmetic device, a data channel controller corresponding with the U data, at least two row cache devices, an interpolation arithmetic device, a data channel controller corresponding with the V data, at least two row cache devices, an interpolation arithmetic device, it is characterized in that described vertically scale unit further comprises:
A configurable row cache device is used for carrying out the Y metadata cache according to the control of Y data channel controller, or carries out U, V metadata cache according to the control of U, V data channel controller; And
A configurable row cache device controller, be used for according to the image pixel data storage mode be provided with described configurable row cache device as the row cache device corresponding with Y data channel controller or with U, row cache device that V data channel controller is corresponding;
When described image pixel data storage mode is a piecemeal when depositing, configurable row cache device is accepted the control of Y data channel controller; When described image pixel data storage mode was deposited for interlocking, configurable row cache device was accepted the control of U, V channel controller.
6, image display as claimed in claim 5 is characterized in that, described configurable row cache device further comprises the first hemistich buffer and the second hemistich buffer;
The described first hemistich buffer and the described second hemistich buffer Y metadata cache that hockets during as the row cache device corresponding with Y data channel controller;
The described first hemistich buffer and the described second hemistich buffer carry out U metadata cache and V metadata cache during as the row cache device corresponding with U, V data channel controller simultaneously.
7, image display as claimed in claim 6 is characterized in that, when described first hemistich buffer and the described second hemistich buffer hocket metadata cache, is enabled to drive by the most significant digit of address control signal and the inversion signal of most significant digit respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101247016A CN100570701C (en) | 2007-11-16 | 2007-11-16 | A kind of image scaling device, method and image display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007101247016A CN100570701C (en) | 2007-11-16 | 2007-11-16 | A kind of image scaling device, method and image display |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101183521A CN101183521A (en) | 2008-05-21 |
| CN100570701C true CN100570701C (en) | 2009-12-16 |
Family
ID=39448771
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2007101247016A Expired - Fee Related CN100570701C (en) | 2007-11-16 | 2007-11-16 | A kind of image scaling device, method and image display |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100570701C (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101727655B (en) * | 2008-10-16 | 2011-11-16 | 展讯通信（上海）有限公司 | Image zooming method and device thereof |
| CN101742081B (en) * | 2009-12-11 | 2012-11-21 | 华亚微电子（上海）有限公司 | Image stabilizer |
| CN102088614A (en) * | 2010-11-23 | 2011-06-08 | 北京邮电大学 | Method and device for magnifying video image |
| US8687922B2 (en) * | 2012-02-24 | 2014-04-01 | Apple Inc. | Parallel scaler processing |
| CN104036754B (en) * | 2013-03-04 | 2016-02-10 | 澜起科技（上海）有限公司 | Share two scaler systems of row cache |
| CN105118424B (en) * | 2014-12-05 | 2017-12-08 | 京东方科技集团股份有限公司 | Data transmission module and method, display panel and driving method, display device |
| CN107680028B (en) | 2016-08-01 | 2020-04-21 | 北京百度网讯科技有限公司 | Processor and method for scaling an image |
| CN109587500B (en) * | 2018-11-26 | 2021-01-01 | 中国航空工业集团公司洛阳电光设备研究所 | FPGA-based dynamically reconfigurable video scaler |
| CN111325804B (en) * | 2018-12-14 | 2023-11-03 | 中移（杭州）信息技术有限公司 | Method and device for determining YUV image display parameters |
| CN111105356B (en) * | 2019-12-26 | 2023-06-02 | Tcl华星光电技术有限公司 | Image processing method, device and computer readable storage medium |
-
2007
- 2007-11-16 CN CNB2007101247016A patent/CN100570701C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101183521A (en) | 2008-05-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN100570701C (en) | A kind of image scaling device, method and image display | |
| CN107633795B (en) | The driving method of display device and display panel | |
| JP4971442B2 (en) | Image processing apparatus and method for pixel data conversion | |
| CN101527134A (en) | Display method, display controller and display terminal | |
| CN106293578A (en) | Video card, image display device, method for displaying image and system | |
| CN101621704A (en) | Color enhancement for graphic images | |
| JPH04204496A (en) | Display control device | |
| JPH1141604A (en) | Block matching arithmetic unit and recording medium storing program and read by machine | |
| US20070041662A1 (en) | Efficient scaling of image data | |
| CN112188262A (en) | Image processing method, device and system and computer readable medium | |
| CN102253818A (en) | Background picture display method and device | |
| CN101854491B (en) | Sample band amplification and self-adaptive template combined image downsampling method | |
| US20030043159A1 (en) | Graphics resampling system and method for use thereof | |
| CN102572207A (en) | Color space transformation method suitable for joint photographic experts group (JPEG) image | |
| US8938133B2 (en) | Image resizing apparatus and method that interpolates image blocks with abuttal regions | |
| JPH07262367A (en) | Apparatus and method for processing of digital image signal | |
| Gribbon et al. | Using design patterns to overcome image processing constraints on FPGAs | |
| CN102651120B (en) | Memory access method for image processing and image processing device | |
| CN103106395A (en) | Geometry normalization kernel device of license plate character real-time recognition system | |
| CN106780291A (en) | A kind of distortion in real time image procossing accelerator | |
| CN102427537A (en) | Video image space scale transformation system and method thereof | |
| US6356656B1 (en) | Contour-information extraction apparatus and method | |
| KR20040082601A (en) | Memory access control apparatus | |
| JP3553376B2 (en) | Parallel image processor | |
| CN102129667A (en) | Image scaling method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP02 | Change in the address of a patent holder |
Address after: 519085 hi tech Zone, Guangdong, Zhuhai science and Technology Innovation Coast Road, No. four, No. 1 Patentee after: Juli Integrated Circuit Design Co., Ltd. Address before: 519085 No. 1, unit 15, building 1, 1 Da Ha Road, Tang Wan Town, Guangdong, Zhuhai Patentee before: Juli Integrated Circuit Design Co., Ltd. |
|
| TR01 | Transfer of patent right | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20170612 Address after: 519085 C District, 1# workshop, No. 1, science and technology No. four road, hi tech Zone, Zhuhai, Guangdong, China Patentee after: ACTIONS (ZHUHAI) TECHNOLOGY Co.,Ltd. Address before: 519085 hi tech Zone, Guangdong, Zhuhai science and Technology Innovation Coast Road, No. four, No. 1 Patentee before: Juli Integrated Circuit Design Co., Ltd. |
|
| CP01 | Change in the name or title of a patent holder | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 519085 High-tech Zone, Tangjiawan Town, Zhuhai City, Guangdong Province Patentee after: ACTIONS TECHNOLOGY Co.,Ltd. Address before: 519085 High-tech Zone, Tangjiawan Town, Zhuhai City, Guangdong Province Patentee before: ACTIONS (ZHUHAI) TECHNOLOGY Co.,Ltd. |
|
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091216 Termination date: 20201116 |