CN100566182C - The accelerated message passing decoder of adapted for decoding LDPC code signal and method - Google Patents

Abstract

The invention discloses AMP (the quickening the message transmission) decoder of a kind of decoding LDPC (low-density checksum) code signal.The present invention proposes new coding/decoding method, can to ldpc coded signal carry out more effective, decode faster and have lower computation complexity.The soft bit information that produces during the high straton square formation of decoding LDPC sign indicating number parity matrix is used to other sub-square formation of following each layer decoded.Described method allow to the row weights of parity matrix greater than 1 the LDPC sign indicating number of (for example 2 or bigger) decode, thereby can in different communication systems, select widely employed LDPC sign indicating number.The present invention also improves the BER/LBER as the function of Eb/No, this method provides very big improvement in performance simultaneously, and can obtain the roughly quite performance index of (or better) when comparing the decoding iteration of carrying out much less (as 50%) with other coding/decoding method.

Description

The accelerated message passing decoder of adapted for decoding LDPC code signal and method

Technical field

The present invention relates to communication system, more specifically, the present invention relates to the signal decoding in the communication system.

Background technology

Data communication system is constantly development always for many years.What this type of communication system received publicity near-mid term very much is a kind of communication system that adopts the iteration error correcting code.Wherein be subjected to special concern with the communication system that adopts LDPC (low-density checksum) sign indicating number again.Under given signal to noise ratio (snr) situation, use the communication system of iterative code can obtain the lower error rate (BER) than the communication system of using alternate code usually.

This area always developing direction before this is and ceaselessly attempts reducing in the communication system for reaching the SNR demand of given BER.Desirable target is the shannon limit that reaches channel (Shannon ' s limit).Shannon limit can be regarded as the data transmission rate in the channel that is applied to have specific SNR (signal to noise ratio), can realize error free transmission by this channel.In other words, shannon limit is the theoretical limit of given modulation and encoding rate lower channel capacity.

The LDPC sign indicating number relates to multiple mode often.For example, the soft decoding of the iteration of LDPC sign indicating number can realize by a lot of modes, comprises based on BP (Belief Propagation, confidence spread) algorithm, SP (Sum-Product and long-pending) algorithm and MP (Message-Passing, message transmission) algorithm; The MP algorithm refers to the SP/BP unified algorithm sometimes.Although the LDPC sign indicating number to these types has carried out a large amount of concerns and effort, no matter adopt which kind of particular form (wherein above mentioning for 3 kinds: BP, SP, MP) of iterative decoding under specific circumstances, in communication equipment, finish the application of this decoding and handle in the room for improvement of old abundance still.For example, for realizing accurate decoding, must carry out multiple relevant complicated and loaded down with trivial details calculating, data management and processing to ldpc coded signal.

The LDPC sign indicating number can provide excellent decoding performance, can approach shannon limit in some cases.For example some LDPC decoder has shown the scope that can reach the theoretical shannon limit 0.3dB of distance (decibel).It is that 1,000,000 abnormal LDPC code realizes that this is the very promising application in communication system of LDPC sign indicating number that this example uses length.

Fig. 4 is the schematic diagram of MP of the prior art (message transmission) decoding function piece 400.In this example of the prior art, bit metric 410 be initialised and offer one or more bit-engine processors (bit-engine 421 as shown in FIG., bit-engine 422, bit-engine 423 ..., bit-engine 424).One or more bit-engine processor 421-424 use initialized bit metric 410 to upgrade a plurality of sidelines message (edge message) Medge relevant with a plurality of bit nodes _b, finish processing to bit node.

This has generated the sideline message Medge about a plurality of bit nodes that upgraded _bAfter this, these sideline message Medge that upgraded about a plurality of bit nodes _bBe transmitted and be stored in the sideline memory (edge memory) 430, subsequently use one or more verification engine processors (as verification engine 441, verification engine 442, verification engine 443 ..., verification engine 444) when carrying out code check node processing, it is suitably taken out in the sideline memory 430.One or more verification engine processor 441-444 use the sideline message Medge about a plurality of bit nodes of recent renewal _bRenewal is about a plurality of sideline message Medge of a plurality of check-nodes _c, to carry out code check node processing.Afterwards, these sideline message Medge that upgraded about a plurality of check-nodes _cBe provided and be stored in the sideline memory 430, subsequently can be with this sideline message Medge _cFrom sideline memory 430, suitably take out, be used to use one or more bit-engine processor 421-424 to carry out bit node and handle.

The common cooperation of one or more bit-engine processor 421-424 and one or more verification engine processor 441-444 is carried out iterative decoding and is handled, and comprises the sideline message Medge of renewal about a plurality of bit nodes _bAnd renewal is about the sideline message Medge of a plurality of check-nodes _cAfter the last decoding iteration, use a plurality of sideline message Medge about a plurality of bit nodes of recent renewal _bGenerate soft bit information (soft bit information), make hard decision according to this soft bit information subsequently, to carry out optimal estimation through LDPC information encoded position one or more.

In addition, other has the prior art of two kinds of known adapted for decoding LDPC code signal to carry out according to LMP (hierarchical message transmission) coding/decoding method.Below two pieces of lists of references the LMP coding/decoding method has been described.

[a]M.M.Mansour?and?N.R.Shanbhag，”High-throughput?LDPC?decoder”IEEE?Trans.Inform.Theory，Vol.11，no.6，pp.976-966，Dec.2003

[b]D.E.Hocevar，“A?reduced?complexity?decoder?architecture?via?layereddecoding?of?LDPC?codes”，Signal?Processing?Systems，2004，SIPS?2004，IEEEWorkshop?on?13-15?October?2004，pp.107-112.

Use the LMP coding/decoding method, the parity check matrix H of LDPC sign indicating number has following form:

H=[H ₁H ₂H _L] ^T(equation 1)

In this equation, each submatrix H _iHas identical line number.And, each submatrix H _iCan further be decomposed into following form:

H _i=[H _{I, 1}H _{I, 2}H _{I, M}] (equation 2)

In above-mentioned decomposition equation, can notice each submatrix H _{I, j}Or all elements of a p * p is the permutation matrix of the unit matrix of a matrix (being full null matrix) of 0 or a p * p.Although the coding/decoding method of above-mentioned two prior aries all can provide a kind of method that reduces total decoding iteration required (because of it adopts the hierarchical decoding method) number of times, these two existing coding/decoding methods all have tangible limitation, because they only are applicable to submatrix H _{I, j}It is the situation of the permutation matrix of a p * p unit matrix.

The use of ldpc coded signal constantly expands to many new applications.Such application is a digital video broadcasting.The digital video broadcasting project organization (DVB) is an industry association of being made up of jointly more than the 260 tame broadcaster, manufacturer, Virtual network operator, software developer, standardisation bodies and other unit that surpass 35 countries, for global standards are formulated in the whole world transmission of Digital Television and data, services.Public information about DVB can obtain from following network address:

http://www.dvb.org

DVB-S2 (being DVB-satellite the 2nd edition) draft standard also can openly obtain from this network address, and the Adobe PDF of current DVB-S2 draft standard can be from following website, download:

www.dvb.org/document//en302307.v1.1.1.draft.pdf

The present invention quotes in full the DVB-S2 draft standard---" Draft ETSI EN 302 307 V1.1.1 (2004-06), Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulation systems for Broadcasting, Interactive Services, News Gathering and other broadband satellite applications ", and with it as the disclosed part of the application.

In addition, " Draft ETSI EN 302 307 V1.1.1 (2004-06), Digital Video Broadcasting (DVB); Second generation framing structure, channel coding and modulationsystems for Broadcasting, Interactive Services, News Gathering and otherbroadband satellite applications " standard in March, 2005 by ETSI (ETSI) official approval.This standard is also quoted in full in this, as the disclosed part of the application.

In addition, DVB-S2 uses efficient FEC (forward error correction) system that combines based on sign indicating number and LDPC ISN outside the BCH (Bose-Chaudhuri-Hocquenghem).The result shows that it has only 0.7dB apart from shannon limit sometimes.The selection of FEC parameter depends on system requirements.Along with VCM (code-change and modulation) and ACM (adaptive coding and modulation), encoding rate can dynamic change on the basis of a frame frame.

The receiving equipment that comprises decoder is followed a plurality of operating parameters that the DVB-S2 standard must use and is clearly pointed out in the transmission system operating parameter is described.But, follow these operating parameters as long as comprise the receiving equipment of decoder by the DVB-S2 standard code, allow the very big degree of freedom on the executive mode.The signal of communication channel transmitting terminal generates and clearly points out in the DVB-S2 standard, and the executive mode that (at the receiving terminal of communication channel) handled in the reception of these signals is extensively open to the designer.Obviously, the constraint of key Design of this kind receiving equipment is to occupy relatively little space and to have relatively low complexity when very high performance is provided, to be applicable to these DVB-S2 signals.

Among DVB-S2 or other communication system, the demand of LDPC encoded signals (code signal that comprises other type equally) being carried out faster and more effective decoding constantly increases, so that multiple design constraint to be provided, to comprise service speed, lower computation complexity, reduce loaded down with trivial details storage administration and less relatively BER (error rate) under different SNR (signal to noise ratio).

In addition, (H has p * p submatrix H not use low-density parity check (LDPC) matrix H at present in the prior art _{I, j}, be a plurality of p * p displacement unit matrix sum) and carry out the method for hierarchical decoding.For example, p * p submatrix H _{I, j}When each row or each were shown more than one " 1 ", existing hierarchical decoding technology just can't be worked.

From prior art as can be known, many more to the constraint that makes up the LDPC sign indicating number, the performance of out-of-limit system LDPC sign indicating number.The hierarchical decoding method of prior art can only be handled p * p submatrix H _{I, j}Each row or each row have only the situation of " 1 ", and this has limited the selection to the LDPC sign indicating number that is adopted.When only being confined to the LDPC sign indicating number of this form, use prior art hierarchical decoding method, the designer can not design the LDPC sign indicating number with better performance more neatly.

Summary of the invention

According to an aspect of the present invention, provide AMP (the quickening the message transmission) decoder of a kind of decoding LDPC (low-density checksum) code signal, described decoder comprises:

Soft bit is new processor more, use is calculated second soft bit information corresponding to the second sub-square formation corresponding to first soft bit information of the first sub-square formation, wherein, row corresponding to the parity matrix that generates the employed generator matrix of ldpc coded signal comprise the described first sub-square formation and the described second sub-square formation;

The verification engine processor uses describedly corresponding to second soft bit information of the second sub-square formation and about the difference between the second sideline message of corresponding check node, upgrades the 3rd sideline message about the corresponding check node; Perhaps use describedly, upgrade the 3rd sideline message about the corresponding check node corresponding to second soft bit information of the second sub-square formation and about the difference between the first sideline message of corresponding check node.

Preferably, described soft bit more new processor uses described second soft bit information corresponding to the second sub-square formation to calculate the 3rd soft bit information corresponding to the 3rd sub-square formation, and described described row corresponding to the parity matrix that generates the employed generator matrix of ldpc coded signal also comprise the described the 3rd sub-square formation.

Preferably, each decodes respectively described decoder to the described first sub-square formation and the second sub-square formation.

Preferably, described soft bit more new processor and the collaborative work of described verification engine processor so that described ldpc coded signal is carried out the iteration error correction decoding, thereby generate best estimate at least one information bit that is coded into described ldpc coded signal.

Preferably, the weights that comprise the described row of the described first sub-square formation and the second sub-square formation are 1.

Preferably, described decoder further comprises:

The average information computing module, use described corresponding to the second sub-square formation second soft bit information and describedly calculate average information about the difference between the sideline message of corresponding check node.

Preferably, comprise that the weights of described row of the described first sub-square formation and the second sub-square formation are greater than 1.

Preferably, described soft bit more new processor use LLR (log-likelihood ratio) information corresponding to the bit of described second soft bit information, upgraded calculate described second soft bit information about the sideline message of corresponding check node with about at least one additional sideline message of corresponding check node corresponding to the second sub-square formation.

Preferably, described decoder further comprises:

The sideline memory upgrades processor communication with described soft bit and is connected, and described at least one additional sideline message about the corresponding check node is obtained from the memory of described sideline.

Preferably, described decoder decode is followed the ldpc coded signal of DVB-S2 (digital video broadcasting-satellite the 2nd edition) standard.

According to an aspect of the present invention, provide AMP (the quickening the message transmission) decoder of a kind of decoding LDPC (low-density checksum) code signal, described decoder comprises:

Soft bit is new processor more, use is calculated second soft bit information corresponding to the second sub-square formation corresponding to first soft bit information of the first sub-square formation, wherein, row corresponding to the parity matrix that generates the employed generator matrix of ldpc coded signal comprise the described first sub-square formation and the described second sub-square formation;

The first average information computing module uses about the sideline message of corresponding check node and describedly calculates first average information corresponding to the difference between second soft bit information of the second sub-square formation;

The second average information computing module, use described about the corresponding check node sideline message and described corresponding to the second sub-square formation second soft bit information and describedly calculate second average information corresponding to the difference between the first soft bit information sum of the two of the first sub-square formation;

The verification engine processor uses described first average information to upgrade described sideline message about the corresponding check node.

Preferably, described software upgrading processor uses described second average information and the described sideline message of having upgraded about the corresponding check node to calculate described second soft bit information corresponding to the second sub-square formation.

Preferably, described soft bit more new processor use described second soft bit information to calculate the 3rd soft bit information corresponding to the 3rd sub-square formation corresponding to the second sub-square formation;

Also comprise the described the 3rd sub-square formation corresponding to described row in order to the parity matrix of the generator matrix that generates described ldpc coded signal.

Preferably, each decodes respectively described decoder to the described first sub-square formation and the second sub-square formation.

Preferably, described soft bit more new processor and the collaborative work of described verification engine processor so that described ldpc coded signal is carried out the iteration error correction decoding, thereby generate best estimate at least one information bit that is coded into described ldpc coded signal.

According to an aspect of the present invention, provide the method for a kind of decoding LDPC (low-density checksum) code signal, described method comprises:

Use is calculated second soft bit information corresponding to the second sub-square formation corresponding to first soft bit information of the first sub-square formation, wherein, row corresponding to the parity matrix that generates the employed generator matrix of ldpc coded signal comprise the described first sub-square formation and the described second sub-square formation;

Use is about the sideline message of corresponding check node and describedly calculate first average information corresponding to the difference between second soft bit information of the second sub-square formation;

Use described first average information to upgrade described sideline message about the corresponding check node;

Described ldpc coded signal is carried out the iteration error correction decoding, thereby generate best estimate at least one information bit that is coded into described ldpc coded signal.

Preferably, described method further comprises:

Each is decoded respectively to the described first sub-square formation and the second sub-square formation.

Preferably, described method further comprises:

Use described about the corresponding check node sideline message and described corresponding to the second sub-square formation second soft bit information and describedly calculate second average information corresponding to the difference between the first soft bit information sum of the two of the first sub-square formation;

Use described second average information and the described sideline message of having upgraded to calculate described second soft bit information corresponding to the second sub-square formation about the corresponding check node.

Preferably, described method further comprises:

Use and describedly calculate average information corresponding to second soft bit information of the second sub-square formation and about the difference between the sideline message of corresponding check node;

Use described average information to upgrade described sideline message about the corresponding check node.

Other features and advantages of the present invention will illustrate in detailed description of the present invention in conjunction with the following drawings.

Description of drawings

The invention will be further described below in conjunction with drawings and Examples, in the accompanying drawing:

Fig. 1 is the schematic diagram of an embodiment of communication system;

Fig. 2 is the schematic diagram of an embodiment of communication system;

Fig. 3 is the bipartite graph of an embodiment of LDPC (low-density checksum) sign indicating number;

Fig. 4 is the schematic diagram of an embodiment of MP of the prior art (message transmission) decoding function piece;

Fig. 5 is that block size is 1248 bits and has the LDPC block bipartite graph that 624 check equations, ratio are parallel-block (parallel-block) LDPC sign indicating number of 1/2;

Fig. 6 is the schematic diagram of the permutation table in all sidelines in the LDPC block bipartite graph among Fig. 5;

Fig. 7 is the schematic diagram of the each several part of parity check matrix H.

Fig. 8 carries out decoding processing generates the current sub-square formation of parity check matrix H with the soft bit information of the last sub-square formation of using parity check matrix H the schematic diagram of soft bit information;

Fig. 9 is its submatrix H when the row weights of parity check matrix H equal 1 _{I, j}Schematic diagram that upgrade to handle of soft bit information;

Figure 10 is as the row weights of parity check matrix H its submatrix H greater than 1 time _{I, j}Schematic diagram that upgrade to handle of soft bit information;

Figure 11 is the submatrix H of parity check matrix H _{I, j}Soft bit upgrade the schematic diagram of another embodiment that handles;

Figure 12 is the performance comparison diagram of MP (message transmission) decoding processing and AMP (quickening the message transmission) decoding processing;

Figure 13 is the flow chart of an embodiment of the method for adapted for decoding LDPC code signal;

Figure 14 is the flow chart of an embodiment of the method for adapted for decoding LDPC code signal;

Figure 15 is the flow chart of an embodiment of the method for adapted for decoding LDPC code signal.

Embodiment

The present invention has introduced the equipment of ldpc coded signal being carried out decoding in conjunction with a plurality of embodiment.In some instances, coding/decoding method of the present invention and function can be to decoding according to the signal of SVB-S2 (being SVB-satellite the 2nd edition) standard generation and handling.

The target of digital communication system is from a position or but subsystem transmits the numerical data of inerrancy or acceptance error rate to another position or subsystem.As shown in Figure 1, data can be transmitted in various communication systems by various communication channels: magnetic media, wireless network, optical fiber, copper cash and other media.

Illustrated in figures 1 and 2 is to be respectively the schematic diagram of the embodiment of communication system 100 and 200.

Referring to Fig. 1, in the communication system 100, the communication equipment 110 (comprising reflector 112 with encoder 114 and the receiver 116 with decoder 118) that communication channel 199 will be positioned at communication channel 199 1 ends is connected with another communication equipment 120 that is positioned at communication channel 199 other ends (comprising reflector 126 with encoder 128 and the receiver 122 with decoder 124).In certain embodiments, communication equipment 110 and 120 all includes only a reflector or a receiver.Communication channel 199 can realize by several dissimilar media (for example: use satellite antenna 132 and 134 satellite communication channel 130, use communications tower 142 and 144 and/or the fiber optic communication channel 160 of local antenna 152 and 154 radio communication channel 140, electric wire communication system 150 and/or use electric light (E/O) interface 162 and photoelectricity (O/E) interface 164).In addition, can use to combine and form communication channel 199 more than a kind of media.

In order to reduce the undesired error of transmission that occurs in the communication system, adopt error correction and channel coding schemes through regular meeting.In general, these error corrections and channel coding schemes use encoder in emitter terminals, use decoder at receiver end.

Referring to communication system shown in Figure 2 200, transmitting terminal in communication channel 299, information bit 201 is provided for reflector 297, reflector 297 uses encoder with symbol mapper 220 (this symbol mapper can be considered different separately functional blocks 222 and 224) information bit 201 to be encoded, thereby generate centrifugal pump modulation symbol sequence 203 and offer emission driver 230, this emission driver 230 uses 232 rise times of digital to analog converter to transmit 204 continuously, and after using emission filter 234 to generate filtering the time transmit 205 continuously, the time transmits 205 abundant consistent with communication channel 299 continuously after this filtering.Receiving terminal in communication channel 299, time, continuous received signal 206 was provided for AFE (analog front end) 260, and this AFE (analog front end) 206 comprises receiving filter 262 (continuous received signal 207 of time after the generation filtering) and analog to digital converter 264 (generating discrete received signal 208).Tolerance maker 270 generates symbol tolerance 209, and these 209 pairs of described centrifugal pump modulation symbols of symbol tolerance of decoder 280 uses and the information bit that is encoded in are wherein made best estimation (210).

Communication equipment in the previous embodiment can use various decoding feature described herein to realize.In addition, ensuing several accompanying drawing is described (some embodiment will provide more detailed introduction) to other and the specific embodiment that is used to support to realize equipment, system, function to the decoding of ldpc coded signal and/or method.Before proposing introduction more specifically, earlier the LDPC sign indicating number is carried out general introduction.

Fig. 3 is the schematic diagram of an embodiment of LDPC sign indicating number 300.In the prior art, the LDPC bipartite graph is also referred to as Tan Natu (Tanner Graph) sometimes.The LDPC sign indicating number can be considered as having the code of binary parity check matrix, and like this, nearly all element value is 0 (for example: this binary parity check matrix is a sparse matrix) in this matrix.For example, H=(h _{I, j}) _{N * M}Can be counted as block length is the parity matrix of the LDPC sign indicating number of N.

In this parity matrix, 1 quantity can be expressed as d in the i row _v(i), 1 the quantity that j is capable can be expressed as d _c(j).If for all i, d _v(i)=d _v, and for all j, d _c(j)=d _c, this LDPC sign indicating number is called as (d so _v, d _c) regular LDPC sign indicating number, otherwise this LDPC sign indicating number is called abnormal LDPC code.

Provided introduction in the list of references [2] that list of references [1] that LDPC sign indicating number R.Gallager is below shown and M.Luby etc. are shown.

[1]R.Gallager，Low-Density?Parity-Check?Codes，Cambrridge，MA：MITPress，1963.

[2]M.Luby，M.Mitzenmacher，M.A.Shokrollahi，D.A.Spielman，and?V.Stemann，“Practical?Loss-Resilient?Codes”，Proc.29 ^th?Symp.on?Theory?ofComputing，1997，pp.150-159

Rule LDPC sign indicating number can be expressed as bipartite graph 300, the left node of its parity matrix is represented bits of coded (or " variable node " (or " bit node ") 310 decoded to ldpc coded signal with the method for bit decoding) variable, and the right side node is represented check equations (or check-node 320).Bipartite graph 300 by the LDPC sign indicating number of H definition can be defined by N variable node (for example N bit node) and M check-node.Each variable node in N variable node 310 has d _v(i) individual sideline (edge, label 330 is depicted as one of them example) is with bit node v _i312 link to each other with one or more check-nodes (M check-node in).Sideline 330 shown in the figure is with bit node v _i312 with check-node c _j322 connect.Sideline d _vQuantity (as d among the figure _vShown in 314) be called the degree (degree) of variable node i again.Approx, each check-node of M check-node 320 has just d _c(j) individual sideline (is expressed as d among the figure _c324) this node is connected with one or more variable nodes (or bit node) 310.The quantity d in this sideline _cThe degree that is called check-node j again.

At variable node v _i(or bit node b _i) 312 and check-node c _jSideline 330 between 322 may be defined as e=(i, j).But on the other hand, (i, j), the node in this sideline also can be represented as e=(v (e), c (e)) (perhaps e=(b (e), c (e)) for given sideline e=.Given variable node v _i(or bit node b _i), can define one group from node v _i(or bit node b _i) sideline of sending is that Ev (i)={ e|v (e)=i} (perhaps is E _b(i)={ e|b (e)=i}).Given check-node c _j, can define one group is E from the sideline that node cj sends _c(j)={ e|c (e)=j}.Therefore, derivation result is | E _v(i)=d _v| (or | E _b(i) |=d _b) and | E _c(j) |=d _c

As a rule, anyly can be characterized as graphic code by the node that bipartite graph is represented.It is also to be noted that abnormal LDPC code also can be described with bipartite graph.Yet the degree of each group node can be selected according to some distribution in abnormal LDPC code.Therefore, for two of an abnormal LDPC code different node v _I1And v _I2, | E _v(i ₁) | may be not equal to | E _v(i ₂) |.This relation is also set up for two check-nodes.The notion of abnormal LDPC code provides introduction by people such as M.Luby at first in list of references [2].

It is noted that coding/decoding method of the present invention both had been applicable to that regular LDPC sign indicating number also was applicable to abnormal LDPC code (as shown in Figure 5 and Figure 6).

The LLR of LDPC sign indicating number (log-likelihood ratio) coding/decoding method may be summarized as follows: to calculate actually has that to send the value that received a certain position in the vector at 1 o'clock be 1 probability.Similarly, the actual value that has transmission to receive a certain position in the vector at 0 o'clock of calculating is 0 probability.This probability can use the parity matrix of the LDPC sign indicating number of the parity that is used for this reception vector of verification to calculate.LLR is the logarithm of the ratio of these two probability that calculate.LLR has provided the tolerance of the communication channel of transmission signals to the position generation harmful effect degree in the vector.

The LLR decoding of LDPC sign indicating number can be described by following mathematical way:

If C={v|v=is (v ₀..., v _N-1) vH ^T=0} is a LDPC sign indicating number, and form is The transmission signal in one to receive vector be y=(y ₀..., y _N-1), then the tolerance of channel can be defined as p (y _i| v _i=0), p (y _i| v _i=1), i=0 ..., N-1.The LLR of tolerance, i.e. L _Metric(i), can be defined as follows:

$L_{\mathrm{metric}}\left(i\right)=\ln \frac{p\left(y_i\right|v_i=0)}{p\left(y_i\right|v_i=1)}$

Notice " ln " in the various mathematic(al) representations refers to e to be the natural logrithm at the end herein.

For each variable node v _i, its LLR value of information can be defined as follows:

$\ln \frac{p(v_i=0|y_i)}{p(v_i=1|y_i)}=L_{\mathrm{metric}}\left(i\right)+\ln \frac{p(v_i=0)}{p(v_i=1)}$

Because variable node v _iBe positioned at the LDPC code word, the ratio of these values $\ln \frac{p(v_i=0)}{p(v_i=1)},$ Can do following replacement:

$\ln \frac{p(v_i=0,{\mathrm{vH}}^T=0|y)}{p(v_i=1,{\mathrm{vH}}^T=0|y_i)}=\underset{(i,j)\∈E_v\left(i\right)}{\mathrm{\Σ}}\ln \frac{p(v_i=0,{\mathrm{vh}}_j^T=0|y)}{p(v_i=1,{\mathrm{vh}}_j^T=0|y_i)}$

E wherein _v(i) be from v as defined above _iOne group of sideline of beginning.

When carrying out the application's BP (confidence spread) coding/decoding method, $\ln \frac{p(v_i=0,{\mathrm{vh}}_j^T=0|y)}{p(v_i=1,{\mathrm{vh}}_j^T=0|y_i)}$ Value can do following replacement:

$L_{\mathrm{check}}(i,j)=\ln \frac{p(\underset{e\∈E_c\left(j\right)\backslash \left\{(i,j)\right\}}{\mathrm{\Σ}}{v}_{v\left(e\right)}=0|y)}{p(\underset{e\∈E_c\left(j\right)\backslash \left\{(i,j)\right\}}{\mathrm{\Σ}}{v}_{v\left(e\right)}=1|y)}$

L _Metric(i j) is known as about sideline (i, check-node c j) _jEXT (extrinsic) information.In addition, e ∈ E _c(j) { (i, j) } represent that all are from check-node c _jThe sideline of launching but do not comprise from check-node c _jTo variable node v _iThe sideline.The extrinsic information value can be regarded the value that the best estimate that generates true information bits in the reception vector is helped out as.And in the BP algorithm, about sideline (i, variable node v j) _iExtrinsic information can be defined as follows:

$L_{\mathrm{var}}\left(i\right)=L_{\mathrm{metric}}\left(i\right)+\underset{(i,k)\∈E_v\left(i\right)\backslash \left\{(i,j)\right\}}{\mathrm{\Σ}}{L}_{\mathrm{metric}}(i,k)$

As mentioned above, the parity check matrix H of LDPC sign indicating number has following form:

(equation 3)

In this form, each submatrix H of parity check matrix H _{I, j}Can be that (1) all elements is p * p matrix of 0, or the permutation matrix of the unit matrix of (2) p * p, or (3) several displacement unit matrix and.

U.S. Patent application No.10/851, in 614 (act on behalf of case number for No.BP3580) disclosed parallel-block LDPC sign indicating number is a kind of LDPC sign indicating number with above-mentioned feature.The application quote in full this U.S. Patent application and with it as the disclosed part of the application.

Can consider the LDPC sign indicating number of a typical ratio 1/2, its block size is 1248 bits, has 624 check equations, p=52, m=24, L=12.The block bipartite graph of this LDPC sign indicating number will be described in conjunction with the following drawings.

Fig. 5 is that ratio is the schematic diagram of the LDPC block bipartite graph 500 of parallel-block LDPC sign indicating number of 1/2, and its block size is 1248 bits, has 624 check equations.Wherein, parallel sideline is represented in the sideline of black.LDPC sign indicating number among this figure is the LDPC sign indicating number of ratio 1/2, and block size is 1248 bits, and 624 check equations are arranged.Make p=52 as mentioned above.24 position pieces so, are then arranged (as B ₀, B ₁, B ₂..., B ₂₃) and 12 check blocks (as C among the figure ₀, C ₁, C ₂..., C ₁₂Shown in).Preceding 12 position pieces are B _i=52i, 52i+1 ..., 52 (i+1) i-1}, i=0,1 ..., 11.Ensuing 12 position pieces are B _j=52j, and 52j+12,52j+24 ..., 52j+51 * 12}, j=0,1 ..., 11.Among the figure, parallel sideline is represented in the sideline of black.The arrangement π in each sideline _{I, j}Be cyclic shift, list in the form of Fig. 6.

Figure 6 shows that the arrangement in all sidelines tabulation 600 in the LDPC block bipartite graph among Fig. 5.Equally, the arrangement π in each sideline _{I, j}Be that circulation is moved, shown in form among the figure.In the form shown in the figure, if do not have numeral in the given unit, this represents between those nodes not connect (for example, not being connected between position piece node and the check block node), the mobile degree of depth otherwise this numeral circulates.2 numerals are then represented two cyclic shifts (being that parallel sideline is represented in the black sideline) in parallel sideline.

At U.S. Patent application No.10/851, in 614 (act on behalf of case number for No.BP3580), enumerated the example (comprise that each independent position node is taken as the regular LPDC sign indicating number that a position piece node and each check-node are taken as a check block node---be that each block has only an element) of some parallel-block LDPC sign indicating numbers.In addition, the LDPC sign indicating number that the European standard of DVB-S2 is used is another example of parallel-block LDPC sign indicating number, can use new method of the present invention to decode.These LDPC sign indicating numbers all have description in DVB-S2 (DVB-satellite the 2nd edition) standard and draft standard mentioned above.

More many cases of parallel-block LDPC sign indicating number can find from following 3 lists of references:

[3]H.Zhong?and?T.Zhang，“Design?of?VLSI?implementation-oriented?LDPCcodes”，IEEE?Semiannual?Vehicular?Technology?Conference(VTC)，Oct.2003.

[4]S.J.Johnson?and?S.R.Weller，”Quasi-cyclic?LDPC?codes?from?differencefamilies”，3 ^rd?AusCTW，Canberra，Australia，Feb.4-5，2002.

[5]F.Verdier?and?D.Declercq，”A?LDPC?parity?check?matrix?construction?forparallel?hardware?decoding”，3 ^rd?International?Symposium?on?Turbo-Codes&Related?Topics?Brest，France，September?2003.

Each monodrome clauses and subclauses (for example n) are represented one 52 * 52 matrix in the form 600, and digital n represents that these clauses and subclauses are unit matrix that n recirculates and is shifted.Accordingly, (as x, y) unit matrix of two cyclic shifts of expression is added in and constitutes corresponding results together each the diadic clauses and subclauses in the form 600.

When consider these or other parallel-during block LDPC sign indicating number, be noted that above-mentioned LMP coding/decoding method can not decode to this type of LDPC sign indicating number.

But new coding/decoding method of the present invention can be decoded to this type of LDPC sign indicating number.The present invention can not only decode to this type of LDPC sign indicating number (this is impossible to the LMP coding/decoding method), and its decode procedure is faster relatively, can also obtain good relatively performance (as the low error rate) aspect signal to noise ratio.

Below will introduce a kind of new at the ldpc coded signal coding/decoding method of (comprising parallel-block LDPC sign indicating number).When describing this coding/decoding method, adopt label same as above.This coding/decoding method generally is called AMP (quickening the message transmission) decoding processing method again.Below introduce the various embodiment of this AMP coding/decoding method.

Fig. 7 is the schematic diagram of an example 700 in a plurality of parts of parity check matrix H.In example 700, parity check matrix H 707 has a plurality of rectangle submatrixs (rectangle submatrix H as shown in FIG. _I-2701, rectangle submatrix H _I-1702, rectangle submatrix H _i703 etc.).Parity check matrix H 707 can be regarded as and has following form:

$H=\left[\begin{array}{c}.\\ .\\ .\\ H_{i-2}\\ H_{i-1}\\ H_i\\ .\\ .\\ .\end{array}\right]$ Or H=[... H _I-2H _I-1H _i] ^T

In addition, each rectangle submatrix all includes a plurality of sub-square formations.This a little square formation can be regarded as is lined up a lot of row.Wherein two row are described to the j row 704 and the j+1 row 705 of parity check matrix H.As seen, the j row 704 of parity check matrix H have its own corresponding a plurality of sub-square formation (submatrix H as shown in FIG. _{I-2, j}713, sub-square formation H _{I-1, j}715, sub-square formation H _{I, j}717 etc.).The j+1 row 705 of parity check matrix H have its own corresponding a plurality of sub-square formations (sub-square formation H as shown in FIG. _{I-2, j+1}723, sub-square formation H _{I-1, j+1}725, sub-square formation H _{I, j+1}727 etc.).

When using parity check matrix H 707 to carry out decoding, adopt top-down method to carry out, comprise that promptly each row of each sub-square formation all begin decoding from the top.Thereby first decoded its corresponding soft bit information that generates of sub-square formation when being in the second sub-square formation below the first sub-square formation and decoding, uses this soft bit information then.This processing procedure is carried out downwards continuously along each row of parity check matrix H 707.This method decoding speed is very fast, at this moment because be used for decoding about the in a single day available sub-square formation that is positioned at same row below that just passes to forward immediately of the soft bit information of a sub-square formation.

As shown in example 700, when the j of parity check matrix H 707 is listed in when decoding sub-square formation H _{I-2, j}The soft bit information that 713 uses are positioned at the sub-square formation (if present) above it to be provided is decoded.Notice that for first the non-0 sub-square formation in each row of parity check matrix H 707, the soft bit information of using as its input is corresponding to the bit metric information (i.e. the LLR of initial reception) of this bit in the first round decoding iteration.But this is the situation of first round iteration.For the decoding iteration after the first round, the soft bit information that last non-0 sub-square formation of each row of first of each row of parity check matrix H 707 non-0 sub-square formation use parity check matrix H 707 produces is as the input of its correspondence.

For example, if sub-square formation H _{I-2, j}713 is first non-0 sub-square formation of parity check matrix H 707 these row, and then its decoding initial condition is the bit metric information (the promptly initial LLR that receives) corresponding to this.Separate numeral square formation H _{I-2, j}The soft bit information 714 that was produced in 713 o'clock is sent to and is applied to sub-square formation H _{I-1, j}715 decode procedure is to generate soft bit information 716.

Similarly, separate numeral square formation H _{I-1, j}The soft bit information 716 that was generated in 715 o'clock is sent to and is applied to sub-square formation H _{I, j}717 decode procedure to generate soft bit information, is used for being positioned at sub-square formation H in the parity check matrix H j row 704 _{I, j}The sub-square formation of under 717 other is decoded.The decode procedure of the decode procedure of the j+1 row 705 of parity check matrix H and parity check matrix H j row is similar.

As can be seen, the decoding processing of parity check matrix H 707 uses decoded soft bit information to carry out, and when respectively each sub-square formation being decoded, soft bit information is listed as downward cascade by each.Make in this way, decode procedure can obtain to separate by the decoding iterations of carrying out still less than other method.When carrying out, can obtain more performance with the as many decoding iteration of other decoding process.This has given the designer the very big degree of freedom, and other method made improvements, also promptly, coding/decoding method of the present invention can provide more performance (using equal decoding iterations) or the method (only using few many decoding iterationses) that obtains equal performance is provided.

Fig. 8 carries out decoding processing generates the current sub-square formation of parity check matrix H with the soft bit information of the last sub-square formation of using parity check matrix H the schematic diagram of an embodiment 800 of soft bit information.Embodiment 800 has showed a kind of parallel configuration, and wherein a plurality of processors are carried out the decoding of each sub-square formation of parity check matrix H.

For example, in the time 891, processor 801 receives corresponding to sub-square formation H _{I-2, j}814 soft bit information.Processor 801 then use receive corresponding to sub-square formation H _{I-2, j}814 soft bit information is separated numeral square formation H _{I-1, j}Processor 801 generates corresponding to sub-square formation H afterwards _{I-1, j}816 soft bit information.

Similarly, in the time 891, processor 802 receives corresponding to sub-square formation H _{I-2, j+1}824 soft bit information.Processor 801 then use receive corresponding to sub-square formation H _{I-2, j+1}824 soft bit information is separated numeral square formation H _{I-1, j+1}Processor 801 generates corresponding to sub-square formation H afterwards _{I-1, j+1}826 soft bit information.

Identical processor 801 and 802 is then by the ensuing separately sub-square formation of these two row of the parity check matrix H that is used for again decoding.

In the time 892, processor 801 receives corresponding to sub-square formation H _{I-1, j}816 soft bit information.Processor 801 then use receive corresponding to sub-square formation H _{I-1, j}816 soft bit information is separated numeral square formation H _{I, j}Processor 801 generates corresponding to sub-square formation H afterwards _{I, j}818 soft bit information.

Similarly, in the time 892, processor 802 receives corresponding to sub-square formation H _{I-1, j+1}826 soft bit information.Processor 801 then use receive corresponding to sub-square formation H _{I-1, j+1}826 soft bit information is separated numeral square formation H _{I, j+1}Processor 801 generates corresponding to sub-square formation H afterwards _{I, j+1}826 soft bit information.

In another embodiment, can use single processor that each row of parity check matrix H are carried out serial decode.For example, each sub-square formation of first row of the parity check matrix H of at first decoding, the sub-square formation of each of the secondary series of the parity check matrix H of decoding then, the rest may be inferred.

Corresponding first embodiment (AMP-I coding/decoding method) of Fig. 9 and Figure 10, corresponding second embodiment (AMP-II decoding) of Figure 11.

Fig. 9 is its submatrix H when the row weights of parity check matrix H equal 1 _{I, j}The schematic diagram of the embodiment 900 that upgrade to handle of soft bit information.

The AMP-I coding/decoding method is according to the feature operation shown in Fig. 9.Those that equal 1 parity check matrix H for the row weights are by sub-square formation H _{I, j}The row that constitute, soft bit upgrade to handle according to functional block shown in Figure 9 to be carried out.

During first round decoding iteration, sideline memory 920 is by reset.H corresponding to the k-1 time decoding iteration _{I, j}Sideline message (among the figure use label 922 expression) from sideline memory 920, extract.Use the H that from soft bit information memory 910, extracts then _{I-1, j}The soft bit information of row deducts this sideline message.

The result that will subtract each other offers verification engine 930 and is used to carry out code check node processing then, thereby upgrades at least one the sideline message about check-node, thereby generates H _{I, j}Corresponding to the sideline message (among the figure use label 932 expression) after the renewal of the k time decoding iteration.

Then with H _{I, j}The sideline message (shown in label 932) corresponding to one or more renewals of k wheel decoding iteration offer summation module, and also return to sideline memory 920.The H that this summation module provides verification engine 930 _{I, j}Corresponding to the sideline message (using label 932 expressions) of the renewal of k wheel decoding iteration be equally verification engine 930 provide subtract each other both additions as a result.

By H _{I, j}Constituted corresponding to the sideline message (using label 932 expressions) of the renewal of k wheel decoding iteration and the above-mentioned result of subtracting each other and value, constituted H _{I, j}The soft bit information of row (using label 908 expressions among the figure).This soft bit information is sent to soft bit memory 910 in order to next rectangle submatrix (the rectangle submatrix H among Fig. 7 for example afterwards _I-2701, rectangle submatrix H _I-1702, rectangle submatrix H _iUse when 703) decoding subsequently.

Figure 10 for when the row weights of parity check matrix H greater than 1 the time, its submatrix H _{I, j}Soft bit upgrade the schematic diagram of processing procedure 1000.This embodiment can be regarded as with Fig. 9 in embodiment 900 combine execution.For example, when the prescription matrix H of parity check matrix H _{I, j}The row weights greater than 1 o'clock, its soft bit information upgrades to handle and uses the processing procedure 1000 shown in Figure 10 to carry out.Processing procedure 900 among processing procedure 1000 and Fig. 9 has a lot of similarities.

H _{I, j}The sideline message corresponding to k-1 wheel decoding iteration (using label 1022 expressions) from sideline memory 1020, take out, deliver to average information I processor 1040 then.

Average information I processor 1040 also receives the last rectangle submatrix H of decoding from soft bit information memory 1010 _jThe time H that produces _{I-1, j}The soft bit information (use label 1022 expression) of row.Then, average information I processor 1040 uses H _{I-1, j}The soft bit information (use label 1022 expression) of row calculate average information, and this average information is offered verification engine 1030.

Average information I processor 1040 calculates the average information M of each row v and each row u according to following equation _I:

$M_I(u,v)=S_{(j-1)p+v}-M_{u,v}^{k-1}\left(H_{i,j}\right)$ (equation 4)

Verification engine 1030 is used for carrying out the node checking treatment, thereby upgrades at least one the sideline information about check-node, thereby generates H _{I, j}The sideline message (using label 1032 expressions) corresponding to the renewal of k wheel decoding iteration.

Then with H _{I, j}The sideline message (using label 1032 expressions) corresponding to one or more renewals of k wheel decoding iteration deliver to bit update module 1060, and also return to sideline memory 1020.Bit update module 1060 is used to calculate H _{I, j}The next soft bit information of row (using label 1008 expressions), and should deliver to soft bit information memory 1010 in order to next rectangle submatrix (the rectangle submatrix H among Fig. 7 by next one soft bit information _I-2701, rectangle submatrix H _I-1702, rectangle submatrix H _i703) usefulness of decoding subsequently.

Bit update module 1060 also is used for receiving the H that satisfies 1 ≠ i (promptly 1 is not equal to i) that is stored in the memory 1050 _{I, j}Sideline message.In addition, bit update module 1060 also is used for receiving LLR (log-likelihood ratio) (using label 1085 expressions).The receiver front end of the communication equipment that this LLR information 1085 can be decoded from using method 1000 partly obtains.For example, the receiver of this communication equipment part can be carried out multiple pretreatment operation, comprises that down converted, sampling, Base-Band Processing, tolerance generate and the calculating of LLR information.Bit update module 1060 is used to calculate H _{I, j}The next soft bit information of row (using label 1008 expressions) should be delivered to soft bit information memory 1010 in order to next rectangle submatrix (the rectangle submatrix H among Fig. 7 by next one soft bit information afterwards _I-2701, rectangle submatrix H _I-1702, rectangle submatrix H _i703) usefulness of decoding subsequently.

Carrying out the bit node of bit update module 1060 indications of " bit renewal " handles and can be described below.For last round of iteration (being the k-1 wheel), (be expressed as Medge sometimes about the sideline message of check-node _c) also can be described to M _{U, v} ^K-1(H _{I, j}) (so that the formula below the reader understanding).For current iteration (being k), (be expressed as Medge sometimes about the sideline message of check-node before _c) also can be described to M _{U, v} ^k(H _{I, j}).In addition, from communication equipment, obtain and the LLR (log-likelihood ratio) of tolerance that is used to calculate the receiving symbol of corresponding specific bit b can be expressed as: met _bSoft bit information S then _{(j-1) p+v}Can be expressed as follows:

$S_{(j-1)p+v}={\mathrm{met}}_b+\underset{u=1}{\overset{p}{\mathrm{\Σ}}}{M}_{u,v}^k\left(H_{i,j}\right)+\underset{1\≠i}{\mathrm{\Σ}}{M}_{u,v}^{k-1}\left(H_{i,j}\right),v=1,...,p$ (equation 5)

As seen,

In comprised the output of verification engine 1030,

In comprised from memory 1050 obtain every.Equally, met _bCan partly obtain from the receiver of this communication equipment.Equally as can be seen, if submatrix H _{K, 1}(u is 0 v), does not then have M _{U, v}(H _{K, 1}).

As described above, Figure 11 (will describe in detail below) is the schematic diagram corresponding to second kind of coding/decoding method of the present invention (being the AMP-II decoding processing)

Figure 11 is the submatrix H of parity check matrix H _{I, j}Soft bit upgrade the schematic diagram of another embodiment 1100 that handles.This embodiment uses label as hereinbefore.The sub-square formation H of hypothesis among the embodiment 1100 _{I, j}Weights are w.At the 1st row, matrix every as follows: ${\mathrm{<figure-callout\; id="1"\; label="h\; r"\; filenames="C2006100588050032H1.png"\; state="\{\{state\}\}">\; <figure-callout\; id="1"\; label="h\; r"\; filenames="C2006100588050032H1.png"\; state="\{\{state\}\}">h</figure-callout>\; </figure-callout>}}_{r_{}{}_{}}={\mathrm{<figure-callout\; id="2"\; label="h\; r"\; filenames="C2006100588050032H1.png,C2006100588050038H1.png"\; state="\{\{state\}\}">\; <figure-callout\; id="1"\; label="h\; r"\; filenames="C2006100588050032H1.png"\; state="\{\{state\}\}">h</figure-callout>\; </figure-callout>}}_{r_{}{}_{}}=\&CenterDot;\&CenterDot;\&CenterDot;=h_{r_w,1}=1.$ In view of the above, handle and to carry out according to embodiment shown in Figure 11 1100 according to the sub-piece of AMP-II decoding processing method.

H _{I, j}The sideline message corresponding to k-1 wheel decoding iteration (using label 1122 expressions) from sideline memory 1120, obtain.These sideline message are sent to average information II processor 1145 then.In addition, these sideline message also are sent to average information I processor 1140.

Average information I processor 1140 also receives H from soft bit information memory 1110 _{I-1, j}The soft bit information of row (using label 1112 expressions), this soft bit information is at the last rectangle submatrix H of decoding _iShi Shengcheng.Afterwards, average information I processor 1140 passes through from H _{I, j}The sideline message corresponding to k-1 wheel decoding iteration in cut H _{I-1, j}The soft bit information of row (using label 1112 expressions) calculates first average information, and this first intermediate bit information is offered verification engine 1130.

Verification engine 1130 is carried out code check node processing, upgrades at least one the sideline message about check-node then, generates H then _{I, j}The sideline message (using label 1132 expressions) corresponding to the renewal of k wheel loop iteration.

H _{I, j}The sideline message (using label 1132 expressions) corresponding to one or more renewals of k wheel decoding iteration be sent to bit update module 1160, and also return to sideline memory 1120.Bit update module 1160 is calculated H _{I, j}The next soft bit information of row (using label 1108 expressions) should be delivered to soft bit information memory 1110 in order to result and H by average information II processor 1145 is generated by next one soft bit information afterwards _{I, j}All sideline message of upgrading corresponding to k wheel decoding iteration (use label 1132 is represented) phase Calais to next rectangle submatrix (the rectangle submatrix H among Fig. 7 _I-2701, rectangle submatrix H _I-1702, rectangle submatrix H _i703) usefulness of decoding.

In addition, average information II processor 1145 also is received in the H that generates the last round of iteration from soft bit information memory 1110 _{I-1, j}The soft bit information of row (using label 1112 expressions).Average information II processor 1145 then passes through from H _{I-1, j}Cut H in the soft bit information of row _{I, j}All sideline message of upgrading corresponding to k wheel decoding iteration (use label 1132 is represented) calculate second average information, and this second average information is offered bit update module 1160.

For example, at H _{I, j}Row in have under the situation of 2 or more " 1 " value, average information II processor 1145 is by cutting H from the soft bit information of these row _{I, j}(corresponding to k-1 wheel decoding iteration) corresponding at H _{I, j}Row in all sideline message of each " 1 " value calculate second average information.

Initial phase (before being first round decoding iteration), soft bit information memory 1110 receives LLR (log-likelihood ratio) (using label 1185 expressions).Similar with top described another embodiment, LLR information 1185 can partly be provided by the receiver front end of the communication equipment of the coding/decoding method that uses embodiment 1000.For example, the receiver of this communication equipment part can be carried out multiple pretreatment operation, comprises the generation of down converted, sampling, Base-Band Processing, tolerance and the calculating of LLR.

Bit update module 1160 is calculated H _{I, j}The next soft bit information of row (using label 1108 expressions) should be delivered to soft bit information memory 1110 in order to next rectangle submatrix (the rectangle submatrix H among Fig. 7 by next one soft bit information afterwards _I-2701, rectangle submatrix H _I-1702, rectangle submatrix H _i703) usefulness of decoding subsequently.Soft bit update module 1160 is added to H with the output of average information II processor 1145 _{I, j}The sideline message of (corresponding to k wheel decoding iteration) renewal on.For example, at H _{I, j}Row in have under the situation of 2 or more " 1 " value, bit update module 1160 is with H _{I, j}(corresponding to k wheel decoding iteration) corresponding H _{I, j}Every row in each " 1 " value sideline message addition.

Average information I processor 1140 calculates the first average information M of each row v and each row u according to following equation ₁(similar) with the processing of the average information I processor 1040 of embodiment among Figure 10 1000:

$M_1(u,v)=S_{(j-1)p+v}-M_{u,v}^{k-1}\left(H_{i,j}\right)$ (equation 6)

Average information II processor 1145 calculates T according to following equation to each row 1 ₁:

${\mathrm{<figure-callout\; id="1"\; label="T"\; filenames="C2006100588050032H1.png"\; state="\{\{state\}\}">T</figure-callout>}}_1=S_{(j-1)p+v}-\underset{j=1}{\overset{w}{\mathrm{\&Sigma;}}}{M}_{u_w,v}^k\left(H_{i,j}\right)$ (equation 7)

The bit of execution " bit renewal " the more bit node processing of new processor 1160 indications is described below, in order to calculate soft bit information S _{(j-1) p+v}

$S_{(j-1)p+v}={\mathrm{<figure-callout\; id="1"\; label="T"\; filenames="C2006100588050032H1.png"\; state="\{\{state\}\}">T</figure-callout>}}_1+\underset{j=1}{\overset{w}{\mathrm{\&Sigma;}}}{M}_{u_w,v}^k\left(H_{i,j}\right)$ (equation 8)

AMP coding/decoding method described in the invention is applicable to that every row or every row have the submatrix H of the p * p of more than " 1 " _{I, j}Ability, make the designer can construct wider LDPC sign indicating number.This comes at specifying the application construction performance better to encode for designer's more freedom degree.

In this application, by BER (error rate) (or BLER (block error rate)) and E _b/ N _o(the ENERGY E of each _bWith noise spectral density N _oRatio) relation curve carry out performance comparison.E _b/ N _oBe tolerance to the SNR in the digital communication system (signal to noise ratio).By observing these performance curves, to any given E _b/ N _o(or signal to noise ratio) can determine BLER or BER, thereby can provide the simple and clear relatively expression of coding/decoding method performance of the present invention.

Figure 12 is that the performance of MP (message transmission) decode procedure and AMP (quickening the message transmission) decode procedure compares 1200 schematic diagram.This performance comparison diagram adopts (1248,624) mentioned above LDPC sign indicating number.

Use various innovation provided by the invention and improved coding/decoding method, as can be seen, the new AMP decoding processing of using the present invention to mention can reduce almost 50% decoding iterations under the condition that obtains identical performance index.And, when carrying out the decoding iteration of same number, compare with the MP decoding processing method, BLER/BER is regarded as E _b/ N _oThe function of (or signal to noise ratio), AMP decoding processing method can provide the gain near 0.2dB on performance index.Therefore, new coding/decoding method of the present invention is when carrying out the decoding of ldpc coded signal, coding/decoding method more performance than prior art can be provided, the performance with prior art coding/decoding method suitable (normally better) can be provided when carrying out less decoding iteration.

Notice that the performance of the hierarchical decoding method in the prior art of mentioning does not mark, because the performance of this existing hierarchical decoding method is more higher than relative with AMP decoding processing method of the present invention on error rate in Figure 12 in above " background technology ".

Figure 13, Figure 14 and Figure 15 have enumerated the various embodiment of the method that ldpc coded signal is decoded.

With reference to the embodiment among Figure 13 1300, shown in step 1310, this method is calculated first soft bit information corresponding to the first sub-square formation.This can regard use as and carry out decoding processing corresponding to the parity matrix of LDPC sign indicating number.Then, use first soft bit information corresponding to the first sub-square formation to calculate second soft bit information in the step 1320, use second soft bit information corresponding to the second sub-square formation to calculate the 3rd soft bit information in the step 1330 corresponding to the 3rd sub-square formation corresponding to the second sub-square formation.At last, shown in step 1340, this method is carried out the iteration error correction decoding to ldpc coded signal, to generate the optimal estimation at least one information bit that is coded into ldpc coded signal.

According to mentioned above and some other embodiment, this decode procedure can be regarded as respectively being listed as soft bit information (each the sub-square formation according to parity matrix calculates) cascade downwards along parity matrix.

With reference to the embodiment among Figure 14 1400, shown in step 1410, this method comprises first soft bit information of calculating corresponding to the first sub-square formation.This method also uses first soft bit information corresponding to the first sub-square formation to calculate second soft bit information corresponding to the second sub-square formation, shown in step 1420.This first sub-square formation and the second sub-square formation are positioned at the same row of parity matrix.

Next this method is used corresponding to second soft bit information of the second sub-square formation and is calculated average information with the difference about the sideline message of corresponding check-node, shown in step 1430.Next this method uses the sideline message of first average information renewal about corresponding check-node, shown in step 1450.This method is carried out the iteration error correction decoding to ldpc coded signal at last, to generate the optimal estimation at least one information bit that is coded into ldpc coded signal, shown in step 1460.

Referring to the embodiment among Figure 15 1500, shown in step 1510, this method comprises first soft bit information of calculating corresponding to the first sub-square formation.Next, this method comprises that use calculates second soft bit information corresponding to the second sub-square formation to first software information corresponding to the first sub-square formation, shown in step 1520.Other method as indicated above is the same, and the first sub-square formation among this embodiment 1500 and the second sub-square formation are positioned at the same row of parity matrix equally.

Next this method is used about the sideline message of corresponding check-node and the difference corresponding to second soft bit information of the second sub-square formation and is calculated first average information, shown in step 1530.Then, use about the sideline message of corresponding check-node with calculate second average information corresponding to second soft bit information of the second sub-square formation with corresponding to the difference of the first soft bit information sum of the two of the first sub-square formation, shown in step 1540.

Afterwards, this method is used the sideline message of first average information renewal about corresponding check-node, shown in step 1550.At last, this method is carried out the iteration error correction decoding to ldpc coded signal, to generate the optimal estimation at least one information bit that is coded into ldpc coded signal, shown in step 1560.

It is also noted that any method described in the figure of front can be applicable to various systems and device design (communication system, communications transmitter, communication sink, communication transceiver and/or other various functional).

In addition, it should be appreciated that, various functional, system or equipment design of introducing among the present invention and the correlation technique that the present invention relates to all can realize in log-domain, and like this, multiply operation can use addition to carry out and divide operations can use subtraction to carry out.

Based on above-mentioned detailed description of the present invention in conjunction with the accompanying drawings, be conspicuous to other modifications and changes of the present invention.And clearly, these modifications and changes do not exceed scope and spirit essence of the present invention.

The application quote in full and require the applying date be February 26 in 2005 day, be called the U.S. Provisional Patent Application No.60/656 of " AMP (the quickening the message transmission) decoder that is applicable to LDPC (low-density checksum) sign indicating number ", the priority of 566 (act on behalf of case number be No.BP4443).

The application also quotes in full following patent application:

The applying date be Mays 21 in 2005 day, be called the U.S. Patent application No.10/851 of " using LDPC (low-density checksum) the code signal decoding of parallel bit node simultaneously and code check node processing ", 614 (act on behalf of case number be No.BP3580).

Claims (9)

1, a kind of accelerated message passing decoder of adapted for decoding LDPC code signal is characterized in that, described decoder comprises:

Soft bit is new processor more, use is calculated second soft bit information corresponding to the second sub-square formation corresponding to first soft bit information of the first sub-square formation, wherein, row corresponding to the parity matrix that generates the employed generator matrix of ldpc coded signal comprise the described first sub-square formation and the described second sub-square formation;

The verification engine processor uses describedly corresponding to second soft bit information of the second sub-square formation and about the difference between the second sideline message of corresponding check node, upgrades the 3rd sideline message about the corresponding check node; Perhaps use describedly, upgrade the 3rd sideline message about the corresponding check node corresponding to second soft bit information of the second sub-square formation and about the difference between the first sideline message of corresponding check node.

2, decoder according to claim 1, it is characterized in that, described soft bit more new processor uses described second soft bit information corresponding to the second sub-square formation to calculate the 3rd soft bit information corresponding to the 3rd sub-square formation, and described described row corresponding to the parity matrix that generates the employed generator matrix of ldpc coded signal also comprise the described the 3rd sub-square formation.

3, decoder according to claim 1 is characterized in that, each decodes respectively described decoder to the described first sub-square formation and the second sub-square formation.

4, decoder according to claim 1, it is characterized in that, described soft bit more new processor and the collaborative work of described verification engine processor so that described ldpc coded signal is carried out the iteration error correction decoding, thereby generate best estimate at least one information bit that is coded into described ldpc coded signal.

5, a kind of accelerated message passing decoder of adapted for decoding LDPC code signal is characterized in that, described decoder comprises:

Soft bit is new processor more, use is calculated second soft bit information corresponding to the second sub-square formation corresponding to first soft bit information of the first sub-square formation, wherein, row corresponding to the parity matrix that generates the employed generator matrix of ldpc coded signal comprise the described first sub-square formation and the described second sub-square formation;

The first average information computing module uses about the sideline message of corresponding check node and describedly calculates first average information corresponding to the difference between second soft bit information of the second sub-square formation;

The second average information computing module, use described about the corresponding check node sideline message and described corresponding to the second sub-square formation second soft bit information and describedly calculate second average information corresponding to the difference between the first soft bit information sum of the two of the first sub-square formation;

The verification engine processor uses described first average information to upgrade described sideline message about the corresponding check node.

6, decoder according to claim 5, it is characterized in that described soft bit more new processor uses described second average information and the described sideline message of having upgraded about the corresponding check node to calculate described second soft bit information corresponding to the second sub-square formation.

7, a kind of method of adapted for decoding LDPC code signal is characterized in that, described method comprises:

Use is calculated second soft bit information corresponding to the second sub-square formation corresponding to first soft bit information of the first sub-square formation, wherein, row corresponding to the parity matrix that generates the employed generator matrix of ldpc coded signal comprise the described first sub-square formation and the described second sub-square formation;

Use is about the sideline message of corresponding check node and describedly calculate first average information corresponding to the difference between second soft bit information of the second sub-square formation;

Use described first average information to upgrade described sideline message about the corresponding check node;

Described ldpc coded signal is carried out the iteration error correction decoding, thereby generate best estimate at least one information bit that is coded into described ldpc coded signal.

8, method according to claim 7 is characterized in that, described method further comprises: each is decoded respectively to the described first sub-square formation and the second sub-square formation.

9, method according to claim 7 is characterized in that, described method further comprises:

Use described about the corresponding check node sideline message and described corresponding to the second sub-square formation second soft bit information and describedly calculate second average information corresponding to the difference between the first soft bit information sum of the two of the first sub-square formation;

Use described second average information and the described sideline message of having upgraded to calculate described second soft bit information corresponding to the second sub-square formation about the corresponding check node.

Images