CN100565930C

CN100565930C - Nonvolatile semiconductor memory device

Info

Publication number: CN100565930C
Application number: CNB2006101309516A
Authority: CN
Inventors: 安田直树; 西川幸江; 村冈浩一
Original assignee: Toshiba Corp
Current assignee: Japanese Businessman Panjaya Co ltd; Kioxia Corp
Priority date: 2005-10-14
Filing date: 2006-10-13
Publication date: 2009-12-02
Anticipated expiration: 2026-10-13
Also published as: CN101026193A

Abstract

Nonvolatile semiconductor memory device of the present invention has been realized increasing the coupling ratio of memory cell and reducing leakage current.The Nonvolatile semiconductor memory device relevant with example of the present invention comprises: the source that disposes in Semiconductor substrate, leakage diffusion layer; First dielectric film (T-ox.) that on the raceway groove between source, the leakage diffusion layer, disposes; Floating gate electrode (FG) configuration, that contain stacked a plurality of first conductive layers on first dielectric film (T-ox.); Second dielectric film (IPD) of configuration on floating gate electrode (FG); And the control grid electrode (CG) of configuration on second dielectric film (IPD).Under with the situation of one first conductive layer except the superiors among a plurality of first conductive layers as datum layer, the work function of datum layer is more than or equal to 4.0eV, work function φ w1, the φ w2 of a plurality of first conductive layers that comprise datum layer on the datum layer ..., φ wn is along with increasing successively towards second dielectric film (IPD).

Description

Nonvolatile semiconductor memory device

Technical field

The present invention relates to have the Nonvolatile semiconductor memory device of the memory cell of stacked gate electrode structure.

Background technology

In Nonvolatile semiconductor memory devices such as NAND type flash memory, memory cell (cell transistor) has the stacked gate electrode structure.So-called stacked gate electrode structure is in the source, leaks on the raceway groove between the diffusion layer structure of stacked floating gate electrode and control grid electrode.

By on the tunnel insulator film between raceway groove and the floating gate electrode, applying high electric field, and exchange charge (for example, electronics) betwixt, carry out write/erase for this memory cell.That is,, make the threshold voltage shift of memory cell, storage data (" 0 " or " 1 ") by changing the quantity of electric charge in the floating gate electrode.

Here, in order to improve write/erase efficient, just must increase the coupling ratio β of memory cell, and the leakage current when reducing write/erase.

Utilize the ratio of (change in voltage of floating gate electrode)/(change in voltage of control grid electrode) to come the coupling ratio β of define storage units, when representing by capacity ratio, for

β＝CIPD/Ctot

Wherein, Ctot is the summation of the electric capacity between control grid electrode and the raceway groove, and CIPD is the electric capacity between control grid electrode and the floating gate electrode.

In the prior art, relate to increase coupling ratio β, mainly come correspondence, for example use ONO (SiO by the material that designs the dielectric film (so-called interlayer polycrystalline (inter-poly) dielectric film) that between floating gate electrode and control grid electrode, disposes ₂/ SiN/SiO ₂) film is as interlayer polycrystalline dielectric film.

Recently, replace the ONO film, research in vogue use have than ONO film more the high-k of high-k (high-k) material as interlayer polycrystalline dielectric film (for example, with reference to patent documentation 1).

Now, as high dielectric constant material, alumite (Al has been proposed ₂O ₃), hafnium oxide-film (HfO ₂), their mixture or mixed crystal (hafnium aluminate: HfAlOx) etc.

Because therefore the miniaturization that these materials are good at double the closing property of silicon technology, can the corresponding stored unit expects the development in the future of these materials very much.

But, even use these high dielectric constant materials, also there is the miniaturization that is accompanied by element as interlayer polycrystalline dielectric film, floating gate electrode during write/erase and the leakage current between the control grid electrode surpass the problem of fiducial value, memory cell characteristics deterioration.

Patent documentation 1: special hope 2005-133624 number

Summary of the invention

In example of the present invention, the technology of leakage current when having proposed a kind of increase coupling ratio of realization simultaneously and having reduced write/erase.

Relate to the Nonvolatile semiconductor memory device of example of the present invention, comprising: the source that in Semiconductor substrate, disposes, leakage diffusion layer; In the source, leak first dielectric film that disposes on the raceway groove between the diffusion layer, constitute by tunnel insulator film; The floating gate electrode that on first dielectric film, disposes, contain stacked a plurality of first conductive layers; Second dielectric film that on floating gate electrode, disposes; And the control grid electrode that on second dielectric film, disposes.With one first conductive layer except the superiors among a plurality of first conductive layers as datum layer, the work function of this datum layer is more than or equal to 4.0eV, and the work function of a plurality of first conductive layers that comprise datum layer on the datum layer is along with increasing successively towards second dielectric film.The said reference layer is formed in the orlop in above-mentioned a plurality of first conductive layer and is made of metal or the conductive semiconductor material that contains impurity, and first conductive layer of one deck at least above the said reference layer is made of metal, and above-mentioned second dielectric film is oxide, nitride or the nitrogen oxide that contains the material that is selected from least a element among Al, Hf, La, Y, Ce, Ti, Zr, the Si.

Embodiment according to the present invention, leakage current in the time of can realizing increasing coupling ratio simultaneously and reduce write/erase.

Description of drawings

Fig. 1 is the profile that the cellular construction of reference example is shown.

Fig. 2 is the profile of manufacture method that the cellular construction of Fig. 1 is shown.

Fig. 3 is the profile of manufacture method that the cellular construction of Fig. 1 is shown.

Fig. 4 is the profile of manufacture method that the cellular construction of Fig. 1 is shown.

Fig. 5 is the profile of manufacture method that the cellular construction of Fig. 1 is shown.

Fig. 6 is the profile of manufacture method that the cellular construction of Fig. 1 is shown.

Fig. 7 is the schematic cross sectional view that example of the present invention is shown.

Fig. 8 is the schematic cross sectional view that example of the present invention is shown.

Fig. 9 is the schematic cross sectional view that example of the present invention is shown.

Figure 10 is the schematic cross sectional view that example of the present invention is shown.

Figure 11 illustrates the relation between effective electric field and the current density.

Figure 12 illustrates the time dependent simulation model of threshold voltage.

Figure 13 illustrates the time dependent result of calculation of threshold voltage.

Figure 14 illustrates the process of the optimum condition of obtaining the threshold voltage variation amount.

Figure 15 illustrates the time dependent analog result of threshold voltage.

Figure 16 is the profile that the cellular construction of first execution mode is shown.

Figure 17 is the profile that the cellular construction of second execution mode is shown.

Figure 18 is the profile that the cellular construction of the 3rd execution mode is shown.

Figure 19 is the profile that the cellular construction of the 4th execution mode is shown.

Figure 20 is the profile that the cellular construction of the 5th execution mode is shown.

Figure 21 is the profile that the variation of cellular construction is shown.

Figure 22 is the profile that the cellular construction of first embodiment is shown.

Figure 23 is the profile that the cellular construction of second embodiment is shown.

Figure 24 is the profile that the cellular construction of the 3rd embodiment is shown.

Figure 25 is the profile that the cellular construction of the 4th embodiment is shown.

Figure 26 is the profile that the cellular construction of the 5th embodiment is shown.

Figure 27 is the profile that the cellular construction of the 5th embodiment is shown.

Embodiment

Below, with reference to accompanying drawing, describe the best mode that is used to implement example of the present invention in detail.

1, work function

When explanation example of the present invention, the notion of so-called " work function " frequently occurs.Therefore, this work function at first is described.

In order to measure the work function of employed material in each layer of the memory cell of Nonvolatile semiconductor memory device, just need the assessment technique of the work function in the microscopic fields.

Here, will adopt as the evaluation method (Kelvin probe method) of a kind of Kelvin probe force microscopy (Kelvin Probe Force Microscopy (KPM)) of scanning probe microscopy (Scanning Probe Microscopy (SPM)) evaluation method as work function.

In the Kelvin probe method, the potential difference between direct measuring samples surface and the probe electrode (probe).If the work function of known probe electrode just can be obtained the work function of sample surfaces exactly.

The Kelvin probe method is obtained potential difference between sample surfaces and the probe electrode according to following principle.

At first, make probe electrode near sample surfaces, forming with both is the capacitor of electrode.Here, if make the probe electrode vibration, then, therefore produce movement of electric charges owing to change the electric capacity of capacitor.This movement of electric charges is detected as alternating current.

Then, on probe electrode, apply bias voltage, when the potential difference between sample surfaces and the probe electrode is eliminated,, therefore can not produce electric charge and move, also just do not have alternating current to flow because the current potential at capacitor two ends is equal.

Therefore, make alternating current become minimum bias voltage, work function that just can the assess sample surface by detection.

As the memory cell of Nonvolatile semiconductor memory device, in microscopic fields, must measure under the situation of work function, principle also is identical.In the case, if probe electrode is diminished, just can measure work function.

But, when probe electrode diminishes,, therefore can produce the problem that can not obtain sufficient resolution because alternating current diminishes.

Therefore, in Kelvin probe force microscopy, replace alternating current, utilize the electrostatic force that between probe electrode and sample surfaces, produces.

If between probe electrode and sample surfaces, there is not potential difference, so just can not produce electrostatic force.Therefore, make electrostatic force become minimum bias voltage, just can measure the work function in the microscopic fields by obtaining.

Yet, owing in fact on market, sell this Kelvin probe force microscopy (evaluating apparatus), therefore,, just can easily carry out the measurement of work function if prepare to observe the sample of section of the memory cell of Nonvolatile semiconductor memory device.

2, coupling ratio

Example of the present invention is applicable to the Nonvolatile semiconductor memory device of the memory cell with stacked gate electrode structure.

In this Nonvolatile semiconductor memory device,, at first adopt to increase floating gate electrode and the opposed Method for Area of control grid electrode even for the memory cell miniaturization can not reduce coupling ratio β yet.

Fig. 1 shows the example of this kind cellular construction.

And, in the figure, establish line direction and be the direction that word line (control grid electrode) extends, column direction is the direction with the line direction quadrature.

This structure is characterised in that, utilizes control grid electrode CG to cover the part of floating gate electrode FG side.Thus, increase floating gate electrode FG and the opposed area of control grid electrode CG, increased the coupling ratio β of memory cell.

But, in recent years, even owing to can not make coupling ratio β become the big like that of the imagination like this, so carrying out the trial of in interlayer polycrystalline dielectric film, using high-k (high-k) material to increase coupling ratio β.

In addition, hereinafter, will between the electrode that disposes between floating gate electrode and the control grid electrode, be referred to as IPD (interlayer polycrystalline silicon medium) by dielectric film.

The example of the manufacture method of the cellular construction of the Fig. 1 when Fig. 2～Fig. 6 shows the use high dielectric constant material.

At first, as shown in Figure 2, utilize thermal oxidation method, be doped with on the silicon substrate of impurity (comprising trap) 101, forming thick is the tunnel oxide film 102 of about 7～8nm.In addition, utilize CVD (chemical vapor deposition) method, on tunnel oxide film 102, forming thickness successively is the phosphorous doped polysilicon film 103 of about 60nm and the mask material 104 that is used for the machine component area of isolation.

After this, on mask material 104, form photoresist, expose and develop this photoresist.Then, utilize RIE (reactive ion etching) method, the figure of transfer printing photoresist on mask material 104.After this, remove photoresist.

In addition, mask material 104 as mask, is utilized the RIE method, etching polysilicon film 103 and tunnel oxide film 102 successively form the slit 105a of the floating gate electrode that is isolated in the memory cell of adjacency on the line direction.

Then, utilize the RIE method, etched silicon substrate 101 in silicon substrate 101, forms the element separation groove 105b of the degree of depth for about 100nm.

Then, as shown in Figure 3, utilize the CVD method, form the silicon oxide film 106 that fills up slit 105a and element separation groove 105b fully.In addition, utilize CMP (chemico-mechanical polishing) method, grind silicon oxide film 106, make the flattening surface of silicon oxide film 106 until exposing mask material 104.

After this, optionally remove mask material 104.

Then, as shown in Figure 4, utilize dilute hydrofluoric acid solution, silicon oxide film 106 is carried out etch-back, expose the part of polysilicon film 103 sides.

In addition, utilize ALD (atomic layer deposition) method, the thickness of the upper surface of formation covering polysilicon film 103 and the part of side is for the pellumina 107 of about 15nm, as IPD.

At this moment, because the influence of employed oxidant during deposit pellumina 107, at polysilicon film 103 and pellumina 107 at the interface, form silicon oxide film 108 as thin as a wafer.Therefore, in fact, IPD just becomes gross thickness and is the pellumina 107 of about 16nm and the double-layer structure of silicon oxide film 108.

Then, as shown in Figure 5, utilize the CVD method, on pellumina 107, for example, form the conducting film 109 of the gross thickness of the double-layer structure that contains tungsten silicide film and polysilicon film for about 100nm.Then, utilize the CVD method, on conducting film 109, form mask material 110.

After this, on mask material 110, form photoresist, expose and develop this photoresist.Then, utilize the RIE method, the figure of transfer printing photoresist on mask material 110.After this, remove photoresist.

And, mask material 110 as mask, is utilized the RIE method, when etching conducting film 109, pellumina 107, silicon oxide film 108, polysilicon film 103 and tunnel oxide film 102, just form floating gate electrode FG and control grid electrode CG successively.

Then, as shown in Figure 6, utilize thermal oxidation method, carry out on the surface of floating gate electrode FG and control grid electrode CG, forming after the processing of silicon oxide film 111, utilize ion implantation, by autoregistration, in the surf zone of silicon substrate 101, formation source, leakage diffusion layer 112 are finished memory cell.

At last, utilize the CVD method, form the interlayer dielectric 113 that covers memory cell.

In the memory cell of utilizing this manufacture method to form, though can realize increasing coupling ratio β, but the leakage current during write/erase between floating gate electrode FG and the control grid electrode CG will surpass the fiducial value by the specification requirement of memory device, and memory cell characteristics can deterioration.

3, summary of the present invention

In example of the present invention, at first, as shown in Figure 7, by a plurality of conductive layer FG1, FG2 ..., FGn constitutes floating gate electrode FG, with a plurality of conductive layer FG1, FG2 ..., a conductive layer among the FGn except that the superiors is as datum layer.And the work function of establishing datum layer is more than or equal to 4.0eV, and the work function of a plurality of conductive layers that comprise datum layer on the datum layer is along with increasing towards the IPD order.

For example, establishing datum layer is under the situation of conductive layer (orlop) FG1, from conductive layer FG1 towards conductive layer FGn, work function

Order increases.

In addition, establish under the situation that datum layer is conductive layer FG2, from conductive layer FG2 towards conductive layer FGn, work function

Order increases.At this moment, with regard to the work function of conductive layer (orlop) FG1

Even, than the work function of conductive layer FG2

Greatly also harmless.

Here, the purpose that the work function of datum layer is made as more than or equal to 4.0eV is, in datum layer, gets rid of the electric conducting material with work function littler than the work function of silicon.

Thus, reduce the leakage current that produces among the IPD.Especially, as shown in Figure 8, example of the present invention is reduced in the floating gate electrode FG iunjected charge and writes the fashionable leakage current that produces, promptly reduces from floating gate electrode FG and move to the electric charge of control grid electrode CG.Its effect is very effective under the situation that is made of IPD high-k (high-k) material.

Have, datum layer is made of the conductive semiconductor material or the metal that contain impurity again, and the conductive layer of one deck at least above the datum layer is made of metal.

Here, so-called metal is the material that has the material of free electron or have Fermi surface in its band structure.Therefore, as long as satisfy this definition, in metal, except that comprising metallic element (atom) monomer, also comprise its compound.

In addition, the work function of control grid electrode CG preferably

Work function than datum layer is bigger.For example, control grid electrode is made of the superiors' identical materials with floating gate electrode FG.

In addition, as shown in Figure 9, also can by a plurality of conductive layer CG1, CG2 ..., CGm constitutes control grid electrode CG, is made of the orlop CG1 of control grid electrode CG the electric conducting material with work function bigger than the work function of datum layer.

For example, by constituting the orlop CG1 of control grid electrode CG with the superiors' FGn identical materials of floating gate electrode FG.

In the case, as shown in Figure 10, can reduce the undesirable phenomenon that is produced when the electric charge that discharges in the floating gate electrode FG is wiped, promptly reduce from control grid electrode CG and move to the electric charge of floating gate electrode FG.

In addition, embodiment according to the present invention can make the work function of conductive layer (orlop) FG1 of the floating gate electrode FG that contacts with tunnel insulator film T-ox. diminish.In the case, owing to increasing tunnel current, being the movement of electric charges amount, so just can shorten the write time.

In addition, if constitute conductive layer (orlop) FG1 of floating gate electrode FG, then owing to can not produce when constituting this conductive layer (orlop) FG1 and become the depletion layer of problem, so improved the characteristic of memory cell by polysilicon by metal.

In the structure of embodiment according to the present invention, owing to can increase the variations in threshold voltage amplitude of " 0 " unit/" 1 " unit, so for example be effective in many-valuedization.

4, principle of the present invention

The following describes principle of the present invention.

Here, although understand that use can make the situation of the significantly reduced high-k of leakage current (high-k) material as IPD, but need to prove that at first example of the present invention is not limited to the situation that IPD is a high dielectric constant material.

When using high dielectric constant material as IPD, when memory cell is carried out write/erase IPD is applied high electric field, wherein flow through leakage current.This leakage current has just hindered through the movement of electric charges of tunnel dielectric film (with respect to the injection/release of the electric charge of floating gate electrode).

Therefore, just must be with this drain current suppressing to the fiducial value that determines smaller or equal to specification by memory device.

Carry out the result of various researchs, distinguished this fiducial value value of about 1/10 for the electric current that before write operation finishes, flows through tunnel insulator film at once.

For example, when the thickness of tunnel insulator film is that about 7.5nm, coupling ratio β are about 0.6 the time, the effective electric field that applies on IPD is about 19M (mega) V/cm.Fiducial value in the case is about 5 * 10 ^-6A/cm ², the IPD leakage current density of allowing becomes the value smaller or equal to this value.Effective electric field " surface density/the SiO of electric charge ₂Dielectric constant " expression.

Here, as IPD, because at present stage hafnium aluminate (HfAlO for example _x) be strong candidate materials, so adopt hereinafter the mos capacitance device of hafnium aluminate as gate insulating film experimentized.

As sample, with the hafnium aluminate (HfAlO of thickness for about 20nm _x) as gate insulating film, as parameter, the grid voltage that applies negative polarity is estimated leakage current-voltage characteristic with the kind of material that constitutes gate electrode.

Figure 11 shows the leakage current-voltage characteristic as evaluation result.

Hence one can see that, and leakage current changes according to the work function of gate electrode.For example, as gate electrode, as the n that uses work function for about 4eV ⁺During the type polysilicon, the leakage current density among the effective electric field 19MV/cm just becomes about 5 * 10 ^-5A/cm ²

Have again, using work function and n as gate electrode ⁺Under the situation of the aluminium that the work function of type polysilicon is worth much at one, also can obtain result much at one.

On the other hand, as gate electrode, when using the molybdenum of the not enough about 5eV of work function, the leakage current density in effective electric field 19MV/cm just becomes about 2 * 10 ^-7A/cm ²

So, bigger by the work function that makes gate electrode than the electron affinity of Semiconductor substrate (comprising trap), can reduce leakage current, and leakage current can be reduced to smaller or equal to by the desired fiducial value of the specification of memory device.

In addition, when the grid voltage that applies positive polarity is estimated leakage current-voltage characteristic (other sundries is identical with above-mentioned condition), leakage current density and do not rely on the material that constitutes gate electrode as can be known.

In the case, the leakage current density among the effective electric field 19MV/cm is not about 6 * 10 by the material that constitutes gate electrode with regard to not depending on ^-5A/cm ²

Result when this value and front apply the grid voltage of negative polarity on polygate electrodes much at one.There is not the effect that reduces leakage current by the work function of controlling the material that constitutes gate electrode this moment.

According to above-mentioned experimental result, the work function of the gate electrode by making the cathode side that injects electronics is bigger than the electron affinity (energy difference from the conduction band bottom to vacuum level) of the conduction band of Semiconductor substrate, be reduced in the leakage current that flows among the IPD (for example, high dielectric constant material).

Therefore, in repeating the Nonvolatile semiconductor memory device of write/erase, in floating gate electrode or the control grid electrode any, the preferred material that uses with big work function.

But, under the situation of NAND type flash memory, preferably floating gate electrode and control grid electrode the two all constitute by material with big work function.

This is because in NAND type flash memory, write together and wipe by making the FN tunnel current flow through tunnel insulator film.In addition, though inject the minimizing effect that can realize leakage current under the situation of the material that side (cathode side) existence has big work function at the electronics of IPD, but in NAND type flash memory, according to writing and wiping, the floating gate electrode electrode side of IPD becomes cathode side, and perhaps the control grid electrode side of IPD becomes cathode side.

As mentioned above, as IPD, relative dielectric constant is the hafnium aluminate (HfAlO in 15～30 scopes _x) be strong candidate materials.

Its reason is because relative dielectric constant is suitably high and compatible good with silicon technology.

Here, it should be noted that when the relative dielectric constant of IPD and cross when low, just can not obtain the effect that leakage current reduces, otherwise when the relative dielectric constant of IPD was too high, the interference between adjacent two memory cell became greatly.

Thus, as IPD, above-mentioned hafnium aluminate (HfAlO _x) certainly be fit to, the material that is in 15～30 scopes of relative dielectric constant also is fit in addition.

As aforesaid material, there be oxide, nitride or the nitrogen oxide of the material that contains at least a element that is selected from Al, Hf, La, Y, Ce, Ti, Zr, Si.

Thus, the work function of the gate electrode by making the cathode side that electronics injects is bigger than the electron affinity of the conduction band of Semiconductor substrate, can be reduced in the leakage current that flows among the IPD.

But, require the work function of floating gate electrode to remain on the size of the electron affinity degree of Semiconductor substrate.

Its reason is because though in order to eliminate charge stored in floating gate electrode, electric charge is moved to raceway groove from floating gate electrode process of passing through tunnel dielectric film, when the work function of floating gate electrode was big, this moved and just becomes difficult.

Therefore, about floating gate electrode, adopt and to contain at the material with big work function of IPD side configuration with at the stacked structure of the material with little work function of tunnel insulator film side configuration.

In addition, it is also very important not produce the electric capacity this point that is caused by depletion layer in the inside of floating gate electrode.This is because when producing electric capacity because of this depletion layer, will reduce the coupling ratio β of memory cell, and make the write/erase deterioration in characteristics.

A kind of method that does not produce the electric capacity that depletion layer thus causes is to constitute floating gate electrode by metal.

In addition, also have a kind of method, make floating gate electrode become metal and the stacked structure that contains the conductive semiconductor material of dopant (impurity) exactly.The conductive semiconductor material is the material based on silicon, is silicon for example, adds the material of germanium etc. in silicon.

According to a kind of method in back, because the material that contacts with tunnel insulator film is the conductive semiconductor material, so the reliability of tunnel insulator film just can not deterioration.

But, when between metal and conductive semiconductor material, forming Schottky barrier,, will reduce the coupling ratio β of memory cell at conductive semiconductor material internal expansion depletion layer.

A scheme of head it off is to constitute the metal that forms floating gate electrode by multiple material.

For example, floating gate electrode contains the conductive semiconductor material that contacts with tunnel insulator film, the material with little work function of conductive semiconductor material side and the material with big work function of IPD side.

But, the multiple material as metal is all had than the big work function of conductive semiconductor material work function.

Thus, because the work function difference that is produced between a plurality of conductive layers in floating gate electrode, each metal in high lattice ion density becomes each other greatly, diminishes between metal and conductive semiconductor material, so the depletion layer in the conductive semiconductor material just can not stretch, can not reduce yet the coupling ratio β of memory cell on a large scale.

In addition, also having a kind of scheme is to make the work function of metal and dopant (impurity) concentration of conductive semiconductor material remain suitable relation.

About this point, the result who utilizes simulation to study is set at value more than or equal to 4.4eV by the work function with the metal in the floating gate electrode as can be known, and dopant (impurity) concentration of conductive semiconductor material is set at more than or equal to 5 * 10 ¹⁹Cm ^-3Value, just can suppress the decline of coupling ratio β.

The details of simulation in this research below is described.

As shown in Figure 12, suppose the memory cell structure of one dimension, simultaneous solution Poisson's equation formula and electric current continous way, the threshold voltage that calculates memory cell is over time.

In this calculated, the metal/Schottky barrier at polysilicon interface had increased the thickness of tunnel insulator film in fact, and the leakage current of IPD then depends on the work function of the metal of cathode electrode side.

In addition, the electric current that flows in tunnel insulator film uses the empirical formula of FN (Fowler-Nordheim) tunnel current.

Employed memory cell is by constituting with the lower part in this simulation: the thickness on the p type silicon substrate is the SiO of about 7.5nm ₂Film; Floating gate electrode on it; Thickness on it is about 20 IPD (for example, HfAlO for about 25nm and relative dielectric constant _x); With and on control grid electrode.

The coupling ratio β of this structure is 0.6.This memory cell structure appears in the later device of the equal proportion rule of 55nm usually.

For this memory cell structure, calculate when applying 19V as control-grid voltage threshold voltage over time.

Figure 13 shows its result of calculation.

In the figure, though relatively show the situation (◆) and the situation (■) of not considering the leakage current of IPD of the leakage current of considering IPD, as can be known, when producing leakage current in IPD, threshold voltage can not change to stationary value or more than the stationary value.

This stationary value has provided the index of the write capability of memory cell.

Therefore, how the offset Vth of investigation threshold voltage when the work function of floating gate electrode produces various the variation changes.

As shown in Figure 14, owing to as the principal element that determines Δ Vth, have these two factors of leakage current and Schottky barrier electric capacity, and bring reciprocal effect, so just must the investigation optimum condition.

Figure 15 shows gathering of analog result.

Here, the work function of threshold shift Δ Vth " datum mark " expression floating gate electrode is the n of 4.0eV ⁺The situation of type polysilicon under the situation that can obtain greater than the threshold shift of this datum mark, is judged as the write diagnostics that improves memory cell.

According to this result of calculation, following as can be known situation.

The first, whether threshold shift Δ Vth widely depends on dopant (impurity) concentration of polysilicon greater than datum mark.If dopant (impurity) concentration is more than or equal to 5 * 10 ¹⁹Cm ^-3, the offset Vth of threshold voltage just can not be lower than datum mark.

In addition, with this understanding,, just can make leakage current, demonstrate the improvement of write diagnostics smaller or equal to fiducial value when the work function of floating gate electrode during more than or equal to 4.4eV.

Therefore, as summary, about floating gate electrode, preferably dopant (impurity) concentration of the conductive semiconductor material of tunnel insulator film side is more than or equal to 5 * 10 ¹⁹Cm ^-3, the work function of the metal of IPD side is more than or equal to 4.4eV.

Sum up effect of the present invention below.

By between floating gate electrode and IPD, disposing the big conductive material of work function at the interface, can suppress to discharge to control grid electrode the phenomenon of electronics from floating gate electrode.

In addition, by between control grid electrode and IPD, disposing the big conductive material of work function at the interface, can suppress to inject to floating gate electrode the phenomenon of electronics from control grid electrode.

Therefore, can be reduced in leakage current when carrying out important write/erase in the operation of flash memory.

In addition, if make between floating gate electrode and the tunnel insulator film at the interface work function and n ⁺At the interface work function is identical between type polysilicon and the silicon oxide film, or remains and its same degree, and the tunnel current in the time of just flash memory being wiped reduces.

And, if the part that contacts with the tunnel insulator film of floating gate electrode is a metal material, just can below floating gate electrode, not produce depletion layer, thereby improve the write/erase characteristic.

As mentioned above, if reduce the leakage current of IPD, then owing to can increase the space (poor) of threshold voltage of the memory cell of write state and erase status, so can utilize many-valuedization of this difference realization flash memory.

5, execution mode

(1) first execution mode

Figure 16 shows the Nonvolatile semiconductor memory device relevant with first execution mode.

In order to prevent in IPD (for example, high-k (high-k) material), to produce leakage current, effectively adopt the structure of the material clamping IPD that utilizes big work function, for example " metal (CG)/insulator (high-k)/metal (FG) structure ".

But,, must adopt " polysilicon (FG)/insulator (T-ox.) structure " that for example use the conductivity polysilicon that contains n type impurity as floating gate electrode in order to ensure the reliability of the tunnel insulator film between raceway groove and the floating gate electrode (gate insulating film).

Therefore, in the first embodiment, floating gate electrode adopts the stacked structure of the metal (metal1) contain the conductivity polysilicon (poly-Si) that contacts with tunnel insulator film (T-ox.) and to contact with IPD (for example, high-k (high-k) material).

This metal (metal1) is selected from the material of the bigger work function of work function 4.0eV with the conductivity polysilicon that than conductivity polysilicon (poly-Si), for example contains n type impurity.In addition, preferably the work function of metal (metal1) more than or equal to 4.4eV, smaller or equal to 5.2eV.

In addition, as control grid electrode, adopt metal structure.

For example, with regard to control grid electrode, adopt the low resistive metal (metal2) of having considered the cloth line resistance; And between IPD and low resistive metal (metal2) configuration, stacked structure with metal (metal3) of the work function bigger than the work function 4.0eV of the conductivity polysilicon that contains n type impurity.

In addition, metal (metal3) also can have than the bigger work function of low resistive metal (metal2).

Thus, realized that not only increase has the coupling ratio β of the memory cell of floating gate electrode and control grid electrode, and reduced the leakage current when the write/erase of the middle generation of IPD (for example, high-k (high-k) material).

In addition, if metal (metal3) and metal (metal1) are formed by same material, just can simplify technology and can reduce manufacturing cost.

(2) second execution modes

Figure 17 shows the Nonvolatile semiconductor memory device relevant with second execution mode.

In second execution mode, floating gate electrode adopts and to contain the conductivity polysilicon (poly-Si) that contact with tunnel insulator film (T-ox.), and the metal (metal1-1) that contacts of IPD (for example, high-k (high-k) material) and the stacked structure of the metal (metal1-2) between conductivity polysilicon (poly-Si) and the metal (metal1-1).

Second execution mode is characterised in that the metal that disposes is multilayer (in the example at Figure 17, being 2 layers) between conductivity polysilicon (poly-Si) and IPD.

The work function of the metal between polysilicon (poly-Si) and the IPD (metal1-1, metal1-2) is along with increasing successively towards IPD from conductivity polysilicon (poly-Si).The work function of these metals (metal1-1, metal1-2) is selected from the material of the bigger work function of work function 4.0eV with the conductivity polysilicon that than conductivity polysilicon (poly-Si), for example contains n type impurity.

In addition, preferably the work function of metal (metal1-1, metal1-2) is more than or equal to 4.4eV, smaller or equal to 5.2eV.

Thus, reduce the work function difference between conductivity polysilicon (poly-Si) and the metal (metal1-2), prevent the decline of the coupling ratio β that causes because of the Schottky barrier that produces at the interface at both, thereby can improve the characteristic of memory cell.

In addition, identical as control grid electrode with first execution mode, adopt metal structure.

For example, for control grid electrode, adopt the low resistive metal (metal2) of having considered the cloth line resistance; Stacked structure configuration, that have the metal (metal3) of the work function bigger between IPD and low resistive metal (metal2) than the work function 4.0eV of the conductivity polysilicon that contains n type impurity.

Have again,, just can simplify technology and can reduce manufacturing cost if metal (metal3) and metal (metal1-1) are made of same material.

(3) the 3rd execution modes

Figure 18 shows the Nonvolatile semiconductor memory device relevant with the 3rd execution mode.

In the 3rd execution mode, floating gate electrode is become contain the metal (metal1) that contacts with tunnel insulator film (T-ox.) and with the stacked structure of the metal (metal2) of IPD (for example, high-k (high-k) material) contact.

The work function of metal (metal1) is the value more than or equal to the work function of silicon, and the work function of metal (metal2) is bigger than the work function of metal (metal1).

The work function of metal (metal1, metal2) is selected from the material that for example has than the bigger work function of work function 4.0eV of the conductivity polysilicon that contains n type impurity.In addition, preferably the work function of metal (metal1, metal2) is more than or equal to 4.4eV, smaller or equal to 5.2eV.

In addition, as control grid electrode, adopt metal structure.

For example, for control grid electrode, adopt considered the low resistive metal (metal3) of cloth line resistance and between IPD and low resistive metal (metal3) configuration, have a stacked structure than the metal (metal4) of the bigger work function of work function of metal (metal1).In addition, metal (metal4) also can have than the bigger work function of low resistive metal (metal3).

In addition, owing to floating gate electrode only is made of metal, so just can not produce the depletion layer that when floating gate electrode is the conductivity polysilicon, becomes problem.Thus, can improve the characteristic of memory cell.

Have again,, just can simplify technology, reduce manufacturing cost if metal (metal4) and metal (metal2) are made of same material.

(4) the 4th execution modes

Figure 19 shows the Nonvolatile semiconductor memory device relevant with the 4th execution mode.

The 4th execution mode is the application examples of first execution mode.

The 4th execution mode is characterised in that, disposes metal (metal4) between tunnel insulator film (T-ox.) and conductivity polysilicon (poly-Si), and others are identical with first execution mode.

Metal (metal4) has prevented the memory cell characteristics deterioration that depletion layer caused because of generation in conductivity polysilicon (poly-Si).

Do not limit the work function of metal (metal4) especially.For example, metal (metal4) also can be than conductivity polysilicon (poly-Si), for example to contain the work function 4.0eV of conductivity polysilicon of n type impurity bigger.

In this structure, also can realize increasing the coupling ratio β of memory cell, and can reduce the leakage current when the write/erase of the middle generation of IPD (for example, high-k (high-k) material).

(5) the 5th execution modes

Figure 20 shows the Nonvolatile semiconductor memory device relevant with the 5th execution mode.

The 5th execution mode is the application examples of second execution mode.

The 5th execution mode is characterised in that, disposes metal (metal1-3) between tunnel insulator film (T-ox.) and conductivity polysilicon (poly-Si), and others are identical with second execution mode.

Metal (metal1-3) has prevented the memory cell characteristics deterioration that depletion layer caused because of generation in conductivity polysilicon (poly-Si).

Do not limit the work function of metal (metal1-3) especially.For example, metal (metal1-3) also can be than conductivity polysilicon (poly-Si), for example to contain the work function 4.0eV of conductivity polysilicon of n type impurity bigger.

(6) other

The floating gate electrode of the unqualified memory cell of example of the present invention and the shape of control grid electrode.

For example, shown in Figure 21 (b), also can be that floating gate electrode FG is outstanding from element separation insulating barrier STI, control grid electrode CG covers the structure of the part of floating gate electrode FG side.

Also can be on element separation insulating barrier STI, there being the gull wing of the end of floating gate electrode FG.

In addition, shown in Figure 21 (c), also can be the consistent in fact structure of upper surface of upper surface with the element separation insulating barrier STI of floating gate electrode FG.

Have, the section shape of the column direction shown in Figure 21 (a) is identical for Figure 21 (b) and structure (c) again.

About constituting the polysilicon (poly-Si) of floating gate electrode, may instead be the material that TaSiN etc. contains metal.

6, material example

In the Nonvolatile semiconductor memory device relevant with example of the present invention, the floating gate electrode on the tunnel insulator film is made of a plurality of first conductive layers.

The orlop of a plurality of first conductive layers (contact layer) with tunnel insulator film by contain be selected among Si, Ta, Hf, Zr, Al, the Ti one or more the material of element or nitride, carbide, silicide, silicon nitride or the silicon-carbon nitride of these materials constitute.

For example, the orlop of a plurality of first conductive layers is made of Si, Hf, Zr, Al, Ti, Ta, TaSix, TaC, TaN, TiN, TaSiN, HfSix, HfSiN etc.

The orlop of a plurality of first conductive layers is under the situation of silicide, and the composition of silicide is the atomicity of the atomicity of Si more than or equal to metallic atom.

For example, under the situation that the orlop of a plurality of first conductive layers is made of Silicon-rich silicide MSix, x 〉=1.Wherein, M represents metal.

The superiors of a plurality of first conductive layers (contact with IPD layer) are made of following material: contain the material that is selected from one or more elements among Pt, W, Ir, Ru, Re, Mo, Ti, Ta, Ni, the Co; The silicide that contains the material that is selected from one or more elements among Pt, W, Ti, Ta, Ni, the Co; The carbide that contains the material that is selected from one or more elements among W, Ti, the Ta; The nitride that contains the material that is selected from one or more elements among W, Mo, Ti, the Ta; The silicon nitride that contains the material of Ti; The oxide that contains the material that is selected from one or more elements among Ir, the Ru; Or their compound or mixture.

For example, the superiors of a plurality of first conductive layers are by Pt, W, Ir, IrO ₂, Ru, RuO ₂, Re, TaC, TaN, Mo, MoNx, MoSix, TiN, TiC, TiSiN, TiCN, Ni, NixSi, PtSix, WC, formations such as WN, WSix.

The superiors of a plurality of first conductive layers are under the situation of silicide, and the composition of silicide is that the atomicity of metallic atom is more than or equal to the Si atomicity.

For example, under the situation that the superiors of a plurality of first conductive layers are made of rich metal silicide MSix, x≤1.Wherein, M represents metal.

Control grid electrode or contain its orlop under the situation of a plurality of second conductive layers (layer that contacts with IPD) at control grid electrode and constitute: contain the material that is selected from one or more elements among Pt, W, Ir, Ru, Re, Mo, Ti, Ta, Ni, the Co by following material; The silicide that contains the material that is selected from one or more elements among Pt, W, Ti, Ta, Ni, the Co; The carbide that contains the material that is selected from one or more elements among W, Ti, the Ta; The nitride that contains the material that is selected from one or more elements among W, Mo, Ti, the Ta; The silicon nitride that contains the material of Ti; The oxide that contains the material that is selected from one or more elements among Ir, the Ru; Or their compound or mixture.

For example, control grid electrode or contain under the situation of a plurality of second conductive layers its orlop at control grid electrode by Pt, W, Ir, IrO ₂, Ru, RuO ₂, Re, TaC, TaN, Mo, MoNx, MoSix, TiN, TiC, TiSiN, TiCN, Ni, NixSi, PtSix, WC, formations such as WN, WSix.

The orlop of a plurality of second conductive layers is under the situation of silicide, and the composition of silicide is that the atomicity of metallic atom is more than or equal to the Si atomicity.

For example, under the situation that the orlop of a plurality of second conductive layers is made of rich metal silicide MSix, x≤1.Wherein, M represents metal.

The orlop of a plurality of second conductive layers of control grid electrode also can be made of the superiors' identical materials with a plurality of first conductive layers of floating gate electrode.

IPD is oxide, nitride or the nitrogen oxide that contains the material that is selected from least a element among Al, Hf, La, Y, Ce, Ti, Zr, the Si.

Though think that IPD is that high-k (high-k) material or the laminated construction that contains this material are effectively, is not limited to this.For example, also can be silica, silicon nitride, silicon oxynitride or their laminated construction.

But, in IPD, use under the situation of high dielectric constant material, preferably, IPD contains the layer more than three layers or three layers, in the layer more than three layers or three layers with the discontiguous layer of floating gate electrode and control grid electrode both for containing oxide, nitride or the nitrogen oxide of the material that is selected from least a element among Al, Hf, La, Y, Ce, Ti, Zr, the Si.

This is because when only constituting IPD by high dielectric constant material, can have the possibility that produces the retention performance deterioration because of carrier capture and release.By utilizing the dielectric film clamping high dielectric constant material of oxide-film and nitride film etc., can improve retention performance.

Particularly, as IPD, adopt SiO ₂/ high dielectric constant material/SiO ₂, SiON/ high dielectric constant material/SiON, Si ₃N ₄/ SiO ₂/ high dielectric constant material/SiO ₂/ Si ₃N ₄, Si ₃N ₄/ SiON/ high dielectric constant material/SiON/Si ₃N ₄Deng laminated construction.

In addition, TaC and TaN can change work function by its manufacture method in wide region.Therefore, for example be listed as the material that can use in the two in the orlop of a plurality of first conductive layers of floating gate electrode and the superiors.

7, embodiment

(1) first embodiment

Figure 22 shows the structure of the memory cell relevant with first embodiment.

On p type silicon substrate, form silicon oxynitride film (SiON) as tunnel insulator film (gate insulating film).On silicon oxynitride film, form TaSiN as the conductive semiconductor material.On TaSiN, form WN as metal material.Floating gate electrode FG is made of the lamination of TaSiN and WN.

On floating gate electrode FG, high-k (high-k) material, the HfAlOx that form as IPD (form: Hf/ (Hf+Al)=0.6).On HfAlOx, form the control grid electrode CG that the lamination by WN and W constitutes.

Here, be value in for example about 7～8nm scope with the thickness setting of SiON, the thickness of TaSiN and WN for example all is set at value in about 30～60nm scope.With the HfAlOx thickness setting is value in for example about 20～30nm scope.

Here, must be noted that the gross thickness of each material of formation floating gate electrode FG is restricted because of the size of cell transistor.That is, in order to suppress the phase mutual interference between the unit, the gross thickness that just must make each material that constitutes floating gate electrode FG is all little with respect to the width of cell transistor and in the length any one.

In addition, for work function, TaSiN is about 4.0eV, and WN is about 4.8～4.9eV, and W is about 4.5eV.The resistivity of W is littler than the resistivity of WN.

In this example, though constituted the layer that contacts with tunnel insulator film among 2 layers of floating gate electrode FG by TaSiN, but in addition, the metal material that can also use TaN, TiN, W, WSi etc. to be suitable for the transistorized metal gate material of n raceway groove MIS or have near the work function of silicon forbidden band central authorities.

In addition, though use WN as the metal material that contacts with IPD, but in addition, can also use Ru, TaC etc. to be suitable for transistorized metal gate material of p raceway groove MIS or material in elements such as Au, Pt, Co, Ni, Pd, Te, Mo, Ir, Hf, Zr, Y, La or compound, that have the work function bigger than Si forbidden band central portion.

In addition, in this example, though use the hafnium aluminate as high-k (high-k) material, in the case, when it being formed Hf/ (Hf+Al) and be set at value in about 0.3～0.8 scope, can obtain good leakage current characteristic and materials processing.

As high dielectric constant material, except HfAlO _xOutside, the oxide that contains at least a or more than one elements among Al, Hf, La, Y, Ce, Ti, Zr, the Si, nitrogen oxide, Si oxide etc. can be used, and the lamination of these materials can be used.

As IPD, can be used in combination the dielectric film of high dielectric constant material and silicon oxide film, silicon nitride film etc.For example, IPD also can be by Si ₃N ₄/ SiO ₂/ high dielectric constant material/SiO ₂/ Si ₃N ₄, Si ₃N ₄/ SiON/ high dielectric constant material/SiON/Si ₃N ₄Deng stacked structure constitute.In addition, IPD and floating gate electrode FG reach IPD and control grid electrode CG at the interface at the interface, also can have the boundary layer that constitutes by as thin as a wafer insulating material respectively.

Have again,, except silicon oxynitride film (SiON), also can use SiO as tunnel insulator film ₂/ Si ₃N ₄/ SiO ₂, Si ₃N ₄/ SiO ₂/ Si ₃N ₄Deng stacked structure, also have the stacked structure that constitutes by high dielectric constant material and silicon insulating film.

Manufacture method about the memory cell of Figure 22 can directly be suitable for Fig. 2～manufacture method illustrated in fig. 6 basically.

Hereinafter, the step different with Fig. 2～Fig. 6 only is described.

About the formation of floating gate electrode FG, use the ALD method.

At first, use with Ta[N (CH ₃) ₂] ₅, NH ₃, SiH ₄Be the ALD method of unstrpped gas, become the TaSiN of the lower floor of floating gate electrode FG.After this, use with WF ₆, NH ₃Be the ALD method of unstrpped gas, become the WN on the upper strata of floating gate electrode FG.

Then, use with Al (CH ₃) ₃, Hf[N (CH ₃) ₂] ₄And H ₂O is the ALD method of unstrpped gas, forms HfAlO in the atmosphere of 250 ℃ of temperature _xAfter this, at 850 ℃, O ₂, 130Pa atmosphere in anneal.

About the formation of control grid electrode CG, use ALD method and these 2 kinds of methods of CVD method.

At first, use with WF ₆, NH ₃Be the ALD method of unstrpped gas, become the WN of the lower floor of control grid electrode CG.After this, use with W (CO) ₆Be the CVD method of unstrpped gas, become the W on the upper strata of control grid electrode CG.

Yet, nothing but an example, can also adopt other manufacture methods to form the memory cell of Figure 22 in the manufacture method shown in this.

For example,, also can use other gases, about the also not restriction especially of use respectively of ALD method and CVD method about employed unstrpped gas in the ALD method.

In addition, the method that can also utilize methods such as sputtering method outside ALD method and the CVD method, vapour deposition method, laser ablation (ablation) method, MBE method and make up these methods waits and forms floating gate electrode FG, control grid electrode CG and IPD.

(2) second embodiment

Figure 23 shows the structure of the memory cell relevant with second embodiment.

On p type silicon substrate, form silicon oxynitride film (SiON) as tunnel insulator film (gate insulating film).On silicon oxynitride film, form the polysilicon (n that contains n type impurity as the conductive semiconductor material ⁺Poly-Si).At n ⁺On the poly-Si, form TiN and WN as metal material.Floating gate electrode FG is by n ⁺The lamination of poly-Si, TiN and WN constitutes.

On floating gate electrode FG, the HfAlOx that forms as high-k (high-k) material (forms: Hf/ (Hf+Al)=0.6).HfAlOx works as IPD.On HfAlOx, form the control grid electrode CG that the lamination by WN and W constitutes.

Here, be value in for example about 7～8nm scope with the thickness setting of SiON, with n ⁺The thickness setting of poly-Si is for example about 30nm, and the thickness of TiN and WN for example all is set at value in about 20～30nm scope.With the thickness setting of HfAlOx is value in for example about 20～30nm scope.

In addition, for work function, n ⁺Poly-Si is about 4.0eV, and TiN is about 4.6eV, and WN is about 4.8～4.9eV, and W is about 4.5eV.The resistivity of W is littler than the resistivity of WN.

In this example, though constitute the lower floor of the metal material in the floating gate electrode FG by TiN, but in addition, can also use having near the work function the central authorities of Si forbidden band and being suitable for the transistorized metal gate material of n raceway groove MIS etc. of TaN etc. for what the diffusion of atom had the material of block and had a work function littler than near the work function the central authorities of Si forbidden band.

In addition, though use WN as the metal material that contacts with IPD, but in addition, can also use the material that is suitable for the transistorized metal gate material of p raceway groove MIS or in elements such as Au, Pt, Co, Ni, Pd, Te, Mo, Ir, Hf, Zr, Y, La or compound, has the work function bigger of Ru, TaC etc. than Si forbidden band central portion.

In addition, in this example,, in the case, when it being formed Hf/ (Hf+Al) and be set at value in about 0.3～0.8 scope, can obtain good leakage current characteristic and materials processing though use the hafnium aluminate as high-k (high-k) material.

As high dielectric constant material, except HfAlOx, the oxide that contains at least a or more than one elements among Al, Hf, La, Y, Ce, Ti, Zr, the Si, nitrogen oxide, Si oxide etc. can be used, and the lamination of these materials can be used.

As IPD, can also be used in combination high dielectric constant material and silicon insulating film.In addition, IPD and floating gate electrode FG reach IPD and control grid electrode CG at the interface at the interface, also can have the boundary layer that constitutes by as thin as a wafer insulating material respectively.

Manufacture method about the memory cell of Figure 23 can directly be suitable for Fig. 2～manufacture method illustrated in fig. 6 basically.

Hereinafter, the step different with Fig. 2～Fig. 6 only is described.

About the formation of floating gate electrode FG, use the CVD method.

At first, use the CVD method, in the about 620 ℃ atmosphere of temperature, become floating gate electrode FG lower floor doping the n of phosphorus (P) ⁺Poly-Si.

After this, use with TiCl ₄And NH ₃Be the CVD method of unstrpped gas, in the about 500 ℃ atmosphere of temperature, form and be configured in n ⁺The metal material TiN of poly-Si side.Then, use with W (CO) ₆And NH ₃Be the CVD method of unstrpped gas, in the about 450 ℃ of atmosphere of temperature, form the metal material WN that is configured in the HfAlOx side.

Then, use with Al (CH ₃) ₃, Hf[N (CH ₃) ₂] ₄And H ₂O is the ALD method of unstrpped gas, in temperature is 250 ℃ atmosphere, forms HfAlOx.After this, at 850 ℃, O ₂, 130Pa atmosphere in anneal.

About the formation of control grid electrode CG, also use the CVD method.

At first, use with W (CO) ₆And NH ₃Be the CVD method of unstrpped gas, in the about 450 ℃ atmosphere of temperature, on HfAlOx, become the WN of the lower floor of control grid electrode CG.Then, use with W (CO) ₆Be the CVD method of unstrpped gas, in the about 450 ℃ atmosphere of temperature, on WN, become the W on the upper strata of control grid electrode CG.

Have, the manufacture method of being showed also can adopt other manufacture methods to form the memory cell of Figure 23 nothing but an example here again.

For example,, can also use other gases, also can use the ALD method to come replaced C VD method about employed unstrpped gas in the CVD method.

In addition, the method that can also utilize methods such as sputtering method outside CVD method and the ALD method, vapour deposition method, laser ablation method, MBE method and make up these methods waits and forms floating gate electrode FG, control grid electrode CG and IPD.

(3) the 3rd embodiment

Figure 24 shows the structure of the memory cell relevant with the 3rd embodiment.

On p type silicon substrate, form silicon oxynitride film (SiON) as tunnel insulator film (gate insulating film).On silicon oxynitride film, form the polysilicon (n that contains n type impurity as the conductive semiconductor material ⁺Poly-Si).At n ⁺On the poly-Si, form WN as metal material.Floating gate electrode FG is by n ⁺The lamination of poly-Si and WN constitutes.

Here, be value in for example about 7～8nm scope with the thickness setting of SiON, with n ⁺The thickness setting of poly-Si is for example about 60nm, is value in for example about 20～30nm scope with the thickness setting of WN.With the thickness setting of HfAlOx is value in for example about 20～30nm scope.

Have again, about the thickness of each material layer of constituting floating gate electrode since the layer that contact with tunnel insulator film become main stored charge layer, so preferably the thickness of this layer is little unlike the thickness of other layers.Especially, shown in this example, be under the situation of semi-conducting material at the layer that contacts with tunnel insulator film, this consideration is essential.

In addition, for work function, n ⁺Poly-Si is about 4.0eV, and WN is about 4.8～4.9eV, and W is about 4.5eV.The resistivity of W is littler than the resistivity of WN.

In this example, though constitute metal material in the floating gate electrode FG by WN, but in addition, can also use work functions such as Ru, TaC to be near being suitable for the transistorized metal gate material of p raceway groove MIS or using as work function approximately more than or equal to the metal material of 4.4eV and have TiN (about 4.6eV), the TaN (about 4.4eV) etc. of block for the diffusion of atom about 5eV.

As the metal material in the floating gate electrode FG, because work function is for getting final product more than or equal to 4.4eV approximately, so can use among the metallic compound of for example Au (about 5.1eV), Pt (about 5.3eV), Co (about 5.0eV), Ni (about 5.0eV), Pd (about 5.2eV), Mo (about 4.9eV), W metals such as (about 4.5eV) or these metals work function more than or equal to the material of 4.4eV.

As high dielectric constant material, except that HfAlOx, also can use the oxide that contains at least a or more than one elements among Al, Hf, La, Y, Ce, Ti, Zr, the Si, nitrogen oxide, Si oxide etc., and can use the lamination of these materials.

As IPD, can be used in combination high dielectric constant material and silicon insulating film.In addition, IPD and floating gate electrode FG reach IPD and control grid electrode CG at the interface at the interface, also can have the boundary layer that constitutes by as thin as a wafer insulating material respectively.

Manufacture method about the memory cell of Figure 24 can directly be suitable for Fig. 2～manufacture method illustrated in fig. 6 basically.

Hereinafter, the step different with Fig. 2～Fig. 6 only is described.

At first, use the CVD method, in the about 620 ℃ atmosphere of temperature, become floating gate electrode FG lower floor doping the n of phosphorus (P) ⁺Poly-Si.At this moment, adjust as the silane of unstrpped gas and the ratio of hydrogen phosphide, so that n ⁺Phosphorus concentration among the poly-Si becomes about 1 * 10 ²⁰Cm ^-3

In addition, as deposit n ⁺The method of poly-Si, in addition, can also employing order (sequential) method.The method alternately repeats to utilize separately SiH ₄Un-doped polysilicon film forming and utilize separately the PH of dilution ₃Phosphorus absorption, concentration of dopant and thickness that can accurate control floating gate electrode FG.

After this, use with W (CO) ₆And NH ₃Be the CVD method of unstrpped gas, in the about 450 ℃ atmosphere of temperature, at n ⁺The last formation of poly-Si WN.

Then, use with Al (CH ₃) ₃, Hf[N (CH ₃) ₂] ₄And H ₂O is the ALD method of unstrpped gas, in temperature is 250 ℃ atmosphere, forms HfAlOx.After this, at 850 ℃, O ₂, anneal in the 130Pa atmosphere.

After this, use with W (CO) ₆And NH ₃Be the CVD method of unstrpped gas, in temperature is about 450 ℃ atmosphere, on HfAlOx, become the WN of control grid electrode CG lower floor.Then, use with W (CO) ₆As the CVD method of unstrpped gas, be in about 450 ℃ of atmosphere in temperature, on WN, become the W on control grid electrode CG upper strata.

Have, the manufacture method of being showed can also adopt other manufacture methods to form the memory cell of Figure 24 nothing but an example here again.

(4) the 4th embodiment

Figure 25 shows the structure of the memory cell relevant with the 4th embodiment.

On p type silicon substrate, form silicon oxynitride film (SiON) as tunnel insulator film (gate insulating film).On silicon oxynitride film, form the polysilicon (n that contains n type impurity as the conductive semiconductor material ⁺Poly-Si).At n ⁺On the poly-Si, form WSi as metal material.Floating gate electrode FG is by n ⁺The lamination of poly-Si and WSi constitutes.

On floating gate electrode FG,, form high-k (high-k) material, HfAlOx (composition: Hf/ (Hf+Al)=0.6) as IPD.On HfAlOx, form the control grid electrode CG that the lamination by WSi and W constitutes.

Here, be value in for example about 7～8nm scope with the thickness setting of SiON, with n ⁺The thickness setting of poly-Si is for example about 60nm, and the thickness setting of WSi is for example about 50nm.With the thickness setting of HfAlOx is value in for example about 20～30nm scope.

In addition, for work function, n ⁺Poly-Si is about 4.0eV, and WSi is about 4.4～4.6eV, and W is about 4.5eV.The resistivity of W is littler than the resistivity of WSi.

In this example, though constitute metal material in the floating gate electrode FG, in addition, noting to use CoSi on the stable on heating basis by WSi ₂, other silicide material such as NiSi.

As high dielectric constant material, except HfAlOx, also can use the oxide that contains at least a or more than one elements among Al, Hf, La, Y, Ce, Ti, Zr, the Si, nitrogen oxide, Si oxide etc., and can use the lamination of these materials.

Manufacture method about the memory cell of Figure 25 can directly be suitable for Fig. 2～manufacture method illustrated in fig. 6 basically.

Hereinafter, the step different with Fig. 2～Fig. 6 only is described.

At first, use the CVD method, in temperature is about 620 ℃ atmosphere, form n as the Doping Phosphorus (P) of floating gate electrode FG lower floor ⁺Poly-Si.

After this, use with W (CO) ₆For the CVD method of unstrpped gas, at n ⁺On the poly-Si, form W.Then, carry out the annealing first time, W and Si are reacted and the WSi of formation metastable phase, utilize wet treatment to remove unreacted W.Then, carry out the annealing second time, change the WSi of stable phase into.

Then, use the CVD method, in temperature is about 620 ℃ atmosphere, on HfAlOx, form the n of thickness for the Doping Phosphorus (P) of about 50nm ⁺Poly-Si.

After this, use with W (CO) ₆For the CVD method of unstrpped gas, at n ⁺On the poly-Si, with the W of enough thickness formation as low resistive metal.Then, carry out the annealing first time, make W and Si reaction, form the WSi of metastable phase, then, carry out the annealing second time, change the WSi of stable phase into.

In addition, the manufacture method of being showed can also adopt other manufacture methods to form the memory cell of Figure 25 nothing but an example here.

For example, the annealing that is used to form silicide layer (WSi) also can with the source, leak diffusion layer activation annealing integrated.

(5) the 5th embodiment

Figure 26 and Figure 27 show the structure of the memory cell relevant with the 5th embodiment.

The 5th embodiment relates to the unit block (cell unit) of NAND type flash memory.Each memory cell in the unit block has the structure identical with the memory cell of first embodiment.

This element assembly is characterised in that with regard to column direction, as shown in Figure 26, the memory cell series connection connects.In addition, with regard to line direction, have following characteristics: the upper surface of floating gate electrode is almost consistent with the upper surface of element separation insulating barrier (STI), disposes high-k (high-k) material, HfAlOx as IPD on them.

Because under the situation of NAND type flash memory, the miniaturization of memory cell is obvious, so the structure of this unit block is the parasitic capacitance that is used to suppress between the adjacent cells and is produced and obtains one of technology of high coupling ratio.

In addition, about floating gate electrode, in order further to reduce the interference between the adjacent cells, be respectively T at thickness, length and the width of floating gate electrode _FG, L and W situation under, T preferably _FG＜L and T _FG＜W.This is because the thickness T of floating gate electrode _FGThe size of the capacitor that has determined between adjacent cells to be produced.

And, in the memory cell of NAND type flash memory, constitute among a plurality of conductive layers of floating gate electrode, main by the conductive layer that contacts with tunnel insulator film (orlop) stored charge.

Therefore, it is the thickest in these a plurality of conductive layers preferably to constitute the orlop of a plurality of conductive layers of floating gate electrode.

Especially, this condition is to be effective under the situation of conductive semiconductor material at the conductive layer that contacts with tunnel insulator film (orlop).

8, application examples

Example of the present invention has the Nonvolatile semiconductor memory device of the memory cell of stacked gate electrode structure applicable to all.

For example, example of the present invention is in NAND type, NOR type, AND type, DINOR type, the NANO type of the advantage of NOR type and NAND type that merged, has by being otherwise effective technique in the 3Tr-NAND type of 2 structures of selecting a memory cell of transistor clamping etc. in addition.

9, conclusion

Embodiment according to the present invention, even high-k (high-k) material that is used to increase coupling ratio is as IPD, owing to, also can reduce the leakage current that when write/erase, in IPD, flows disposing metal as material between floating gate electrode and the IPD and between control grid electrode and IPD with big work function.

In addition, the leakage current and the raising data that also can realize reducing when reading keep (retention) characteristic etc.

And, for metal with big work function, interim its work function that reduces makes it be suppressed at the depletion-layer capacitance that produces in the floating gate electrode near the work function of polysilicon, can prevent that thus the descend coupling ratio of the memory cell that caused of the current potential that causes because of depletion-layer capacitance from descending.

Thus, embodiment according to the present invention is even make the memory cell miniaturization, also can realize increasing coupling ratio and reduce leakage current simultaneously.

Example of the present invention is not limited to above-mentioned execution mode, is not breaking away within the aim scope of the present invention, can also change and specific each element.In addition, just can constitute various inventions by disclosed multiple inscape in the above-mentioned execution mode of appropriate combination.For example, also can be from above-mentioned execution mode reject several inscapes in disclosed whole inscapes, inscape that also can the different execution modes of appropriate combination.

Claims

1, a kind of Nonvolatile semiconductor memory device is characterized in that, comprising:

The source that in Semiconductor substrate, disposes, leakage diffusion layer; In above-mentioned source, leak first dielectric film that disposes on the raceway groove between the diffusion layer, constitute by tunnel insulator film; The floating gate electrode that on above-mentioned first dielectric film, disposes, contain stacked a plurality of first conductive layers; Second dielectric film that on above-mentioned floating gate electrode, disposes; And the control grid electrode that on above-mentioned second dielectric film, disposes,

With one first conductive layer except the superiors among above-mentioned a plurality of first conductive layers as datum layer, the work function of this datum layer is more than or equal to 4.0eV, the work function of a plurality of first conductive layers that comprise the said reference layer on the said reference layer is along with increasing successively towards above-mentioned second dielectric film

The said reference layer is formed in the orlop in above-mentioned a plurality of first conductive layer and is made of metal or the conductive semiconductor material that contains impurity, and first conductive layer of one deck at least above the said reference layer is made of metal,

Above-mentioned second dielectric film is oxide, nitride or the nitrogen oxide that contains the material that is selected from least a element among Al, Hf, La, Y, Ce, Ti, Zr, the Si.

2, Nonvolatile semiconductor memory device according to claim 1 is characterized in that,

Above-mentioned impurity is n type impurity, and above-mentioned conductive semiconductor material is a polysilicon, and the doping content of said n type impurity is more than or equal to 5 * 10 ¹⁹Cm ^-3

3, Nonvolatile semiconductor memory device according to claim 1 and 2 is characterized in that,

The work function of said reference layer and top first conductive layer of one deck at least thereof is included in the scope of 4.0eV～5.2eV.

4, Nonvolatile semiconductor memory device according to claim 3 is characterized in that,

The work function of first conductive layer of one deck at least above the said reference layer is more than or equal to 4.4eV.

5, according to claim 1 or 2 described Nonvolatile semiconductor memory devices, it is characterized in that,

Above-mentioned control grid electrode is made of the work function electric conducting material bigger than the work function of said reference layer.

6, Nonvolatile semiconductor memory device according to claim 1 and 2 is characterized in that,

Above-mentioned control grid electrode is made of the superiors' identical materials with above-mentioned a plurality of first conductive layers.

7, Nonvolatile semiconductor memory device according to claim 1 and 2 is characterized in that,

Above-mentioned control grid electrode contains stacked a plurality of second conductive layers, and the orlop of above-mentioned a plurality of second conductive layers is made of the work function electric conducting material bigger than the work function of said reference layer.

8, Nonvolatile semiconductor memory device according to claim 7 is characterized in that,

The work function of above-mentioned a plurality of second conductive layers is along with increasing successively towards above-mentioned second dielectric film.

9, Nonvolatile semiconductor memory device according to claim 7 is characterized in that,

The resistivity of above-mentioned a plurality of second conductive layers is along with reducing successively away from above-mentioned second dielectric film.

10, Nonvolatile semiconductor memory device according to claim 7 is characterized in that,

The orlop of above-mentioned a plurality of second conductive layers is made of the superiors' identical materials with above-mentioned a plurality of first conductive layers.

11, Nonvolatile semiconductor memory device according to claim 1 and 2 is characterized in that,

The thickness of above-mentioned floating gate electrode, length and width are respectively T _FG, L and W, and T _FG＜L and T _FG＜W.

12, Nonvolatile semiconductor memory device according to claim 1 and 2 is characterized in that,

The orlop of above-mentioned a plurality of first conductive layers is the thickest in above-mentioned a plurality of first conductive layers.

13, Nonvolatile semiconductor memory device according to claim 1 and 2 is characterized in that,

Above-mentioned second dielectric film is made of the layer more than three layers, is oxide, nitride or the nitrogen oxide that contains the material that is selected from least a element among Al, Hf, La, Y, Ce, Ti, Zr, the Si with the two all discontiguous layer of above-mentioned floating gate electrode and above-mentioned control grid electrode among the above-mentioned layer more than three layers.

14, a kind of Nonvolatile semiconductor memory device is characterized in that, comprising:

The said reference layer is formed in the orlop in above-mentioned a plurality of first conductive layer and constitutes by containing the material that is selected from more than one elements among Si, Ta, Hf, Zr, Al, the Ti or nitride, carbide, silicide, silicon nitride or the silicon-carbon nitride of these materials, and first conductive layer of one deck at least above the said reference layer is made of metal

15, Nonvolatile semiconductor memory device according to claim 14 is characterized in that,

The orlop of above-mentioned a plurality of first conductive layers is a silicide, and the composition of above-mentioned silicide is the atomicity of the atomicity of Si more than or equal to metallic atom.