CN100553098C - Adopt the standard CMOS logic process to realize high withstand voltage rectifier - Google Patents
Adopt the standard CMOS logic process to realize high withstand voltage rectifier Download PDFInfo
- Publication number
- CN100553098C CN100553098C CNB2006100215831A CN200610021583A CN100553098C CN 100553098 C CN100553098 C CN 100553098C CN B2006100215831 A CNB2006100215831 A CN B2006100215831A CN 200610021583 A CN200610021583 A CN 200610021583A CN 100553098 C CN100553098 C CN 100553098C
- Authority
- CN
- China
- Prior art keywords
- grid
- connects
- electric capacity
- rectifier
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
A kind of standard CMOS logic process that adopts is realized high withstand voltage rectifier, it is characterized in that by electric capacity (C1)-electric capacity (C4), nmos pass transistor (T1)-nmos pass transistor (T4), resistance (R
L) wait formation; The present invention by series electrical on the employed transistorized grid of rectifier perhaps the device of class capacitance structure come dividing potential drop to add to voltage on transistorized grid, be used for the realization of the RFID electronic tags of integrated memory based on the non-volatile type that adopts the standard CMOS logic process to realize.Adopt rectifier of the present invention, help integrated memory, and help to reduce the manufacturing and the technology cost of RFID electronic tags based on the non-volatile type that adopts the standard CMOS logic process to realize.
Description
Technical field
The present invention relates to adopt the CMOS logic process of standard to realize high withstand voltage rectifier, especially, as an example, rectifier of the present invention can be used to adopt in the electronic tag or intelligent card chip in RFID (RadioFrequency IDentification, the radio-frequency (RF) identification) system that the CMOS logic process of standard realizes.Adopt this rectifier will be convenient to integrated memory based on the non-volatile type that adopts the standard CMOS logic process to realize.
Background technology
Rectifier is that the electrical signal conversion that exchanges is become direct current signal, and what adopt usually is full-wave bridge rectifier circuit, and as shown in Figure 7, its input is to come from power transformer, and itself is by four rectifier diode D1-D4 and load resistance R
LForm.Four rectifier diodes are connected into the electric bridge form, so claim bridge rectifier.The operation principle of full-wave bridge rectifier circuit as shown in Figure 8.At the positive half cycle of AC signal u, D1, D3 conducting, D2, D4 end, electric current by transformer secondary output upper end through D1 → R
L→ D3 gets back to the transformer secondary output lower end, at load R
LOn obtain a half-wave commutating voltage, shown in Fig. 8 a.At the negative half period of u, D1, D3 end, D2, D4 conducting, electric current by the lower end of transformer secondary output through D2 → R
L→ D4 gets back to the transformer secondary output upper end, at load R
LOn obtain another half-wave commutating voltage, shown in Fig. 8 b.So just at load R
LOn obtain the voltage waveform of a full-wave rectification, as shown in Figure 9.In full-wave bridge rectifier circuit, the differential concatenation of two diodes has been born the highest input voltage.
When integrated circuit is realized, the common full-wave bridge rectifier circuit that adopts as shown in figure 10, it adopts four MOS transistor T1-T4 to replace four diodes, the wherein drain and gate short circuit of transistor T 3 and T4 forms the MOS diode.The operation principle of this rectifier as shown in figure 11.At the positive half cycle of AC signal u, T3 diode current flow, T2 transistor are opened, and T4 diode and T1 transistor end, electric current by an end S1 of AC signal through T3 → R
LThe source-drain electrode of → ground → T2 is got back to the other end S2 of AC signal, at load R
LOn obtain a half-wave commutating voltage, shown in Figure 11 a.At the negative half period of u, T3 diode and T2 transistor end, the T4 diode current flow, and the T1 transistor is opened, and electric current is held through T4 → R by S2
LThe source-drain electrode of → ground → T1 is got back to the S1 end, at load R
LOn obtain another half-wave commutating voltage, shown in Figure 11 b.So also at load R
LOn obtain the voltage waveform of a full-wave rectification.In this rectifier, the highest input voltage is to be added on the grid of a MOS diode that ends and a MOS transistor of ending.
What the standard CMOS logic process adopted usually all is the low voltage logic transistor, these transistorized gate oxides are useful on the superthin grid oxide layer of internal element, such as, for 0.25 its thickness of μ m technology is the 50 Izod right sides, for 0.18 its thickness of μ m technology is the 30 Izod right sides, is the 20 Izod right sides for 0.13 its thickness of μ m technology; With the thick oxide layer that is used for I/O (" I/O ") unit, such as, be the 70 Izod right sides for the technology of 3.3V I/O, be the 50 Izod right sides for the technology of 2.5V I/O.
For instance, for adopting 0.18 μ m standard CMOS logic process, what inside unit adopted is the technology of 1.8V, and its thin oxide gate layer thickness is the 30 Izod right sides; What its I/O unit adopted is the technology of 3.3V, and its thick oxide layer thickness is the 70 Izod right sides.Different gate oxide thickness has different voltage endurance capabilities, the oxidated layer thickness of 70 dusts its withstand voltage when 5V its life-span be 2000-3000 hour, its life-span is several seconds during 10V.
Because the RFID electronic tags reaches as high as 10 volts by the peak-to-peak value that coil is coupled out as the carrier signal of rectifier input, such voltage is the life-span that will influence this rectifier as directly adding on the transistor of the CMOS logic process realization of the standard of employing.
Usually, the T1-T4 transistor that the RFID electronic tags is adopted all adopts high voltage bearing MOS transistor, promptly when MOS transistor forms, on its source-drain electrode, mix again the concentration of a same sex lower mix the district, with the grid source of improving this MOS transistor and the puncture voltage of grid leak; Or the puncture of adopting thicker gate oxide thickness to improve grid.So, need extra process complexity, maybe can not adopt the oxidated layer thickness of continuous progress along with semiconductor process techniques, transistor gate constantly to reduce, characteristic line breadth constantly reduces (as 0.18 μ m, 0.13 μ m, 90nm, 65nm, or the like, advanced semiconductor process techniques) advanced person's standard CMOS logic process.
Summary of the invention
Purpose of the present invention is intended to overcome above-mentioned deficiency of the prior art, provides a kind of standard CMOS logic process that adopts to realize high withstand voltage rectifier, and the present invention does not increase extra process complexity, can be applicable in the RFID electronic tags.
Content of the present invention is: a kind of rectifier is characterized in that comprising:
The first nmos pass transistor T1, its drain electrode connects first input end S1, and its grid connects an end of second capacitor C 2, and its source electrode links to each other with substrate and ground connection;
The second nmos pass transistor T2, its drain electrode connects the second input S2, and its grid connects an end of first capacitor C 1, and its source electrode links to each other with substrate and ground connection;
The 3rd capacitor C 3, its end connects first input end S1, and the other end connects the grid of the 3rd nmos pass transistor T3;
The 3rd nmos pass transistor T3, its drain electrode connects first input end S1, and its grid connects an end of the 3rd capacitor C 3, and the source electrode of its source electrode and the 4th nmos pass transistor T4 links to each other and as the output V of rectifier
L, its substrate ground connection;
The 4th capacitor C 4, its end connects the second input S2, and the other end connects the grid of the 4th nmos pass transistor T4;
The 4th nmos pass transistor T4, its drain electrode connects the second input S2, and its grid connects an end of the 4th capacitor C 4, and the source electrode of its source electrode and the 3rd nmos pass transistor T3 links to each other and as the output V of rectifier
L, its substrate ground connection;
Resistance R
L, its end connects the source electrode of the 3rd nmos pass transistor T3 and the 4th nmos pass transistor T4, other end ground connection.
In the content of the present invention: can also come dividing potential drop to add to voltage on the grid at nmos pass transistor at the two-stage of connecting on the grid of each nmos pass transistor of this rectifier, three grades or multistage electric capacity or class capacitance structure device.
In the content of the present invention: the device of described electric capacity or class capacitance structure can adopt in P type substrate, N type trap the device of the class mos capacitance structure that the mode that forms the NMOS pipe realizes, or the mos capacitance that adopts the mode that on P type substrate, forms depletion type NMOS pipe to realize, or the mos capacitance that adopts the mode that in N type substrate, P type trap, forms depletion type NMOS pipe to realize.
In the content of the present invention: described rectifier can have the output of several roads simultaneously.
Another content of the present invention is: a kind of rectifier is characterized in that comprising:
The 5th capacitor C 5, its end connects first input end S1, and the other end connects the grid of the 6th PMOS transistor T 6;
The 5th PMOS transistor T 5, its source electrode connects first input end S1, and its grid connects an end of the 6th capacitor C 6, and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 6th PMOS transistor T 6, as the output V of rectifier
L
The 6th capacitor C 6, its end connects the second input S2, and the other end connects the 5th PMOS transistor T 5 grids;
The 6th PMOS transistor T 6, its source electrode connect the second input S2, and its grid connects an end of the 5th capacitor C 5, and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 5th PMOS transistor T 5, as the output V of rectifier
L
The 7th capacitor C 7, its end connects first input end S1, and the other end connects the grid of the 7th PMOS transistor T 7;
The 7th PMOS transistor T 7, its source electrode link to each other with substrate and are connected to first input end S1, and its grid connects an end of the 7th capacitor C 7, its grounded drain;
The 8th capacitor C 8, its end connects the second input S2, and the other end connects the grid of the 8th PMOS transistor T 8;
The 8th PMOS transistor T 8, its source electrode link to each other with substrate and are connected to the second input S2, and its grid connects an end of the 8th capacitor C 8, its grounded drain;
Resistance R
L1, its end connects the drain electrode of the 5th PMOS transistor T 5 and the 6th PMOS transistor T 6, other end ground connection.
In the content of the present invention: the method for the two-stage of can also connecting on the transistorized grid of each PMOS of this rectifier, three grades or multistage electric capacity or class capacitance structure device comes dividing potential drop to add to voltage on the transistorized grid of PMOS.
In the content of the present invention: described electric capacity can adopt the mode that forms depletion type PMOS pipe in P type substrate, N type trap to realize.
The described rectifier of content of the present invention can have the output of several roads simultaneously.
Another content of the present invention is: a kind of rectifier is characterized in that comprising:
The 9th capacitor C 9, its an end ground connection, the other end connects the grid of the 9th nmos pass transistor T9;
The 9th nmos pass transistor T9, its drain electrode connects first input end S1, and its grid connects an end of the 9th capacitor C 9, and its source electrode links to each other with substrate and ground connection;
The tenth capacitor C 10, its an end ground connection, the other end connects the grid of the tenth nmos pass transistor T10;
The tenth nmos pass transistor T10, its drain electrode connects the second input S2, and its grid connects an end of the tenth capacitor C 10, and its source electrode links to each other with substrate and ground connection;
The 11 capacitor C 11, its end connects first input end S1, and the other end connects the grid of the 11 nmos pass transistor T11;
The 11 nmos pass transistor T11, its drain electrode connects first input end S1, and its grid connects an end of the 11 capacitor C 11, and the source electrode of its source electrode and the tenth bi-NMOS transistor T12 links to each other and as the output V of rectifier
L, its substrate ground connection;
The 12 capacitor C 12, its end connects the second input S2, and the other end connects the grid of the tenth bi-NMOS transistor T12;
The tenth bi-NMOS transistor T12, its drain electrode connects the second input S2, and its grid connects an end of the 12 capacitor C 12, and the source electrode of its source electrode and the 11 nmos pass transistor T11 links to each other and as the output V of rectifier
L, its substrate ground connection;
Resistance R
L2, its end connects the source electrode of the 11 nmos pass transistor T11 and the tenth bi-NMOS transistor T12, other end ground connection.
In the content of the present invention: can also come dividing potential drop to add to voltage on the grid at nmos pass transistor in the method for the two-stage of connecting on the grid of each nmos pass transistor of this rectifier, three grades or multistage electric capacity or class capacitance structure device.
In the content of the present invention: the device of described electric capacity or class capacitance structure then can adopt in P type substrate, N type trap the device of the class mos capacitance structure that the mode that forms the NMOS pipe realizes, or the mos capacitance that adopts the mode that on P type substrate, forms depletion type NMOS pipe to realize, or the mos capacitance that adopts the mode that in N type substrate, P type trap, forms depletion type NMOS pipe to realize.
The described rectifier of content of the present invention can have the output of several roads simultaneously.
Another content of the present invention is: a kind of rectifier is characterized in that comprising:
The 13 capacitor C 13, its a termination output V
L, the other end connects the grid of the 13 PMOS transistor T 13;
The 13 PMOS transistor T 13, its source electrode connects first input end S1, and its grid connects an end of the 13 capacitor C 13, and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 14 PMOS transistor T 14, as the output V of rectifier
L
The 14 capacitor C 14, its a termination output V
L, the other end connects the grid of the 14 PMOS transistor T 14;
The 14 PMOS transistor T 14, its source electrode connect the second input S2, and its grid connects an end of the 14 capacitor C 14, and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 13 PMOS transistor T 13, as the output V of rectifier
L
The 15 capacitor C 15, its end connects first input end S1, and the other end connects the grid of the 15 PMOS transistor T 15;
The 15 PMOS transistor T 15, its source electrode link to each other with substrate and are connected to first input end S1, and its grid connects an end of the 15 capacitor C 15, its grounded drain;
The 16 capacitor C 16, its end connects the second input S2, and the other end connects the grid of the 16 PMOS transistor T 16;
The 16 PMOS transistor T 16, its source electrode link to each other with substrate and are connected to the second input S2, and its grid connects an end of the 16 capacitor C 16, its grounded drain;
Resistance R
L3, its end connects the drain electrode of the 13 PMOS transistor T 13 and the 14 PMOS transistor T 14, other end ground connection.
In the content of the present invention: the method for the two-stage of can also connecting on the transistorized grid of each PMOS of this rectifier, three grades or multistage electric capacity or class capacitance structure device comes dividing potential drop to add to voltage on the transistorized grid of PMOS.
In the content of the present invention: described electric capacity can adopt the mode that forms depletion type PMOS pipe in P type substrate, N type trap to realize.
The described rectifier of content of the present invention can have the output of several roads simultaneously.
Another content of the present invention is: a kind of rectifier is characterized in that comprising:
The 17 capacitor C 17, its end connects first input end S1, and the other end connects the grid of the 18 nmos pass transistor T18;
The 17 nmos pass transistor T17, its drain electrode connects first input end S1, and its grid connects an end of the 18 capacitor C 18, and its source electrode links to each other with substrate and ground connection;
The 18 capacitor C 18, its end connects input S2, and the other end connects the grid of the 17 nmos pass transistor T17;
The 18 nmos pass transistor T18, its drain electrode connects the second input S2, and its grid connects an end of the 17 capacitor C 17, and its source electrode links to each other with substrate and ground connection;
The 19 capacitor C 19, its end connects first input end S1, and the other end connects the grid of the 20 PMOS transistor T 20;
The 19 PMOS transistor T 19, its source electrode connects first input end S1, and its grid connects an end of the 20 capacitor C 20, and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 20 PMOS transistor T 20, as the output V of rectifier
L
The 20 capacitor C 20, its end connects the second input S2, and the other end connects the grid of the 19 PMOS transistor T 19;
The 20 PMOS transistor T 20, its source electrode connect the second input S2, and its grid connects an end of the 19 capacitor C 19, and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 19 PMOS transistor T 19, as the output V of rectifier
L
Resistance R
L4, its end connects the drain electrode of the 19 PMOS transistor T 19 and the 20 PMOS transistor T 20, other end ground connection.
In the content of the present invention: the method for the two-stage of can also connecting on each NMOS of this rectifier and the transistorized grid of PMOS, three grades or multistage electric capacity or class capacitance structure device comes dividing potential drop to add to voltage on NMOS and the transistorized grid of PMOS.
In the content of the present invention: the device of described electric capacity or class capacitance structure can adopt in P type substrate, N type trap the device of the mos capacitance structure that the mode that forms depletion type PMOS pipe realizes, or adopts the device of the class mos capacitance structure that the mode that forms the NMOS pipe in P type substrate, N type trap realizes.
The described rectifier of content of the present invention can have the output of several roads simultaneously.
The device of described electric capacity or class capacitance structure, can also adopt the various realization electric capacity that the standard CMOS logic process provided or the method for class capacitance structure device to realize, comprise: can form by the battery lead plate of any two adjacent and mutual isolation, they can be the polycrystalline utmost point/gate oxide/N trap utmost points, the polycrystalline utmost point/gate oxide/P trap the utmost point, the grid of NMOS and its source-drain electrode, the grid of PMOS and its source-drain electrode, the first metal layer 1 and the polycrystalline utmost point, second metal level 2 and the first metal layer 1, the three metal level 3 and second metal level 2.
The present invention by series electrical on the employed transistorized grid of this rectifier perhaps the device of class capacitance structure come dividing potential drop to add to voltage on transistorized grid, with Fig. 1 is example, and the dividing potential drop of the grid capacitance of grid capacitance, C4 and the T4 of grid capacitance, C3 and the T3 of grid capacitance, C2 and T1 by capacitor C 1 and T2 improves rectifier withstand voltage to high input voltage.
Principle of the present invention is to utilize the partial pressure properties of series capacitance: the total voltage at series capacitance two ends equal each series capacitance two ends voltage and, the inverse of total capacitance equal each series capacitance value inverse and.Be expressed as follows with Figure 16 and formula one, two.So; the highest input voltage of rectifier is except on the grid that is added in a MOS diode that ends and a MOS transistor of ending; also divide and be depressed on two dividing potential drop electric capacity that are added in respectively on these two metal-oxide-semiconductor grids; therefore; the voltage that directly is added on the metal-oxide-semiconductor grid is reduced, and has played the effect of protection metal-oxide-semiconductor grid.If what the electric capacity of series connection adopted is the MOS transistor electric capacity of same size and gate oxide thickness, then be equivalent to the thickness of grid oxygen is doubled.The voltage endurance capability of this structure has obtained raising.
U=U
1+ U
2Formula one
The electric capacity that is adopted in the rectifier of the present invention can adopt the various realization electric capacity that the standard CMOS logic process provided or the method for class capacitance structure device to realize, promptly, can be by the battery lead plate formation of any two adjacent and mutual isolation, they can be the polycrystalline utmost point/gate oxide/N trap utmost points, the polycrystalline utmost point/gate oxide/P trap the utmost point, the grid of NMOS and its source-drain electrode, the grid of PMOS and its source-drain electrode, the metal level 1 and the polycrystalline utmost point, metal level 2 and metal level 1, metal level 3 and metal level 2, or the like, but also be not restricted to the device of these electric capacity or class electric capacity.Therefore, rectifier of the present invention need not to increase extra process complexity, and can adopt the CMOS logic process of standard, has saved manufacturing and technology cost.The more important thing is, adopted the memory of the non-volatile type that the RFID electronic tags of this rectifier can be integrated realizes based on the CMOS logic process of the standard of employing.
The withstand voltage input that the transistor that the present invention can adopt the CMOS logic process of standard to realize bears high voltage.Along with improving constantly of CMOS logic process technology, constantly reducing of characteristic line breadth, the oxidated layer thickness of grid is also constantly reducing, grid withstand voltage also in continuous reduction, and the present invention can come dividing potential drop to add to voltage on transistor gate by series connection two-stage, three grades even multistage method.The realization of rectifier of the present invention helps integrated memory based on the non-volatile type that adopts the standard CMOS logic process to realize, helps to reduce the manufacturing and the technology cost of RFID electronic tags.
Advantage of the present invention is that the CMOS logic process of employing standard has been realized high withstand voltage rectifier, has reduced the technology cost that integrated circuit is made; Characteristics of the present invention be adopt series electrical on the grid of each MOS transistor of rectifier of the present invention perhaps the method for class capacitance structure device come dividing potential drop to add to voltage on the grid in MOS transistor, simple in structure, and be not subject to the continuous development of advanced CMOS logic process technology; Rectifier of the present invention is used for the realization of the RFID electronic tags of integrated memory based on the non-volatile type that adopts the standard CMOS logic process to realize.The realization of the non-volatile type memory of existing RFID electronic tags is to adopt the EEPROM technology, and the realization of the non-volatile type memory that the applied RFID electronic tags of the present invention is adopted is the CMOS logic process of employing standard.The minimum feature main points of CMOS logic process technology are prior to the EEPROM technology; With the RFID electronic tags that CMOS logic process technology is made, under the situation of identical memory density, its cost is less than the EEPROM technology that adopts.
Description of drawings
Fig. 1 is the example one that the present invention adopts the rectifier of nmos pass transistor realization;
Fig. 2 is the example two that the present invention adopts the rectifier of PMOS transistor realization;
Fig. 3 is the physics profile (P type substrate, N trap) that the present invention adopts the rectifier of NMOS pipe realization;
Fig. 4 is physics profile (P type substrate, the N trap that the present invention adopts the rectifier of NMOS pipe realization; The N type exhausts pipe);
Fig. 5 is physics profile (N type substrate, the P trap that the present invention adopts the rectifier of NMOS pipe realization; The N type exhausts pipe);
Fig. 6 is the physics profile (P type substrate, N trap) that the present invention adopts the rectifier of PMOS pipe realization;
Fig. 7 is the full-wave bridge rectifier circuit schematic diagram;
Fig. 8 is the operation principle of full-wave bridge rectifier circuit;
Fig. 9 is the voltage waveform of full-wave rectification;
Figure 10 is a kind of realization of full-wave bridge rectifier circuit;
Figure 11 is the operation principle of bridge full wave rectifier shown in Figure 10;
Figure 12 is the example three that the present invention adopts the rectifier of nmos pass transistor realization;
Figure 13 is the example four that the present invention adopts the rectifier of PMOS transistor realization;
Figure 14 is the example five that the present invention adopts the rectifier of nmos pass transistor and the realization of PMOS transistor;
Figure 15 is the rectifier with multichannel output;
Figure 16 is the dividing potential drop schematic diagram of series capacitance.
Embodiment
First embodiment scheme of rectifier provided by the invention comprises: first capacitor C 1, and its end connects input S1, and the other end connects the grid of the second nmos pass transistor T2; The first nmos pass transistor T1, its drain electrode connects input S1, and its grid connects an end of second capacitor C 2, and its source electrode links to each other with substrate and ground connection; Second capacitor C 2, its end connects input S2, and the other end connects the grid of the first nmos pass transistor T1; The second nmos pass transistor T2, its drain electrode connects input S2, and its grid connects an end of first capacitor C 1, and its source electrode links to each other with substrate and ground connection; The 3rd capacitor C 3, its end connects input S1, and the other end connects the grid of the 3rd nmos pass transistor T3; The 3rd nmos pass transistor T3, its drain electrode connects input S1, and its grid connects an end of the 3rd capacitor C 3, and the source electrode of its source electrode and the 4th nmos pass transistor T4 links to each other and as the output V of rectifier
L, its substrate ground connection; The 4th capacitor C 4, its end connects input S2, and the other end connects the grid of the 4th nmos pass transistor T4; The 4th nmos pass transistor T4, its drain electrode connects input S2, and its grid connects an end of the 4th capacitor C 4, and the source electrode of its source electrode and the 3rd nmos pass transistor T3 links to each other and as the output V of rectifier
L, its substrate ground connection; Resistance R
L, its end connects the source electrode of the 3rd nmos pass transistor T3 and the 4th nmos pass transistor T4, other end ground connection.As shown in Figure 1.
Second embodiment scheme of rectifier provided by the invention comprises: the 5th capacitor C 5, and its end connects input S1, and the other end connects the grid of the 6th PMOS transistor T 6; The 5th PMOS transistor T 5, its source electrode connects input S1, and its grid connects an end of the 6th capacitor C 6, and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 6th PMOS transistor T 6, as the output V of rectifier
LThe 6th capacitor C 6, its end connects input S2, and the other end connects the 5th PMOS transistor T 5 grids; The 6th PMOS transistor T 6, its source electrode connects input S2, and its grid connects an end of the 5th capacitor C 5, and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 5th PMOS transistor T 5, as the output V of rectifier
LThe 7th capacitor C 7, its end connects input S1, and the other end connects the grid of the 7th PMOS transistor T 7; The 7th PMOS transistor T 7, its source electrode link to each other with substrate and are connected to input S1, and its grid connects an end of the 7th capacitor C 7, its grounded drain; The 8th capacitor C 8, its end connects input S2, and the other end connects the grid of the 8th PMOS transistor T 8; The 8th PMOS transistor T 8, its source electrode link to each other with substrate and are connected to input S2, and its grid connects an end of the 8th capacitor C 8, its grounded drain; Resistance R
L1, its end connects the drain electrode of the 5th PMOS transistor T 5 and the 6th PMOS transistor T 6, other end ground connection.As shown in Figure 2.
The 3rd embodiment scheme of rectifier provided by the invention comprises: the 9th capacitor C 9, and its an end ground connection, the other end connects the grid of the 9th nmos pass transistor T9; The 9th nmos pass transistor T9, its drain electrode connects input S1, and its grid connects an end of the 9th capacitor C 9, and its source electrode links to each other with substrate and ground connection; The tenth capacitor C 10, its an end ground connection, the other end connects the grid of the tenth nmos pass transistor T10; The tenth nmos pass transistor T10, its drain electrode connects input S2, and its grid connects an end of the tenth capacitor C 10, and its source electrode links to each other with substrate and ground connection; The 11 capacitor C 11, its end connects input S1, and the other end connects the grid of the 11 nmos pass transistor T11; The 11 nmos pass transistor T11, its drain electrode connects input S1, and its grid connects an end of the 11 capacitor C 11, and the source electrode of its source electrode and the tenth bi-NMOS transistor T12 links to each other and as the output V of rectifier
L, its substrate ground connection; The 12 capacitor C 12, its end connects input S2, and the other end connects the grid of the tenth bi-NMOS transistor T12; The tenth bi-NMOS transistor T12, its drain electrode connects input S2, and its grid connects an end of the 12 capacitor C 12, and the source electrode of its source electrode and the 11 nmos pass transistor T11 links to each other and as the output V of rectifier
L, its substrate ground connection; Resistance R
L2, its end connects the source electrode of the 11 nmos pass transistor T11 and the tenth bi-NMOS transistor T12, other end ground connection.As shown in figure 12.
The 4th embodiment scheme of rectifier provided by the invention comprises: the 13 capacitor C 13, its a termination output V
L, the other end connects the grid of the 13 PMOS transistor T 13; The 13 PMOS transistor T 13, its source electrode connects input S1, and its grid connects an end of the 13 capacitor C 13, and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 14 PMOS transistor T 14, as the output V of rectifier
LThe 14 capacitor C 14, its a termination output V
L, the other end connects the grid of the 14 PMOS transistor T 14; The 14 PMOS transistor T 14, its source electrode connects input S2, and its grid connects an end of the 14 capacitor C 14, and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 13 PMOS transistor T 13, as the output V of rectifier
LThe 15 capacitor C 15, its end connects input S1, and the other end connects the grid of the 15 PMOS transistor T 15; The 15 PMOS transistor T 15, its source electrode link to each other with substrate and are connected to input S1, and its grid connects an end of the 15 capacitor C 15, its grounded drain; The 16 capacitor C 16, its end connects input S2, and the other end connects the grid of the 16 PMOS transistor T 16; The 16 PMOS transistor T 16, its source electrode link to each other with substrate and are connected to input S2, and its grid connects an end of the 16 capacitor C 16, its grounded drain; Resistance R
L3, its end connects the drain electrode of the 13 PMOS transistor T 13 and the 14 PMOS transistor T 14, other end ground connection.As shown in figure 13.
The 5th embodiment of rectifier provided by the invention comprises: the 17 capacitor C 17, and its end connects input S1, and the other end connects the grid of the 18 nmos pass transistor T18; The 17 nmos pass transistor T17, its drain electrode connects input S1, and its grid connects an end of the 18 capacitor C 18, and its source electrode links to each other with substrate and ground connection; The 18 capacitor C 18, its end connects input S2, and the other end connects the grid of the 17 nmos pass transistor T17; The 18 nmos pass transistor T18, its drain electrode connects input S2, and its grid connects an end of the 17 capacitor C 17, and its source electrode links to each other with substrate and ground connection; The 19 capacitor C 19, its end connects input S1, and the other end connects the grid of the 20 PMOS transistor T 20; The 19 PMOS transistor T 19, its source electrode connects input S1, and its grid connects an end of the 20 capacitor C 20, and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 20 PMOS transistor T 20, as the output V of rectifier
LThe 20 capacitor C 20, its end connects input S2, and the other end connects the grid of the 19 PMOS transistor T 19; The 20 PMOS transistor T 20, its source electrode connects input S2, and its grid connects an end of the 19 capacitor C 19, and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 19 PMOS transistor T 19, as the output V of rectifier
LResistance R
L4, its end connects the drain electrode of the 19 PMOS transistor T 19 and the 20 PMOS transistor T 20, other end ground connection.As shown in figure 14.
Investigate now accompanying drawing, Figure 1 shows that nmos pass transistor of the present invention realize the example one of rectifier, comprising: AC signal input 1 and 2, nmos pass transistor 3, electric capacity 4, electric capacity 5, nmos pass transistor 6, nmos pass transistor 7, electric capacity 8, electric capacity 9, nmos pass transistor 10, rectifier output end 20, resistance 19.For the ease of the explanation of back, at this connecting line between transistor 10 and the electric capacity 9 is labeled as 17, the connecting line between transistor 3 and the electric capacity 5 is labeled as 18.
AC signal voltage inputs to rectifier by AC signal input 1 and 2, is positive half cycle, input 2 during for negative half period at AC signal input 1, and forward voltage adds to transistor 6 and 7 by electric capacity 4 and 8, and transistor 6 and 7 is opened; Reverse voltage adds to transistor 3 and 10 by electric capacity 5 and 9, transistor 3 and 10 is ended, forward current is got back to input 2 by input 1 through the source-drain electrode of the drain-source utmost point → resistance 19 → ground → transistor 6 of transistor 7, obtains a positive halfwave rectifier voltage on resistance 19.At AC signal input 1 is negative half period, input 2 during for positive half cycle, and forward voltage adds to transistor 3 and 10 by electric capacity 5 and 9, and transistor 3 and 10 is opened; Reverse voltage adds to transistor 6 and 7 by electric capacity 4 and 8, transistor 6 and 7 is ended, forward current is got back to input 1 by input 2 through the source-drain electrode of the drain-source utmost point → resistance 19 → ground → transistor 3 of transistor 10, obtains another positive halfwave rectifier voltage on resistance 19.On load resistance 19, obtain the voltage waveform of a positive full-wave rectification like this.Output 20 outputs from rectifier.
Fig. 3 shows a physics profile 300 of an illustrative electric capacity of rectifier shown in Figure 1, the transistor 3 and 10 in this profile correspondence and Fig. 1 circuit diagram, and electric capacity 5 and 9.The substrate 310 of the silicon wafer of hypothesis employing here is that positivity is mixed.Trap 308 is that negativity is mixed.N+ source region and drain region 301,302,303,304,305,306 and 307 are to adopt negativity to mix simultaneously to form.The draw-out area 311 of p+ ground connection is to adopt positivity to mix formation.Exit 320 ground connection of p+.371,372,373 and 374 is oxide-isolated grooves.The exit 331 that leak in the n+ source is connected to output shown in Figure 1 20.The exit that leaks in the n+ source 332,333,334 links to each other with 335 and is connected to input shown in Figure 12.Exit 336 ground connection that leak in the n+ source.The exit 337 that leak in the n+ source is connected to input shown in Figure 11.Grid exit 340 links to each other as connecting line shown in Figure 1 17 with 341.Grid exit 342 links to each other as connecting line shown in Figure 1 18 with 343.Grid 351 and trap 308 have formed electric capacity shown in Figure 19, and the one end is drawn by exit 341, and the other end is linked to each other with 334 by exit 333 and draws.Grid 352 and trap 308 have formed electric capacity shown in Figure 15, and the one end is drawn by exit 342, and the other end is linked to each other with 335 by exit 334 and draws.Grid 353 and n+ source-drain area 301 and 302 have formed transistor shown in Figure 1 10.Grid 354 and n+ source-drain area 306 and 307 have formed transistor shown in Figure 13.
Fig. 4 shows the profile 400 of the another kind of physics realization of electric capacity shown in Figure 1, the transistor 3 and 10 in the same correspondence of this profile and Fig. 1 circuit diagram, and electric capacity 5 and 9.The substrate 410 of the silicon wafer of hypothesis employing here is that positivity is mixed.N+ source region and drain region 401,402,403,404,405,406 and 407 are to adopt negativity to mix simultaneously to form.N+ raceway groove 461 and 462 is to adopt negativity to mix simultaneously to form, and they are forming the negativity raceway groove between n+ source-drain area 403 and 404 and between n+ source-drain area 404 and 405.The draw-out area 411 of p+ ground connection is to adopt positivity to mix formation.Exit 420 ground connection of p+.471,472,473 and 474 is oxide-isolated grooves.The exit 431 that leak in the n+ source is connected to output shown in Figure 1 20.The exit that leaks in the n+ source 432,433,434 links to each other with 435 and is connected to input shown in Figure 12.Exit 436 ground connection that leak in the n+ source.The exit 437 that leak in the n+ source is connected to input shown in Figure 11.Grid exit 440 links to each other as connecting line shown in Figure 1 17 with 441.Grid exit 442 links to each other as connecting line shown in Figure 1 18 with 443.Grid 451 and raceway groove 461 have formed electric capacity shown in Figure 19, and the one end is drawn by exit 441, and the other end is linked to each other with 434 by exit 433 and draws.Grid 452 and raceway groove 462 have formed electric capacity shown in Figure 15, and the one end is drawn by exit 442, and the other end is linked to each other with 435 by exit 434 and draws.Grid 453 and n+ source-drain area 401 and 402 have formed transistor shown in Figure 1 10.Grid 454 and n+ source-drain area 406 and 407 have formed transistor shown in Figure 13.
Fig. 5 shows the profile 500 of the third physics realization of electric capacity shown in Figure 1, the transistor 3 and 10 in the same correspondence of this profile and Fig. 1 circuit diagram, and electric capacity 5 and 9.The substrate 510 of the silicon wafer of hypothesis employing here is that negativity is mixed.Trap 508 is that positivity is mixed.N+ source region and drain region 501,502,503,504,505,506 and 507 are to adopt negativity to mix simultaneously to form.N+ raceway groove 561 and 562 is to adopt negativity to mix simultaneously to form, and they are forming the negativity raceway groove between n+ source-drain area 503 and 504 and between n+ source-drain area 504 and 505.The draw-out area 511 of p+ ground connection is to adopt positivity to mix formation.Exit 520 ground connection of p+.571,572,573,574 and 575 is oxide-isolated grooves.The exit 531 that leak in the n+ source is connected to output shown in Figure 1 20.The exit that leaks in the n+ source 532,533,534 links to each other with 535 and is connected to input shown in Figure 12.Exit 536 ground connection that leak in the n+ source.The exit 537 that leak in the n+ source is connected to input shown in Figure 11.Grid exit 540 links to each other as connecting line shown in Figure 1 17 with 541.Grid exit 542 links to each other as connecting line shown in Figure 1 18 with 543.Grid 551 and raceway groove 561 have formed electric capacity shown in Figure 19, and the one end is drawn by exit 541, and the other end is linked to each other with 534 by exit 533 and draws.Grid 552 and raceway groove 562 have formed electric capacity shown in Figure 15, and the one end is drawn by exit 542, and the other end is linked to each other with 535 by exit 534 and draws.Grid 553 and n+ source-drain area 501 and 502 have formed transistor shown in Figure 1 10.Grid 554 and n+ source-drain area 506 and 507 have formed transistor shown in Figure 13.
Figure 2 shows that PMOS transistor of the present invention realize the example two of rectifier, comprising: AC signal input 21 and 22, PMOS transistor 23, electric capacity 24, electric capacity 25, PMOS transistor 26, PMOS transistor 27, electric capacity 28, electric capacity 29, PMOS transistor 30, rectifier output end 40, resistance 39.For the ease of the explanation of back, at this connecting line between transistor 30 and the electric capacity 29 is labeled as 37, the connecting line between transistor 23 and the electric capacity 25 is labeled as 38.
AC signal voltage inputs to rectifier by AC signal input 21 and 22, is positive half cycle, input 22 during for negative half period at AC signal input 21, and forward voltage adds to transistor 26 and 27 by electric capacity 24 and 28, and transistor 26 and 27 is ended; Reverse voltage adds to transistor 23 and 30 by electric capacity 25 and 29, transistor 23 and 30 is opened, forward current is got back to input 21 by input 21 through the drain-source utmost point of the source-drain electrode → resistance 39 → ground → transistor 30 of transistor 23, obtains a positive halfwave rectifier voltage on resistance 39.At AC signal input 21 is negative half period, input 22 during for positive half cycle, and forward voltage adds to transistor 23 and 30 by electric capacity 25 and 29, and transistor 23 and 30 is ended; Reverse voltage adds to transistor 26 and 27 by electric capacity 24 and 28, transistor 26 and 27 is opened, forward current is got back to input 21 by input 22 through the drain-source utmost point of the source-drain electrode → resistance 39 → ground → transistor 27 of transistor 26, obtains another positive halfwave rectifier voltage on resistance 39.On load resistance 39, obtain the voltage waveform of a positive full-wave rectification like this.Output 40 outputs from rectifier.
Fig. 6 shows a physics profile 600 of an illustrative electric capacity of rectifier shown in Figure 2, the transistor 23 and 30 in this profile correspondence and Fig. 2 circuit diagram, and electric capacity 25 and 29.The substrate 610 of the silicon wafer of hypothesis employing here is that positivity is mixed.Trap 608 is that negativity is mixed.P+ source region and drain region 601,602,603,604,605,606 and 607 are to adopt positivity to mix simultaneously to form.P+ raceway groove 661 and 662 is to adopt positivity to mix simultaneously to form, and they are forming the positivity raceway groove between p+ source-drain area 603 and 604 and between p+ source-drain area 604 and 605.The draw-out area 611 that n+ connects biasing is to adopt negativity to mix formation.The exit 620 of n+ is connected to output voltage terminal shown in Figure 2 40.671,672,673,674 and 675 is oxide-isolated grooves.Exit 631 ground connection that leak in the p+ source.The exit that leaks in the p+ source 632,633,634 links to each other with 635 and is connected to input shown in Figure 2 22.The exit 636 that leak in the p+ source is connected to output voltage terminal shown in Figure 2 40 in succession.The exit 637 that leak in the p+ source is connected to input shown in Figure 2 21.Grid exit 640 links to each other as connecting line shown in Figure 2 37 with 641.Grid exit 642 links to each other as connecting line shown in Figure 2 38 with 643.Grid 651 and raceway groove 661 have formed electric capacity shown in Figure 2 29, and the one end is drawn by exit 641, and the other end is linked to each other with 634 by exit 633 and draws.Grid 652 and raceway groove 662 have formed electric capacity shown in Figure 2 25, and the one end is drawn by exit 642, and the other end is linked to each other with 635 by exit 634 and draws.Grid 653 and p+ source-drain area 601 and 602 have formed transistor shown in Figure 2 30.Grid 654 and p+ source-drain area 606 and 607 have formed transistor shown in Figure 2 23.
Fig. 3 to Fig. 6 has provided some and has adopted the CMOS logic process of standard to realize the example of rectifier of the present invention and electric capacity or class capacitance structure device.In fact, the electric capacity that is adopted can adopt the various realization electric capacity that the standard CMOS logic process provided or the method for class capacitance structure device to realize, promptly, can be by the battery lead plate formation of any two adjacent and mutual isolation, they can be the polycrystalline utmost point/gate oxide/N trap utmost points, the polycrystalline utmost point/gate oxide/P trap the utmost point, the grid of NMOS and its source-drain electrode, the grid of PMOS and its source-drain electrode, the metal level 1 and the polycrystalline utmost point, metal level 2 and metal level 1, metal level 3 and metal level 2, or the like, but also be not restricted to the device of these electric capacity or class electric capacity.
The profile of the CMOS logic process that Fig. 3 is extremely shown in Figure 6 is also just as a kind of illustrative diagram, they are in order to help to illustrate the present invention, they can be the realizations of various standard CMOS logic process, and are not subject to further developing of CMOS logic process technology.
Continuous development along with CMOS logic process technology, constantly reducing of characteristic line breadth, the oxidated layer thickness of transistor gate is also constantly reducing, transistor gate withstand voltage also in continuous reduction adds to voltage on the grid in MOS transistor by come dividing potential drop in the method for the two-stage of connecting on the grid of each MOS transistor of rectifier of the present invention, three grades even multistage electric capacity or class capacitance structure device.Therefore, rectifier of the present invention is not subject to the continuous development of advanced CMOS logic process technology.
Figure 12 to Figure 14 show the present invention adopt nmos pass transistor, PMOS transistor and NMOS and PMOS transistor realize the example three, four and five of rectifier.
Figure 15 has provided a kind of rectifier with multichannel output of the RFID of can be used for electronic tags.This rectifier exports three the tunnel simultaneously, output V
VExport subordinate's filter regulator circuit to, output V
MExport subordinate's filtering modulation circuit to, output V
DExport subordinate's demodulation by filter circuit to.
The invention provides a kind of high withstand voltage rectifier that can adopt the standard CMOS logic process to realize.As a kind of application of the present invention, this rectifier can be used for the RFID electronic tags, this implementation makes and can adopt the standard CMOS logic process to realize the rectifier of RFID electronic tags, help integrated memory like this, to reduce the manufacturing and the technology cost of RFID electronic tags based on the non-volatile type that adopts the standard CMOS logic process to realize.
Here for narration of the present invention rectifier is described just, one is not to provide complete physics realization, for example, for the connection of some substrates biasing etc., does not do detailed narration, and these are all understood for the people that technology circle has general technical ability; Its two for rectifier with the statement of external circuit just in order to help to illustrate the application of this rectifier in the RFID electronic tags; It is three for the circuit of statement not beyond the rectifier, and for example, the current-limiting resistance of rectifier input etc. do not influence narration of the present invention.
More than be not the meticulous form of the exhaustive or limited introduction invention of attempt to the detailed description of a plurality of examples of the present invention.For example, the rectifier of the employing nmos pass transistor of Pi Luing, PMOS transistor and NMOS and PMOS transistor realization here, when this mode that with the illustration is purpose is described the MOS transistor adopted realizes the specific example of rectifier, realize that in the various employing MOS transistor of the scope of the invention rectifier all is possible, comprise the rectifier that positive rectification output and negative rectification are exported.Equally, principle of the present invention can be applied to other circuit, must not be rectifier above-mentioned.
The invention is not restricted to the foregoing description, content of the present invention is described all can implement and have described good result.
Claims (20)
1. rectifier is characterized in that comprising:
First electric capacity (C1), its end connects first input end (S1), and the other end connects the grid of second nmos pass transistor (T2);
First nmos pass transistor (T1), its drain electrode connects first input end (S1), and its grid connects an end of second electric capacity (C2), and its source electrode links to each other with substrate and ground connection;
Second electric capacity (C2), its end connects second input (S2), and the other end connects the grid of first nmos pass transistor (T1);
Second nmos pass transistor (T2), its drain electrode connect second input (S2), and its grid connects an end of first electric capacity (C1), and its source electrode links to each other with substrate and ground connection;
The 3rd electric capacity (C3), its end connects first input end (S1), and the other end connects the grid of the 3rd nmos pass transistor (T3);
The 3rd nmos pass transistor (T3), its drain electrode connects first input end (S1), and its grid connects an end of the 3rd electric capacity (C3), and the source electrode of its source electrode and the 4th nmos pass transistor (T4) links to each other and as the output (V of rectifier
L), its substrate ground connection;
The 4th electric capacity (C4), its end connects second input (S2), and the other end connects the grid of the 4th nmos pass transistor (T4);
The 4th nmos pass transistor (T4), its drain electrode connect second input (S2), and its grid connects an end of the 4th electric capacity (C4), and the source electrode of its source electrode and the 3rd nmos pass transistor (T3) links to each other and as the output (V of rectifier
L), its substrate ground connection;
Resistance (R
L), its end connects the source electrode of the 3rd nmos pass transistor (T3) and the 4th nmos pass transistor (T4), other end ground connection.
2. rectifier according to claim 1 is characterized in that: come dividing potential drop to add to voltage on the grid at nmos pass transistor at the two-stage of connecting on the grid of each nmos pass transistor of this rectifier, three grades or multistage electric capacity or class capacitance structure device.
3. rectifier according to claim 2, it is characterized in that: the device of the class mos capacitance structure that the mode of the device employing of electric capacity or class capacitance structure formation NMOS pipe in P type substrate, N type trap realizes, or the mos capacitance that adopts the mode that on P type substrate, forms depletion type NMOS pipe to realize, or the mos capacitance that adopts the mode that in N type substrate, P type trap, forms depletion type NMOS pipe to realize.
4. rectifier according to claim 1 and 2 is characterized in that: this rectifier has the output of several roads simultaneously.
5. rectifier is characterized in that comprising:
The 5th electric capacity (C5), its end connects first input end (S1), and the other end connects the grid of the 6th PMOS transistor (T6);
The 5th PMOS transistor (T5), its source electrode connects first input end (S1), and its grid connects an end of the 6th electric capacity (C6), and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 6th PMOS transistor (T6), as the output (V of rectifier
L);
The 6th electric capacity (C6), its end connects second input (S2), and the other end connects the 5th PMOS transistor (T5) grid;
The 6th PMOS transistor (T6), its source electrode connects second input (S2), and its grid connects an end of the 5th electric capacity (C5), and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 5th PMOS transistor (T5), as the output (V of rectifier
L);
The 7th electric capacity (C7), its end connects first input end (S1), and the other end connects the grid of the 7th PMOS transistor (T7);
The 7th PMOS transistor (T7), its source electrode link to each other with substrate and are connected to first input end (S1), and its grid connects an end of the 7th electric capacity (C7), its grounded drain;
The 8th electric capacity (C8), its end connects second input (S2), and the other end connects the grid of the 8th PMOS transistor (T8);
The 8th PMOS transistor (T8), its source electrode link to each other with substrate and are connected to second input (S2), and its grid connects an end of the 8th electric capacity (C8), its grounded drain;
Resistance (R
L1), its end connects the drain electrode of the 5th PMOS transistor (T5) and the 6th PMOS transistor (T6), other end ground connection.
6. rectifier according to claim 5 is characterized in that: the method for the two-stage of connecting on the transistorized grid of each PMOS of this rectifier, three grades or multistage electric capacity or class capacitance structure device comes dividing potential drop to add to voltage on the transistorized grid of PMOS.
7. according to claim 5 or 6 described rectifiers, it is characterized in that: electric capacity adopts the mode that forms depletion type PMOS pipe in P type substrate, N type trap to realize.
8. according to claim 5 or 6 described rectifiers, it is characterized in that: this rectifier has the output of several roads simultaneously.
9. rectifier is characterized in that comprising:
The 9th electric capacity (C9), its an end ground connection, the other end connects the grid of the 9th nmos pass transistor (T9);
The 9th nmos pass transistor (T9), its drain electrode connects first input end (S1), and its grid connects an end of the 9th electric capacity (C9), and its source electrode links to each other with substrate and ground connection;
The tenth electric capacity (C10), its an end ground connection, the other end connects the grid of the tenth nmos pass transistor (T10);
The tenth nmos pass transistor (T10), its drain electrode connect second input (S2), and its grid connects an end of the tenth electric capacity (C10), and its source electrode links to each other with substrate and ground connection;
The 11 electric capacity (C11), its end connects first input end (S1), and the other end connects the grid of the 11 nmos pass transistor (T11);
The 11 nmos pass transistor (T11), its drain electrode connects first input end (S1), and its grid connects an end of the 11 electric capacity (C11), and the source electrode of its source electrode and the tenth bi-NMOS transistor (T12) links to each other and as the output (V of rectifier
L), its substrate ground connection;
The 12 electric capacity (C12), its end connects second input (S2), and the other end connects the grid of the tenth bi-NMOS transistor (T12);
The tenth bi-NMOS transistor (T12), its drain electrode connect second input (S2), and its grid connects an end of the 12 electric capacity (C12), and the source electrode of its source electrode and the 11 nmos pass transistor (T11) links to each other and as the output (V of rectifier
L), its substrate ground connection;
Resistance (R
L2), its end connects the source electrode of the 11 nmos pass transistor (T11) and the tenth bi-NMOS transistor (T12), other end ground connection.
10. rectifier according to claim 9 is characterized in that: come dividing potential drop to add to voltage on the grid at nmos pass transistor in the method for the two-stage of connecting on the grid of each nmos pass transistor of this rectifier, three grades or multistage electric capacity or class capacitance structure device.
11. rectifier according to claim 10, it is characterized in that: the device of electric capacity or class capacitance structure then adopts in P type substrate, N type trap the device of the class mos capacitance structure that the mode that forms the NMOS pipe realizes, or the mos capacitance that adopts the mode that on P type substrate, forms depletion type NMOS pipe to realize, or the mos capacitance that adopts the mode that in N type substrate, P type trap, forms depletion type NMOS pipe to realize.
12. according to claim 9 or 10 described rectifiers, it is characterized in that: this rectifier has the output of several roads simultaneously.
13. a rectifier is characterized in that comprising:
The 13 electric capacity (C13), its a termination output (V
L), the other end connects the grid of the 13 PMOS transistor (T13);
The 13 PMOS transistor (T13), its source electrode connects first input end (S1), its grid connects an end of the 13 electric capacity (C13), and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 14 PMOS transistor (T14), as the output (V of rectifier
L);
The 14 electric capacity (C14), its a termination output (V
L), the other end connects the grid of the 14 PMOS transistor (T14);
The 14 PMOS transistor (T14), its source electrode connects second input (S2), its grid connects an end of the 14 electric capacity (C14), and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 13 PMOS transistor (T13), as the output (V of rectifier
L);
The 15 electric capacity (C15), its end connects first input end (S1), and the other end connects the grid of the 15 PMOS transistor (T15);
The 15 PMOS transistor (T15), its source electrode link to each other with substrate and are connected to first input end (S1), and its grid connects an end of the 15 electric capacity (C15), its grounded drain;
The 16 electric capacity (C16), its end connects second input (S2), and the other end connects the grid of the 16 PMOS transistor (T16);
The 16 PMOS transistor (T16), its source electrode link to each other with substrate and are connected to second input (S2), and its grid connects an end of the 16 electric capacity (C16), its grounded drain;
Resistance (R
L3), its end connects the drain electrode of the 13 PMOS transistor (T13) and the 14 PMOS transistor (T14), other end ground connection.
14. rectifier according to claim 13 is characterized in that: the method for the two-stage of connecting on the transistorized grid of each PMOS of this rectifier, three grades or multistage electric capacity or class capacitance structure device comes dividing potential drop to add to voltage on the transistorized grid of PMOS.
15. according to claim 13 or 14 described rectifiers, it is characterized in that: electric capacity adopts the mode that forms depletion type PMOS pipe in P type substrate, N type trap to realize.
16. according to claim 13 or 14 described rectifiers, it is characterized in that: this rectifier has the output of several roads simultaneously.
17. a rectifier is characterized in that comprising:
The 17 electric capacity (C17), its end connects first input end (S1), and the other end connects the grid of the 18 nmos pass transistor (T18);
The 17 nmos pass transistor (T17), its drain electrode connects first input end (S1), and its grid connects an end of the 18 electric capacity (C18), and its source electrode links to each other with substrate and ground connection;
The 18 electric capacity (C18), its end connects input (S2), and the other end connects the grid of the 17 nmos pass transistor (T17);
The 18 nmos pass transistor (T18), its drain electrode connect second input (S2), and its grid connects an end of the 17 electric capacity (C17), and its source electrode links to each other with substrate and ground connection;
The 19 electric capacity (C19), its end connects first input end (S1), and the other end connects the grid of the 20 PMOS transistor (T20);
The 19 PMOS transistor (T19), its source electrode connects first input end (S1), its grid connects an end of the 20 electric capacity (C20), and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 20 PMOS transistor (T20), as the output (V of rectifier
L);
The 20 electric capacity (C20), its end connects second input (S2), and the other end connects the grid of the 19 PMOS transistor (T19);
The 20 PMOS transistor (T20), its source electrode connects second input (S2), its grid connects an end of the 19 electric capacity (C19), and its drain electrode links to each other with substrate and is connected to the drain electrode and the substrate of the 19 PMOS transistor (T19), as the output (V of rectifier
L);
Resistance (R
L4), its end connects the drain electrode of the 19 PMOS transistor (T19) and the 20 PMOS transistor (T20), other end ground connection.
18. rectifier according to claim 17 is characterized in that: the method for the two-stage of connecting on each NMOS of this rectifier and the transistorized grid of PMOS, three grades or multistage electric capacity or class capacitance structure device comes dividing potential drop to add to voltage on NMOS and the transistorized grid of PMOS.
19. rectifier according to claim 18, it is characterized in that: the device of electric capacity or class capacitance structure adopts the device of the mos capacitance structure that the mode that forms depletion type PMOS pipe in P type substrate, N type trap realizes, or adopts the device of the class mos capacitance structure that the mode that forms the NMOS pipe in P type substrate, N type trap realizes.
20. rectifier according to claim 18 is characterized in that: this rectifier has the output of several roads simultaneously.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100215831A CN100553098C (en) | 2006-08-11 | 2006-08-11 | Adopt the standard CMOS logic process to realize high withstand voltage rectifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100215831A CN100553098C (en) | 2006-08-11 | 2006-08-11 | Adopt the standard CMOS logic process to realize high withstand voltage rectifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1905345A CN1905345A (en) | 2007-01-31 |
| CN100553098C true CN100553098C (en) | 2009-10-21 |
Family
ID=37674512
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100215831A Active CN100553098C (en) | 2006-08-11 | 2006-08-11 | Adopt the standard CMOS logic process to realize high withstand voltage rectifier |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100553098C (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101405932B (en) * | 2007-04-02 | 2011-06-01 | 上海凯路微电子有限公司 | Rectifier implementing high voltage resistance by employing standard CMOS transistor |
| KR101095724B1 (en) * | 2010-02-05 | 2011-12-21 | 주식회사 하이닉스반도체 | Semiconductor device including reservoir capacitor and method for fabricating the same |
| CN104333239B (en) * | 2014-10-23 | 2017-03-01 | 中山大学 | A kind of fully integrated AC DC transducer of high efficiency |
| CN109962723B (en) * | 2017-12-14 | 2021-08-20 | 紫光同芯微电子有限公司 | Modulation circuit with automatic load resistance adjustment function |
-
2006
- 2006-08-11 CN CNB2006100215831A patent/CN100553098C/en active Active
Also Published As
| Publication number | Publication date |
|---|---|
| CN1905345A (en) | 2007-01-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1914787B (en) | Switching power supply and semiconductor integrated circuit | |
| CN102128973B (en) | Voltage zero-crossing detecting circuit and DC-DC converter with same | |
| Afshar et al. | A robust 24mW 60GHz receiver in 90nm standard CMOS | |
| CN100553098C (en) | Adopt the standard CMOS logic process to realize high withstand voltage rectifier | |
| CN1645733A (en) | Alternating current switching circuit | |
| CN107437933A (en) | A kind of high-end load switching circuit and IC | |
| CN103138568B (en) | Rectifying circuit and radio frequency identification (RFID) chip | |
| CN103618468A (en) | High-efficiency rectifier constituting RFID electronic tag and rectifier units | |
| CN100459397C (en) | Floating-grid threshold-value adjustable rectifying circuit for radio electronic label | |
| US6359793B2 (en) | High efficiency converter for zero voltage switching | |
| CN101405932B (en) | Rectifier implementing high voltage resistance by employing standard CMOS transistor | |
| Asli et al. | − 31 dBm sensitivity high efficiency rectifier for energy scavenging | |
| CN103209150B (en) | The demodulation method of amplitude shift keying demodulator and amplitude shift keying signal | |
| CN207135003U (en) | Active rectifier | |
| CN206620056U (en) | A kind of LLC DC converters of self-driving type synchronous rectification | |
| CN109387688A (en) | A kind of current detection circuit | |
| CN103647539A (en) | Switching device and multichannel coupling selector provided with same | |
| CN105680107B (en) | A kind of battery management chip circuit based on SOI technology | |
| CN101834535A (en) | CMOS (Complementary Metal-Oxide-Semiconductor Transistor) rectifier | |
| EP0389515A4 (en) | Integratable synchronous rectifier | |
| CN107482934A (en) | A kind of rectifier | |
| CN105790574A (en) | Voltage multiplying circuit | |
| Rastmanesh | High efficiency RF to DC converter with reduced leakage current for RFID applications | |
| CN207233006U (en) | A kind of antenna switch circuit and smart card | |
| CN110445482A (en) | A kind of comparator of the high Slew Rate of low-power consumption |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| TR01 | Transfer of patent right |
Effective date of registration: 20191118 Address after: 621000 a412, No.133, mianxing East Road, high tech Zone, Mianyang City, Sichuan Province Patentee after: Sichuan kailuwei Technology Co., Ltd Address before: 1 building 96, No. 621000 East Hing Road, Gaoxin District, Sichuan, Mianyang Patentee before: Sichuan Kiloway Electron Inc. |
|
| TR01 | Transfer of patent right |