CN100552652C - Be used for judging the electronic installation and the correlation technique thereof of the kind of storer - Google Patents

Be used for judging the electronic installation and the correlation technique thereof of the kind of storer Download PDF

Info

Publication number
CN100552652C
CN100552652C CNB2006101494146A CN200610149414A CN100552652C CN 100552652 C CN100552652 C CN 100552652C CN B2006101494146 A CNB2006101494146 A CN B2006101494146A CN 200610149414 A CN200610149414 A CN 200610149414A CN 100552652 C CN100552652 C CN 100552652C
Authority
CN
China
Prior art keywords
storer
reference voltage
voltage
judgment signal
electronic installation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2006101494146A
Other languages
Chinese (zh)
Other versions
CN101187907A (en
Inventor
郭国仁
陈厚甫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Prolific Technology Inc
Original Assignee
Prolific Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Prolific Technology Inc filed Critical Prolific Technology Inc
Priority to CNB2006101494146A priority Critical patent/CN100552652C/en
Publication of CN101187907A publication Critical patent/CN101187907A/en
Application granted granted Critical
Publication of CN100552652C publication Critical patent/CN100552652C/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

A kind of electronic installation that is used for judging the kind of storer includes comparer, is used for first voltage exported according to reference voltage and this storer, produces judgment signal; And reset controller, be used for judging the kind of this storer according to this judgment signal.This comparer includes first input end, is used for receiving this first voltage; Second input end is used for receiving this reference voltage; Logical circuit is coupled to this first input end and this second input end, is used for relatively this first voltage and this reference voltage, to produce this judgment signal; And output terminal, be coupled to this logical circuit, be used for exporting this judgment signal.

Description

Be used for judging the electronic installation and the correlation technique thereof of the kind of storer
Technical field
The invention relates to a kind of electronic installation and correlation technique thereof that is used for judging the kind of storer, refer to a kind of electronic installation and correlation technique thereof that utilizes reference voltage to judge the storer kind especially.
Background technology
In electronic system, storer is a critical elements indispensable in the System Operation.High-speed cache (Cache Memory) in the central processing unit, to the video memory (VideoMemory) of display card collocation, even hard disk built-in memory buffer (Buffer) all belong to the category of storer.Wherein, dynamic RAM (Dynamic Random Access Memory; DRAM) cheap and circuit framework is simple, makes demand significantly increase, and its range of application is mainly in industries such as computing machine communication and consumer electronics, as personal computer, digital camera, mobile phone or the like.The kind of dynamic RAM is divided into that several are dissimilar, Synchronous Dynamic Random Access Memory (SynchronousDRAM for example, hereinafter to be referred as SDRAM) and double data rate synchronous dynamic access memory (Double Data RateSDRAM is hereinafter to be referred as DDR-SDRAM).What so-called SDRAM was meant clock signal that it is synchronized with system bus (System Bus) rises edge (Rising Edge), continues to write or reading of data (this operation also can be described as burst transfer (Burst Transfer)) with high clock rate.By synchronous operation, system bus and processor can carry out pipeline (Pipeline) transmission, thereby promote data processing rate.DDR-SDRAM goes up the execution burst transfer in the edge that rises of synchronous clock with falling edge (Falling Edge) simultaneously, to reach the effect of double data rate.In other words, the clock rate of DDR-SDRAM is equivalent to the twice of SDRAM.
Along with science and technology is fast-developing, electronic product marches toward microminiaturization, system single chip technology thereby come into one's own gradually.Because the purpose of system single chip is operating system is embedded in the microchip, system single chip generally comprises polytype storer.Yet, the different driving transmission specification of the many uses of dissimilar storeies, employed input and outputting standard are also different, for example electronic component industrial combination meeting (JointElectron Device Engineering Council; JEDEC) formulate low-voltag transistor logic (the Low Voltage Transistor-Transistor Logic that can be used for the synchronous dynamic access memory; LVTTL) or can be used for stitch series terminal logic (the StubSeries Terminated Logic of double data rate synchronous dynamic access memory; SSTL).Thus, system need know the type of storer in advance, just can provide or switch suitable input and output voltage.Therefore, it is essential prejudging type of memory.
In order to reach the compatibility of system for dissimilar storeies, U.S. Patent Publication No. US2004/0133758/A1 proposes a kind of circuit of judging type of memory, as shown in Figure 9 of the patent, this circuit comprises default bias voltage (Preset Bias) circuit, bolt-lock (Latch) circuit and selecting side (OptionTerminal; OPT).After default bias circuit provides biasing selected end in advance, whether supply the selecting side one external voltage, the mode signal (modesignal) of the exportable high or low level of this circuit according to ground pin (GNDPin).At last, according to two kinds of level of mode signal, but decision systems operates on haploidy number according to speed (Single Data Rate; SDR) or Double Data Rate (DDR) pattern.
But in order to make system's normal operation in two kinds of type of memory, known technology uses a ground pin whether to provide the selecting side external voltage, and then the judgement system pattern that should operate.Yet in the realization of system single chip, cost and chip area mainly one of are considered often.For the application that needs spininess pin system single chip, each stitch needs properly utilization.Therefore, the cost that makes system can judge correctly that type of memory is taken into account in the saving realization needs.
Summary of the invention
The present invention discloses a kind of electronic installation that is used for judging the kind of storer, includes comparer, is used for first voltage exported according to reference voltage and this storer, the generation judgment signal; And reset controller, be used for judging the kind of this storer according to this judgment signal.This comparer includes first input end, is used for receiving this first voltage; Second input end is used for receiving this reference voltage; Logical circuit is coupled to this first input end and this second input end, is used for relatively this first voltage and this reference voltage, to produce this judgment signal; And output terminal, be coupled to this logical circuit, be used for exporting this judgment signal.
The present invention also discloses a kind of method that is used for judging the kind of storer, includes: receive reference voltage; Receive first voltage that this storer is exported; Relatively this first voltage and this reference voltage; According to the comparative result of this first voltage and this reference voltage, produce judgment signal; And, judge the kind of this storer according to this judgment signal.
Description of drawings
Fig. 1 is used for judging the synoptic diagram of system and device of the kind of storer for the present invention.
Fig. 2 is the functional block diagram of the electronic installation of Fig. 1.
Fig. 3 is the process flow diagram according to the flow process of the present invention of Fig. 2.
[main element label declaration]
100 system and devices
110 electronic installations
120 voltage adjusters
130,140 storeies
150,160 jumpers
102 comparers
104 bias generators
106 reset controllers
108 logical circuits
VCM, Vref1, Vref2 voltage
S1, S2, S3, Ip1, Ip2, Op1 end points
So, S RSETSignal
R1, R2 resistance
200 metal oxide semiconductor transistors
30 flow processs
300,310,320,330,340,350,360 steps
Embodiment
Double data rate synchronous dynamic access memory is divided into the first kind double data rate synchronous dynamic access memory (hereinafter to be referred as DDR1) and the second class double data rate synchronous dynamic access memory (hereinafter to be referred as DDR2).According to stitch series terminal logical specification, DDR1 must follow the SSTL-2 specification, i.e. the voltage of the I/O of its storer (I/O) port must be 2.5V, and reference voltage is required to be 1.25V; DDR2 must follow the SSTL-18 specification, and promptly the voltage of the input/output end port of its storer must be 1.8V, and reference voltage is required to be 0.9V; And according to low-voltag transistor logical specification, the voltage of the I/O of SDRAM (I/O) port must be 3.3/2.5V/1.8V, and does not need reference voltage.
The present invention is a difference of utilizing the reference voltage of different memory standard, need not pass through extra stitch, makes system can judge the kind of storer automatically, with the adaptability and the compatibility of elevator system.In realization, the present invention can reduce a stitch (pin) with the saving cost, or stitch is made other more practical purposes, with elevator system usefulness.
Please refer to Fig. 1.Fig. 1 is used for judging the synoptic diagram of system and device 100 of the kind of storer for the present invention.System and device 100 comprises electronic installation 110, voltage adjuster (Terminal regulator) 120, first memory 130, second memory 140, first jumper (Jumper) 150 and second jumper 160.Wherein first memory 130 can be DDR1 or DDR2 etc., as long as its input/output end port needs reference voltage; Second memory 140 can be SDRAM etc., and its input/output end port does not need the storer of reference voltage.120 of voltage adjusters are responsible for first memory 130 and produce reference voltage.In addition, electronic installation 110 is used for judging the electronic installation of the kind of storer for the present invention.
When system and device 100 was opened, operating voltage VCM provided simultaneously to voltage adjuster 120, first memory 130 and second memory 140.Voltage adjuster 120 promptly produces the reference voltage Vref 1 of DDR-SDRAM, and inputs to first jumper 150.Wherein, if first memory 130 is DDR1, then reference voltage Vref 1 is 1.25V; If first memory 130 is DDR2, then reference voltage Vref 1 is 0.9V.First jumper 150 comprises three end points S1, S2 and S3, and wherein end points S1 is used for receiving reference voltage Vref 1, end points S3 ground connection.When system and device 100 needed operation first memory 130, the end points S2 of first jumper 150 was connected in end points S1, and transmitted reference voltage Vref 1 to electronic installation 110; On the contrary, when system and device 100 needed operation second memories 140, end points S2 then was connected in end points S3, transmitted ground voltage 0V to electronic installation 110, and meaning is that low-voltag transistor logical specification there is no reference voltage is provided.Behind first jumper, 150 reception reference voltages or ground voltage, electronic installation 110 promptly begins to judge the operation of storer kind, and after judging successfully,, receive the data and the control signal of first memory 130 or second memory 140 by second jumper 160.Therefore, system and device 100 mainly is to produce the reference voltage Vref 1 that meets aforementioned standard by voltage adjuster 120, and, the employed reference voltage of different types of memories is sent to electronic installation 110, and then judges the kind of storer by 150 switchings of first jumper.In addition, the interior arrangement of electronic installation 110 of the present invention and How It Works will be in describing in detail down.
Please refer to Fig. 2.Fig. 2 is the functional block diagram of the electronic installation 110 of Fig. 1.Electronic installation 110 comprises comparer 102, bias circuit 104 and reset controller 106.Comparer 102 comprises logical circuit 108, first input end Ip1, the second input end Ip2 and output terminal Op1.Logical circuit 108 is coupled to the first input end Ip1 and the second input end Ip2, and behind the voltage that receives this two input end, relatively this two voltage at last by output terminal Op1, is exported judgment signal So to produce judgment signal So.Bias circuit 104 comprises p type metal oxide semiconductor transistor 200, is used for the switch of circuit for this reason, reaches two resistance R 1, R2, is used for producing internal reference voltage after circuit is opened.
After system and device 100 was opened, first jumper 150 transmit reference voltage Vref 1 or ground voltage 0V to first input end Ip1, and electronic installation 110 can be by coming into operation after the external signal activation with bias circuit 104 by switching.For example, with signal S RSETWhen being pulled to the signal low level, metal oxide semiconductor transistor 200 conductings, 104 of bias circuits pass through resistance R 1 and R2 at this moment, produce internal reference voltage Vref2, and export the second input end Ip2 to.Present embodiment is set at 0.6V in this with internal reference voltage Vref2.Then, logical circuit 108 begins relatively to input to two voltages of comparer 102, and whether the voltage of judging first input end Ip1 is greater than the voltage of the second input end Ip2.If the voltage that first input end Ip1 receives is reference voltage Vref 1, according to stitch series terminal logical specification, reference voltage Vref 1 should be 0.9V or 1.25V, and internal reference voltage Vref2 is 0.6V.Therefore, logical circuit 108 is judged as very, and produces judgment signal So, be worth for ' 1 '.If the voltage that first input end Ip1 receives is ground voltage 0V, be significantly less than the 0.6V of internal reference voltage Vref2, then logical circuit 108 is judged as vacation, and produces judgment signal So, be worth for ' 0 '.Then, after judgment signal So exported reset controller 106 to, reset controller 106 was judged the kind of this storer according to the value of judgment signal So.Wherein, the value of judgment signal So is ' 1 ' then to represent the DDR storer, is worth for ' 0 ' then to represent SDRAM.The operation of the kind of whole judgement storer is promptly finished.In addition, delayer (not being shown in Fig. 2) can be set between comparer 102 and the reset controller 106, this delayer can comprise several D flip-flops (Flip-Flop), is used for prolonging judgment signal So, makes reset controller 106 can stably receive comparative result.
Therefore, according to stitch series terminal logical OR low-voltag transistor logical specification, when DDR-SDRAM operated, it was 0.9V or 1.25V reference voltage Vref 1 that system and device 100 produces voltage; When SDRAM operated, first jumper 150 was connected to the end points S3 of ground connection, and this measure can be represented the standard that low-voltag transistor logical specification does not have provides reference voltage.Then, reference voltage Vref that electronic installation 110 of the present invention relatively receives 1 and the inner internal reference voltage Vref2 that produces, at last by reset controller 106 according to comparative result, finish the judgement of storer kind.
Please refer to Fig. 3.Fig. 3 is the process flow diagram according to the flow process of the present invention 30 of Fig. 2.Flow process 30 comprises following steps:
300: beginning.
310: receive internal reference voltage Vref2.
320: receive reference voltage Vref 1.
330: whether comparison reference voltage Vref1 is greater than internal reference voltage Vref2.If, produce judgment signal So, its value for ' 1 '; If not, produce judgment signal So, its value for ' 0 '.
340:, judge the kind of this storer according to the value of judgment signal So.
350: finish.
According to flow process 30, in the step 310, internal reference voltage Vref2 is produced by bias circuit 104, and its value is 0.6V.In step 320, if DDR-SDAM when running, reference voltage Vref 1 size is 0.9V or 1.25V; If during the SDRAM running, reference voltage Vref 1 size is 0V.In step 340,, then be judged as the DDR storer if the value of judgment signal So is ' 1 ' time; If the value of judgment signal So is ' 0 ' time, then be judged as SDRAM.
What pay special attention to is that according to using different memory kind or user's demand in the system, internal reference voltage Vref2 can adjust, and should not be limited to 0.6V.Judgment signal is the visible system inner setting also, changes the definition of its value, as also can be with value ' 1 ' be expressed as SDRAM, and value ' 0 ' be expressed as DDR.
In sum, known technology is to utilize a stitch to be connected in circuit arrangement, to judge the storer kind.Compared to known technology, the present invention is according to existing specification, by the voltage of comparison compliant and the size of internal reference voltage, to judge the storer kind.Therefore, the present invention utilizes the difference of the reference voltage of different memory standard, makes system's detection of stored device kind automatically, so can increase the adaptability and compatibility of system to storer, and on hardware is realized, can save a stitch, reduce the external circuit wiring, to save cost.
The above only is preferred embodiment of the present invention, and all equalizations of being done according to claim scope of the present invention change and modify, and all should belong to covering scope of the present invention.

Claims (13)

1. electronic installation that is used for judging the kind of storer includes:
Comparer is used for first voltage exported according to reference voltage and this storer, produces judgment signal, includes:
First input end is used for receiving this first voltage;
Second input end is used for receiving this reference voltage;
Logical circuit is coupled to this first input end and this second input end, is used for relatively this first voltage and this reference voltage, to produce this judgment signal; And
Output terminal is coupled to this logical circuit, is used for exporting this judgment signal; And
Reset controller is used for judging the kind of this storer according to this judgment signal.
2. electronic installation according to claim 1, it also includes bias circuit, is used for producing this reference voltage.
3. electronic installation according to claim 1, it also comprises delayer, is coupled between this output terminal and this reset controller, is used for prolonging the sequential of this judgment signal.
4. electronic installation according to claim 3, wherein this delayer comprises a plurality of D flip-flops.
5. electronic installation according to claim 1, wherein this storer is the double data rate (DDR) synchronous dynamic random access memory.
6. electronic installation according to claim 1, wherein this storer is a synchronous dynamic random access memory.
7. electronic installation according to claim 1, wherein this reference voltage is 0.6 volt.
8. method that is used for judging the kind of storer includes:
Receive reference voltage;
Receive first voltage that this storer is exported;
Relatively this first voltage and this reference voltage;
According to the comparative result of this first voltage and this reference voltage, produce judgment signal; And
According to this judgment signal, judge the kind of this storer.
9. method according to claim 8, wherein this reference voltage is produced by bias circuit.
10. method according to claim 8, it also comprises the sequential that prolongs this judgment signal.
11. method according to claim 8, wherein this storer is a synchronous dynamic random access memory.
12. method according to Claim 8, wherein this storer is the double data rate (DDR) synchronous dynamic random access memory.
13. method according to claim 8, wherein this reference voltage is 0.6 volt.
CNB2006101494146A 2006-11-17 2006-11-17 Be used for judging the electronic installation and the correlation technique thereof of the kind of storer Expired - Fee Related CN100552652C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2006101494146A CN100552652C (en) 2006-11-17 2006-11-17 Be used for judging the electronic installation and the correlation technique thereof of the kind of storer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2006101494146A CN100552652C (en) 2006-11-17 2006-11-17 Be used for judging the electronic installation and the correlation technique thereof of the kind of storer

Publications (2)

Publication Number Publication Date
CN101187907A CN101187907A (en) 2008-05-28
CN100552652C true CN100552652C (en) 2009-10-21

Family

ID=39480306

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2006101494146A Expired - Fee Related CN100552652C (en) 2006-11-17 2006-11-17 Be used for judging the electronic installation and the correlation technique thereof of the kind of storer

Country Status (1)

Country Link
CN (1) CN100552652C (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102637456B (en) * 2011-02-11 2016-03-23 慧荣科技股份有限公司 Memory Controller Hub, memory storage and judge the method for pattern of memory storage

Also Published As

Publication number Publication date
CN101187907A (en) 2008-05-28

Similar Documents

Publication Publication Date Title
CN1551235B (en) Semiconductor device for domain crossing
US6795906B2 (en) Memory controller, interface device and method using a mode selection signal to support different types of memories
US7253655B2 (en) Output driver robust to data dependent noise
US20030158981A1 (en) Memory bus polarity indicator system and method for reducing the affects of simultaneous switching outputs (SSO) on memory bus timing
US11551741B2 (en) Protocol for refresh between a memory controller and a memory device
US20030105932A1 (en) Emulation of memory clock enable pin and use of chip select for memory power control
JP5235036B2 (en) Differential online termination
US20050278490A1 (en) Memory access control apparatus and method of controlling memory access
US6498759B2 (en) System for automatic generation of suitable voltage source on motherboard
CN101131864A (en) Method and circuit for transmitting a memory clock signal
US7830733B2 (en) Devices, systems, and methods for independent output drive strengths
CN102467959A (en) Integrated circuit
US7761725B2 (en) Clock generation for synchronous circuits with slow settling control signals
CN110310684A (en) For providing the device and method of clock signal in semiconductor devices
US10192593B2 (en) Reception circuit for reducing current and electronic apparatus including the same
CN100552652C (en) Be used for judging the electronic installation and the correlation technique thereof of the kind of storer
CN106354679A (en) Interface circuit for high speed communication and system including the same
US20080111586A1 (en) Method for determining a memory type and related electronic device
US9853641B2 (en) Internal voltage generation circuit
US11189328B1 (en) Semiconductor devices and semiconductor systems
CN209804269U (en) Static power consumption circuit for reducing LPDAR (low power random Access memory) in deep sleep mode
CN1937075A (en) Data transfer operation completion detection circuit and semiconductor memory device provided therewith
KR100870424B1 (en) Internal voltage generating circuit
US11169562B1 (en) Electronic devices for controlling clock generation
US6556051B2 (en) Apparatus for providing both supports including synchronous dynamic random access memory (SDRAM) module and double data rate (DDR) DRAM module

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20091021

Termination date: 20171117