CN100552601C - Power control circuit - Google Patents
Power control circuit Download PDFInfo
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- CN100552601C CN100552601C CNB2006101003303A CN200610100330A CN100552601C CN 100552601 C CN100552601 C CN 100552601C CN B2006101003303 A CNB2006101003303 A CN B2006101003303A CN 200610100330 A CN200610100330 A CN 200610100330A CN 100552601 C CN100552601 C CN 100552601C
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Abstract
The invention discloses a kind of power control circuit, be used to change the output signal of a chipset, to be applicable to an electricity interface (ACPI) controller, this chipset is exported a dormant control signal and a power control signal.Above-mentioned signal power source control circuit is in the logical operation mode, dormant control signal and a power control signal is converted to the control signal of electricity interface controller, to adjust the power supply state of a host computer system.
Description
Technical field
The present invention is about a kind of power control circuit of power supply signal, and is applicable to power control circuit between chipset and the electricity interface controller especially in regard to kind.
Background technology
Because present attention for environmental protection and electrical efficiency, advanced configuration and electricity interface (advancedconfiguration and power interface, ACPI) specification, become the necessary specification of electronic product (as notebook computer) gradually, just on the mainboard the specification that must support.
Yet, be not that each designed chipset (South Bridge chip, north bridge chips) of tame chip design company all has the specification of supporting advanced configuration and electricity interface controller (being called for short electricity interface controller or ACPI controller).In the prior art, the ACPI controller is adjusted the power supply state of host computer system usually according to two control signals (being commonly referred to S3 and S5).But do not support the chipset of ACPI specification but can't provide above-mentioned S3 and S5 two control signals simultaneously.Just can't directly control the power supply supply status that the ACPI controller is adjusted host computer system.
Summary of the invention
One of them is that a kind of power control circuit is being provided for a purpose of the present invention, with the power control signal and the dormant control signal of logical operation circuit conversion chip group itself, meets the control signal of ACPI specification with generation.Allow the chipset of not supporting the ACPI specification also can produce the S3 of equivalence and the control signal of S5, and then control electricity interface controller.
One of them is that a kind of power control circuit is being provided for a purpose of the present invention, can be directly realizes in the mode of discrete component (as SMT), is integrated on the pcb board with chipset, and then shortens design and manufacturing process, reduces cost.
For reaching above-mentioned and other purpose, the present invention proposes a kind of power control circuit, be applicable to the output signal of conversion one chipset, to be applicable to an electricity interface controller, this chipset is exported a dormant control signal and a power control signal, and this power control circuit comprises: first phase inverter, second phase inverter, one and Men Yuyi or door.
Wherein, above-mentioned first phase inverter is in order to anti-phase dormant control signal, and exports an anti-phase dormant control signal, and second phase inverter is in order to an anti-phase power control signal, and exports an inverting power supplies control signal.Be coupled to second phase inverter with door, and, export one first interface signal according to dormant control signal and inverting power supplies control signal.Or door is coupled to the output terminal of this first phase inverter and the output terminal of this second phase inverter, and according to this anti-phase dormant control signal and this inverting power supplies control signal, exports one second interface signal.Wherein, above-mentioned electricity interface controller is adjusted the power supply state of a host computer system according to first interface signal and second interface signal.
The present invention can be directly realizes in the mode of discrete component, and is integrated on the pcb board with chipset, therefore, can shorten design and manufacturing process, reduces cost.In addition, the present invention is converted to the control signal of ACPI specification because of utilizing logic arithmetic element with the dormant control signal of chipset itself and the sequential of power control signal.Therefore, the present invention can be applicable to not support the chipset of the control signal of S3 and S5, makes chipset also can be used for controlling the ACPI controller.
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment of the present invention cited below particularly, and conjunction with figs. are described in detail below.
Description of drawings
Fig. 1 is the circuit diagram of power control circuit according to an embodiment of the invention.
Fig. 2 is the signal waveforms according to present embodiment.
Embodiment
See also Fig. 1, Fig. 1 is the circuit diagram according to one embodiment of the invention power control circuit.Power control circuit 110 is coupled between chipset (north bridge chips 120 and South Bridge chip 130) and the electricity interface controller 140 (hereinafter to be referred as ACPI controller 140).Wherein, north bridge chips 120 output one dormant control signal SCS (for example the SiS of Silicon Integration Systems Corp.(SIS) chipset 3V3AUX# pin position exported signal), South Bridge chip 130 then export a power control signal PCS (for example the SiS of Silicon Integration Systems Corp.(SIS) chipset pson# pin position exported signal).The first interface signal S3 and the second interface signal S5 that ACPI controller 140 is then exported according to power control circuit 110 adjust the power supply state of a host computer system.Those of ordinary skills should know above-mentioned north bridge chips 120, South Bridge chip 130 and the ACPI controller 140 operation details in system by inference easily via announcement of the present invention, do not add tired stating at this.
Next, further specify the signal waveform of present embodiment, see also Fig. 2, Fig. 2 is the signal waveforms according to present embodiment.Anti-phase dormant control signal ISCS then is the signal waveform of dormant control signal SCS after anti-phase.Inverting power supplies control signal IPCS then is the signal waveform of power control signal PCS after anti-phase.The first interface signal S3 and the second interface signal S5 that power control circuit 110 is exported are then as shown in Figure 2.
Above-mentioned dormant control signal SCS has two states, be dormant state and normal condition, in the present embodiment then with logic low potential (logical zero) expression dormant state (as the dormant control signal SCS in during the T3), with logic high potential (logical one) expression normal condition (as the dormant control signal SCS in during the T2).And above-mentioned power control signal PCS, has two states equally, be open state and off-mode, then represent open state (as the power control signal PCS in during the T2) in the present embodiment with logic low potential, in addition, power control signal PCS represents that then host computer system enters off-mode if be converted to logic high potential (as the power control signal PCS in during the T3) by logic low potential.
Then utilize the combination of dormant control signal SCS and the power control signal PCS logic current potential under different conditions in the present embodiment, and carry out logical operation, produce the first interface signal S3 and the second interface signal S5 by power control circuit 110.Make chipset come the power supply state of Adjustment System by control ACPI controller 140.
In the present embodiment, for host computer system is under initialization (for example just starting shooting) situation, dormant control signal SCS and power control signal PCS are all logic high potential during the T1.At this moment, the first interface signal S3 and the second interface signal S5 are all logic low potential, so that (S3 S5) equals (0,0) expression.
During T2, dormant control signal SCS is a logic high potential, and power control signal PCS is a logic low potential, the first interface signal S3 that produces through power control circuit 110 backs is a logic high potential, and the second interface signal S5 is a logic high potential, with (S3, S5) equal (1,1) expression.At this moment, ACPI controller 140 makes host computer system be in the normal power supply state.
During T3, dormant control signal SCS is a logic low potential, power control signal PCS is converted to logic high potential by logic low potential, the first interface signal S3 that produces through power control circuit 110 backs is a logic low potential, the second interface signal S5 is a logic high potential, so that (S3 S5) equals (0,1) expression.At this moment, ACPI controller 140 makes host computer system be in dormant state, and system data is stored among the internal memory, for example DRAM (Dynamic Random Access Memory) or static random access memory.
During T4, dormant control signal SCS is a logic high potential, and power control signal PCS is a logic low potential, the first interface signal S3 that produces through power control circuit 110 backs is a logic high potential, and the second interface signal S5 is a logic high potential, with (S3, S5) equal (1,1) expression.At this moment, ACPI controller 140 makes host computer system be in the normal power supply state.To similar during the above-mentioned T2.
During T5, dormant control signal SCS is a logic high potential, and power control signal PCS is a logic high potential, the first interface signal S3 that produces through power control circuit 110 backs is a logic low potential, and the second interface signal S5 is a logic low potential, with (S3, S5) equal (0,0) expression.At this moment, ACPI controller 140 makes host computer system be in dormant state, and system data is stored among the disk, for example hard disk.In another embodiment of the present invention, if (S3, when S5) equaling (0,0), ACPI controller 140 also can make host computer system only be in dormant state, and does not carry out the action of memory system data.
During above-mentioned T2～T5 dormant control signal SCS and the waveform combination of power control signal PCS under the different system state.Wherein, during the T2 be the normal power supply state during the T4, then represent signal waveform combination under the different dormant states respectively during the T3 with during the T5.Chipset (north bridge chips 120 with South Bridge chip 130) can utilize the variation of the signal waveform of the dormant control signal SCS that exported and power control signal PCS, by power control circuit 110, exports the first interface signal S3 and the second interface signal S5.140 power supply states of adjusting host computer system according to the first interface signal S3 and the second interface signal S5 of electricity interface controller.
Dormant control signal SCS and power control signal PCS that the present invention utilizes chipset itself to be provided export the control signal that is applicable to the ACPI specification via power control circuit.The chipset of not supporting the ACPI specification also can be integrated mutually with the ACPI controller, and then produce the effect of same power supplies control.Significantly promote the design convenience and the design cost of chipset.Simultaneously, circuit of the present invention is realized because of can directly utilizing discrete component, is had more the effect that shortens design time-histories and design cost.
Though the present invention discloses as above with preferred embodiment; right its is not in order to qualification the present invention, any those of ordinary skills, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is when with being as the criterion that claim was defined.
Claims (8)
1. power control circuit is used to change the output signal of a chipset,, it is characterized in that described chipset is exported a dormant control signal and a power control signal to be applicable to an electricity interface controller, and described power control circuit comprises:
One first phase inverter in order to anti-phase described dormant control signal, and is exported an anti-phase dormant control signal;
One second phase inverter in order to anti-phase described power control signal, and is exported an inverting power supplies control signal;
One with the door, be coupled to described second phase inverter, and, export one first interface signal according to described dormant control signal and described inverting power supplies control signal; And
One or the door, be coupled to the output terminal of described first phase inverter and the output terminal of described second phase inverter, and, export one second interface signal according to described anti-phase dormant control signal and described inverting power supplies control signal;
Wherein, described electricity interface controller is adjusted the power supply state of a host computer system according to described first interface signal and described second interface signal.
2. power control circuit as claimed in claim 1 is characterized in that described chipset comprises a north bridge chips, in order to export described dormant control signal.
3. power control circuit as claimed in claim 1 is characterized in that described chipset comprises a South Bridge chip, in order to export described power control signal.
4. power control circuit as claimed in claim 1 is characterized in that, if described first interface signal and described second interface signal are all logic high potential, then described electricity interface controller makes described host computer system be in the normal power supply state.
5. power control circuit as claimed in claim 1 is characterized in that, if described first interface signal and described second interface signal are all logic low potential, then described electricity interface controller makes described host computer system be in dormant state.
6. power control circuit as claimed in claim 1, it is characterized in that, if described first interface signal and described second interface signal are all logic low potential, then described electricity interface controller makes described host computer system be in dormant state, and described host computer system is stored in system data among one disk.
7. power control circuit as claimed in claim 1, it is characterized in that, if described first interface signal is a logic low potential, described second interface signal is a logic high potential, then described electricity interface controller makes described host computer system be in dormant state, and described host computer system is stored in system data among one internal memory.
8. power control circuit as claimed in claim 1 is characterized in that, described chipset is Silicon Integration Systems Corp.'s chipset.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101003303A CN100552601C (en) | 2006-06-30 | 2006-06-30 | Power control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101003303A CN100552601C (en) | 2006-06-30 | 2006-06-30 | Power control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101097484A CN101097484A (en) | 2008-01-02 |
| CN100552601C true CN100552601C (en) | 2009-10-21 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101003303A Expired - Fee Related CN100552601C (en) | 2006-06-30 | 2006-06-30 | Power control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100552601C (en) |
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2006
- 2006-06-30 CN CNB2006101003303A patent/CN100552601C/en not_active Expired - Fee Related
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| Publication number | Publication date |
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| CN101097484A (en) | 2008-01-02 |
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Granted publication date: 20091021 Termination date: 20110630 |