CN100547734C - Multilayered semiconductor substrate, semiconductor free-standing substrate and preparation method thereof and semiconductor device - Google Patents

Abstract

The invention provides a kind of 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE (1) and be used to prepare the method for this substrate.Go up formation semiconductor layer (12) in base substrate (11), and go up formation mask (13) at described semiconductor layer (12).Then, forming 3-5 group-III nitride semiconductor crystallizing layer (14) afterwards, 3-5 group-III nitride semiconductor crystallizing layer (14) and described base substrate (11) are being separated from each other by selective growth.The crystallinity of described semiconductor layer (12) is lower than the crystallinity of 3-5 group-III nitride semiconductor crystallizing layer (14).

Description

Multilayered semiconductor substrate, semiconductor free-standing substrate and preparation method thereof and semiconductor device

Technical field

The present invention relates to a kind of MULTILAYER SUBSTRATE of 3-5 group-III nitride semiconductor, a kind of method and a kind of semiconductor device that is used to prepare the self-support substrate of 3-5 group-III nitride semiconductor.

Background technology

The 3-5 group-III nitride semiconductor is used to prepare semiconductor device, and described semiconductor device is used for various displays.For example, as the material that is used for luminescent device such as ultraviolet ray or blue light-emitting diode or laser diode or be used for the material of high output or high-frequency electronic device, by the general formula I n of x+y+z=1,0≤x≤1,0≤y≤1 and 0≤z≤1 wherein _xGa _yAl _zThe compound semiconductor that N represents is known.Described compound semiconductor will abbreviate " 3-5 group-III nitride semiconductor " as.

By way of parenthesis, although forming the method for the luminescent device that comprises the 3-5 group-III nitride semiconductor on substrates such as sapphire knows, but when using by the material different with the 3-5 group-III nitride semiconductor, be sapphire etc. make substrate the time, the lattice constant or the thermal coefficient of expansion of substrate and 3-5 group-III nitride semiconductor differ from one another, therefore there is such problem, promptly after the epitaxial growth of 3-5 group-III nitride semiconductor, produce highdensity dislocation, perhaps on substrate, produce warpage, and in the worst case, it causes breaking.Owing to this reason, proposed a kind of double-heterostructure 3-5 group-III nitride semiconductor, it has n type 3-5 nitride semiconductor layer on the self-support substrate of 3-5 group-III nitride semiconductor, as the 3-5 nitride semiconductor layer and the p type 3-5 nitride semiconductor layer of active layer.According to open, this semiconductor growing is on the self-support substrate of the 3-5 group-III nitride semiconductor with low-dislocation-density, therefore its crystallinity is excellent, and provides the controlled luminescent device of a kind of deterioration of wherein emitting performance (for example, JP-A-2000-223743).Yet, at this moment, can not be industrial and the bulk substrate of being made by the 3-5 group-III nitride semiconductor is provided at an easy rate.

Therefore, proposed a kind of method that obtains the substrate of high crystalline, described method comprises the following steps: on Sapphire Substrate once property growth regulation 3-5 group-III nitride semiconductor, subsequently by using SiO ₂Mask selective growth on the 3-5 group-III nitride semiconductor (for example, JP-A-2002-170778).

In addition, proposed the method for the 3-5 group-III nitride semiconductor that a kind of acquisition separates with the base substrate of sapphire etc., described method is included in the step of growth regulation 3-5 group-III nitride semiconductor on the base substrate.For example, JP-A-2001-53056 discloses a kind of method that base substrate and GaN layer are separated from each other, and described method comprises the following steps: on base substrate once property growing GaN layer; On the GaN layer, form SiO ₂Striped; And the other GaN layer of regrowth thereon; Afterwards other GaN layer segment is etched to SiO ₂Striped is to form channel structure; On channel structure, further form the GaN layer so that the surface planarization of GaN layer is incorporated into etching solution in the channel structure subsequently with etching SiO ₂Striped.

Yet, in order on Sapphire Substrate, to form the GaN layer of the 3-5 group-III nitride semiconductor of high crystalline according to disclosed method in JP-A-2002-170778, need the following step, be step: implement so-called two step growth methods, described two step growth methods are included in and form low temperature buffer layer and under the high temperature more than 1000 ℃ that the GaN layer is formed thereon on the Sapphire Substrate; Disposable unloading 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE from the growing semiconductor crystal equipment; On the 3-5 nitride semiconductor layer, form SiO ₂The striped mask; It is reinstalled in the growing semiconductor crystal equipment, under the high temperature more than 1000 ℃, form the 3-5 group-III nitride semiconductor subsequently.Therefore, disclosed method must will need the crystal growth of the high temperature more than 1000 ℃ of some hrs to carry out twice in JP-A-2002-170778.

On the other hand, in order to obtain 3-5 group-III nitride semiconductor substrate, need the following step, i.e. step: need be such as the photoetching process processing channel structure of resist step of exposing by using according to disclosed method in JP-A-2001-53056; And further will under the high temperature more than 1000 ℃, the GaN crystal growth of some hrs surpass three times.

Therefore, each problem that has among JP-A-2002-170778 and the JP-A-2001-53056 is that it needs production cost high long process time.Therefore, can not produce high performance 3-5 group nitride compound semiconductor light emitting element at an easy rate.

Summary of the invention

The purpose of this invention is to provide method and a kind of semiconductor device of a kind of 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE, a kind of preparation 3-5 group-III nitride semiconductor self-support substrate, thereby can solve the aforementioned problems in the prior.

In order to address the above problem, the inventor throws oneself into the method for research a kind of preparation 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE (will abbreviate " 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE " as) with themselves, and 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE comprises the high-quality 3-5 group-III nitride semiconductor that is laminated on the substrate that is used for growth regulation 3-5 group-III nitride semiconductor (following will be called " base substrate ").The result, find at first on base substrate, to form low crystallizing layer, on low crystallizing layer, form the film of inorganic material then, form the 3-5 group-III nitride semiconductor subsequently thereon, provide a kind of high-quality 3-5 nitride semiconductor layer thus easily and easily with 3-5 nitride semiconductor layer leafing on the base substrate, thereby finished the present invention.

According to an aspect, the invention provides a kind of 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE, it comprises: base substrate; In order to apply the semiconductor layer of described base substrate; Mask in order to the part of the upper surface that applies described semiconductor layer; With in order to the exposed surface of the upper surface that applies described semiconductor layer and the 3-5 group-III nitride semiconductor crystallizing layer of described mask, described exposed surface is not applied by described mask, and the crystallinity of wherein said semiconductor layer is lower than 3-5 group-III nitride semiconductor crystallizing layer.

Preferably comprise hole in described semiconductor layer inside.

Preferred mask is in the shape of striped or point, and perhaps unshielded part is in shape a little.

Preferred mask comprises at least a material that is selected from the following material: SiO ₂, TiO ₂, ZrO ₂, CrO ₂, W, Re, Mo, Cr, Co, Si, Au, Zr, Ta, Ti, Nb, Ni, Pt, V, Hf, Pd, BN, W-nitride, Re-nitride, Mo-nitride, Cr-nitride, Si-nitride, Zr-nitride, Ta-nitride, Ti-nitride, Nb-nitride, V-nitride, Hf-nitride and Fe-nitride.

The preferred semiconductor layer is the resilient coating with material of following general formula: In _xGa _yAl _zN, wherein 0≤x≤1,0≤y≤1,0≤z≤1 and x+y+z=1; And described resilient coating is to grow under 400 ℃ to 700 ℃ temperature.

According to another aspect, the invention provides a kind of method of preparation 3-5 group-III nitride semiconductor self-support substrate, described method comprises the following steps: to form semiconductor layer on base substrate; On the part of the upper surface of described semiconductor layer, form mask; Form exposed surface and the described mask of 3-5 group-III nitride semiconductor crystallizing layer with the upper surface that applies described semiconductor layer with 3-5 group-III nitride semiconductor crystallizing layer by selective growth, described exposed surface is not applied by described mask; With 3-5 group-III nitride semiconductor crystallizing layer and described base substrate are separated from each other, the crystallinity of wherein said semiconductor layer is lower than 3-5 group-III nitride semiconductor crystallizing layer.

The preferable separate step comprise by stress application from the 3-5 group-III nitride semiconductor crystallizing layer mechanical layer from the step of base substrate.

Preferably after separating step, also comprise step with at least one chemical etching in mask and the semiconductor layer.

The preferable separate step comprises by reducing the step of atmosphere temperature leafing base substrate from the 3-5 group-III nitride semiconductor crystallizing layer.

According to another aspect, the invention provides 3-5 group-III nitride semiconductor self-support substrate according to any preparation in the said method.

According to another aspect, the invention provides any one semiconductor device that comprises in the above-mentioned 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE.

According to another aspect, the invention provides the semiconductor device that comprises above-mentioned 3-5 group-III nitride semiconductor self-support substrate.

According to the present invention, can under the situation that need not complicated processing, easily provide high-quality 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE, 3-5 group-III nitride semiconductor self-support substrate and high-performance semiconductor device.

Implement mode of the present invention

Describe an example of embodiment of the present invention in detail below with reference to accompanying drawing.

Fig. 1 is the cross-sectional view of expression according to the MULTILAYER SUBSTRATE of the 3-5 group-III nitride semiconductor of one embodiment of the invention.3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE (1) has following array structure, wherein will comprise the base substrate (11) as sapphire material; Semiconductor layer (12); Mask (13); With 3-5 group-III nitride semiconductor crystallizing layer (14) with this order lamination.Provide mask (13) to be used for 3-5 group-III nitride semiconductor crystallizing layer (14) selective growth, can go up the 3-5 group-III nitride semiconductor that forms the crystallinity excellence in base substrate (11) thus in base substrate (11).Word " selective growth " is illustrated on the part of substrate and forms mask, and on the exposed surface that the mask of no use of substrate applies the selective growth crystal.

In the present embodiment, mask (13) can be the striated mask, and with the proper spacing extension that is parallel to each other, the shape of mask (13) is not limited thereto wherein a plurality of striped bodies on predetermined direction.For example, can use point-like mask or have wherein not that masked portion is the mask of the shape of point-like.In addition, as the material that is used for mask (13), the material that preferred 3-5 group-III nitride semiconductor can not be grown or be difficult to grow thereon.Below concrete material will be described.

In order to improve the crystallinity of using the 3-5 group-III nitride semiconductor crystallizing layer (14) that the mask (13) be placed on the base substrate (11) forms by selective growth, and 3-5 group-III nitride semiconductor crystallizing layer (14) separated to obtain to comprise the 3-5 group-III nitride semiconductor self-support substrate of 3-5 group-III nitride semiconductor crystal (4) as key component from as shown in fig. 1 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE (1), settle semiconductor layer (12).Forming semiconductor layer (12) makes it be in the level that crystallinity is lower than 3-5 group-III nitride semiconductor crystallizing layer (14).At this, settle semiconductor layer (12) as resilient coating.

Because the low-crystalline of semiconductor layer (12), at the inner many holes (12A) that form of semiconductor layer (12), described hole (12A) is to produce by heating in the step that forms 3-5 group-III nitride semiconductor crystallizing layer (14).These holes (12A) trend towards frequently producing in the zone that is clipped between mask (13) and the base substrate (11).

The composition of semiconductor layer (12) can be substantially the same with the composition of 3-5 group-III nitride semiconductor crystallizing layer (14).Word " substantially the same " presentation layer (12,14) is differing from one another aspect the kind of dopant and the concentration.

The material of the semiconductor layer of An Zhiing (12) (can be called " low-crystalline semiconductor layer (12) ") preferably has general formula: In for this reason _xGa _yAl _zN, wherein 0≤x≤1,0≤y≤1,0≤z≤1 and x+y+z=1 make semiconductor layer (12) can fully realize the function that it needs.In addition, growth temperature is preferably in 400 ℃ to 700 ℃ scope.That is, be preferably formed low-crystalline semiconductor layer (12) as low temperature buffer layer.

This hole (12A) has reduced the mechanical strength of low-crystalline semiconductor layer (12), therefore design some good methods to provide little adaptability to changes to low-crystalline semiconductor layer (12), easily base substrate (11) is separated with 3-5 group-III nitride semiconductor crystallizing layer (14) thus, thereby the 3-5 group-III nitride semiconductor self-support that mainly comprises 3-5 group-III nitride semiconductor crystallizing layer (14) substrate can easily be provided.

Go up the semiconductor layer (15) that further formation is made by the 3-5 group-III nitride semiconductor on the surface of 3-5 group-III nitride semiconductor crystallizing layer (14) (14A), described semiconductor layer (15) has the function of the known luminescent device of structure, and 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE (1) is formed for the substrate of 3-5 group nitride compound semiconductor light emitting element thus.This semiconductor layer (15) with luminescent device function can have the structure of so-called double-heterostructure, and wherein emission layer is clipped in the middle by p type layer and n type layer.

Fig. 2 is the cross-sectional view according to the light emitting semiconductor device of one embodiment of the invention.This light emitting semiconductor device can be made by 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE (1) as shown in fig. 1.Base substrate (11) is separated and removed from 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE (1) as shown in fig. 1.Where necessary, with semiconductor layer (12) and mask (13) chemically or physical method remove.On the surface of 3-5 group-III nitride semiconductor crystallizing layer (14), form electrode (16), and on the surface of semiconductor layer (15), form electrode (17).In addition, 3-5 group-III nitride semiconductor crystallizing layer (14) has the n type electric conductivity in Fig. 2.

With reference now to Fig. 3,, will method that prepare 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE as shown in fig. 1 and the method for preparing 3-5 group-III nitride semiconductor self-support substrate according to one embodiment of the invention be described.

As the method for epitaxial growth 3-5 group-III nitride semiconductor crystallizing layer (14) and as the method for epitaxial growth semiconductor layer (12), can enumerate various known methods.For example, can use hydride vapour phase epitaxy method (HVPE method), molecular beam epitaxy (MBE method) or organic metal vapour phase epitaxy method (MOVPE method) independently, perhaps can be with any each layer that suitably is used for the multi-lager semiconductor layer on single MULTILAYER SUBSTRATE in these growing methods.Following description has illustrated the situation of wherein using MOVPE method and HVPE method, but the epitaxial growth method of the 3-5 group-III nitride semiconductor that is used for using in the present invention is not limited thereto.

At first, as shown in Fig. 3 (a), preparation base substrate (11).Preferred base substrate (11) is stable to obtain high-quality 3-5 group-III nitride semiconductor under growth conditions.Particularly, can use sapphire, SiC, Si etc. as base substrate (11).Particularly, compare with SiC or Si, sapphire occurs because of the stress after the crystal growth of compound semiconductor causes the frequency of breaking less, so sapphire can suitably be used for the present invention.

Now, as shown in Fig. 3 (b), go up growth low-crystalline semiconductor layer (12) in base substrate (11).At this, low-crystalline semiconductor layer (12) is the resilient coating of being made by the 3-5 group-III nitride semiconductor.Low-crystalline semiconductor layer (12) is preferably the low temperature buffer layer of being made by the material with following formula: In _xGa _yAl _zN, wherein 0≤x≤1,0≤y≤1,0≤z≤1 and x+y+z=1.In this case, when the film thickness of low-crystalline semiconductor layer (12) is crossed when thin, at high temperature form therein in the step step afterwards of 3-5 group-III nitride semiconductor crystallizing layer (14), crystal as the nuclear that is used for crystal growth evaporates, thereby will reduce the crystal mass of 3-5 group-III nitride semiconductor crystallizing layer (14).On the other hand, when the film thickness of low-crystalline semiconductor layer (12) is blocked up, increase, thereby will reduce the crystal mass of 3-5 group-III nitride semiconductor crystallizing layer (14) as the crystal of the nuclear that is used for crystal growth.Therefore, the film thickness of low-crystalline semiconductor layer (12) preferably is equal to or greater than 1nm and is equal to or less than 200nm, more preferably is equal to or greater than 10nm and is equal to or less than 100nm, and more preferably be equal to or greater than 10nm and be equal to or less than 50nm.In order to give low crystallizability to low-crystalline semiconductor layer (12), the growth temperature of low-crystalline semiconductor layer (12) is at preferred 400 ℃ to 700 ℃ and more preferably in 450 ℃ to 600 ℃ the scope.

Forming low-crystalline semiconductor layer (12) afterwards, going up at low-crystalline semiconductor layer (12) and form mask (13) (referring to Fig. 3 (c)).As the material that is used for mask (13), the material that preferred 3-5 group-III nitride semiconductor can not be grown or be difficult to grow thereon.For example, preferably this material is at least a material that is selected from the following material: SiO ₂, TiO ₂, ZrO ₂, CrO ₂, W, Re, Mo, Cr, Co, Si, Au, Zr, Ta, Ti, Nb, Ni, Pt, V, Hf, Pd, BN, W-nitride, Re-nitride, Mo-nitride, Cr-nitride, Si-nitride, Zr-nitride, Ta-nitride, Ti-nitride, Nb-nitride, V-nitride, Hf-nitride and Fe-nitride.When using metal such as W and Ti as mask, make at the interface between the 3-5 group-III nitride semiconductor crystal on mask and the mask and be exposed under the etching action that uses hydrogen or ammonium, thereby can in the interface, form hole, thus can be with the easy leafing of the semiconductor crystal that obtains.

The shape of mask (13) can be in any suitable shape such as striated, point-like or wherein not masked portion be the shape of point-like or the shape that is in mutual combination.When using metal such as W or Ti, can use H as mask ₂Or NH ₃The described material of etching makes low-crystalline semiconductor layer (12) part expose, and can use the whole surface of mask coated substrate.

When using the striated mask, width of fringe preferably is equal to or greater than 0.1 μ m and is equal to or less than 50 μ m, more preferably be equal to or greater than 1 μ m and be equal to or less than 30 μ m, also preferably be equal to or greater than 1 μ m and be equal to or less than 20 μ m, and more preferably be equal to or greater than 1 μ m and be equal to or less than 10 μ m.When width of fringe is wide, is difficult to use not masked portion of crystal embedding, and when narrow, is difficult to obtain high-quality crystal.In addition, the interval between described striped preferably is equal to or greater than 0.1 μ m and is equal to or less than 50 μ m, more preferably is equal to or greater than 1 μ m and is equal to or less than 20 μ m, also preferably is equal to or greater than 1 μ m and is equal to or less than 10 μ m.

When base substrate (11) by C (0001)-when surperficial sapphire is made, the direction of the striped of mask (13) can with＜1-100 direction or＜11-20 direction is parallel, perhaps can slightly be inclination with it.When direction tilted, preferred angle was more than 0.095 ° and less than 9.6 °.

When using the point-like mask, the shape of point-like mask can be any in polygon such as circle, triangle, quadrangle or the hexagon or can be these polygonal combinations.In these cases, the diameter of mask is (when it is shaped as polygon, diameter is corresponding to the area diameter of a circle identical with polygonal area) preferably be equal to or greater than 0.1 μ m and be equal to or less than 50 μ m, more preferably be equal to or greater than 1 μ m and be equal to or less than 30 μ m, also preferably be equal to or greater than 1 μ m and be equal to or less than 20 μ m, and more preferably be equal to or greater than 1 μ m and be equal to or less than 10 μ m.When mask diameters is excessive, is difficult to use not masked portion of crystal embedding, and when mask diameters is too small, is difficult to obtain high-quality crystal.In addition, mask space preferably is equal to or greater than 0.1 μ m and is equal to or less than 50 μ m, more preferably is equal to or greater than 1 μ m and is equal to or less than 20 μ m, also preferably is equal to or greater than 1 μ m and is equal to or less than 10 μ m.

When to use point-like mask and base substrate (11) be C (0001)-surperficial sapphire, the direction on the limit of point can with＜1-100 direction or＜11-20 direction is parallel, perhaps can slightly be inclination with it.When direction tilted, preferred angle was more than 0.095 ° and less than 9.6 °.

When masked portion did not have the shape of point-like, the some shape of masked portion can not be any in polygon such as circle, triangle, quadrangle or the hexagon or can be these polygonal combinations.The diameter of masked portion is not (when it is shaped as polygon, diameter is corresponding to the area diameter of a circle identical with polygonal area) preferably be equal to or greater than 0.1 μ m and be equal to or less than 50 μ m, more preferably be equal to or greater than 1 μ m and be equal to or less than 30 μ m, also preferably be equal to or greater than 1 μ m and be equal to or less than 20 μ m, and more preferably be equal to or greater than 1 μ m and be equal to or less than 10 μ m.When mask diameters is excessive, is difficult to use not masked portion of crystal embedding, and when mask diameters is too small, is difficult to obtain high-quality crystal.In addition, mask space preferably is equal to or greater than 0.1 μ m and is equal to or less than 50 μ m, more preferably is equal to or greater than 1 μ m and is equal to or less than 20 μ m, also preferably is equal to or greater than 1 μ m and is equal to or less than 10 μ m.

Can form mask by the photoetching of in field of semiconductor manufacture, knowing.The surface and the low-crystalline semiconductor layer (12) that to not have masked (13) to apply expose to form the growth district of growth regulation 3-5 group-III nitride semiconductor crystal (Q) (referring to Fig. 3 (c)) thereon.

Then, go up epitaxial growth 3-5 group-III nitride semiconductor at growth district (Q).At first, do not apply growth regulation 3-5 group-III nitride semiconductor on the surface of mask (13) thereon, and when forming facet-structure (14A), make low-crystalline semiconductor layer (12) exposure (referring to Fig. 3 (d)).Use this facet-structure of 3-5 group-III nitride semiconductor embedding (14A) of surface planarization then, and on the 3-5 group-III nitride semiconductor grown crystal, form 3-5 group-III nitride semiconductor crystallizing layer (14) (referring to Fig. 3 (e)) thus.

To be described more specifically as Fig. 3 (d) and the step (e).Low-crystalline semiconductor layer (12) is formed by the layer with following formula: In _xGa _yAl _zN, wherein 0≤x≤1,0≤y≤1,0≤z≤1 and x+y+z=1.When low-crystalline semiconductor layer (12) when comprising AlN, it is difficult to decompose, and therefore preferred low-crystalline semiconductor layer (12) is GaN and/or InGaN.When grown semiconductor layer (12) at low temperatures, the crystallinity of the semiconductor layer that obtains (12) is low.Therefore, use hydrogen or ammonium are etched in the semiconductor layer (12) under the mask (13), thereby form crystallization atmosphere or growth atmosphere, therefore, in low-crystalline semiconductor layer (12) inside is in zone between mask (13) and the base substrate (11), form hole (12A).In the x ray analysis of crystal structure, can be by the crystallinity of for example peak height and full width at half maximum (FWHM) assessment semiconductor layer (12).

When mask (13) is arranged on the low-crystalline semiconductor layer (12), afterwards according to the epitaxial growth method that is used for the 3-5 group-III nitride semiconductor, when being fed to unstripped gas etc. on the low-crystalline semiconductor layer (12), the 3-5 group-III nitride semiconductor is grown (referring to Fig. 3 (d)) from growth district (Q), and goes up the mask (13) that growth regulation 3-5 group-III nitride semiconductor is provided with embedding at low-crystalline semiconductor layer (12).The further growth of 3-5 group-III nitride semiconductor makes that almost all mask (13) is embedded in the 3-5 group-III nitride semiconductor.Then, after being embedded in mask (13) in the 3-5 group-III nitride semiconductor, further thereon epitaxial growth 3-5 group-III nitride semiconductor forms the 3-5 group-III nitride semiconductor crystallizing layer (14) (referring to Fig. 3 (e)) with the film thickness that needs thus.

Therefore, preferably include the method for the preparation 3-5 group-III nitride semiconductor crystallizing layer (14) of the following step: the low-crystalline semiconductor layer (12) that mask (13) is set is thereon gone up when forming facet-structure, growth regulation 3-5 group-III nitride semiconductor, the nitride-based semiconductor of the wherein embedding facet-structure of growing then and its surface planarization is to form 3-5 group-III nitride semiconductor crystallizing layer (14).Reason is as follows:

When mask (13) is arranged on the low-crystalline semiconductor layer (12), carry out then as go up this growth that forms facet-structure at growth district (Q), growth regulation 3-5 group-III nitride semiconductor is to pass through to promote lateral growth embedding facet-structure afterwards, and during with crystrallographic planeization (referring to Fig. 3 (e)), because it is crooked in the horizontal to arrive the dislocation of facet, can and be contained in the 3-5 group-III nitride semiconductor crystallizing layer (14) mask (13) embedding.In this case, can sharply reduce crystal defect.And when this growth carried out as the embedding facet-structure, the zone that can be positioned in 3-5 group-III nitride semiconductor crystallizing layer (14) inside on the mask (13) produces the hole part.Because it is crooked in the horizontal to arrive the dislocation of facet, and dislocation may end at the hole part, so high-quality crystal can be provided.

Then, the separating step (referring to Fig. 3 (f)) that 3-5 group-III nitride semiconductor crystallizing layer (14) is separated with base substrate (11) will be described.

Can 3-5 group-III nitride semiconductor crystallizing layer (14) be bonded to the step of supporting on the substrate (not have demonstration) providing before the step of separating base substrate (11).In this case, as supporting substrate, can use known film, for example metallic film and resin molding are as polymer film.Can be according to known method, by using low-temperature alloy lamination metal substrate.And, when using resin molding, can use thermosetting resin or light-cured resin as the support substrate.

When going up at the low-crystalline semiconductor layer (12) that applies base substrate (11) and when mask (13) is gone up growth regulation 3-5 group-III nitride semiconductor crystallizing layer (14), there is not the part of the low-crystalline semiconductor layer (12) that masked (13) apply etched when growth regulation 3-5 group-III nitride semiconductor crystallizing layer (14).Therefore, base substrate (11) is connected with 3-5 group-III nitride semiconductor crystallizing layer (14) is weak mutually.Owing to this reason, when the thickness of 3-5 group-III nitride semiconductor crystallizing layer (14) fully increases, internal stress and external carbuncle become easily and the concentrated area acts on zone between base substrate (11) and 3-5 group-III nitride semiconductor crystallizing layer (14), thereby cause this weak connection.As a result, particularly, these stress act on this zone with the form of shear stress etc.When this stress increases, the coupling part fracture between base substrate (11) and 3-5 group-III nitride semiconductor crystallizing layer (14), both are separated from one another.Therefore, fracture between base substrate (11) and 3-5 group-III nitride semiconductor crystallizing layer (14) specifically occurs in the following column region: the borderline region between base substrate (11) and low-crystalline semiconductor layer (12), borderline region between low-crystalline semiconductor layer (12) and mask (13), borderline region between low-crystalline semiconductor layer (12) and 3-5 group-III nitride semiconductor crystallizing layer (14), or the borderline region between mask (13) and 3-5 group-III nitride semiconductor crystallizing layer (14), or a plurality of borderline regions in these borderline regions.

As the another kind of method that 3-5 group-III nitride semiconductor crystallizing layer (14) is separated with base substrate (11), can enumerate by the method for stress application with its mechanical separation.Stress can be internal stress or external carbuncle.Particularly, can enumerate the method that internal stress and/or external carbuncle is applied to the zone between base substrate (11) and 3-5 group-III nitride semiconductor crystallizing layer (14).Internal stress and/or external carbuncle are applied on this zone, thereby base substrate (11) can be separated (or leafing) easily with 3-5 group-III nitride semiconductor crystallizing layer (14).

As comprising the method for using internal stress, can enumerate difference, by the applied stress method of leafing base substrate (11) spontaneously based on the thermal coefficient of expansion between 3-5 group-III nitride semiconductor crystallizing layer (14) and base substrate (11).Particularly, this method can be used the following step: they are cooled to room temperature from the growth temperature of 3-5 group-III nitride semiconductor crystallizing layer (14); By using cryogenic media such as liquid nitrogen that they are cooled off from room temperature; Perhaps that they are hot again from room temperature, subsequently by using cryogenic media such as liquid nitrogen that they are cooled off.

As comprising the method for using external carbuncle, can enumerate the method that comprises the following steps: one in 3-5 group-III nitride semiconductor crystallizing layer (14) and the base substrate (11) is fixed and mechanical shock is administered on another.

According to said method, can mainly be comprised the 3-5 group-III nitride semiconductor crystal of the 3-5 group-III nitride semiconductor crystallizing layer (14) that is independent of base substrate (11), thereby be obtained 3-5 group-III nitride semiconductor self-support substrate.

The downside surface of the 3-5 group-III nitride semiconductor crystallizing layer (14) that separates with base substrate (11) comprises mask (13), therefore can handle as etching or Physical Processing processing by chemical process and remove mask (13) to utilize as grinding or polishing.For example, can remove oxide such as SiO with acid ₂In this case, can settle raceway groove or through hole to make etching solution such as acid can easily arrive mask (13) material to base substrate (11) in advance.Forming 3-5 group-III nitride semiconductor crystallizing layer (14) afterwards, can settle through hole or raceway groove from the surface of 3-5 group-III nitride semiconductor crystallizing layer (14).And, can make in radiation such as the laser interface between base substrate (11) and low-crystalline semiconductor layer (12) to be absorbed, part is decomposed low-crystalline semiconductor layer (12) to promote the leafing between low-crystalline semiconductor layer (12) and the base substrate (11).

As the method for epitaxial growth 3-5 group-III nitride semiconductor crystallizing layer (14), can enumerate MOVPE method, HVPE method, MBE method etc.When using MOVPE method growth low-crystalline semiconductor layer (12) or 3-5 group-III nitride semiconductor crystallizing layer (14), can use following compounds as raw material.

As the 3rd family's raw material, for example can enumerate, by general formula R ₁R ₂R ₃Ga (R wherein ₁, R ₂, R ₃In each is identical with other independently or different with other, and the expression low alkyl group) trialkyl gallium of expression, as trimethyl gallium [(CH ₃) ₃Ga below can be described to " TMG "] or triethyl-gallium [(C ₂H ₅) ₃Ga below can be described to " TEG "]; By general formula R ₁R ₂R ₃Al (R wherein ₁, R ₂, R ₃In each is identical with other independently or different with other, and the expression low alkyl group) trialkylaluminium of expression, as trimethyl aluminium [(CH ₃) ₃Al below can be described to " TMA "], triethyl aluminum [(C ₂H ₅) ₃Al below can be described to " TEA "] or triisobutyl aluminium [(i-C ₄H ₉) ₃Al]; Trimethyl amine alane [(CH ₃) ₃N:AlH ₃]; By general formula R ₁R ₂R ₃In (R wherein ₁, R ₂, R ₃In each is identical with other independently or different with other, and the expression low alkyl group) the trialkyl indium of expression, as trimethyl indium [(CH ₃) ₃In below can be described to " TMI "] or triethylindium [(C ₂H ₅) ₃In]; By replace the raw material of one or two alkyl preparation in the trialkyl indium respectively with one or two halogen atom, as chlorination diethyl indium [(C ₂H ₅) ₂InCl]; By the indium halide of general formula I nX (wherein X is a halogen atom) expression, as inidum chloride; Or the like.These raw materials can use separately or with the form of its mixture.In these the 3rd family raw materials, the gallium source is preferably TMG, and the aluminium source is preferably TMA, and the indium source is preferably TMI.

As the 5th family's raw material, can enumerate for example ammonia, hydrazine, methylhydrazine, 1,1-Dimethylhydrazine, 1,2-Dimethylhydrazine, tert-butylamine, ethylenediamine etc.These raw materials can be separately or are used with their form of mixtures of any combination.Because among these raw materials, ammonia and hydrazine do not comprise carbon atom in their molecule, so semiconductor is little by carbon contamination.Therefore preferred ammonia and hydrazine.Be easy to acquired viewpoint, more preferably ammonia for high purity product.

In the MOVPE method, as the atmosphere gas in growth course with as being used for the carrier gas of organic metal raw material, can be separately or such as the gas of nitrogen, hydrogen, argon gas and helium with their the form use of mixture.Wherein, preferred hydrogen and helium.

Above-mentioned raw materials gas is incorporated in the reactor, subsequently the growing nitride semiconductor.Described reactor comprises and is used for the raw material supply pipeline of unstripped gas from the raw material supply system supply to reactor and the pedestal that is used for heated substrate at inside reactor.Pedestal have usually can be by the circulator rotation structure with growing nitride semiconductor layer equably.Heater with heating base is placed in the pedestal as infrared lamp.By this heating, make the unstripped gas that is fed in the reactor by the raw material supply pipeline pass through this heating pyrolysis on growth substrates, make that the compound that needs can vapor phase growth on substrate.The unreacted feed gas that is fed to the unstripped gas in the reactor is discharged from reactor by exhaust line, be transported in the waste gas treatment equipment subsequently.

And, when according to HVPE method growing nitride semiconductor layer, can use following compounds as raw material.

As the 3rd family's raw material, can enumerate gallium chloride gas by making gallium metal and hydrogen chloride gas prepared in reaction, the inidum chloride gas by making indium metal and hydrogen chloride gas prepared in reaction etc.As the 5th family's raw material, can enumerate ammonia.As carrier gas, can be separately or use such as the gas of nitrogen, hydrogen or helium with their form of mixture.Wherein, preferred hydrogen and helium.Above-mentioned raw materials gas is incorporated in the reactor, subsequently the growing nitride semiconductor.

In addition, when according to MBE method growing nitride semiconductor layer, can use following compounds as raw material.

As the 3rd family's raw material, can enumerate metal such as gallium, aluminium or indium.As the 5th family's raw material, can enumerate gas such as nitrogen or ammonia.As carrier gas, can be separately or use such as the gas of nitrogen, hydrogen, argon gas or helium with their form of mixture.Wherein, preferred hydrogen and helium.Above-mentioned raw materials gas is incorporated in the reactor, subsequently the growing nitride semiconductor.

After finishing the step shown in Fig. 3 (e), can go up at 3-5 group-III nitride semiconductor crystallizing layer (14) and form another kind of 3-5 nitride semiconductor layer.In this case, on 3-5 group-III nitride semiconductor crystallizing layer (14), mask is set further, and further forms facet-structure, then with the facet-structure embedding, subsequently with the complanation of 3-5 nitride semiconductor layer.Even in this case, the dislocation that arrives facet is crooked on side direction, thereby can and be contained in nitride semiconductor layer inside with the mask embedding.So crystal defect sharply reduces.The 3-5 nitride semiconductor layer can not mixed or is doped with impurity.

Can be according to MOVPE method or the HVPE method this 3-5 group-III nitride semiconductor of growing.When by stressor layers during from the 3-5 nitride semiconductor layer, the total film thickness of 3-5 nitride semiconductor layer is equal to or greater than 3 μ m and is equal to or less than 500 μ m, preferably be equal to or greater than 10 μ m and be equal to or less than 400 μ m, more preferably be equal to or greater than 10 μ m and be equal to or less than 65 μ m, also preferably be equal to or greater than 10 μ m and be equal to or less than 45 μ m.When film thickness increased, dislocation density trended towards reducing.Yet when the thickness of lamination increased, it is high a lot of that production cost becomes, therefore not preferred excessive thickness.3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE can be unloaded from reactor after cooling, and separate, reinstall afterwards in the reactor to form n type contact layer, emission layer and p type layer with base substrate.

In addition, can on 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE, form n type contact layer, emission layer and p type layer continuously, wherein form the 3-5 group-III nitride semiconductor with preset thickness.Afterwards, epitaxial substrate is unloaded from reactor, and remove substrate, on the nitride-based semiconductor substrate that obtains, form electrode to form luminescent device by known method.

In order not increase the operating voltage of luminescent device, the n type carrier density of n type contact layer preferably is equal to or greater than 1 * 10 ¹⁸Cm ^-3And be equal to or less than 1 * 10 ¹⁹Cm ^-3When growth under 850 ℃ to 1100 ℃ growth temperature has the wherein general formula I n of 0≤x≤1,0≤y≤1,0≤z≤1 and x+y+z=1 _xGa _yAl _zDuring the crystal of N, n type dopant gas or organic metal raw material are mixed into known method in the InGaAlN raw material with suitable amount, can obtain this n type contact layer easily by comprising.As n type dopant gas, preferred silane, disilane, germane, tetramethyl germanium etc.

In addition, when the molar fraction of In or Al was high, particularly at low temperatures, crystal mass reduced, and carrier density increases.Therefore, In content preferably is equal to or less than 5%, and more preferably is equal to or less than 1%, and Al content preferably is equal to or less than 5%, and more preferably is equal to or less than 1%.N type contact layer most preferably comprises GaN.

Can be with by the general formula I n of a+b+c=1,0≤a≤1,0≤b≤1,0≤c≤1 wherein _aGa _bAl _cThe 3-5 nitride semiconductor layer of the material that N represents is placed between n type contact layer and the luminescent layer.The 3-5 group-III nitride semiconductor can have sandwich construction, wherein each layer form with carrier density aspect different with other layer.

On n type contact layer, form luminescent layer.Luminescent layer has multi-quantum pit structure, and described multi-quantum pit structure comprises and has the wherein general formula I n of a+b+c=1,0≤a≤1,0≤b≤1,0≤c≤1 _aGa _bAl _cThe barrier layer of the material of N and have the wherein general formula I n of a+b+c=1,0≤a≤1,0≤b≤1,0≤c≤1 _aGa _bAl _cThe trap layer of the material of N.The trap layer can have multilayer or can have one deck at least.

Can the wherein general formula I n of a+b+c=1,0≤a≤1,0≤b≤1,0≤c≤1 will be had _aGa _bAl _cThe layer of the material of N is placed between luminescent layer and the above-mentioned p type contact layer.This layer is preferably the AlGaN layer.The AlGaN layer can be p type or n type.When it was the n type, carrier density preferably was equal to or less than 1 * 10 ^-18Cm ^-3, more preferably be equal to or less than 1 * 10 ^-17Cm ^-3, and preferably be equal to or less than 1 * 10 ^-16Cm ^-3In order to reduce the n type carrier density of AlGaN layer, doping Ma.By way of parenthesis, can be with by the general formula I n of 0≤d≤1,0≤e≤1,0≤f≤1, d+e+f=1 wherein _dGa _eAl _fThe layer of the material that N represents, the space charge density of this layer is lower than the space charge density of AlGaN layer, is placed between p type contact layer and the AlGaN layer.

On the AlGaN layer, form p type contact layer.In order not increase the operating voltage of luminescent device, the p type carrier density of p type contact layer preferably is equal to or greater than 5 * 10 ¹⁵Cm ^-3, and more preferably 1 * 10 ¹⁶Cm ^-3To 5 * 10 ¹⁹Cm ^-3Scope in.When having the wherein general formula I n of a+b+c=1,0≤a≤1,0≤b≤1,0≤c≤1 _aGa _bAl _cThe crystal of N is mixed into doped raw material gas in the InGaAlN raw material with grown crystal with appropriate amount by comprising when growing under 800 ℃ to 1100 ℃ the growth temperature, and heat treated subsequently known method can easily be settled this p type contact layer.

In addition, when the molar fraction of Al was high, the contact resistance of p type contact layer trended towards increasing.Therefore, Al content is generally equal to or less than 5%, and preferably is equal to or less than 1%.

P type contact layer more preferably comprises GaAlN or GaN, and most preferably comprises GaN.

When using above-mentioned each layer of MOVPE method growth, can suitably select to use following raw materials according.

As the 3rd family's gallium material, can enumerate by general formula R ₁R ₂R ₃Ga (R wherein ₁, R ₂, R ₃In each is identical with other independently or different with other, and be low alkyl group) trialkyl gallium of expression, as trimethyl gallium (TMG) or triethyl-gallium (TEG).

As aluminum feedstock, can enumerate by general formula R ₁R ₂R ₃Al (R wherein ₁, R ₂, R ₃In each is identical with other independently or different with other, and be low alkyl group) trialkylaluminium of expression, as trimethyl aluminium (TMA) or triethyl aluminum (TEA) or triisobutyl aluminium.

As the indium raw material, can enumerate by general formula R ₁R ₂R ₃In (R wherein ₁, R ₂, R ₃In each is identical with other independently or different with other, and the expression low alkyl group) the trialkyl indium of expression, as trimethyl indium (TMI) or triethylindium; By replace the raw material of one to three alkyl preparation in the trialkyl indium respectively with one to three halogen atom, as chlorination diethyl indium; By the indium halide of general formula I nX (wherein X is a halogen atom) expression, as inidum chloride; Or the like.

As the 5th family's raw material, can enumerate for example ammonia, hydrazine, methylhydrazine, 1,1-Dimethylhydrazine, 1,2-Dimethylhydrazine, tert-butylamine, ethylenediamine etc.These raw materials can be separately or are used with their form of mixtures of any combination.Because among these raw materials, ammonia and hydrazine do not comprise carbon atom in their molecule, so semiconductor is little by carbon contamination.Therefore preferred ammonia and hydrazine.

As p type dopant, can enumerate for example Mg, Zn, Cd, Ca and Be.Wherein, preferably use Mg and Ca.As Mg raw material, can use for example two (cyclopentadienyl group) magnesium [(C as p type dopant ₅H ₅) ₂Mg], two (methyl cyclopentadienyl) magnesium [(C ₅H ₄CH ₃) ₂Mg], two (ethyl cyclopentadienyl group) magnesium [(C ₅H ₄C ₂H ₅) ₂Mg] etc.As the Ca raw material, can use two (cyclopentadienyl group) calcium [(C ₅H ₅) ₂Ca] or derivatives thereof, for example two (methyl cyclopentadienyl) calcium [(C ₅H ₄CH ₃) ₂Ca], two (ethyl cyclopentadienyl group) calcium [(C ₅H ₄C ₂H ₅) ₂Ca] or two (perfluor cyclopentadienyl group) calcium [(C ₅F ₅) ₂Ca]; (two-1-naphthyl) calcium or derivatives thereof; Or ethinylation calcium or derivatives thereof, for example, two (4,4-two fluoro-3-butene-1-alkynyls) calcium or two (phenylacetylene base) calcium.These raw materials can be separately or are used with their two or more the form of mixture.

By way of parenthesis, although above-mentioned embodiment has illustrated the situation of using the MOVPE method, but the invention is not restricted to this method, and can use any other known method of growth regulation 3-5 group-III nitride semiconductor crystal, as hydride gas-phase epitaxy (HVPE) method or molecular beam epitaxy (MBE) method.

Preparation method of the present invention is characterised in that on low-crystalline semiconductor layer such as low temperature buffer thing and forms mask.Form mask on low crystallizing layer, the 3-5 group-III nitride semiconductor is grown on side direction, and growth makes mask by embedding, can obtain low dislocation and high-quality 3-5 group-III nitride semiconductor crystal thus.

In addition, in the semi-conductive process of growing nitride, with hydrogen in the atmosphere or ammoniacal etchant low-crystalline semiconductor layer, make the bond strength at interface of low-crystalline semiconductor layer and nitride-based semiconductor reduce, the leafing from the substrate thereby the 3-5 group-III nitride semiconductor becomes easily, thus can be by because the strain that heat or mechanical stress cause, with 3-5 group-III nitride semiconductor leafing from the substrate.

Alternatively, radiation such as laser are absorbed in the interface of base substrate and 3-5 group-III nitride semiconductor or mask, thus with base substrate and the mutual leafing of nitride-based semiconductor.As a result, can provide high-quality 3-5 group-III nitride semiconductor substrate.In addition, when base substrate is separated with nitride, can chemically remove mask material or low crystallizing layer.

Can use above-mentioned 3-5 group-III nitride semiconductor self-support substrate same as before and wherein form the nitride-based semiconductor substrate of layer with emission function with the self-support substrate.Yet,, these substrates suitably can be placed on the support member to utilize in order to improve heat-radiating properties and/or rigidity.In addition, can in subsequent step, remove support member.

For example, as shown in Figure 9, can 3-5 group-III nitride semiconductor self-support substrate (19) be placed in the metal with the thickness that needs by bonding or other appropriate method and support on the substrate (18).Alternatively, the nitride-based semiconductor substrate that comprises 3-5 group-III nitride semiconductor self-support substrate (19) can be placed on the support substrate (18).Alternatively, as shown in Figure 10, can nitride-based semiconductor substrate (21) be applied in the recess of light emitting semiconductor device assembly (20) by bonding or other method that is fit to.

When in this way directly being applied to nitride-based semiconductor substrate of the present invention on the light emitting semiconductor device assembly with high specific thermal conductivity, the linearity of brightness-electric current line can be remained to high current density.

Embodiment

Below, will further specify the present invention based on embodiment, but the present invention is not intended to and is limited to this.

(embodiment 1)

As described below, prepare 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE (1) shown in Figure 1.Use its C-surface by bright finished sapphire as base substrate (11).The MOVPE method is used for epitaxial growth.Carrier gas, ammonia and TMG are fed in the growth room under 1atm, and the temperature with pedestal remains on 485 ℃ simultaneously, and uses hydrogen as carrier gas, and growth thickness is about the GaN resilient coating (low-crystalline semiconductor layer (12)) of 60nm subsequently.

In case base substrate (11) is unloaded from the growth room, just forming film thickness by photoetching technique is the SiO of 80nm ₂(at this, width of fringe is 5 μ m to striped; The fringe spacing is 5 μ m; And described striped and Sapphire Substrate＜1-100〉direction is parallel) as mask (13).Then, the base substrate (11) that forms low-crystalline semiconductor layer (12) on it is refitted in the growth room, described low-crystalline semiconductor layer (12) has the mask (13) that forms thereon.

Then, as described below, form 3-5 group-III nitride semiconductor crystallizing layer (14).At first, the pressure of inside reactor is set at 500Torr, and the temperature of pedestal is set at 1120 ℃, afterwards, carrier gas, ammonia and TMG were fed in the reactor to form unadulterated GaN layer with 4.0slm, 4.0slm and 35sccm respectively in 90 minutes.In addition, remain at pressure under the situation of 500Torr inside reactor, base-plate temp is set at 1080 ℃, afterwards carrier gas, ammonia and TMG was fed in the reactor to form unadulterated GaN layer with 4.0slm, 4.0slm and 50sccm respectively in 360 minutes.At last, make the thickness of unadulterated GaN layer growth to 35 μ m to form 3-5 group-III nitride semiconductor crystallizing layer (14).

Afterwards, temperature of reactor is reduced to room temperature, and the product that obtains is unloaded from reactor, cause leafing in the Sapphire Substrate (being growth substrates (11)) and the interface of 3-5 group-III nitride semiconductor crystallizing layer (14) thus, thus the nitride semiconductor free-standing substrate (GaN monocrystalline) that acquisition separates with Sapphire Substrate.X ray and SiO when incident ₂When striped was parallel, the horizontal narrow slit width of accepting side at X ray was under the condition of 62.5 μ m, and the full width at half maximum (FWHM) of (0004) of being calculated by X-ray diffraction is 165arcsec, and as the X ray and the SiO of incident ₂When striped was vertical, it was 189arcsec.Thereby can obtain high crystalline GaN self-support substrate.

(embodiment 2)

According to method identical in embodiment 1, make the CaN layer grows to 35 μ m on Sapphire Substrate thickness to form 3-5 group-III nitride semiconductor crystal (14), difference is SiO ₂Striped is set at the fringe spacing of width of fringe, 3 μ m of 7 μ m and described striped and Sapphire Substrate＜1-100〉direction is parallel.

Afterwards, temperature of reactor is reduced to room temperature, and the product that obtains is unloaded from reactor, cause leafing at the interface of Sapphire Substrate and 3-5 group-III nitride semiconductor crystal (14) thus, thereby the nitride-based semiconductor substrate (GaN monocrystalline) that acquisition separates with Sapphire Substrate.X ray and SiO when incident ₂When striped was parallel, the GaN layer that obtains was 156arcsec by the full width at half maximum (FWHM) of (0004) that X-ray diffraction calculates, and worked as the X ray and the SiO of incident ₂When striped was vertical, it was 120arcsec.Thereby can obtain high crystalline GaN self-support substrate.

(embodiment 3)

According to method identical in embodiment 1, make the GaN layer grows to 35 μ m on Sapphire Substrate thickness to form 3-5 group-III nitride semiconductor crystal (14), difference is SiO ₂Striped is set at the fringe spacing of width of fringe, 7 μ m of 3 μ m and described striped and Sapphire Substrate＜1-100〉direction is parallel.

Afterwards, temperature of reactor is reduced to room temperature, and the product that obtains is unloaded from reactor.X ray and SiO when incident ₂When striped was parallel, the GaN layer that obtains was 184arcsec by the full width at half maximum (FWHM) of (0004) that X-ray diffraction calculates, and worked as the X ray and the SiO of incident ₂When striped was vertical, it was 120arcsec.Thereby can obtain high crystalline GaN self-support substrate.

(comparative example 1)

According to embodiment 1 in the identical method of method, the thickness that makes GaN layer growth to 35 μ m is to form 3-5 group-III nitride semiconductor crystal (14), difference is not form SiO ₂Striped.Do not observe the leafing of GaN layer on the Sapphire Substrate.Then, the full width at half maximum (FWHM) of (0004) of being calculated by X-ray diffraction of the GaN layer that obtains is 360arcsec, and is irrelevant with the incident direction of X ray.

(embodiment 4)

Under the situation of the excitation peak wavelength of 364nm and GaN plane of crystal cathodoluminescence (abbreviating " CL " as), observe the non-luminous component in each sample that in embodiment 1 to 3 and comparative example 1, obtains.Non-luminous component is called " stain ", and described " stain " is considered to corresponding dislocation.Therefore calculate dislocation density by the quantity of non-luminous component.The result is summarized as follows:

	Width of fringe/at interval	Dislocation density
			Embodiment
1	5μm/5μm	5 to 8 * 10 7cm -2
			Embodiment 2	7μm/3μm	5 to 8 * 10 7cm -2
Embodiment 3	3μm/7μm	4×10 8cm -2
			Comparative example	Do not have	＞1×10 9cm -2

(embodiment 5)

Make the GaN layer on Sapphire Substrate, grow to 35 μ m with method similar to Example 1.Then, in order to give electronic transmission performance, with the GaN layer of silane Doped GaN layer with formation Si doping to the GaN layer.According to following method, on this layer, be formed for the luminescent layer of blue-ray LED.At first, temperature of reactor is reduced to 780 ℃, and uses nitrogen as carrier gas, thus the thickness of AlGaN layer growth to the 25 μ m that mixes by the Mg that described method is repeated 5 secondary growth GaN (InGaN, GaN), make afterwards to have 0.05%Al.Then, temperature of reactor is increased to 1040 ℃, and with carrier gas, ammonia, TMG and Cp ₂The mist of Mg is incorporated in the reactor, and forming thickness with 30 minutes growth time subsequently is the GaN layer that the Mg-of 150nm mixes.Afterwards, temperature of reactor is reduced to room temperature, and product is unloaded from reactor, the interface of the GaN layer that mixes at growth substrates and Mg causes leafing thus, thereby obtains the nitride-based semiconductor substrate that separates with growth substrates.

The 3-5 compound semiconductor substrate of preparation is as mentioned above unloaded from reactor, and under 800 ℃ temperature, AN 20 minutes, the GaN layer that Mg is mixed is transformed into low resistance p type layer.On each sample that obtains, form electrode to form light-emitting diode (LED) with common method.Use the Ni-Au alloy as p type electrode, and use Al as n type electrode.

When the luminescent properties of the luminescent device that voltage is applied on the luminescent device that obtains and detects wafer shape, it demonstrates bright and blue luminous.

(reference example 1)

About the grown buffer layer step, form striped step, unadulterated GaN layer 1020 ℃ 75 minutes step of temperature growth, according to the identical method of method in embodiment 1, form unadulterated GaN layer.After with the product cooling, (SEM) observes its cross section by scanning electron microscopy.As shown in Figure 4, many holes have been formed in the low temperature buffer layer below mask.In addition, as shown in " bird's eye " SEM image of Fig. 5, in side surface, form GaN layer with [11-22] faceted surface.

(reference example 2)

After the GaN crystal growth in reference example 1, form unadulterated GaN layer according to the method identical with method among the embodiment 1, until with embodiment 1 in the similar method of method make unadulterated GaN layer 1120 ℃ temperature growth 90 minutes.After with the product cooling, observe " bird's eye " SEM image of GaN crystal.As shown in Figure 6, on the whole surface of GaN crystal, obtain smooth film.

(reference example 3)

Form unadulterated GaN layer according to the method identical with method in the reference example 2, difference is growth temperature is set at 1100 ℃.After with the product cooling, observe " bird's eye " SEM image of GaN crystal.As shown in Figure 7, the surface of GaN crystal is not by embedding.

(reference example 4)

Form unadulterated GaN layer according to the method identical with method in the reference example 2, difference is growth temperature is set at 1140 ℃.After with the product cooling, observe " bird's eye " SEM image of GaN crystal.As shown in Figure 8, on the whole surface of GaN crystal, obtain smooth film.

(comparative example 2)

According to two one-step growths on as the Sapphire Substrate of base substrate with 2 μ m lamination GaN layers, on the surface of GaN layer, form SiO then ₂Striped (have the width of fringe of 5 μ m, the fringe spacing of 5 μ m, and described striped and Sapphire Substrate＜1-100〉direction is parallel), in reactor, make the GaN crystal finally grow to 35 μ m subsequently to form 3-5 group-III nitride semiconductor crystallizing layer.After cooling, product is unloaded from reactor.Yet, can not be with GaN layer leafing on the Sapphire Substrate.

The accompanying drawing summary

Fig. 1 is the end view according to the substrate of one embodiment of the invention;

Fig. 2 is the end view by the light emitting semiconductor device of the acquisition of the substrate shown in Fig. 1;

Fig. 3 is the process schematic representation of another embodiment of the invention;

Fig. 4 is the cross section SEM figure of reference example 1;

Fig. 5 is reference example 1 " bird's eye " SEM figure;

Fig. 6 is reference example 2 " bird's eye " SEM figure;

Fig. 7 is reference example 3 " bird's eye " SEM figure;

Fig. 8 is reference example 4 " bird's eye " SEM figure;

Fig. 9 is the cross-sectional view according to the substrate of another embodiment of the invention; With

Figure 10 is the cross-sectional view according to the substrate of another embodiment of the invention.

Claims (12)

1. 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE, it comprises:

Base substrate;

In order to apply the semiconductor layer of described base substrate;

Mask in order to the part of the upper surface that applies described semiconductor layer; With

In order to the exposed surface of the upper surface that applies described semiconductor layer and the 3-5 group-III nitride semiconductor crystallizing layer of described mask, described exposed surface is not applied by described mask,

The crystallinity of wherein said semiconductor layer is lower than the crystallinity of 3-5 group-III nitride semiconductor crystallizing layer.

2. according to the 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE of claim 1, wherein comprise hole in described semiconductor layer inside.

3. according to the 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE of claim 1, wherein said mask is in the shape of striped or point or described not masked portion and is in a little shape.

4. according to the 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE of claim 1, wherein said mask comprises at least a material that is selected from the following material: SiO ₂, TiO ₂, ZrO ₂, CrO ₂, W, Re, Mo, Cr, Co, Si, Au, Zr, Ta, Ti, Nb, Ni, Pt, V, Hf, Pd, BN, W-nitride, Re-nitride, Mo-nitride, Cr-nitride, Si-nitride, Zr-nitride, Ta-nitride, Ti-nitride, Nb-nitride, V-nitride, Hf-nitride and Fe-nitride.

5. according to the 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE of claim 1, wherein said semiconductor layer is to have general formula I n _xGa _yAl _zThe resilient coating of the material of N, wherein 0≤x≤1,0≤y≤1,0≤z≤1 and x+y+z=1, described resilient coating is to grow under 400 ℃ to 700 ℃ temperature.

6. method for preparing 3-5 group-III nitride semiconductor self-support substrate, described method comprises the following steps:

On base substrate, form semiconductor layer;

On the part of the upper surface of described semiconductor layer, form mask;

Form exposed surface and the described mask of 3-5 group-III nitride semiconductor crystallizing layer with the upper surface that applies described semiconductor layer with 3-5 group-III nitride semiconductor crystallizing layer by selective growth, described exposed surface is not applied by described mask; With

Described 3-5 group-III nitride semiconductor crystallizing layer and described base substrate are separated from each other,

The crystallinity of wherein said semiconductor layer is lower than the crystallinity of 3-5 group-III nitride semiconductor crystallizing layer.

7. according to the method for the preparation 3-5 group-III nitride semiconductor self-support substrate of claim 6, wherein said separating step comprises by stress application step of the described base substrate of leafing mechanically from the 3-5 group-III nitride semiconductor crystallizing layer.

8. according to the method for the preparation 3-5 group-III nitride semiconductor self-support substrate of claim 6, wherein after described separating step, also comprise step with at least one chemical etching in described mask and the described semiconductor layer.

9. according to the method for the preparation 3-5 group-III nitride semiconductor self-support substrate of claim 6, wherein said separating step comprises by reducing the step of atmosphere temperature described base substrate of leafing from the 3-5 group-III nitride semiconductor crystallizing layer.

10. 3-5 group-III nitride semiconductor self-support substrate according to each preparation in the claim 6 to 9, described 3-5 group-III nitride semiconductor self-support substrate comprises:

Semiconductor layer;

Be formed on the mask of a part of the upper surface of described semiconductor layer; With

In order to the exposed surface of the upper surface that applies described semiconductor layer and the 3-5 group-III nitride semiconductor crystallizing layer of described mask, described exposed surface is not applied by described mask,

The crystallinity of wherein said semiconductor layer is lower than the crystallinity of 3-5 group-III nitride semiconductor crystallizing layer.

11. a semiconductor device, it comprises according to each 3-5 group-III nitride semiconductor MULTILAYER SUBSTRATE in the claim 1 to 5.

12. a semiconductor device, it comprises the 3-5 group-III nitride semiconductor self-support substrate according to claim 10.

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