CN100546387C - One kind of high-definition signal decoder - Google Patents

One kind of high-definition signal decoder Download PDF

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CN100546387C
CN100546387C CN 200710074037 CN200710074037A CN100546387C CN 100546387 C CN100546387 C CN 100546387C CN 200710074037 CN200710074037 CN 200710074037 CN 200710074037 A CN200710074037 A CN 200710074037A CN 100546387 C CN100546387 C CN 100546387C
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CN 200710074037
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CN101060627A (en )
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庞恩林
李小明
丹 苏
宇 雷
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深圳安凯微电子技术有限公司
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Abstract

本发明适用于高清视频解码领域,提供了一种高清信号解码器,包括DMA接口,所述解码器通过所述DMA接口从系统内存中读取数据用于解码,所述解码器还包括:与DMA接口直接连接,从所述系统内存中更新并保存参考帧中高概率补偿区间数据的缓存区;所述高概率补偿区间为解码器中4x4子块在参考帧中所对应的横向带状像素区间。 The present invention is applicable to the field of high-definition video decoding, there is provided a high-definition signal decoder, comprising a DMA interface, the interface to the decoder for decoding data read from system memory through the DMA, the decoder further comprising: DMA interface connects directly, updating from the system memory buffer and stored in the reference frame is a high probability that the compensation interval data; high probability of the compensation interval 4x4 sub-block decoder section transverse banded pixel in the reference frame corresponding to . 本发明实施例通过在解码器中设置一与DMA接口直接连接的缓存区,保存解码器中当前4x4子块的高概率补偿区间的数据,并不断从系统内存更新,使得4x4子块进行运动补偿时,大部分数据来自于该缓存区,解码器的存储带宽得到了极大的缓解。 Embodiments of the present invention, the data set a cache with DMA interface directly connected in the decoder, stored in the decoder the current 4x4 sub-block is a high probability compensation section through, and continue from the system memory to be updated, so that 4x4 sub-block motion compensation when most of the data from the buffer, the decoder memory bandwidth has been greatly alleviated.

Description

一种高清信号解码器 One kind of high-definition signal decoder

技术领域 FIELD

本发明属于高清视频解码领域,尤其涉及一种高清信号解码器。 The present invention belongs to the field of high-definition video decoding, more particularly to a high-definition signal decoder. 背景技术 Background technique

参考图1,高清视频解码的三个核心算法是: Referring to FIG 1, the three core HD video decoding algorithm is:

1. 使用B帧 1. B-frames

普通清晰度解码算法仅使用一个参考帧进行运动补偿,而高清视频解码算法使用两个参考帧进行运动补偿。 Standard definition decoding algorithm using only one reference frame for motion compensation for high definition video decoding algorithm uses two reference frames for motion compensation. 这样对于每一个子块都有两个参考帧对其进行运动补偿,补偿效率明显提高,减少了残留系数的信息量,从而减少了码流量。 Thus for each sub-block has two reference frames subjected to motion compensation, compensation efficiency is significantly improved, reducing the amount of information remaining coefficients, thereby reducing the traffic code.

2. 使用4x4子块 2. Use the 4x4 subblock

经典视频解码算法使用16x16或8x8子块进行运动预测,而高清视频解码算法使用4x4子块进行运动预测,如图2所示。 Classical video decoding algorithm using 16x16 or 8x8 sub-block motion estimation, the high-definition video decoding algorithm using 4x4 sub-block motion estimation, as shown in FIG. 这样每一个子块都可以进行更精确的运动补偿,预测效率明显提高,也减少了残留系数的信息量,从而減少了码流量。 Thus each sub-block may be a more precise motion compensation prediction efficiency is significantly improved, but also reduces the amount of information remaining coefficients, thereby reducing the traffic code.

3. 使用滤波插值 3. Use the filter interpolation

经典视频解码算法使用1/2nd精度非滤波插值,而高清视频解码算法使用1/4th精度滤波插值。 Classical video decoding algorithm using 1 / 2nd Non-precision filter interpolation, and high-definition video decoding algorithm using 1 / 4th precision filter interpolation. 这样提高了运动补偿的精度到1/4th像素,减少了残留系数的信息量,从而减少了码流量。 This improves the accuracy of motion compensation to 1 / 4th pixel, reducing the amount of information remaining coefficients, thereby reducing the traffic code.

虽然运用上述三个核心算法可以得到高质量的图像画面和出色的数据压缩比,但由于解码器是通过DMA接口( Direct Memory Access)读取存储在系统内存(通常为SDRAM)中的数据,所以上述三个核心算法的引入也极大地提高了存储带宽的要求。 Although the use of the above-described three core algorithm can obtain a high quality image and excellent picture data compression ratio, but because the decoder is a read memory through the DMA Interface (Direct Memory Access) system memory (typically SDRAM) the data, introducing the above three core algorithm is also greatly improved memory bandwidth requirements. 例如,对于视频格式为1920x1080的4: 2: 0的图像信号,在全部4xA子块运动预测,1/4th精度滤波插值的极端情况下,需要的存储带宽为:[4x4子块数]x [4x4滤波所需像素数]x每秒帧数x参考帧数呵亮度4x4 子块数+色度4x4子块数]x [4x4滤波所需像素数]x每秒帧数x参考帧数=[1920/4 x 1080/4 + 960/4 x 540/4 + 960/4 x 540/4] x [9 x 9] x 30 x 2 =[1920/4 x 1080/4 x 1.5] x [9 x 9] x 30 x 2 =944784000bits/s=901MB/s。 For example, the video format of 1920x1080 4: image signal 0, all 4xA sub-block motion prediction, the 1 / 4th extreme case precision filter interpolation, the memory bandwidth required for:: 2 [4x4 sub-block number] x [ 4x4 filter required number of pixels] x x frames per second of the reference frames Oh luminance chroma 4x4 + 4x4 subblock number of subblocks] x [4x4 filter required number of pixels] x x frames per second of the reference frames = [ 1920/4 x 1080/4 + 960/4 x 540/4 + 960/4 x 540/4] x [9 x 9] x 30 x 2 = [1920/4 x 1080/4 x 1.5] x [9 x 9] x 30 x 2 = 944784000bits / s = 901MB / s.

因为每八位总线在双倍数据速率同步动态随机存取存储器(Double Data Rate-Synchronous Dynamic Random Access Memory, DDR-SDRAM)电3各氺反的带宽为2 x 100MB/s = 200 MB/s,所以当总线利用率为90%时,至少需要的总线数量为:901MB/s/200MB/s/0.9*8«41位,因此现有解码方案一般使用64 位总线,这在成本和功耗上都是一笔较大的开支。 Because each eight synchronous dynamic random access memory bus in a double data rate (Double Data Rate-Synchronous Dynamic Random Access Memory, DDR-SDRAM) each electrically 3 Shui anti bandwidth 2 x 100MB / s = 200 MB / s, when the bus utilization of 90%, the number of buses needed is at least: 901MB / s / 200MB / s / 0.9 * 8 «41 bits, the conventional decoding schemes typically use a 64-bit bus, which in the cost and power consumption It is a large sum of money.

发明内容 SUMMARY

本发明实施例的目的在于提供一种高清信号解码器,旨在解决现有技术中存在的高清视频解码过程中存储带宽太宽,需要的总线较多造成硬件带宽设计难度大以及成本、功耗大的问题。 Object of embodiments of the present invention to provide a high-definition signal decoder, to solve the high-definition video decoding in the prior art process memory bandwidth is too wide, the bus bandwidth is required to cause hardware design more difficult, and the cost, power consumption big problem.

本发明实施例是这样实现的, 一种高清信号解码器,包括DMA接口,所述解码器通过所述DMA接口从系统内存中读取数据用于解码,所述解码器还包括: Embodiment of the present invention is implemented as a high-definition signal decoder, comprising a DMA interface, the interface to the decoder for decoding data read from system memory through the DMA, the decoder further comprises:

与DMA接口直接连接,从所述系统内存中更新并保存参考帧中高概率补偿区间数据的缓存区;所述高概率补偿区间为解码器中4x4子块在参考帧中所对应的横向带状像素区间。 Directly connected to the DMA interface, updating the system memory from the cache and stored in the reference frame data with a high probability of the compensation interval; high probability of the compensation interval decoder 4x4 sub-block in the reference frame pixel corresponding transverse banded range.

本发明实施例通过在解码器中设置一与DMA接口直接连接的緩存区,保存解码器中当前4x4子块的高概率补偿区间的数据,并不断从系统内存更新, 使得4x4子块进行运动补偿时,大部分数据来自于该緩存区,解码器的存储带宽得到了极大的緩解。 Embodiments of the present invention, the data set a cache with DMA interface directly connected in the decoder, stored in the decoder the current 4x4 sub-block is a high probability compensation section through, and continue from the system memory to be updated, so that 4x4 sub-block motion compensation when most of the data from the buffer, the decoder memory bandwidth has been greatly alleviated. 附图说明图l是现有技术中的解码器的结构图; BRIEF DESCRIPTION OF DRAWINGS Figure l is a block diagram of the decoder of the prior art;

图2是现有技术中亮度4x4子块的B帧预测示意图; 图3是本发明实施例提供的高概率补偿区间示意图; 图4是本发明实施例提供的解码器的结构图; 图5是本发明实施例提供的解码器解码的原理示意图。 FIG 2 is a schematic of a prior art predictive B-frame luminance 4x4 sub-blocks; FIG. 3 is a schematic view of the high probability that the compensation section provided in the embodiment of the present invention; FIG. 4 is a block diagram of a decoder embodiment of the present invention is provided; FIG. 5 is the decoder decodes a schematic view of the principle according to an embodiment of the present invention.

具体实施方式 detailed description

为了使本发明的目的、技术方案及优点更加清楚明白,以下结合附图及实施例,对本发明进4亍进一步详细说明。 To make the objectives, technical solutions and advantages of the present invention will become more apparent hereinafter in conjunction with the accompanying drawings and embodiments of the present invention into the right foot 4 is further described in detail. 应当理解,此处所描述的具体实施例仅仅用以解释本发明,并不用于限定本发明。 It should be understood that the specific embodiments described herein are only intended to illustrate the present invention and are not intended to limit the present invention.

本发明实施例通过在解码器中设置一与DMA接口直接连接的緩存区,用于保存解码器当前4x4子块的参考帧中高概率补偿区间的数据,并不断从系统内存更新,使得4x4子块进行运动补偿时,大部分数据来自于该缓存区,解码器的存储带宽得到了极大的緩解。 Embodiments of the present invention is provided in the decoder in a buffer with DMA interface directly connected, for data having a high probability correction section reference frame is stored decoder the current 4x4 sub-block, and continue from the system memory to be updated, so that 4x4 sub-block when motion compensation, most of the data from the buffer, the decoder memory bandwidth has been greatly alleviated.

仍以^L频格式为1920x1080的4: 2: 0的信号为例, 一般情况下4x4子块的运动幅度不会太大,所以90%的子块可以使用就近两幅参考帧的+/-8横条内的像素进行运动补偿,但少数情况,例如画面中一些高速运动的物体往往会超出如图3所示的高概率补偿区间的范围,所以10。 ^ L still video format of 1920x1080 4: 2: 0 signal, for example, the amplitude of motion generally 4x4 sub-block is not too large, so that 90% of the sub-blocks can use the nearest two reference frames + 8 stripe pixels within the motion compensation, but a few cases, such as some of the screen fast-moving objects is often beyond the scope of the high probability correction section shown in FIG. 3, it is 10. /。 /. 的数据就需要通过DMA从系统内存中读取。 It is necessary to read data from system memory via DMA.

参考图4,本发明实施例在解码器芯片内植入容量为L2的内存作为緩存区保存当前4x4子块的参考帧中高概率补偿区间的数据,即高度为[16+8+8]的横条内的像素,并不断/人系统内存更新。 Referring to Figure 4, a cross embodiments implanted within the decoder chip capacity as L2 memory as the buffer area to save the data in a reference frame a high probability that the compensation section of the current 4x4 sub-block, i.e., a height of [16 + 8 + 8] The embodiment of the present invention in article pixels, and continue / person memory system update. 该緩存区与DMA接口直接连接,当解码器对当前4x4子块进行运动补偿时,90%的数据可以通过读取该緩存区获得, 10%需要从系统内存中读取,使得解码器的存储带宽得到了极大的缓解。 The cache is directly connected to the DMA interface, when the decoder for the current 4x4 sub-block motion compensation, 90% can be obtained by reading the data buffer 10% to read from system memory, so that the decoder memory the bandwidth has been greatly eased.

緩存区容量L2的计算方法如下: Calculation of capacity L2 cache as follows:

L2-亮度行宽x [亮度高概率补偿区间高度]+色度行宽x [色度高概率补偿区间高度]x2-亮度行宽x[亮度滤波高度要求+高概率补偿区间上、下偏移] +色度行宽x [色度滤波高度要求+高概率补偿区间上、下偏移]x 2=1920 x [16+8+8]+ 960x [8+8+8] x2 = 105KB。 L2- luminance line width x [height interval compensated luminance high probability] + line width of the chromaticity x [probability of high color compensation section height] X2- luminance line width x [height requirements + filtered luminance compensation range with high probability, the offset ] + line width of chromaticity x [height requirements + chroma filtering high probability correction interval, the offset] x 2 = 1920 x [16 + 8 + 8] + 960x [8 + 8 + 8] x2 = 105KB. 其中,高概率补偿区间上、下偏移量为统计意义量,通常为8。 Among them, the high probability compensation range, lower offset statistically significant amount, typically 8.

通过本发明实施例提供的緩存区,参考图5,可以看出解码器的存储带宽可减少为: Buffer provided by the embodiment of the present invention, with reference to FIG. 5, it can be seen that the decoder memory bandwidth can be reduced to:

[4x4子块数]x [4x4滤波所需像素数]x每秒帧数x参考帧数xl0% + [4x4子块数]x [4x4搬移到緩存区的像素数]x每秒帧数x参考帧数x 90%= [The number of pixels moved to the buffer area 4x4] [4x4 number of subblocks] x [number of pixels required 4x4 filter] x x frames per second of the reference frames xl0% + [4x4 subblock] x x x frames per second reference frames x 90% =

[1920/4 x 1080/4 x 1.5] x [9 x 9] x 30 x 2 * 10% + [1920/4 x 1080/4 x 1.5] x [9 x 9] x 30 x 2 * 10% +

[1920/4 x 1080/4 x 1.5] x [4 x 4] x 30 x 2 * 90% = 250廳/s [1920/4 x 1080/4 x 1.5] x [4 x 4] x 30 x 2 * 90% = 250 Room / s

需要的总线至少为:250MB/s/200MB/s/0.9+8"12位,所以32位的总线 Bus requires at least: 250MB / s / 200MB / s / 0.9 + 8 "12 bits, 32-bit bus

就可以实现整个解码系统了,从而使存储带宽得到了极大的緩解。 Decoding can be achieved throughout the system, so that the memory bandwidth has been greatly eased.

综上,本发明实施例通过在解码器中设置一与DMA接口直接连接的緩存 In summary, the embodiment by providing a DMA interface in the decoder cache is directly connected embodiment of the present invention

区,保存解码器中当前4x4子块的高概率补偿区间的数据,并不断从系统内存 Area, the data currently stored in the decoder to compensate high probability interval 4x4 sub-blocks, and continue from the system memory

更新,使得4x4子块进行运动补偿时,大部分数据来自于该缓存区,解码器的 Updated so that when 4x4 sub-block motion compensation, most of the data from the buffer, the decoder

存储带宽得到了极大的緩解。 Memory bandwidth has been greatly eased.

以上所述仅为本发明的较佳实施例而已,并不用以限制本发明,凡在本发 The foregoing is only preferred embodiments of the present invention but are not intended to limit the present invention, where in the present

明的精神和原则之内所作的任何修改、等同替换和改进等,均应包含在本发明 Any modifications within the spirit and principle of the next, equivalent replacements, improvements, etc., are all included in the present invention,

的保护范围之内。 Within the scope of protection.

Claims (3)

  1. 1、一种高清信号解码器,包括DMA接口,所述解码器通过所述DMA接口从系统内存中读取数据用于解码,其特征在于,所述解码器还包括: 与DMA接口直接连接,从所述系统内存中更新并保存参考帧中高概率补偿区间数据的缓存区;所述高概率补偿区间为解码器中4×4子块在参考帧中所对应的横向带状像素区间。 An HD signal decoder, DMA interface includes a decoder for decoding read data from system memory via the DMA interface, wherein said decoder further comprises: a direct connection to the DMA interface, updated and saved in the reference frame buffer section high probability correction data from the system memory; the high probability interval compensation decoder 4 × 4 pixel sub-block lateral strip section in the reference frame corresponding to.
  2. 2、 如权利要求1所述的高清信号解码器,其特征在于,所述横向带状像素区间的高度为亮度滤波高度要求与高概率补偿区间上、下偏移量之和。 2, as claimed in claim 1 HD decoder, characterized in that the height of the transverse strip section pixel luminance filter height requirement and a high probability correction interval, the shift amounts.
  3. 3、 如权利要求2所述的高清信号解码器,其特征在于,所述緩存区的容量按下式计算得出:L2二亮度行宽x [亮度高概率补偿区间高度]+色度行宽x [色度高概率补偿区间高度]乂2=亮度行宽x [亮度滤波高度要求+高概率补偿区间上、下偏移量]+色度行宽x [色度滤波高度要求+高概率补偿区间上、下偏移量]xl其中,高;f既率补偿区间上、下偏移量为统计意义量。 Two luminance chrominance line width L2 of the line width of x [height interval compensated luminance high probability] +: 3, as claimed in claim 2 HD decoder, characterized in that the capacity of the buffer area derived from the following formula x [probability of high color compensation section height] qe luminance line width = 2 x [height requirements + luminance filtering high probability correction interval, the offset] + line width of the chromaticity x [height requirements + chroma filtering high probability correction the interval, the offset] XL wherein high; f on both rate compensation interval, the offset is statistically significant amount.
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