CN100546387C - A kind of high definition signal decoder - Google Patents
A kind of high definition signal decoder Download PDFInfo
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- CN100546387C CN100546387C CN 200710074037 CN200710074037A CN100546387C CN 100546387 C CN100546387 C CN 100546387C CN 200710074037 CN200710074037 CN 200710074037 CN 200710074037 A CN200710074037 A CN 200710074037A CN 100546387 C CN100546387 C CN 100546387C
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Abstract
The present invention is applicable to the high definition video decoding field, a kind of high definition signal decoder is provided, comprise DMA interface, described decoder is used for decoding by described DMA interface reading of data from Installed System Memory, described decoder also comprises: directly be connected with DMA interface, upgrade and preserve the buffer area of high probability compensation interval censored data in the reference frame from described Installed System Memory; It between described high probability compensating basin 4x4 piece pairing horizontal banded pixel range in reference frame in the decoder.The embodiment of the invention by in decoder, be provided with one with the direct-connected buffer area of DMA interface, data in the preservation decoder between the high probability compensating basin of current 4x4 piece, and constantly upgrade from Installed System Memory, make when 4x4 piece carries out motion compensation, most of data come from this buffer area, and the memory bandwidth of decoder has obtained great alleviation.
Description
Technical field
The invention belongs to the high definition video decoding field, relate in particular to a kind of high definition signal decoder.
Background technology
With reference to figure 1, three core algorithms of high definition video decoding are:
1. use the B frame
The ordinary sharpness decoding algorithm only uses a reference frame to carry out motion compensation, and the high definition video decoding algorithm uses two reference frames to carry out motion compensation.All have two reference frames that it is carried out motion compensation for each height piece like this, compensation efficient obviously improves, and has reduced the amount of information of residual coefficients, thereby has reduced code flow.
2. use 4x4 piece
Classical video decode algorithm uses 16x16 or 8x8 piece to carry out motion prediction, and the high definition video decoding algorithm uses 4x4 piece to carry out motion prediction, as shown in Figure 2.Each height piece can carry out more accurate motion compensation like this, and forecasting efficiency obviously improves, and has also reduced the amount of information of residual coefficients, thereby has reduced code flow.
3. use the filtering interpolation
Classical video decode algorithm uses the non-filtering interpolation of 1/2nd precision, and the high definition video decoding algorithm uses 1/4th precision filtered interpolation.The precision that has improved motion compensation has like this reduced the amount of information of residual coefficients, thereby has reduced code flow to the 1/4th pixel.
Though use above-mentioned three core algorithms can obtain high-quality image frame and outstanding data compression ratio, but because decoder is to read the data that are stored in the Installed System Memory (being generally SDRAM) by DMA interface (Direct Memory Access), so the introducing of above-mentioned three core algorithms has also greatly improved the requirement of memory bandwidth.For example, for video format is the picture signal of the 4:2:0 of 1920x1080, at whole 4x4 piece motion predictions, under the extreme case of 1/4th precision filtered interpolation, the memory bandwidth that needs is: [4x4 piece number] required pixel count of x[4x4 filtering] x number of pictures per second x reference frame number=[brightness 4x4 piece number+colourity 4x4 piece number] required pixel count of x[4x4 filtering] x number of pictures per second x reference frame number=[1920/4x1080/4+960/4x540/4+960/4x540/4] x[9x9] x30x2=[1920/4x1080/4x1.5] x[9x9] x30x2=944784000bits/s=901MB/s.
Because per eight buses are at double data speed synchronous dynamic RAM (Double DataRate-Synchronous Dynamic Random Access Memory, DDR-SDRAM) bandwidth of circuit board is 2x100MB/s=200MB/s, so when total line use ratio is 90%, at least the bus number that needs is: 41 of 901MB/s/200MB/s/0.9*8 ≈, 64 buses of the general use of therefore existing decoding scheme, this all is a bigger spending on cost and power consumption.
Summary of the invention
The purpose of the embodiment of the invention is to provide a kind of high definition signal decoder, it is too wide to be intended to solve in the high definition video decoding process that exists in the prior art memory bandwidth, and the bus that needs is more to cause the big and cost of hardware bandwidth design difficulty, problem that power consumption is big.
The embodiment of the invention is achieved in that a kind of high definition signal decoder, comprises DMA interface, and described decoder is used for decoding by described DMA interface reading of data from Installed System Memory, and described decoder also comprises:
Directly be connected with DMA interface, from described Installed System Memory, upgrade and preserve the buffer area of high probability compensation interval censored data in the reference frame; It between described high probability compensating basin 4x4 piece pairing horizontal banded pixel range in reference frame in the decoder.
The embodiment of the invention by in decoder, be provided with one with the direct-connected buffer area of DMA interface, data in the preservation decoder between the high probability compensating basin of current 4x4 piece, and constantly upgrade from Installed System Memory, make when 4x4 piece carries out motion compensation, most of data come from this buffer area, and the memory bandwidth of decoder has obtained great alleviation.
Description of drawings
Fig. 1 is the structure chart of decoder of the prior art;
Fig. 2 is the B frame prediction schematic diagram of brightness 4x4 piece in the prior art;
Fig. 3 is a schematic diagram between the high probability compensating basin that provides of the embodiment of the invention;
Fig. 4 is the structure chart of the decoder that provides of the embodiment of the invention;
Fig. 5 is the principle schematic of the decoder decode that provides of the embodiment of the invention.
Embodiment
In order to make purpose of the present invention, technical scheme and advantage clearer,, the present invention is further elaborated below in conjunction with drawings and Examples.Should be appreciated that specific embodiment described herein only in order to explanation the present invention, and be not used in qualification the present invention.
The embodiment of the invention by in decoder, be provided with one with the direct-connected buffer area of DMA interface, be used for preserving the data between the reference frame high probability compensating basin of the current 4x4 piece of decoder, and constantly upgrade from Installed System Memory, make when 4x4 piece carries out motion compensation, most of data come from this buffer area, and the memory bandwidth of decoder has obtained great alleviation.
The signal that still with the video format is the 4:2:0 of 1920x1080 is an example, the motion amplitude of 4x4 piece is not too large generally speaking, so 90% sub-piece can use the pixel in two width of cloth reference frames nearby+/-8 horizontal stripes to carry out motion compensation, but a few cases, for example some swiftly passing objects tend to exceed scope between as shown in Figure 3 high probability compensating basin in the picture, so 10% data just need read from Installed System Memory by DMA.
With reference to figure 4, it is that the internal memory of L2 is preserved the data between the high probability compensating basin in the reference frame of current 4x4 piece as buffer area that the embodiment of the invention is implanted into capacity at decoder chip, promptly highly be the interior pixel of horizontal stripe of [16+8+8], and constantly upgrade from Installed System Memory.This buffer area directly is connected with DMA interface, when decoder carries out motion compensation to current 4x4 piece, 90% data can obtain by reading this buffer area, and 10% need read from Installed System Memory, makes the memory bandwidth of decoder obtain great alleviation.
The computational methods of buffer area capacity L2 are as follows:
Height between L2=brightness line width x[brightness high probability compensating basin]+colourity line width x[colourity high probability compensating basin between height] upper and lower skew between x2=brightness line width x[luminance filtering requirement for height+high probability compensating basin]+colourity line width x[colourity filtering requirement for height+high probability compensating basin between upper and lower skew] x2=1920x[16+8+8]+960x[8+8+8] x2=105KB.Wherein, upper and lower side-play amount is the statistical significance amount between the high probability compensating basin, is generally 8.
By the buffer area that the embodiment of the invention provides, with reference to figure 5, the memory bandwidth of decoder can be reduced to as can be seen:
[4x4 piece number] required pixel count of x[4x4 filtering] x number of pictures per second x reference frame number x10%+
[4x4 piece number] x[4x4 moves the pixel count of buffer area] x number of pictures per second x reference frame number x90%=
[1920/4x1080/4x1.5]x[9x9]x30x2*10％+
[1920/4x1080/4x1.5]x[4x4]x30x2*90％＝250MB/s
The bus that needs is at least: 12 of 250MB/s/200MB/s/0.9*8 ≈ so 32 bus just can realize whole decode system, thereby make memory bandwidth obtain great alleviation.
To sum up, the embodiment of the invention by in decoder, be provided with one with the direct-connected buffer area of DMA interface, data in the preservation decoder between the high probability compensating basin of current 4x4 piece, and constantly upgrade from Installed System Memory, make when 4x4 piece carries out motion compensation, most of data come from this buffer area, and the memory bandwidth of decoder has obtained great alleviation.
The above only is preferred embodiment of the present invention, not in order to restriction the present invention, all any modifications of being done within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (3)
1, a kind of high definition signal decoder comprises DMA interface, and described decoder is used for decoding by described DMA interface reading of data from Installed System Memory, it is characterized in that described decoder also comprises:
Directly be connected with DMA interface, from described Installed System Memory, upgrade and preserve the buffer area of high probability compensation interval censored data in the reference frame; It between described high probability compensating basin 4 * 4 sub-pieces pairing horizontal banded pixel range in reference frame in the decoder.
2, high definition signal decoder as claimed in claim 1 is characterized in that, the height of described horizontal banded pixel range is a upper and lower side-play amount sum between luminance filtering requirement for height and high probability compensating basin.
3, high definition signal decoder as claimed in claim 2 is characterized in that, the capacity of described buffer area is calculated as follows and draws:
L2=brightness line width * [height between brightness high probability compensating basin]+colourity line width * [height between colourity high probability compensating basin] * 2=brightness line width * [upper and lower side-play amount between luminance filtering requirement for height+high probability compensating basin]+colourity line width * [upper and lower side-play amount between colourity filtering requirement for height+high probability compensating basin] * 2; Wherein, upper and lower side-play amount is the statistical significance amount between the high probability compensating basin.
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| CN 200710074037 CN100546387C (en) | 2007-04-13 | 2007-04-13 | A kind of high definition signal decoder |
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| CN101645052B (en) * | 2008-08-06 | 2011-10-26 | 中兴通讯股份有限公司 | Quick direct memory access (DMA) ping-pong caching method |
| CN102111615B (en) * | 2009-12-29 | 2012-11-28 | 中兴通讯股份有限公司 | Method and system for implementing video filtering in DMA removal |
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Non-Patent Citations (2)
| Title |
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| HDTV 集成解码芯片的一种总线设计. 李东晓，姚庆栋，刘鹏，周莉.电路与系统学报，第8卷第3期. 2003 |
| HDTV 集成解码芯片的一种总线设计. 李东晓，姚庆栋，刘鹏，周莉.电路与系统学报，第8卷第3期. 2003 * |
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