CN100541966C - Mains by harmonics and flash comprehensive inhibitor - Google Patents

Abstract

The invention discloses a kind of mains by harmonics and flash comprehensive inhibitor, comprise main circuit and control circuit, control circuit passes through voltage sensor respectively, current sensor obtains the voltage signal of electrical network, current signal, control circuit passes through voltage sensor respectively, current sensor obtains the d. c. voltage signal of main circuit, output current signal, input current signal, the controlling and driving signal port of control circuit is connected in the controlling and driving end of main circuit, above-mentioned control circuit also is used for electrical network three-phase current ia that sampling is obtained, ib, the ic data obtain equivalent conductance Gp (t) by conversion, Gq (t), obtain the alternating current component Gph of equivalent conductance then, Gqh, utilize equivalent conductance alternating current component harmony to involve the linear relationship of reactive current, the process linear transformation needing can obtain the current component i α h of inhibition or compensation, i β h, i0h.

Description

Mains by harmonics and flash comprehensive inhibitor

Technical field

The present invention relates to a kind of mains by harmonics and flash comprehensive inhibitor, belong to quality of power supply aspect harmonic compensation technical field based on the IGBT device.

Background technology

Since the eighties in 20th century, development along with power electronic technology, non-linear power electronic device and device have obtained extensive use in modern industry, simultaneously, in order to solve the problem that the electric power system self-growth exists, direct current transportation and FACTS technology constantly drop into practical engineering application, and buncher and reactive power compensation capacitor also put into effect in a large number.The operation of these equipment makes that the voltage and current wave distortion is more and more serious in the electrical network, and harmonics level constantly rises.In addition, impact, fluctuation load, for example arc furnace, heavy (merchant) mill, electric locomotives etc. in servicely not only can produce a large amount of high order harmonic components, but also can produce power quality problems such as voltage fluctuation, flickering, three-phase imbalance.But then, along with various complexity, precision, constantly universal to the power consumption equipment of quality of power supply sensitivity, people are more and more higher to the requirement of the quality of power supply, so electric power system must suppress mains by harmonics and flickering.

Past, a large amount of both at home and abroad problems of using passive filtration unit (Passive Filter) to solve the harmonic wave aspect.Traditional Passive LC filter can reduce harmonic wave, improves the power factor of AC load, but exists tangible deficiency and defective; The selected usually characteristic frequency of the passive filter of design can only filtering be specified subharmonic; There is possibility with electrical network generation resonance; Also very responsive to electric network impedance and frequency change.In addition, also exist problems such as volume is big, loss is big.Because passive filtering has above shortcoming, along with the continuous development of power electronic technology, people progressively turn to active power filtering with the filtering research direction.Raising along with development of computer, controlling level, and going deep into to power electronic equipment research, the developing direction that improves quality of power supply device concentrate on control flexibly, on the power electronic equipment of excellent performance, in line with the principle that economizes on resources and invest, one-machine-multi-function becomes the future thrust of power electronic equipment again.

Summary of the invention

The present invention proposes and a kind ofly can suppress flickering, eliminate resonance and cause danger and can guarantee fast detecting, improve the mains by harmonics and the flash comprehensive inhibitor of precision that the present invention has the advantage of high controllability and fast-response, the reliability and stability height.

The present invention adopts following technical scheme:

A kind of mains by harmonics and flash comprehensive inhibitor, comprise main circuit and control circuit, control circuit passes through voltage sensor respectively, current sensor obtains the voltage signal of electrical network, current signal, control circuit passes through voltage sensor respectively, current sensor obtains the d. c. voltage signal of main circuit, output current signal, input current signal, the controlling and driving signal port of control circuit is connected in the controlling and driving end of main circuit, above-mentioned control circuit also is used for electrical network three-phase current ia that sampling is obtained, ib, the ic data obtain equivalent conductance Gp (t) by conversion, Gq (t), obtain the alternating current component Gph of equivalent conductance then, Gqh, utilize equivalent conductance alternating current component harmony to involve the linear relationship of reactive current, needing can obtain the current component i α h of inhibition or compensation through linear transformation, i β h, i0h

Described control circuit comprises sample circuit, logical signal is handled and the switching value imput output circuit, Programmable Logic Device and governor circuit, sample circuit is used to obtain the voltage of electrical network and load, electric current is sampled, the digital signal output end of sample circuit is connected with the data/address bus of the master control chip of governor circuit, the control signal output ends of governor circuit and switching value signal output part handle with logical signal and the signal input end and the switching value signal input part of switching value imput output circuit are connected, logical signal is handled and the control signal output ends of switching value imput output circuit is connected with the signal input end of sample circuit, logical signal is handled and the switching value imput output circuit is used for obtaining logical process signal and synthetic control signal corresponding and switching value output signal from governor circuit, control signal exports sample circuit to, the switching value output signal is connected to the switching value lead-out terminal and is used to control mains by harmonics and flash comprehensive inhibitor, the address bus of governor circuit, data/address bus, reseting signal line, the interrupt signal line, the enable signal line, the chip selection signal line, reading signal lines and write signal line respectively with the address bus of the fpga chip EP1C6Q240C8 of Programmable Logic Device, data/address bus, reseting signal line, the interrupt signal line, the enable signal line, the chip selection signal line, reading signal lines and write signal line connect.

Main circuit is under the control of the control signal of control circuit, by rectification circuit the alternating current of electrical network is carried out rectification and provide direct voltage for electric capacity, under the control of control signal, dc inverter is become simultaneously the alternating current of different frequency by inverter circuit, the mains by harmonics that produces when working owing to nonlinear load with counteracting, and reactive power that can compensating load, thereby regulate power factor and suppress voltage flicker.Voltage on voltage sensor and current sensor senses circuit and the electric capacity, detect the electric current on rectification and four brachium pontis of inverter circuit, the distribution network, and testing result is transferred to control circuit.Control circuit obtains judging, calculating from the control signal of transducer, adopt suitable Detection ﹠ Controling algorithm that inverter circuit in the main circuit and rectification circuit are carried out accurate, real-time control, thereby mains by harmonics in the distribution network system and flickering are comprehensively suppressed.

Compared with prior art, main circuit of the present invention has following advantage:

● because this device can detect the harmonic wave and the reactive current of distribution network system, so this device can not only compensate each harmonic, thereby can also suppress flickering by compensating reactive power, and the characteristics of one-machine-multi-function are arranged, and is comparatively reasonable on cost performance;

● because this device belongs to the active filter that adopts power electronic device,, can eliminate danger with system impedance generation resonance so the filtering characteristic of this device is not subjected to the influence of system impedance etc.;

● because the novel detection algorithm of this device employing, so this device has adaptation function, but the harmonic wave that automatic tracking and compensating is changing promptly has advantages such as high controllability and fast-response.

● this device has designed a kind of novel detection algorithm at harmonic wave and idle characteristics, can reduce by nearly 1/3 operand, has guaranteed the quick of detection, has also improved precision simultaneously, for harmonic wave and idle real-time comprehensive inhibition are provided the foundation.

● this device adopts redundant symmetric design, and inverter circuit also can be realized rectification function, and rectification circuit also can be realized invert function simultaneously.Carry out rectification and inversion during operate as normal respectively, when breaking down, certain part this partial circuit can be stopped, and adopt its symmetric part to carry out rectification and inversion simultaneously, and comprehensively suppress to realize mains by harmonics and flickering, can improve the reliability and stability of system so greatly.

Description of drawings

Fig. 1 is the connection diagram of main circuit part in novel power grid harmonic wave and the flash comprehensive inhibitor, and wherein 1-1 partly is an inverter circuit, and 1-2 is a dc bus capacitor, and 1-3 partly is a rectification circuit, and 1-4 and 1-5 are fling-cut switch and inductive circuit.

Fig. 2 is that the system of control circuit in novel power grid harmonic wave and the flash comprehensive inhibitor forms signal, wherein 2-1 voltage/current sensor and A/D sampling section, and 211 is Hall voltage, current sensor among the figure, 212,213,214,215 is four A/D chip AD7865; 2-2 partly is the inputs of CPLD (ComplexProgrammable Logic Device, CPLD) and switching value, output, and 221 is CPLD chip XC95144 among the figure; 2-3 partly is the man-machine interface part of control circuit, and 231 is dual port RAM pin-saving chip IDT70V08 among the figure, and 232 is LCDs, and 233 are liquid crystal display control chip SED1335, and 234 is 51 singlechip chip W77E58, and 235 is keyboard; 2-4 partly is the data communication part of control circuit among the figure, and 241 is Ethernet transceiving chip LXT971 among the figure, and 242 is serial communication RS485 chip, and 243 is serial communication RS232 chip; 2-5 is the external memory storage expansion partly, and 251,252 is two synchronous dynamic random storage chip IS42SI16400A among the figure, and 253,254 is two FLASH storage chip SST39VF160; 2-6 partly is FPGA (Field-Programmable Gate Array, the field programmable gate array) part of control circuit, and 261 is fpga chip among the figure, adopts the EP1C6Q240C8 chip; 2-7 partly is the master control chip circuit part of control circuit, and 271 is main control chip among the figure, adopts the AT91RM9200 chip of ARM9 series.

The structure chart of Fig. 3 novel power grid harmonic wave and flash comprehensive inhibitor.Wherein 1 is the main circuit part of system, and 1-1 partly is an inverter circuit, and 1-2 is a dc bus capacitor, and 1-3 partly is a rectification circuit, and 1-4 and 1-5 are fling-cut switch and inductance.2 is the control circuit of system.3 is AC power supply system, and 4 is nonlinear load, and PT1, PT2 are voltage sensor, and CT1, CT2 are current sensor.

Fig. 4 new harmonic electric current and reactive current detection method schematic diagram, A partly is the conversion of calculating equivalent conductance among the figure, and B partly is the wave digital lowpass filter part among the figure, and C partly is the conversion fraction that calculates offset current among the figure.

Fig. 5 is A/D sample circuit figure of the present invention.

Fig. 6 is a CPLD circuit diagram of the present invention.

Fig. 7 is external memory storage expanded circuit figure of the present invention.

Fig. 8 is the connection layout of FPGA device of the present invention and ARM chip.

Fig. 9 is ARM microcontroller circuit figure of the present invention.

Embodiment

A kind of mains by harmonics and flash comprehensive inhibitor, comprise main circuit 1 and control circuit 2, control circuit 2 is respectively by voltage sensor PT1, current sensor CT3 obtains the voltage signal of electrical network, current signal, control circuit 2 is respectively by voltage sensor PT2, current sensor CT1, CT2 obtains the d. c. voltage signal of main circuit 1, input current signal and output current signal, the controlling and driving signal port of control circuit 2 is connected in the controlling and driving end of main circuit 1, above-mentioned control circuit 2 also is used for electrical network three-phase current ia that sampling is obtained, ib, the ic data obtain equivalent conductance Gp (t) by conversion, Gq (t), obtain the alternating current component Gph of equivalent conductance then, Gqh, utilize equivalent conductance alternating current component harmony to involve the linear relationship of reactive current, the process linear transformation needing can obtain the current component i α h of inhibition or compensation, i β h, i0h.

The main circuit 1 of described mains by harmonics and flash comprehensive inhibitor, comprise electric capacity 1-2, first inductance and switching circuit 1-4 and second inductance and switching circuit 1-5, first inductance and switching circuit (1-4) and second inductance and switching circuit (1-5) all comprise the branch road that four tunnel series circuits of being made up of inductance and switch respectively constitute, between first inductance and switching circuit 1-4 and electric capacity 1-2, be provided with inverter circuit 1-1, and, the sa of inverter circuit 1-1, sb, sc, the sn ac input end respectively with the sa of the four tunnel above-mentioned branch roads of first inductance and switching circuit 1-4, sb, sc, the sn ac input end connects, the DC+ of the dc terminal of inverter circuit 1-1 and electric capacity 1-2, the DC-dc terminal connects; Between second inductance and switching circuit 1-5 and electric capacity 1-2, be provided with rectification circuit 1-3, and, the dc terminal of the rectification circuit 1-3 of rectification circuit 1-3 be connected with DC+, the DC-dc terminal of electric capacity 1-2, the la of the 1-3 of rectification circuit, lb, lc, ln exchange end and hold with la, lb, lc, the ln of the four tunnel above-mentioned branch roads of switching circuit 1-5 with second inductance respectively and be connected.

In described mains by harmonics and the flash comprehensive inhibitor inverter circuit 1-1 comprise 4 road and bridge arm, the two ends of brachium pontis interconnect respectively and these two ends are respectively the dc terminal of inverter circuit 1-1, per road and bridge, arm was made up of the electronic power switch of 2 series connection, 4 road and bridge arm mid point be respectively sa, sb, sc, the sn ac input end of inverter circuit 1-1, above-mentioned electronic power switch is formed by igbt and with the diode of igbt parallel connected in reverse phase.

In described mains by harmonics and the flash comprehensive inhibitor rectification circuit 1-3 comprise 4 road and bridge arm, the two ends of brachium pontis interconnect respectively and these two ends are respectively the dc terminal of rectification circuit 1-3, per road and bridge, arm was made up of the electronic power switch of 2 series connection, 4 road and bridge arm mid point la, the lb, lc, the ln that are respectively rectification circuit 1-3 exchange end, above-mentioned electronic power switch is formed by igbt and with the diode of igbt parallel connected in reverse phase.

Control circuit 2 comprises sample circuit 2-1 in described mains by harmonics and the flash comprehensive inhibitor, logical signal is handled and switching value imput output circuit 2-2, Programmable Logic Device 2-6 and governor circuit 2-7, sample circuit 2-1 is used to obtain the voltage of electrical network and load, electric current is sampled, the digital signal output end of sample circuit 2-1 is connected with the data/address bus of the master control chip 271 of governor circuit, the control signal output ends of governor circuit 2-7 and switching value signal output part handle with logical signal and signal input end and the switching value signal input part of switching value imput output circuit 2-2 are connected, logical signal is handled and the control signal output ends of switching value imput output circuit 2-2 is connected with the signal input end of sample circuit 2-1, logical signal is handled and switching value imput output circuit 2-2 is used for obtaining logical process signal and synthetic control signal corresponding and switching value output signal from governor circuit 2-7, control signal exports sample circuit 2-1 to, the switching value output signal is connected to the switching value lead-out terminal and is used to control mains by harmonics and flash comprehensive inhibitor, the address bus of governor circuit 2-7, data/address bus, reseting signal line, the interrupt signal line, the enable signal line, the chip selection signal line, reading signal lines and write signal line are the address bus of EP1C6Q240C8 chip 261 with the fpga chip of Programmable Logic Device circuit 2-6 respectively, data/address bus, reseting signal line, the interrupt signal line, the enable signal line, the chip selection signal line, reading signal lines and write signal line connect.

Described mains by harmonics and flash comprehensive inhibitor, be provided with external memory storage expanded circuit 2-5 on governor circuit 2-7, the address wire of external memory storage expanded circuit 2-5, data signal bus and control signal bus are connected with address bus, data/address bus and the control signal bus of governor circuit 2-7 respectively.

With reference to the accompanying drawings, specific embodiments of the present invention being done one describes in detail:

With reference to Fig. 3, mains by harmonics and flash comprehensive inhibitor are made up of main circuit 1, control circuit 2, voltage sensor PT1, PT2 and current sensor CT1, CT2, CT3.Wherein the inverter circuit 1-1, the electric capacity 1-2 that are made up of igbt T1～T8 of main circuit, rectification circuit 1-3, inductance L and switching circuit 1-4, the 1-5 that igbt T9～T16 forms form.Wherein specialized designs new harmonic electric current and reactive current detection method, this algorithm is by the conversion fraction that calculates equivalent conductance, i.e. Fig. 2-A part, the wave digital lowpass filter part, i.e. Fig. 2-B part is calculated the conversion fraction of offset current, promptly Fig. 2-C partly forms.Realize the current component of compensation is calculated fast and accurately by this algorithm, for the comprehensive inhibition that realizes harmonic wave and flickering provides the basis.

With reference to Fig. 1, Fig. 3, this main circuit 1 is made up of five parts, the SA of AC power wherein, SB, SC, the SN end is connected to inductance L and switching circuit 1-4, process inductance L and switching circuit 1-4 are connected to the ac input end sa of inverter circuit 1-1 then, sb, sc, sn, the dc terminal of inverter circuit is connected to the dc terminal DC+ of electric capacity 1-2, DC-, the dc terminal DC+ of while electric capacity 1-2, DC-also is connected to the dc terminal of rectification circuit 1-3, the interchange end la of the 1-3 of rectification circuit, lb, lc, ln is connected to inductance L and switching circuit 1-5, exchanges end LA by what inductance L and switching circuit 1-5 were connected to load-side then, LB, LC, LN.

With reference to Fig. 2, Fig. 5～9, voltage, the current signal that voltage/current sensor in the control circuit 2 and A/D sample circuit 2-1 obtain measuring by voltage, current sensor 211 delivered to pin 13, pin 15, pin 18, the pin 20 of 4 A/D sample circuits 212,213,214,215 respectively and changed, data/address bus pin 179～pin 198 that the result of conversion receives master control chip 271 by the digital quantity output pin DB0-DB13 pin 27～pin 34 and the pin 38～pin 43 of each A/D sample circuit, the master control chip utilizes these measured values to handle; Data-interface pin 139, pin 140 and pin 142～pin 155 that CPLD in this control circuit and switching value are imported, output circuit 2-2 passes through its CPLD chip 221 and control interface pin 12, pin 22, pin 24, pin 26, pin 28, pin 130, pin 133, pin 138 synthesize control signal corresponding and switching value output signal CPLD chip 221 after the processing signals that master control chip 271 obtains being correlated with.Wherein export the control end of 4 A/D chips to by the IRQ0 pin 11 of CPLD chip about the control signal of A/D chip, wherein switching value output signal pin 48,49,50, pin 52～60, pin 62～65, pin 82～93, pin 95～98, pin 103～109, pin 111～119 are connected to the switching value lead-out terminal and are used to control mains by harmonics and the comprehensive suppression equipment of flickering; Man-machine interface circuit in this control circuit adopts one 51 single-chip microcomputer W77E58 chip 234 by on the data/address bus that is connected to master control chip 271 that adopts dual port RAM chip 231, control LCDs 232 showed that keyboard 235 is delivered to master control chip 271 by W77E58 chip 234 with the data of keying in after liquid crystal display control chip 233 need to obtain data presented and control signal from W77E58 chip 234; Communicating circuit in this control circuit adopts Ethernet transceiving chip LXT971241, serial communication RS485 chip 242, serial communication RS232 chip 243 are connected with the data communication interface of master control chip 271 respectively to realize Ethernet, RS485 and three kinds of communication modes of RS232; Two synchronous dynamic random storage chip IS42SI16400A251 of the external memory storage expanded circuit in this control circuit, the address pin 20～pin 26 of 252 and two FLASH storage chips 253,254, pin 30～35, data-signal and control signal are connected with address, data/address bus and the control signal of master control chip 71 respectively; The address bus AB[0..23 of the fpga chip 261 of the FPGA circuit in this control circuit], data/address bus (DB[0..15], reset signal (nRST) and interrupt signal line (INT), enable signal (nOE), chip selection signal (nCS), read signal (nRD), write signal (nWE) respectively with the address bus AB[0..23 of master control chip 721]), data/address bus (DB[0..15], reset signal (nRST) and interrupt signal line (INT), enable signal (nOE), chip selection signal (nCS), read signal (nRD), write signal (nWE) are connected.

When device is started working, judge the working condition of rectifying part and inversion partial circuit earlier, if the equal operate as normal of two parts, then closed fling-cut switch SW2, SW1, rectification circuit is connected in control circuit control mutually by inductance L 5～L8 and alternating current circuit to carry out the direct voltage that controlled rectification obtains down electric capacity is charged, support for inversion provides direct current, electric capacity also plays the ripple component of filtering direct voltage simultaneously.The voltage that control circuit obtains by transducer and sample circuit, current values calculate the current component that needs compensation by custom-designed detection algorithm, control circuit adopts suitable control strategy, inverter circuit carries out the alternating voltage that inversion obtains different frequency with direct voltage on the electric capacity, 1～L4 is coupled to circuit by inductance L, thereby the reactive current of load is provided and offsets harmonic wave.In this course of work, the diode D1～D16 in inversion and the rectification circuit plays the effect of protection igbt T1～T16.When system works, at set intervals inverter circuit and rectification circuit are detected, when finding that wherein certain part breaks down, then close this partial circuit, open the fling-cut switch of this part simultaneously.This moment, corresponding another one part was then utilized the corresponding actions that igbt in this part main circuit and diode carry out rectification and inversion simultaneously, thereby realize suppressing the function of mains by harmonics and flickering, and improved the stability and the reliability of system.

The explanation of main circuit each several part

1, net side filter inductance L1～L4: when inverter circuit adopts the mode that inserts by reactor, be equivalent to incorporate the output voltage of comprehensive restraining device into system through reactor the electric current that the difference that offset current is system voltage and comprehensive restraining device output voltage is produced during by reactor.Inductance is the necessary condition of the normal operation of assurance device.The size of inductance value is very big to systematic influence, choose suitable inductance value and can reach the purpose that suppresses high order harmonic component, if but senior general causes the dynamic responding speed of system slack-off excessively, and the transient current that the mistake young pathbreaker causes device to produce when putting into operation can not be effectively suppressed.Select 1.5～4mH, the inductance of 25～100A through calculating according to different occasions.

2, DC side filter capacitor: the sign of voltage source inverter.Its effect is a filtering dc voltage ripple composition, guarantees that its direct voltage remains unchanged when operate as normal, the assurance device operate as normal.The dc bus capacitor capacity is the bigger the better in allowed limits, and capacity is big more, and the ability that suppresses the capacitance voltage fluctuation is strong more.The selection of electric capacity also will be considered the problem of withstand voltage of electric capacity, through calculating the electric capacity of selecting 1200V, 4700 μ F.

3, rectification circuit 1-3: this partial circuit is reached by igbt T9～T16 and the diode D9～D16 of igbt parallel connected in reverse phase forms; To the control circuit part 2 employing pulse-width modulation (PWMs of this partial circuit by system, Pulse-Width Modulation) method is controlled, can be so that each phase input current be approximately sinusoidal wave and identical with the voltage-phase of system, power factor is approximately 1, press for the DC side filter capacitor provides a galvanic current by the PWM rectification circuit, support for the comprehensive inhibition of carrying out harmonic wave and flickering provides direct voltage.

4, inverter circuit 1-1: this partial circuit is reached by igbt T1～T8 and the diode D1～D8 of igbt parallel connected in reverse phase forms; This partial circuit adopts harmonic wave and flickering comprehensively to suppress control strategy under the control of the control circuit part 2 of system, produces corresponding offset current at the harmonic wave of introducing owing to the access of nonlinear load and offsets with it, thereby suppressed harmonic wave.Simultaneously, needed reactive power when this partial circuit also can provide the distribution system operation has played the effect of the supply power voltage of stable distribution system by compensating power, thereby can suppress the generation of flickering.In fact the circuit topological structure of this part inverter circuit and above-mentioned rectification circuit is identical, and inverter circuit and above-mentioned rectification circuit can be finished the corresponding actions of rectification and inversion independently under the control of system, control circuit, why adopt two identical structure main causes to have: 1) in order can to carry out accurately the voltage at DC side filter capacitor two ends, to control timely, improve control precision, thereby realize that harmonic wave and flickering suppress the optimization of ability; 2) for the redundancy running of implement device, inverter circuit also can be realized rectification function, and rectification circuit also can be realized invert function simultaneously.Carry out rectification and inversion during operate as normal respectively, when breaking down, certain part this partial circuit can be stopped, and adopt its symmetric part to carry out rectification and inversion simultaneously, and comprehensively suppress to realize mains by harmonics and flickering, can improve the reliability and stability of system so greatly.

5, load-side filter inductance L5～L8 and switching circuit 1-4,1-5: rectification circuit adopts the mode that inserts by reactor, when rectification circuit is worked,, the action of switching device igbt T9～T16 contains the very high high order harmonic component of frequency in each phase current because making.The load-side filter inductance plays the high order harmonic component in each phase current of filtering when rectification circuit is worked, and the ripple component of each phase input current is significantly reduced.Identical with net side filter inductance, the value of load-side filter inductance also is taken as 1.5～4mH, 25～100A.In order to control the use of this device, design has switch SW 1 and SW2 in main circuit.

The design of detection algorithm

In order to realize comprehensive inhibition to mains by harmonics and flickering, this device must carry out real-time detection to the electric current in the electrical network, voltage signal, calculate the humorous reactive component that involves in the electric current, thereby by the comprehensive inhibition of control power electronic device realization to harmonic current and reactive current.

Traditional method is based on the method for instantaneous reactive power theory, and threephase load current i a, ib, ic to α, β, 0 phase, calculate ip, iq according to sin ω t, cos ω t through coordinate transform again, and ip, iq deduct their DC component i respectively _p, i _qObtain iph, iqh and transform to harmonic wave and the idle component that α, β, 0 coordinate system obtain load current again.Another conventional method is to adopt the FBD method, a, b, c phase current ia, ib, ic and voltage effect are obtained equivalent conductance Gp (t), Gq (t), and DC component Gp, Gq that Gp (t), Gq (t) deduct them respectively obtain Gph, Gqh and obtain a, b, c harmonic wave and reactive current i mutually with each phase voltage effect again _Ah, i _Bh, i _Ch, because the variable that control section needs is the current value of α, β, 0 phase, therefore will carry out a, b, c arrives α, β, 0 phase coordinates conversion mutually.Two kinds of conventional methods described above all will be carried out cubic transformation for the detection that realizes signal, calculate also relatively loaded down with trivial detailsly, have influenced detection speed idle, the harmonic current composition, have also influenced the comprehensive inhibition to mains by harmonics and flickering.

Therefore, this device in specialized designs a kind of novel detection method.This method is with ip, iq method and the combination of FBD method, the first half of algorithm FBD method, three-phase current ia, ib, ic and reference voltage effect obtain equivalent conductance Gp (t), Gq (t), DC component Gp, Gq that Gp (t), Gq (t) deduct them obtain Gph, Gqh, then according to the linear ratio relation of Gp and ip, latter half adopts ip, iq method, and coordinate transform obtains α, β, 0 phase reference value i _{α h}, i _{β h}, i _0hMore independent ip, iq method and the FBD method of this method all saves nearly 1/3rd calculation step, reduced software overhead, and real-time is good.

Schematic diagram as shown in Figure 2, being described below of wherein each part:

● when compensation harmonic, need calculate Gp (t) and Gq (t):

$G_p\left(t\right)=\frac{P_{\mathrm{\&Sigma;}}}{{\left|\right|v_{\mathrm{\&Sigma;}}\left|\right|}^2}=\frac{\stackrel{\&OverBar;}{u_a{i}_a+u_b{i}_b+u_c{i}_c}}{u_a^2+u_{\mathrm{<figure-callout\; id="2"\; label="b"\; filenames="C20071002145500201.png,C20071002145500212.png"\; state="\{\{state\}\}">b</figure-callout>}}^2+u_{\mathrm{<figure-callout\; id="2"\; label="c"\; filenames="C20071002145500201.png,C20071002145500212.png"\; state="\{\{state\}\}">c</figure-callout>}}^2}$

$G_q\left(t\right)=\frac{P_{\mathrm{\&Sigma;}}}{{\left|\right|v_{\mathrm{\&Sigma;}}\left|\right|}^2}=\frac{\stackrel{\&OverBar;}{u_a^{*}{i}_a+u_b^{*}{i}_b+u_c^{*}{i}_c}}{{\left(u_a^{*}\right)}^2+{\left(u_b^{*}\right)}^2+{\left(u_c^{*}\right)}^2}$

U wherein _a, u _b, u _cBe three-phase voltage, u _a ^*, u _b ^*, u _c ^*Be respectively the conjugation voltage of three-phase voltage, i _a, i _b, i _cIt is three-phase current.

Only need calculate Gp (t) when compensation harmonic with when idle:

$G_p\left(t\right)=\frac{P_{\mathrm{\&Sigma;}}}{{\left|\right|v_{\mathrm{\&Sigma;}}\left|\right|}^2}=\frac{\stackrel{\&OverBar;}{u_a{i}_a+u_b{i}_b+u_c{i}_c}}{u_a^2+u_{\mathrm{<figure-callout\; id="2"\; label="b"\; filenames="C20071002145500201.png,C20071002145500212.png"\; state="\{\{state\}\}">b</figure-callout>}}^2+u_{\mathrm{<figure-callout\; id="2"\; label="c"\; filenames="C20071002145500201.png,C20071002145500212.png"\; state="\{\{state\}\}">c</figure-callout>}}^2}$

● LPF is an IIR type wave digital lowpass filter among the figure, and sample frequency is 12800Hz, is 40Hz by frequency.

● Matrix C among the figure ^-1Expression formula is:

$C^{-1}=\left[\begin{array}{cc}\sin \mathrm{\&omega;t}& -\cos \mathrm{\&omega;t}\\ -\cos \mathrm{\&omega;t}& -\sin \mathrm{\&omega;t}\end{array}\right]$

Like this through just obtaining the humorous reactive component component that involves rapidly after 2 conversion, thereby provide the basis to the comprehensive inhibition of harmonic current and reactive current for realizing by threephase load current i a, ib, ic.

The explanation of control circuit each several part

Voltage, current sensor and A/D sample circuit (with reference to Fig. 5)

Voltage sensor adopts the HNV025T Hall voltage transducer of Zhongxu Electronics Tech Co., Ltd. in the device.Former limit of this transducer and secondary turn ratio are 2500: 1000, just can obtain voltage on the former limit by multiply by conversion coefficient by measuring the voltage on the measuring resistance Rm on this transducer M pin like this.

Current sensor adopts the HNC050LA Hall current sensor of Zhongxu Electronics Tech Co., Ltd. in the device.The specified measurement electric current in the former limit of this transducer is that 50A (AC/DC) secondary output current is 50mA (AC/DC).The terminal voltage of the measuring resistance of the measurement termination by measuring this transducer just can draw the value of the electric current on the former limit like this.

Device has designed the analog quantity input of maximum 16 passages, adopts the AD7865 sampling A of 4 high speeds, low-power consumption, and this chip is 14 analog to digital converters of a kind of 4 passages, single supply 5V power supply, extremely low power dissipation with mW level, input range be-5V～+ 5V, 4 channel sample speed are 100kSPS.The AD7965 chip internal has 4 groups follows/hold amplifier, can carry out synchronized sampling and conversion to 4 road input signals, and the analog-to-digital conversion time is 2.4us.This partial circuit as shown in Figure 2.

AD7865 sampling A pin 1 produces EOC signal busy, inserts the CPLD chip.Pin 3,4,5 meet conversion commencing signal CONVST respectively, and chip selection signal CS reads enable signal RD.Pin 20,21 connects analog quantity 0 input, and pin 18,19 connects analog quantity 1 input, and pin 15,16 connects analog quantity 2 inputs, and pin 13,14 connects analog quantity 3 inputs.Digital quantity output pin DB0-DB13 receives the data/address bus of master control chip.

Device has higher requirements to the synchronism of analog quantity sampling, and the sampling instant of each road analog quantity requires synchronously on the one hand, and the starting point in sampling period and sample frequency will be adjusted according to the system voltage waveform on the other hand.Sample-synchronous can just realize by the hardware timer of master control chip, utilizes the waveform output function of one group of timer to produce the unified transition trigger signal of adjustable trigger impulse as 4 AD7865.Another group timer carries out zero passage detection and frequency measurement by acquisition mode to the system voltage AC signal, adjust the trigger impulse of AD sampling then according to the variation of system voltage waveform, revise sample frequency, thereby realize high accuracy, the analog quantity sampling of high synchronism.After the whole conversions of 4 AD7865 chips finish, utilize the quick interruption of the busy signal triggering master control chip of sampling A, the master control chip reads sampled value successively from sampling A.

Logical signal is handled and switching value is imported, output circuit (with reference to Fig. 6)

The master control chip is by the chip selection signal of CPLD circuit generation to some peripheral hardwares, and expansion I/O is realized the input and output of switching value, and finishes some corresponding logic functions.Programmable logic controller (PLC) adopts the XC95144CPLD chip of Xilinx company.This chip has 144 macrocells, 3200 available doors, and 133 I/O pins are arranged.I/O ability with 3.5V or 5V can be programmed easily to realize certain logic input and output.This partial circuit as shown in Figure 3.

The major function of CPLD circuit:

● the M120 pin is outside 12MHz signal (active crystal oscillator) input, and inner process CB4CE (4 binary counters) and D416E (416 decoder) form 5 frequency dividing circuits and export from the M24 pin

2.4MHz signal passes through CB2CE (2 binary counters) 2 frequency divisions again and obtains the 1.2MHz signal.

● (2) obtain corresponding P (15:0) behind address wire AB21, AB22, the AB23 pin process D38E (38 decoder), PP (31:16), PPP (47:32), NCS_AD1, NCS_AD2, NCS_AD3, NCS_AD4 is the chip selection signal of totally 7 output modules, again in conjunction with NCS3, WRL, the RD signal is realized the gating function to 7 modules.P (15:0), PP (31:16), PPP (47:32) respectively corresponding PA, PC, these 3 of PB open into leaving mouth.

● corresponding respectively 4 the AD7865 chips of (3) AD1_BUSY, AD2_BUSY, AD3_BUSY, AD4_BUSY convert signal, pass through FDC (d type flip flop) respectively and obtain a total triggering signal IRQ0 output through 4 with door again.Wherein PC5 is the reset signal of FDC trigger.

Man-machine interface circuit and communicating circuit

Use the controller of SED1335 in the man-machine interface circuit as LCD LCD, because the read or write speed of LCD is very slow, and task is frequent, in order not influence the major function of device, use one 51 single-chip microcomputer W77E58 to be responsible for the Control work of LCD and keyboard specially in the device, adopted dual port RAM chip id T70V08 swap data between W77E58 and the master control chip.

The main ethernet communication mode that adopts of device, the master control chip internal has Ethernet media interviews controls (MAC) layer controller, adopt the working method of direct memory access (DMA) (DMA) and first in first out (FIFO), the transmitting-receiving of data does not account for processor resource, connect physical layer (PHY) twisted-pair feeder or fiber optical transceiver by Media Independent Interface (MII), realize the adaptive Ethernet of 10MbitS-1/100MbitS-1.Use the LXT971 chip as Fast Ethernet physical layer adaptive transceiver.Because LXT971 supports the IEEE802.3 standard, MII (media independent interface) is provided interface, LXT971 can support MAC, and the master control chip internal just in time is integrated with the Ethernet medium access controller, so can realize seamless link with the master control chip.

RS232 transmission/the receiving chip that this device uses is MAX232, and MAX232 is a kind of pair of set drive/receiver.Sheet contains a capacitive character level generator so that provide EIA-TIA-232-E level at single supply+5V during power supply, and each receiver is converted into 5V TTL/CMOS level with the EIA-TIA-232-E level.Each driver is converted into the EIA-TIA-232-E level with 5V TTL/CMOS level.The RS485 transponder chip MAX485 that this device has also adopted MAXIM company to produce.Its inner integrated receiver and transmitter, DC/DC converter only need provide single+5V power supply just can provide power supply for the interface both sides by internal DC/DC converter in the logic side; Communication mode is half-duplex, and transmission rate can reach 250KBPS, and is provided with the transmission rate restricting circuits, can realize the error free transmission of data.

External memory storage expanded circuit (with reference to Fig. 7)

The external memory storage expanded circuit selects for use speed fast, and capacity is big, cheap Synchronous Dynamic Random Access Memory SDRAM and FLASH memory.Wherein adopt 2 64Mbit SDRAM (IS42SI16400A) to constitute 32 high speeds (133MHz) data/address bus, program code and various data when being used for the storing unit operation.For the speed that improves program running and the hit rate of streamline, after device started, all programs copy among the SDRAM to be moved.

SDRAM pin of chip 23-34 is address wire pin A0-A9, receives the address wire A2-A11 of master control chip, and the A10 signal of pin 22 is received the SDA10 pin of master control chip, and the A11 signal of pin 35 is received the A13 pin of master control chip.The CKE of pin 37,38, the CLK signal is received the SDCKE of master control chip, the SDCK pin, pin 16,17,18,19 WE, CAS, RAS, the CS signal is received the SDWE of master control chip, CAS, RAS, SDCS pin.The data pin DQ0-DQ15 of first SDRAM chip receives low 16 of master control chip data bus, corresponding D0-D15, and the data pin DQ0-DQ15 of second SDRAM chip receives the high 16 of master control chip data bus, corresponding D16-D31.This partial circuit as shown in Figure 4.

The FLASH memory adopts 2 16Mbit FLASH (SST39VF160), and a slice is used for the cure applications program code, and another sheet is used for depositing various event information and the historical datas that need preservation.The address signal A0-A20 of FALSH chip receives the address bus signal A1-A21 of master control chip, and data-signal DQ0-DQ15 receives the data bus signal D0-D15 of master control chip.The chip selection signal CS of two FLASH chips receives the chip selection signal NCS0 and the NCS2 of master control chip respectively.This partial circuit as shown in Figure 5.

FPGA circuit (with reference to Fig. 7)

FPGA selects the EP 1C6Q240C8 of the Cyclone series of Altera for use, EPIC6Q240C8 type FPGA contains 5980 LEs (Logic Elements), 185 available I/O pins, can reach 500MHz to 1GHz through dominant frequency after PLL (PhaseLocked Loop) frequency multiplication in the sheet.

Connect by parallel bus between fpga chip and the master control chip, this bus can comprise the address bus AB[0..23 of master control chip]), data/address bus (DB[0..15], control bus, reset signal (nRST) and interrupt signal line (INT), wherein control bus comprises enable signal (nOE), chip selection signal (nCS), read signal (nRD), write signal (nWE), the benefit of doing like this is, with the fpga chip memoryization, be that the master control chip can be by controlling fpga chip work to the visit of particular address, and can master control chip and fpga chip be resetted simultaneously by common reset signal, avoid the appearance of bus contention and risk phenomenon as far as possible.Fpga chip can send interrupt requests to the master control chip by bus, waits for the processing of master control chip to particular event.This partial circuit connects as shown in Figure 6.

Master control chip circuit (with reference to Fig. 8,9)

Microcontroller adopts the 32 8-digit microcontroller AT91RM9200 based on ARM920T of atmel corp.Performance had Memory Management Unit up to 200MIPS when this microcontroller worked in 180MHz; In the metadata cache of 16K byte, the Instructions Cache of 16K byte, the SRAM of 16K byte, the ROM of 128K byte are arranged; External bus interface is supported SDRAM, static memory, Burst Flash, multiple memory such as SmrtMedia; 4 programmable external timing signals comprise the system timer of periodic interruptions, house dog and second counter; The high level interrupt controller that 8 priority are arranged, maskable interrupts source independently, pseudo-interrupt protection; Four 32 PIO controllers of 122 programmable I/O mouth lines, each line all have input to change and open leakage ability; Its plenty hardware resources can well satisfy the performance requirement of this device.In addition, AT91RM9200 supports the hybrid programming of C/C++ and compilation, and abundant exploiting natural resources is provided, and comprises software module and development support that C CompilerTools, compilation/linker, C source code debugger, JTAG simulator and third party provide.This partial circuit as shown in Figure 7.

The signal of master control chip circuit mainly consists of the following components:

● 32 bit data bus D0～D31,26 bit address bus A0～A25, chip selection signal NCS0, NCS2-NCS6, the control signal SDCS of SDRAM, SDA10, CAS, RAS, SDCKE, SDCK, SDWE utilizes these signals to finish control and visit to external equipment.

● power pins VDDIOM, VDDIOP, VDDPLL, VDDCORE, VDDOSC, ground pin GND, GNDPLL, GNDOSC. crystal oscillator clock pin XIN, XOUT, XIN32, XOUT32, ICE and JATG pin TCK, TDI, TDO, TMS, NTRST, JTAGSEL.

● serial communication interface USART pin SCK0-SCK3, TXD0-TXD3, RXD0-RXD3, RTS0-RTS3, CTS0-CTS3, DSR1, DTR1, DCD1.

● ethernet mac pin EREFCK, ETXCK, ERXCK, ETXEN, ETX0-ETX3, ETXER, ERXDV, ECRSDV.

Claims (5)

1, a kind of mains by harmonics and flash comprehensive inhibitor, it is characterized in that: comprise main circuit (1) and control circuit (2), control circuit (2) is respectively by first voltage sensor (PT1), the 3rd current sensor (CT3) obtains the voltage signal of electrical network, current signal, control circuit (2) is respectively by second voltage sensor (PT2), first, second current sensor (the CT1, CT2) d. c. voltage signal of acquisition main circuit (1), input current signal and output current signal, the controlling and driving signal port of control circuit (2) is connected in the controlling and driving end of main circuit (1), above-mentioned control circuit (2) also is used for electrical network three-phase current ia that sampling is obtained, ib, the ic data obtain equivalent conductance Gp (t) by conversion, Gq (t), obtain the alternating current component Gph of equivalent conductance then, Gqh, utilize equivalent conductance alternating current component harmony to involve the linear relationship of reactive current, needing can obtain the current component i α h of inhibition or compensation through linear transformation, i β h, i0h

Described control circuit (2) comprises sample circuit (2-1), logical signal is handled and switching value imput output circuit (2-2), Programmable Logic Device (2-6) and governor circuit (2-7), sample circuit (2-1) is used to obtain the voltage of electrical network and load, electric current is sampled, the digital signal output end of sample circuit (2-1) is connected with the data/address bus of the master control chip (271) of governor circuit, the control signal output ends of governor circuit (2-7) and switching value signal output part handle with logical signal and the signal input end and the switching value signal input part of switching value imput output circuit (2-2) are connected, logical signal is handled and the control signal output ends of switching value imput output circuit (2-2) is connected with the signal input end of sample circuit (2-1), logical signal is handled and switching value imput output circuit (2-2) is used for obtaining logical process signal and synthetic control signal corresponding and switching value output signal from governor circuit (2-7), control signal exports sample circuit (2-1) to, the switching value output signal is connected to the switching value lead-out terminal and is used to control mains by harmonics and flash comprehensive inhibitor, the address bus of governor circuit (2-7), data/address bus, reseting signal line, the interrupt signal line, the enable signal line, the chip selection signal line, reading signal lines and write signal line respectively with the address bus of the fpga chip EP1C6Q240C8 (261) of Programmable Logic Device (2-6), data/address bus, reseting signal line, the interrupt signal line, the enable signal line, the chip selection signal line, reading signal lines and write signal line connect.

2. mains by harmonics according to claim 1 and flash comprehensive inhibitor, it is characterized in that main circuit (1), comprise capacitor C 1 (1-2), first inductance and switching circuit (1-4) and second inductance and switching circuit (1-5), first inductance and switching circuit (1-4) and second inductance and switching circuit (1-5) all comprise the branch road that four tunnel series circuits of being made up of inductance and switch respectively constitute, between first inductance and switching circuit (1-4) and capacitor C 1 (1-2), be provided with inverter circuit (1-1), and, the sa of inverter circuit (1-1), sb, sc, the sn ac input end respectively with the sa of four tunnel above-mentioned branch roads of first inductance and switching circuit (1-4), sb, sc, the sn ac input end connects, the DC+ of the dc terminal of inverter circuit (1-1) and capacitor C 1 (1-2), the DC-dc terminal connects; Between second inductance and switching circuit (1-5) and capacitor C 1 (1-2), be provided with rectification circuit (1-3), and, the dc terminal of rectification circuit (1-3) is connected with the DC+ of capacitor C 1 (1-2), DC-dc terminal, and la, the lb of (1-3) of rectification circuit, lc, ln exchange end and be connected with la, lb, lc, the ln end of four tunnel above-mentioned branch roads of switching circuit (1-5) with second inductance respectively.

3, mains by harmonics according to claim 2 and flash comprehensive inhibitor, it is characterized in that inverter circuit (1-1) comprise 4 road and bridge arm, the two ends of brachium pontis interconnect respectively and these two ends are respectively the dc terminal of inverter circuit (1-1), per road and bridge, arm was made up of the electronic power switch of 2 series connection, 4 road and bridge arm mid point be respectively sa, sb, sc, the sn ac input end of inverter circuit (1-1), above-mentioned electronic power switch is formed by igbt and with the diode of igbt parallel connected in reverse phase.

4, according to claim 2 or 3 described mains by harmonics and flash comprehensive inhibitors, it is characterized in that rectification circuit (1-3) comprise 4 road and bridge arm, the two ends of brachium pontis interconnect respectively and these two ends are respectively the dc terminal of rectification circuit (1-3), per road and bridge, arm was made up of the electronic power switch of 2 series connection, 4 road and bridge arm mid point la, the lb, lc, the ln that are respectively rectification circuit (1-3) exchange end, above-mentioned electronic power switch is formed by igbt and with the diode of igbt parallel connected in reverse phase.

5, mains by harmonics according to claim 1 and flash comprehensive inhibitor, it is characterized in that being provided with on governor circuit (2-7) external memory storage expanded circuit (2-5), the address wire of external memory storage expanded circuit (2-5), data signal bus and control signal bus are connected with address bus, data/address bus and the control signal bus of governor circuit (2-7) respectively.

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