CN100535827C - Method and network interface circuit for transmission of multi-terminal signals triggered by clocks with different phases - Google Patents
Method and network interface circuit for transmission of multi-terminal signals triggered by clocks with different phases Download PDFInfo
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- CN100535827C CN100535827C CNB021604347A CN02160434A CN100535827C CN 100535827 C CN100535827 C CN 100535827C CN B021604347 A CNB021604347 A CN B021604347A CN 02160434 A CN02160434 A CN 02160434A CN 100535827 C CN100535827 C CN 100535827C
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Abstract
The present invention provides a network interface circuit with multi-ports and relevant controlling method. The network interface circuit with multi-ports is used to transmit a plurality of signals through the multi-ports to the different nodal points of the network (imaging terminal machnie), wherein the network interface circuit triggers the signal transmission of each port using different clock with difference of phase, making the conversions of data of the signals transmitted at each port not take place at same time.
Description
Technical field
The present invention relates to a kind of multiport network interface circuit and corresponding control methods, particularly relate to a kind of network interface circuit and correlation technique that can trigger signal transmission on the different port, ring (cross-talk) with power supply concussion (power bounce) and the signal string that reduces network interface circuit with different clocks.
Background technology
In modern information society, can the quick exchange data, the computer network of data, information and knowledge, become one of interpersonal communication, the most important resource of technical development.Expansion, accelerating network capital construction effectively, and even the major tasks that information industry government endeavours promotion and implementation also become.
Different computer terminals to be connected to network, can use different networks to connect topology (topology).Connect in the topology at these, terminating machine (can be computing machine, memory storage or network printer or the like) can be regarded as network of network node (node); Direct, indirect connection between each network node just can form a network.For instance, in the Local Area Network (LAN, Local Area Network) of 10 BASET commonly used at present or 100 BASE T, promptly form network with starlike topology; Each terminating machine can be connected to a hub (hub) or interchanger (switch) respectively, be connected with other the network node or other the network equipment (similarly being other hub, interchanger or router) again, just can be combined into a network, and by the various network device on the network at each network node swapping data.In other words, similarly be these network equipments of hub, interchanger or router, can couple together each independent network node, form the huge network that can exchange information at last, allow the user of each terminating machine can be in vast network the abundant Internet resources of access.
For the data that will coordinate to come and go between each network node, these network equipments that are used for connecting each network node have a plurality of network connection ports that are used for swap data mostly, and each network connection port is connected in a network node (or other network equipment).By a network interface circuit, these network equipments just can transmit data signals to each network node via a plurality of different network connection ports, and receive the data signals of being sent by each network node, reach the function of network interconnection.Please refer to Fig. 1, it has shown the functional block diagram of known multiport network interface circuit 10; Network interface circuit 10 can be the network interface circuit that is contained in the network equipments such as hub, interchanger or router.At this hypothesis network interface circuit 10 is the network interface circuit of eight ports, have eight network connection ports, be connected to eight network node 19A to 19H in the topology network (the just terminating machine or other the network equipment, similarly be computing machine, the network printer or other hub, interchanger or the like), simultaneously the transmission signal data are to these eight network nodes, and receive data, the signal that is transmitted by these eight network nodes simultaneously.In network interface circuit 10, be provided with a medium accesses circuit (MAC, medium access control circuit) 12 and one physical layer circuit (PHY) 14 is used for realizing the function of medium accesses layer and physical layer under open system interlink (the open svstem interconnection) framework respectively.Eight network node 19A to 19H that cooperate network interface circuit 10 to connect, also be provided with eight signal circuit 16A to 16H in the physical layer circuit 14, be connected to the signal port Sp1 to Sp8 of medium accesses circuit 12, to handle the signal that will transfer to each network node 19A to 19H, and form corresponding signal mp1 to mp8 respectively, by transmit port 22A to 22H these signals are transferred to network node 19A to 19H respectively again.Transfer to the signal of network interface circuit 10 respectively by network node 19A to 19H, then can transfer to a receiving circuit 18 via receiving port 24A to 24H respectively, after handling, be back to medium accesses circuit 12 again through signal.In other words, transmit port 22A, receiving port 24A just form a network connection port altogether, can transmit, receive data, the signal of network node 19A in the mode of duplex (duplex); In like manner, receiving port 24B, transmit port 22B form the network connection port of 10 pairs of network node 19B transmitting-receivings of network interface circuit signal, by that analogy.
Except the signal circuit 16A to 16H that handles the signal transmission, be used for handling the signal circuit 18 that signal receives, also be provided with a clock generator 14 in the known entities layer circuit 14, be used for producing a clock CLK0, running, especially signal circuit 16A to 16H with each function square in the coordination entity layer circuit 14.Accordingly, signal circuit 16A to 16H also is respectively equipped with a clock end 25, the synchronous operation with the triggering of receive clock CLK0.Clock generator 14 can be a phase-locked loop, is electrically connected on medium accesses circuit 12, produces a synchronous clock CLK0 with the reference clock CLKr0 that produces according to medium accesses layer circuit 12.In other words, by the control to reference clock CLKr0, medium accesses circuit 12 is the clock of energy controlled entity layer circuit 14 runnings just, the sequential of especially each network node 19A to 19H being received and dispatched signal.As a phase-locked loop, be provided with a phase detectors PD0, a charging circuit (charge pump) CP0, an oscillator VCO0 in the clock generator 14, also optionally add a frequency divider DIV0.Phase detectors PD0 is used for detecting frequency and the phase differential between a reference clock CLKr0 and a concussion clock CLKd0, and produces an error signal Se0.Charging circuit CP0 can be converted to error signal Se0 the controlling signal Sc0 of one voltage, similarly is to utilize error signal Se0 to control the size of current of a current source, and electric current is charged into an electric capacity to produce controlling signal Sc0.Oscillator VCO0 as a voltage-controlled oscillator (VCO) can produce clock (concussion clock) CLK0, and adjusts the frequency speed of clock CLK0 according to the voltage swing of controlling signal Sc0.The concussion clock CLKd0 that clock CLK0 produces after via frequency divider DIV0 frequency division just can feedback to phase detectors PD0, enable clock generator 14 can be revised the frequency of clock CLK0 once again according to the frequency between concussion clock CLKd0 and reference clock CLKr0, it is synchronous that clock CLK0 is able to the reference clock CLKr0 of medium accesses circuit 12 generations.
The situation of medium accesses circuit 12 and 14 coordinate operation of physical layer circuit can be described below.To transfer to the data of each network node 19A to 19H by network interface circuit 10, encapsulated to form package by medium accesses circuit 12, comprise that the address with data affix header (header), bug check sign indicating number and related entities device (similarly is the medium accesses control address, MAC address) or the like, to make things convenient for the transmission of package on network.The package that transfers to heterogeneous networks node 19A to 19H transfers to each corresponding signal circuit 16A to 16H (similarly being that the package that will transfer to network node 19A can be handled by signal circuit 16A) respectively, by each corresponding signal circuit package being carried out necessary signal handles, similarly be scrambler (scramble), coding (encode, as the coding of the MLT3 under the 100BASE T Local Area Network) and suitably modulation, signal drives, make signal that enough driving forces and preferable signal waveform can be arranged, can successfully transfer to each network node via transmission line by corresponding transmit port.Transfer to the signal of network interface circuit 10 by each network node, then by receiving circuit 18 suitably decode, descrambling code or demodulation, be reduced to the data of package form, and be back to medium accesses circuit 12, by medium accesses circuit 12 it is reduced processing, obtain the data in the package.When reality is implemented, transfer to the form of the signal mp1 to mp8 of each network node with differential signal, simultaneously two anti-phase each other signals are transferred to corresponding network node by corresponding transmit port with transmission line (similarly being that twisted wire is right, twisted pair) respectively.In like manner, each network node also is with the corresponding receiving port 24A to 24H of data transmission to network interface circuit 10 with two anti-phase each other signals.
Please refer to Fig. 2 (and simultaneously with reference to figure 1).Fig. 2 is the signal mp1 to mp8 of known network interface circuit 10 in each transmit port 22A to 22H transmission, and the synoptic diagram of clock CLK0 waveform sequential; The transverse axis of Fig. 2 is the time; The longitudinal axis of each signal waveform is the signal size.Suppose the signal circuit that rising edge (rising edge) triggers on each signal circuit 16A to 16H is at this; That is to say that each signal circuit is after receiving a clock that triggers by separately clock end 25, the last rising edge of this clock can trigger the signal processing that each signal circuit is correlated with, and produces data.As shown in Figure 1, because in the known network interface circuit 10, each signal circuit 16A to 16H is all synchronously triggered by clock CLK0, and data-switching (transition) may take place each signal mp1 to mp8 at one time, is converted to another data by data.For instance, as shown in Figure 2, clock CLK0 is increased to high level and is produced a rising edge by low level in time point tp0, and the data of transmitting among the signal mp1 also are converted to the data of a stroke numeral " 1 " by the data (one data just) of a stroke numeral " 0 ".In like manner, at the rising edge of clock CLK0 at time point tp1, signal mp1 also can be converted to the data of a time stroke numeral " 0 " by the data of a stroke numeral " 1 "; Clock CLK0 is then gone out the data of another stroke numeral " 0 " by the data-triggered of a stroke numeral " 0 " at signal mp1 at the rising edge of time point tp4.In known network interface circuit 10, because each signal circuit 16A to 16H is triggered by same clock CLK0, so each signal circuit will transfer to the signal mp1 to mp8 of each network node, all in the same time data-switching takes place.As shown in Figure 2, each signal mp1 to mp8 is converted to the data of a stroke numeral " 1 " by the data of a stroke numeral " 0 " at the rising edge of time point tp0; At the rising edge of time point tp8, signal mp3 to mp8 is converted to the data of digital " 0 " by the data of numeral " 1 "; By that analogy, signal mp1 to mp6 can be converted to the data of digital " 0 " by the data of numeral " 1 " at the rising edge of time point tp11, or the like.
As known for those skilled in the art, each signal circuit 16A to 16H will be with signal mp1 to mp8 by transmission line during to corresponding network node 19A to 19H, enough driving forces are arranged, could be with the data of each position in each signal smoothly via the network node of transmission line to far-end.For instance, signal circuit 16A has a data-switching at time point tp0, transmit the data of a numeral " 1 " again to network node 19A after the data of transmission of digital " 0 "; Signal circuit 16A will drive transmission line between (drive) transmit port 22A, network node 19A with big electric current by transmit port 22A this moment, could apace the voltage on the whole transmission line be drawn high to the high level of numeral " 1 " by the low level of original digital " 0 ".Relatively, in case smoothly the signal on the transmission line is pulled to high level, the required signal driving force of signal circuit 16A just can significantly reduce, and only needs less power, just can keep the high level on the transmission line.Picture does not have the generation of data-switching at time point tpA, and the power consumption change minimum of physical layer circuit 14 integral body is not so there is the concussion (power bounce) in the power supply to produce.On the other hand, arrived time point tp1, signal circuit 16A also will discharge to whole transmission line with big electric current, the voltage on the transmission line could be pulled low to low level by high level originally, so that after the data of numeral " 1 ", sends the data of a digital " 0 ".In like manner, other signal circuit 16B is to 16H, also will be when each corresponding signal generation data-switching, change to drive signal by the map network node of transmission line to far-end with big electric current.Yet, because the known multiport network interface circuit 10 among Fig. 1 is to trigger each signal circuit 16A to 16H simultaneously with single clock CLK0, so each signal circuit all in the same time (rising edge of clock CLK0 just) data-switching takes place, and to drive corresponding data-switching respectively with big electric current at one time.Because each signal circuit all will be quoted powerful electric current at one time and drive signal, can increase the overall power of physical layer circuit 14 suddenly, and cause power supply concussion (power bounce).In general, network interface circuit 10 is to supply its required power with the Dc bias of outside; If each signal circuit 16A to 16H increases power demand at one time in order to want the driving data conversion in the network interface circuit 10, outside Dc bias can be responded this power demand in smooth-going ground immediately, and cause fluctuation (ripple) in the response, make this Dc bias can't keep firm power supply to network interface circuit 10, the normal operation that jeopardizes each signal circuit 16A to 16H jointly.Especially when network interface circuit 10 has just come into operation, can send link pulse wave (linkpulses) and transfer to each network node to set up synchronous contact with each network node; More serious power supply concussion just can take place setting up the link initial stage, because identical data-switching can take place in each signal mp1 to mp8 simultaneously, and increase power demand at one time and change with driving data, similarly be in Fig. 2 by time point tp0 to tp7 during this period of time shown in.Even each signal mp1 to mp8 can transmit different data after a while, there are several signals simultaneously data-switching to take place and produce no small power supply concussion but have sizable probability, similarly be at time point tp8, have six signal mp3 to mp8 that data-switching can take place simultaneously.
Except causing the power supply concussion, the data-switching that known network interface circuit 10 triggers simultaneously, also the string that causes easily between each signal circuit, transmission line rings (cross-talk).For instance, at time point tp0, signal mp1 to mp8 will be increased to high level by low level simultaneously, because the long mutually property electrical couplings between signal circuit 16A, the 16B, signal mp1 can be coupled to raise the at one time portion of energy of level of signal mp2, the signal level of signal mp1 may be risen to than the also high level of numeral " 1 " standard high level, shown in dotted line waveform 27a among Fig. 2.In other words, after being elevated to the predetermined level of representing numeral " 1 ", the signal level of signal mp1 also can be because of electrical couplings continues to rise, and surpasses the specified signal level of circuit, damages signal circuit.In like manner, at time point tp9, signal mp2 will be converted to low level by high level, and signal mp3 will be a high level by low transition also simultaneously; Signal mp2 is in being pulled low to low level process, can can't really be reduced to the standard low level (maybe will just can be reduced to the standard low level of digital " 0 ") of representing digital " 0 " because being coupled to the portion of energy of signal mp3 level rising, shown in dotted line waveform 27b with the long reaction time; And signal mp3 also may be because the energy being coupled of part can't really be elevated to the standard high level (maybe will just can rise to high level with the long period) of representing numeral " 1 " to signal mp2, shown in dotted line waveform 27c.In case above-mentioned distortion and delay take place the waveform of signal mp1 to mp8, will cause data erroneous judgements (similarly being the data that the error in data ground of digital " 0 " become numeral " 1 "), signal sequential to be difficult to synchronous or the like the influence bad to network data transmission.
Sum up above-mentioned discussion as can be known, because known multiport network interface circuit 10 is to trigger the signal that will transfer to the heterogeneous networks node by same clock, make each signal that data-switching can synchronously take place at one time, the ill effect that concussion and string ring that causes powering makes known network interface circuit have power shakiness, signal waveform distortion or the like shortcoming.Especially modern to the having relatively high expectations of network data transmission speed, make the bit data that will transmit in the unit interval increase, be equivalent to increase the data-switching in the unit interval; Concerning known network interface circuit 10, the time enough and to spare just shortens power more by recovering stably after shaking, and the situation of power supply concussion relatively will be more serious.Because it is bigger that driving data conversion apace, each signal circuit drive the required energy of signal, and even the caused power supply concussion of data-switching, electrical couplings waveform distortion simultaneously, it is more obvious also will to become.
Summary of the invention
Therefore, fundamental purpose of the present invention, be to provide a kind of clock to trigger the network interface circuit and the corresponding control methods of each signal circuit transmission signal with out of phase, data-switching (transition) can not take place simultaneously so that will transfer to the signal of each network node, reduce the adverse effect that power supply concussion and string ring.
In order to realize above-mentioned purpose of the present invention, the present invention proposes a kind of network interface circuit, in order to a plurality of network node communications; This network interface circuit includes: one first signal circuit is used for according to one first clock generating, one first signal; One second signal circuit is used for producing one second signal according to a second clock; One first transmit port and one second transmit port are used for respectively this first signal and this second signal are transferred to these network nodes; And a clock generator, be used for producing this first clock and this second clock, and have a default phase differential between this first clock and this second clock.
The invention allows for a kind of network interface circuit, in order to a plurality of network node communications; This network interface circuit includes: a phase-locked loop in order to receiving an external reference clock producing a plurality of clocks, and has a default phase differential each other between these clocks; A plurality of signal circuits are coupled to this phase-locked loop, in order to produce a plurality of transmission signals respectively according to these clocks; And a plurality of network connection ports, be coupled to these signal circuits, in order to these transmission signals are transferred to these network nodes respectively.
The invention allows for a kind of method of electromagnetic interference (EMI) of reduction by one physical layer circuit, comprise the following step: receive an external reference clock to produce a plurality of clocks, these clocks have a same frequency, and have phase differential to each other; Produce a plurality of transmission signals respectively according to these clocks; And these transmission signals are transferred to a plurality of network nodes respectively.
In known technology, each is used for producing the signal circuit of transmission signal all with an identical clock triggering, make each signal that data-switching can take place simultaneously, can cause power supply concussion and string to ring, make the known network interface circuit stably not work, and cause negative effects such as network data transmission waveform distortion, delay and misinformation.
In the present invention, different signal circuits is that the clock according to out of phase is triggered, data-switching can not take place together in a flash in the signal that makes each signal circuit will transfer to each network node, network interface circuit yet therefore of the present invention does not have the phenomenon that power demand moment uprushes, the generation of the concussion of avoiding powering; And the string that produces because of electric mutual coupling in data-switching moment rings phenomenon and is also significantly alleviated.
Description of drawings
Fig. 1 is the functional block diagram of a known multiport network interface circuit.
Fig. 2 is the waveform sequential chart that each port transmission signal reached relevant clock when network interface circuit operated among Fig. 1.
Fig. 3 is the functional block diagram of multiport network interface circuit of the present invention.
Fig. 4 is network interface circuit control clock and a related signal waveform sequential chart in one embodiment among Fig. 3.
Fig. 5 is network interface circuit control clock and a related signal waveform sequential chart in another embodiment among Fig. 3.
Fig. 6 is the functional block diagram of clock generator one embodiment among Fig. 3.
The reference numeral explanation
10,30 network interface circuits
12,32 medium accesses circuit
14,34 physical layer circuit
16A-16H, 36A-36A signal circuit
18,38 receiving circuits
19A-19H, 39A-39H network node
20,40 clock generators
22A-22H, 42A-42H transmit port
24A-24H, 43A-43H receiving port
25,45 clock end
The 27a-27c dotted line waveform
48 phase inverters
CLKr0, CLKr reference clock
CK0, CK clock end
PD0, PD phase detectors
CP0, CP charging circuit
VCO0, VCO oscillator
DIV0, DIV frequency divider
Se0, Se error signal
Sc0, Sc controlling signal
Sp1-Sp8, S1-S8 signal port
Mp1-mp8, m1-m8 signal
The T cycle
Td, ta, td period
Tp0-tp11, tpa, t0-t1 time point
CLK0, CLKd0, c1-c8, CLKd, CLK, CKa-CKe, CL1-CL8 clock
Embodiment
Describe the preferred embodiments of the present invention in detail below in conjunction with accompanying drawing.
Please refer to Fig. 3.Fig. 3 is the synoptic diagram of multiport network interface circuit 30 function squares of the present invention.It similarly is in the network equipment of interchanger, hub or router or the like that network interface circuit 30 can be used on, and is used for and a plurality of network node swap datas, signal.Among the embodiment in Fig. 3, also suppose that network interface circuit 30 is the network interface circuit of one or eight ports, with eight network connection ports respectively with eight network node 39A to 39H swap datas.Also be provided with a medium accesses circuit 32 and a physical layer circuit 34 in the network interface circuit 30.Medium accesses circuit 22 is used for the carrying out of Control Network transmission.Be provided with a clock generator 40, a receiving circuit 38 and eight signal circuit 36A to 36H in the physical layer circuit 34.Signal circuit 36A to 36H is used for respectively producing signal m1 to m8, and by transmit port 42A to 42H each signal m1 to m8 is transferred to corresponding network node 39A to 39H respectively.Be back to the signal of network interface circuit 30 by network node 39A to 39H, then can transfer to receiving circuit 38 by each receiving port 43A to 43H respectively, and after signal is handled, be back to medium accesses circuit 32.Signal circuit 36A to 36H is respectively equipped with a clock end 45, is used for receiving the triggering of a clock to coordinate the running of each signal circuit.Wherein each signal circuit 36A to 36H can be respectively triggered by the clock c1 to c8 of out of phase, rather than is triggered uniformly by single clock.In order to cooperate such mechanism, clock generator 40 also can produce each clock c1 to c8 according to the reference clock CLKr of medium accesses circuit 32 by clock end CK output.
The situation of network interface circuit 30 runnings can be described below.Be similar to the operation principles of network interface circuit 10 among Fig. 1, the data encapsulation that medium accesses circuit 32 can transfer to each network node is a package, transfers to corresponding signal circuit 36A to 36H respectively by each network connection port S1 to S8.The steering order that signal circuit 36A to 36H transmits according to medium accesses circuit 32 is carried out signal to each package and is handled (similarly being scrambler, coding or modulation) and signal driving, and respectively under the triggering of clock c1 to c8, produce signal m1 to m8, the transmit port 42A to 42H by correspondence transfers to each network node 39A to 39H respectively with signal m1 to m8 again.The signal that is transferred to network interface circuit 30 by each network node 39A to 39H reaches receiving circuit 38 via each receiving port 43A to 43H, separate signals such as volume, descrambling code or demodulation by receiving circuit 38 and handle, be back to medium accesses circuit 32 to restore the data of package form.Medium accesses circuit 32 just can carry out decapsulation to these packages, takes out data wherein.Each transmit port 42A to 42H together with receiving port 43A to 43H, just forms the network connection port to each network node 39A to 39H transceive data respectively.
As long as each signal m1 to m8 data-switching can not take place at one time, each signal circuit 36A to 36H just can not increase power demand at one time and come the driving data conversion, just can avoid the power supply concussion yet.As previously mentioned, when each signal generation data-switching, the power demand of corresponding signal circuit signal will heighten, so that increase the signal driving capability, and the driving data conversion.If as known technology, data-switching all takes place in each signal at one time, and the power demand of each signal circuit will increase the same time, and 10 overall power moments of known network interface circuit are uprushed, and causes power supply to be shaken.In comparison, the present invention can stagger the time that each signal data m1 to m8 data-switching takes place, each signal circuit 36A to 36H just can not increase power demand simultaneously jointly, network interface circuit 30 overall power also can be dispersed in time domain fifty-fifty, can at a time not explode suddenly, and then avoid the power supply concussion.In like manner, because the time of each signal m1 to m8 data-switching staggers, the string that causes because of the electrical energy mutual coupling during each signal data-switching rings also to be avoided, and makes the waveform of each signal among the present invention can meet ideal waveform, does not also have extra delay.Particularly the problem for electromagnetic interference (EMI) in the chip design also can obtain significant improvement; Along with the rate of change reduction of drive current in the unit interval, the electromagnetic interference (EMI) in the chip also can decrease.When reality was implemented, the length that the visual power response of phase place extent between each clock c1 to c8 (length of period td just), string ring effect and period T decided.For instance, if at a certain signal circuit because data-switching and after increasing power demand, can behind a period ts, recover steadily the power supply of network interface circuit 30, period td only is larger than period ts so, just can significantly reduce the situation of powering and shaking.In like manner, if after a certain signal generation data-switching, as long as again through a period ts2, the transient state of this signal just can significantly reduce the influence degree of other signal electrical couplings, so as long as period td is slightly larger than period ts2, just can significantly alleviate the influence that string rings.And among Fig. 4 between each clock of embodiment mutual phase differential also not necessarily identical, can be different as the phase differential between clock c1, c2 with the phase differential between clock c2, c2.
Please refer to Fig. 5 (and in the lump with reference to figure 3).Fig. 5 is in the second embodiment of the invention, the synoptic diagram of signal m1 to m8, clock c1 to c8 waveform sequential; Identical with Fig. 4, the transverse axis of Fig. 5 is the time, and the longitudinal axis of each signal, clock is a size waveforms.In this embodiment, clock generator 40 produces four groups of clocks that phase place is different, wherein clock c1, c5 are the synchronous clock of same frequency (same cycle), and clock c2, c6 are that c3, c7 and c4, c8 are other two groups of synchronous clocks of same frequency with the synchronous clock of frequency.Each is organized then phase differential mutually between clock, be reflected as the time delay of period ta.As shown in Figure 5, the rising edge of the rising edge of clock c1, c5 and clock c2, c6 has the delay of period ta, and the rising edge between the rising edge of clock c3, c7 and clock c2, c6 also has the delay of period ta, by that analogy.Under the triggering of these clocks, the data-switching of signal m1, m5 can be triggered at one time, and the data-switching of signal m2, m6 can be triggered at one time, but data-switching can not take place simultaneously between signal m1, m5 and signal m2, m6.For instance, in Fig. 5, signal m1, m5 are under the triggering of clock c1, c5, be converted to the numeral " 1 " of high level by low level digital " 0 " at time point t1, signal m2, m6 are under the triggering of clock c2, c6, then can postpone period ta, just data-switching can take place, be converted to the data of numeral " 1 " by the data of digital " 0 " at time point t1+ta.Data-switching just takes place when in like manner, signal m3, m7 then can be delayed to time point t1+2ta again.If the power deliverability to network interface circuit 30 is preferable, can stably deal with the power demand of allowing that several signal circuits increase at one time, just can adopt the embodiment among Fig. 5, with several signal circuits is one group (Fig. 5 embodiment be one group with two signal circuits), triggers different signal circuits in same group with synchronous clock.In such an embodiment, the number of the different clock of phase place that clock generator 40 will produce just can reduce, also can be more flexible when the phase differential of planning between each clock (length of period ta just).Signal circuit increases the caused power supply concussion of power demand simultaneously but present embodiment still can be avoided a plurality of (or owning); Because present embodiment can be grasped the number that can increase the signal circuit of power demand in the same time really, also can comparatively accurately design, plan the power supply to network interface circuit 30.With the embodiment among Fig. 5, have only two signal circuits in same group can increase power demand with driving data conversion (for example having only signal circuit 36A, 36E can drive data-switching among signal m1, the m5 at most at time point t1) in the same time at most, so circuit designers just can preferably be grasped the power demand of network interface circuit 30 of the present invention in each time.In comparison, known network interface circuit 10 has eight signal circuits at one time and wants the driving data conversion, also may only there be a signal circuit to want the driving data conversion, because the uncertainty of power demand is bigger, the difficulty when increasing circuit design, planning.In addition, when reality was implemented the similar embodiment shown in Figure 5 of the present invention, can select layout far away two (or several) signal circuit was one group, triggers with same clock.The electrical couplings that string rings can be stronger on the nearer circuit of layout, and the negative effect that causes is also bigger.If trigger with same clock at layout different signal circuits far away, even data-switching can take place at one time, the electrical couplings between different circuits is also less, and the influence that string is rung can effectively reduce.
Please continue with reference to figure 6 (and in the lump with reference to figure 3).Fig. 6 is the function block schematic diagram of clock generator 40 1 embodiment among Fig. 3.In this embodiment, be provided with a phase detectors PD, a charging circuit CP, an oscillator VCO in the clock generator 40 forming a phase-locked loop, and optionally add a frequency divider DIV.Be similar to the clock generator 20 among Fig. 1, clock generator 40 also is to produce each clock c1 to c8 according to the reference clock CLKr that medium accesses circuit 32 provides, and produces signal m1 to m8 to trigger each signal circuit 36A to 36H.The principle of work of clock generator 40 can be described below: phase detectors PD detects the frequency between a clock CLKd and reference clock CLKr or the error of phase place, and produces an error signal Se; Charging circuit CP produces corresponding Control of Voltage signal Sc according to error signal Se; Oscillator VCO can shake a clock (a concussion clock) CLK, and adjusts the frequency size of clock CLK according to controlling signal Sc.The clock CLKd that produces behind the clock CLK process frequency divider DIV frequency division will feedback to phase detectors PD, according to the frequency of the error repetitiousness correction clock CLK of the frequency between clock CLKd and reference clock CLKr, phasetophase, it is synchronous that clock CLK is able to reference clock CLKr again.In clock generator 40, oscillator VCO can realize with ring oscillator, oscillator VCO in the image pattern 6 promptly forms a typical ring oscillator with five phase inverters of contacting mutually 48, the time delay of the anti-phase output of each phase inverter of controlling signal Sc may command is to control the cycle of the clock CLK that this ring oscillator produces.And the present invention can utilize the output of each phase inverter 48 in this ring oscillator to produce the clock of out of phase.As shown in Figure 6, the waveform of the clock CKa to CKe that draws among Fig. 6 is the signal waveform that each phase inverter is exported among the oscillator VCO, and (transverse axis of each waveform is the time, the longitudinal axis is a size waveforms), the rising edge that can find out each clock CKb to CKe has the time delay (just with respect to clock CKa phase differential) of period tc, 2tc, 3tc and 4tc respectively with respect to the rising edge of clock CKa.The period tg that marks in Fig. 6 waveform is time delay of the anti-phase output of a phase inverter; For instance, clock CKa is clock CKd through the result that a phase inverter 48 postpones anti-phase output.Configuration in using Fig. 6 realizes when of the present invention, for instance, desirable with clock CKa to CKd respectively as clock c1 to c4 (and c5 to c8), can realize the embodiment of the present invention in Fig. 5.In addition, implement the embodiment among Fig. 4, but then nine phase inverters of polyphone among the earthquake device VCO (or phase inverter of four differential drivings, differential output) to produce the clock of eight outs of phase.In the time of will in each phase inverter 48, taking out each clock among Fig. 6, also can increase the driving force of each clock with impact damper 50 in addition, and prevent that noise warning signal from entering in the phase-locked loop at phase inverter 48 places.
Generally speaking, in known multiport network interface circuit, be used for a plurality of signal circuits of transmission signal to be subjected to the triggering of same clock, can improve power demand at one time to drive the data-switching in the transmission signal, cause power demand moment to uprush, cause the power supply concussion; And each signal circuit drives signal when conversion at the same time, also can because of electrical energy be coupled mistakenly the waveform distortion that causes transmission signal, postpone or the like network signal transmission adverse influence.In comparison, be that clock with out of phase drives different signal circuits in the multiport network interface circuit of the present invention, can stagger the different signals time that data-switching takes place when transmission, make power demand can not explode suddenly, avoid the power supply concussion, also can significantly reduce the influence that string rings, the quality of maintaining network signal transmission.In the Local Area Network framework of 100BASE T, the signal that transfers to network node can be encoded to the coded system of MLT-3 have " 1 ", " 0 " reach the signal of " 1 " three kinds of numerical datas, but spirit of the present invention still can be used in the multiport network equipment under the 100BASE T network architecture, avoids the power supply concussion and the string of circuit in the network equipment to ring.
The above only is preferred embodiment of the present invention, and all equalizations of doing according to claim of the present invention change and modify, and all should belong to the covering scope of claim of the present invention.
Claims (9)
1. network interface circuit, in order to a plurality of network node communications;
This network interface circuit includes:
One first signal circuit is used for according to one first clock generating, one first signal;
One second signal circuit is used for producing one second signal according to a second clock;
One first transmit port and one second transmit port are used for respectively this first signal and this second signal are transferred to these network nodes; And
One clock generator is used for producing this first clock and this second clock, and has a default phase differential between this first clock and this second clock.
2. network interface circuit as claimed in claim 1, wherein this clock generator includes:
One phase detectors are used for detecting the error of frequency between a reference clock and a concussion clock or phase place and produce a corresponding error signal;
One charging circuit is electrically connected on this phase detectors, is used for producing a controlling signal according to this error signal; And
One oscillator is electrically connected on this charging circuit, is used for adjusting according to this controlling signal the frequency of this concussion clock.
3. network interface circuit as claimed in claim 2, wherein this oscillator is a ring oscillator, it includes: a plurality of phase inverters, and it is connected in series each other, and each phase inverter is used for the signal of adjacent another phase inverter output is anti-phase and postpone a time delay to produce corresponding output signal; This oscillator can be adjusted the time delay of each phase inverter according to this controlling signal, and shakes clock with the output signal of the phase inverter in these phase inverters as this.
4. network interface circuit, in order to a plurality of network node communications; This network interface circuit includes:
One phase-locked loop in order to receiving an external reference clock producing a plurality of clocks, and has a default phase differential each other between these clocks;
A plurality of signal circuits are coupled to this phase-locked loop, in order to produce a plurality of transmission signals respectively according to these clocks; And
A plurality of network connection ports are coupled to these signal circuits, in order to these transmission signals are transferred to these network nodes respectively.
5. network interface circuit as claimed in claim 4, wherein this phase-locked loop includes:
One phase detectors are used for detecting the error of frequency between this an external reference clock and a concussion clock or phase place and produce a corresponding error signal;
One charging circuit is electrically connected on this phase detectors, is used for producing a controlling signal according to this error signal; And
One oscillator is electrically connected on this charging circuit, is used for adjusting according to this controlling signal the frequency of this concussion clock.
6. network interface circuit as claimed in claim 5, wherein this oscillator is a ring oscillator, it includes: a plurality of phase inverters, and it is connected in series each other, and each phase inverter is used for the signal of adjacent another phase inverter output is anti-phase and postpone a time delay to produce corresponding output signal; This oscillator can be adjusted the time delay of each phase inverter according to this controlling signal, and shakes clock with the output signal of the phase inverter in these phase inverters as this.
7. network interface circuit as claimed in claim 6, wherein this controlling signal provides the identical retardation of each phase inverter one.
8. method that reduces the electromagnetic interference (EMI) of a physical layer circuit comprises the following step:
Receive an external reference clock to produce a plurality of clocks, these clocks have a same frequency, and have phase differential to each other;
Produce a plurality of transmission signals respectively according to these clocks; And
These transmission signals are transferred to a plurality of network nodes respectively.
9. method as claimed in claim 8 wherein has an identical phase differential each other between these clocks.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021604347A CN100535827C (en) | 2002-12-30 | 2002-12-30 | Method and network interface circuit for transmission of multi-terminal signals triggered by clocks with different phases |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB021604347A CN100535827C (en) | 2002-12-30 | 2002-12-30 | Method and network interface circuit for transmission of multi-terminal signals triggered by clocks with different phases |
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| Publication Number | Publication Date |
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| CN1424635A CN1424635A (en) | 2003-06-18 |
| CN100535827C true CN100535827C (en) | 2009-09-02 |
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| CN102110463A (en) * | 2009-12-29 | 2011-06-29 | 三星电子株式会社 | Semiconductor memory interface device and method |
| TWI451259B (en) * | 2010-08-26 | 2014-09-01 | Mstar Semiconductor Inc | Multi-input interface circuit and associated power saving method |
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