CN100534190C - A real time frame rate control method and its device - Google Patents

Abstract

A real time frame rate control method is characterized in that: updating frame rate control factor FC according to frame rate control factor updating principle period, and using frame rate control register whose value length is B and containing dispatch frame whose identification number equals to FC to update frame rate control register; circulation using each bit of frame rate control register in turn as identifying bit to identify received each picture frame separately: when the picture frame corresponding identifying bit is dispatch frame identification, dispatching the frame; otherwise discarding the frame; the frame rate control factor updating principle is: using new frame rate control factor to make the ratio of it and B equal to the ratio of Ftarget and Fsensor, or closer the ratio of Ftarget and Fsensor than the ratio of frame rate control factor before updating; Ftarget and Fsensor is target frame rate and picture sensor outputting frame rate separately; the dispatch frame identification is 1 or 0.

Description

Real-time frame rate control method and device

Technical Field

The invention relates to a method for realizing real-time frame rate control in a digital camera and a real-time frame rate control device thereof.

Background

During the use of the camera, the output frame rate Fsensor of the image sensor is different from the frame rates required by the subsequent image processing module and the image data transmission module. In order to avoid the phenomenon of congestion (queuing) of image frames in the image processing module or the image data transmission module due to the fact that the Fsensor is too large, it is generally required to set a target frame rate Ftarget and set a frame rate control module to perform frame rate control on the image frames output by the image sensor.

The frame rate control method adopted in the prior art is to buffer image frames output by an image sensor, and discard image frame data stored in a current buffer queue at a fixed rate when an Fsensor is greater than an Ftarget.

The frame rate control method is suitable for the case that the Fsensor and the Ftarget do not change much. However, in the practical application environment of the camera, there is a high possibility that the exposure time of the image sensor is changed due to the change of the scene, and the change of the exposure time affects the output frame rate Fsensor of the image sensor. In this case, the frame rate control method using frame loss with a fixed rate often causes excessive frame loss. Moreover, when image frame data stored in the cache queue is discarded, if a method of discarding frames at intervals is adopted to discard frames, namely, one frame is discarded every several frames, a large amount of linked list operation is required, and system resource consumption is too large; if the method of continuous frame loss is adopted, the continuity of the image is affected.

Disclosure of Invention

The technical problem to be solved by the present invention is to overcome the shortcomings of the prior art frame rate control method, and to provide a method for controlling the frame rate of an image sensor without causing the frame rate change when the frame rate output by the image sensor and/or the target frame rate change

A real-time frame rate control method and a frame rate control device thereof for preventing frame loss.

In order to solve the above problems, the present invention provides a real-time frame rate control method, which is characterized in that a frame rate control factor FC is periodically updated according to a frame rate control factor update principle, and a frame rate control register is updated by using a frame rate control register value with a length of B, the number of released frame identifiers of which is the same as that of the FC; and sequentially and circularly using each bit of the frame rate control register as a discrimination bit to respectively discriminate each received image frame: when the distinguishing bit corresponding to the image frame is a releasing frame mark, releasing the frame; otherwise, the frame is discarded;

the frame rate control factor updating principle is as follows: using a new frame rate control factor to make the ratio of the new frame rate control factor to B equal to the ratio of Ftarget to Fsensor, or making the ratio of the frame rate control factor to B before updating closer to the ratio of Ftarget to Fsensor; ftarget and Fsensor are respectively a target frame rate and an image sensor output frame rate; the clear frame is identified as either 1 or 0.

In addition, the method comprises a frame rate control register updating process which is executed periodically, and the frame rate control register updating process comprises the following steps:

A) if the frame rate control factor updating condition is met, executing the next step, otherwise, ending the frame rate control register updating process;

B) updating the FC value according to the frame rate control factor updating principle;

C) obtaining a frame rate control register value through table lookup, and enabling the number of released frame identifications contained in the value to be equal to the FC value;

D) updating a frame rate control register by using the value of the frame rate control register;

the frame rate control factor updating condition is one of the following conditions:

1) fsensor × FC/B > Ftarget; or

2) Fsensor × FC/B < Ftarget, and FC < B; or

3) Fcurrent > Ftarget; or

4) Fcurrent < Ftarget, and FC < B; wherein Fcurrent is the release frame rate.

Further, the FC value is updated in said step B) using one of the following equations and a constraint operation:

the formula I is as follows: FC ═ Ftarget × B/Fsensor;

the formula II is as follows: if Fcurrent/Ftarget <1/4, FC is 4 × FC _ OLD;

if 1/4 ≦ Fcurrent/Ftarget <1/2, FC ═ 2 × FC _ OLD;

if 1/2 ≦ Fcurrent/Ftarget <3/4, FC ═ 4/3 × FC _ OLD;

if 3/4 is not more than Fcurrent/Ftarget <1, then FC is FC _ OLD + 1;

if 1< Fcurrent/Ftarget ≦ 4/3, FC — OLD-1;

if 4/3< Fcurrent/Ftarget ≦ 2, FC ═ 3/4 × FC _ OLD;

if 2< Fcurrent/Ftarget ≦ 4, FC — 1/2 × FC _ OLD;

if 4< Fcurrent/Ftarget, FC is 1/4 × FC _ OLD;

wherein, FC _ OLD is a frame rate control factor before updating;

the frame rate control factor obtained by using the above calculation formula is further subjected to the following constraint operation:

if FC > B, let FC be B; if FC <1, let FC be 1; if FC is not an integer, then a round-down operation is performed on it.

In addition, the method comprises a frame rate control flow, and when an image frame is received, the following operations are carried out:

a) judging the discrimination bit of the current frame rate control register: if the distinguishing position is a releasing frame mark, releasing the image frame; otherwise, discarding the image frame;

b) performing cyclic shift operation in a specified direction on the frame rate control register;

the discrimination bit corresponds to the lowest order or the highest order or any other designated position of the frame rate control register.

In addition, the method comprises a frame rate control flow, and when an image frame is received, the following operations are carried out:

a') judging the discrimination bit of the current frame rate control register: if the discrimination bit is the identification of releasing the frame, releasing the frame; otherwise, the frame is discarded;

b') letting counter n be n + 1; performing shift operation in a designated direction on the frame rate control register;

c') if n is greater than B, using the frame rate control backup register to restore the original value of the frame rate control register; let n equal to 1;

the step D) is followed by the following steps: updating a frame rate control backup register using the frame rate control register value; and let n equal to 1;

the distinguishing bit is the lowest bit of the frame rate control register, and the shifting operation is right shifting by 1 bit; or the distinguishing bit is the highest bit of the frame rate control register, and the shifting operation is left shifting by 1 bit.

The present invention also provides a real-time frame rate control apparatus for performing frame rate control on an image frame output from an image sensor, the apparatus comprising: the device comprises a counting unit, a frame rate control factor updating unit, a frame rate control register and a frame rate control unit; wherein,

the statistical unit is used for carrying out real-time statistics on the output frame rate Fsensor of the image sensor;

the frame rate control factor updating unit is used for acquiring the Fsensor value from the counting unit and periodically updating the frame rate control factor FC according to a frame rate control factor updating principle;

the frame rate control register updating unit is used for acquiring an FC value from the frame rate control factor updating unit and updating a frame rate control register by using a frame rate control register value which contains the same number of released frame identifications as the FC and has the length of B;

a frame rate control unit, configured to sequentially and cyclically use each bit of the frame rate control register as a discrimination bit to discriminate each image frame received from the image sensor: when the distinguishing bit corresponding to the image frame is a releasing frame mark, releasing the frame; otherwise, the frame is discarded;

the frame rate control factor updating principle is as follows: using a new frame rate control factor to make the ratio of the new frame rate control factor to B equal to the ratio of Ftarget to Fsensor, or making the ratio of the frame rate control factor to B before updating closer to the ratio of Ftarget to Fsensor; ftarget and Fsensor are respectively a target frame rate and an image sensor output frame rate; the clear frame is identified as either 1 or 0.

In addition, the frame rate control factor updating unit is further configured to determine a frame rate control factor updating condition, and update the FC value when the frame rate control factor updating condition is satisfied; the frame rate control factor updating condition is one of the following conditions:

1) fsensor × FC/B > Ftarget; or

2) Fsensor × FC/B < Ftarget, and FC < B; or

3) Fcurrent > Ftarget; or

4) Fcurrent < Ftarget, and FC < B; wherein, Fcurrent is the output frame rate of the frame rate control unit;

the counting unit is also used for counting the output frame rate Fcurrent of the frame rate control unit in real time.

Further, the frame rate control factor updating unit updates the FC value using one of the following formulas and a constraint operation:

the formula I is as follows: FC ═ Ftarget × B/Fsensor;

the formula II is as follows: if Fcurrent/Ftarget <1/4, FC is 4 × FC _ OLD;

if 1/4 ≦ Fcurrent/Ftarget <1/2, FC ═ 2 × FC _ OLD;

if 1/2 ≦ Fcurrent/Ftarget <3/4, FC ═ 4/3 × FC _ OLD;

if 3/4 is not more than Fcurrent/Ftarget <1, then FC is FC _ OLD + 1;

if 1< Fcurrent/Ftarget ≦ 4/3, FC — OLD-1;

if 4/3< Fcurrent/Ftarget ≦ 2, FC ═ 3/4 × FC _ OLD;

if 2< Fcurrent/Ftarget ≦ 4, FC — 1/2 × FC _ OLD;

if 4< Fcurrent/Ftarget, FC is 1/4 × FC _ OLD;

wherein, FC _ OLD is the frame rate control factor before updating;

the frame rate control factor obtained by using the above calculation formula is further subjected to the following constraint operation:

if FC > B, let FC be B; if FC <1, let FC be 1; if FC is not an integer, then a round-down operation is performed on it.

In addition, the frame rate control unit judges the discrimination bit of the current frame rate control register when receiving an image frame: if the discrimination bit is the identification of releasing the frame, releasing the frame; otherwise, the frame is discarded; after the judgment is finished, the frame rate control register is subjected to cyclic shift operation;

the discrimination bit corresponds to the lowest order or the highest order or any other designated position of the frame rate control register.

In addition, the device also comprises a frame rate control backup register; the frame rate control register updating unit is also used for updating a frame rate control backup register by using the same value when the frame rate control register is updated, and enabling a counter value n to be 1; the frame rate control unit judges the discrimination bit of the current frame rate control register when receiving an image frame: if the discrimination bit is the identification of releasing the frame, releasing the frame; otherwise, the frame is discarded; after the judgment is finished, making n equal to n + 1; shifting the frame rate control register; when n is greater than B, the frame rate control backup register is used for recovering the original value of the frame rate control register, and n is made to be 1;

the distinguishing bit is the lowest bit of the frame rate control register, and the shifting operation is right shifting by 1 bit; or the distinguishing bit is the highest bit of the frame rate control register, and the shifting operation is left shifting by 1 bit.

As can be seen from the above description, the real-time frame rate control method and apparatus of the present invention can always set the image sensor at the operating condition of the maximum frame rate, and adjust the frame passing rate in real time by updating the frame rate control register along with the real-time changes of Fsensor/Fcurrent and Ftarget, thereby achieving the purpose of real-time frame rate control.

Drawings

FIG. 1 is a flowchart illustrating a method for controlling a real-time frame rate according to a first embodiment of the present invention;

FIG. 2 is a flowchart illustrating a real-time frame rate control method according to a second embodiment of the present invention;

fig. 3 is a schematic structural diagram of a real-time frame rate control apparatus according to an embodiment of the invention.

Detailed Description

The basic idea of the present invention is to use a frame rate control register to perform frame rate control on an image output by an image sensor, and update the value of the frame rate control register in real time according to the change of the output frame rate and/or the target frame rate of the image sensor, so as to achieve the purpose of frame rate real-time control.

The real-time frame rate control method according to the present invention will be described in detail with reference to the accompanying drawings and embodiments.

Fig. 1 is a flowchart illustrating a method for controlling a real-time frame rate according to a first embodiment of the present invention. As shown in fig. 1, the method for controlling a real-time frame rate of the present invention includes 3 processes: a statistical process, a frame rate control register updating process and a frame rate control process; each process can be synchronously executed in different threads, and the method specifically comprises the following steps:

and (3) statistical process:

101: counting an output frame rate Fsensor value of the image sensor in real time;

with T as a period, repeatedly executing the following frame rate control register updating process:

102: acquiring and judging whether frame rate control factor updating conditions are met or not according to current values of the Fsensor and the Ftarget, and executing the next step if the frame rate control factor updating conditions are met; otherwise, the frame rate control factor updating process is finished.

In this embodiment, the frame rate control factor updating condition is as follows:

(1) fsensor × FC/B > Ftarget; or

(2) Fsensor × FC/B < Ftarget, and FC < B;

where B is the frame rate control register length (i.e., the number of bits) and FC is the frame rate control factor.

When the system starts up and executes the updating process of the frame rate control register for the first time, the initial value FC of the frame rate control factor is B.

103: updating the frame rate control factor FC, and enabling:

FC＝Ftarget×B/Fsensor；

for the FC calculated by the above formula, the following constraint operations are also required: if FC > B, let FC be B; if FC <1, let FC be 1; if FC is not an integer, then a round-down operation is performed on it.

104: and performing table lookup operation by using the updated frame rate control factor FC, and acquiring a corresponding frame rate control register value FCB from the frame rate control register table.

The first column of the frame rate control register table is a frame rate control factor, and the second column is a frame rate control register value corresponding to the frame rate control factor.

Wherein, each frame rate control register value satisfies the following conditions:

the sum of the number of bits of value 1 (i.e. the sum of the bits of the frame rate control register value) is equal to the corresponding frame rate control factor FC. (3)

The values of the frame rate control registers given in the table are not unique, and other values may be used, but the above condition (3) needs to be satisfied.

The frame rate control register table is as follows, and in this embodiment, B is 64.

FC	FCB	FC	FCB
				1	0x0400 0000 0000 0000	33	0x5555 5555 5555 5557
2	0x0400 0000 0400 0000	34	0x5555 5557 5555 5557
				3	0x0400 0000 0400 0400	35	0x5555 5557 5557 5557
4	0x0400 0400 0400 0400	36	0x5557 5557 5557 5557
				5	0x0400 0400 0400 0404	37	0x5557 5557 5557 5757
6	0x0400 0404 0400 0404	38	0x5557 5757 5557 5757
				7	0x0004 0404 0404 0404	39	0x5557 5757 5757 5757
8	0x0404 0404 0404 0404	40	0x5757 5757 5757 5757
				9	0x0404 0404 0404 0444	41	0x5757 5757 5757 5777
10	0x0404 0444 0404 0444	42	0x5757 5777 5757 5777
				11	0x0404 0444 0444 0444	43	0x5757 5777 5777 5777
12	0x0444 0444 0444 0444	44	0x5777 5777 5777 5777
				13	0x0444 0444 0444 4444	45	0x5777 5777 5777 7777
14	0x0444 4444 0444 4444	46	0x5777 7777 5777 7777
				15	0x0444 4444 4444 4444	47	0x5777 7777 7777 7777
16	0x0444 4444 4444 4444	48	0x7777 7777 7777 7777
				17	0x4444 4444 4444 4444	49	0x7777 7777 7777 777F
18	0x4444 4445 4444 4445	50	0x7777 777F 7777 777F
				19	0x4444 4445 4445 4445	51	0x7777 777F 777F 777F
20	0x4445 4445 4445 4445	52	0x777F 777F 777F 777F
				21	0x4445 4445 4445 4545	53	0x777F 777F 777F 7F7F
22	0x4445 4545 4445 4545	54	0x777F 7F7F 777F 7F7F
				23	0x4445 4545 4545 4545	55	0x777F 7F7F 7F7F 7F7F
24	0x4545 4545 4545 4545	56	0x7F7F 7F7F 7F7F 7F7F
				25	0x4545 4545 4545 4555	57	0x7F7F 7F7F 7F7F 7FFF
26	0x4545 4555 4545 4555	58	0x7F7F 7FFF 7F7F 7FFF
				27	0x4545 4555 4555 4555	59	0x7F7F 7FFF 7FFF 7FFF
28	0x4555 4555 4555 4555	60	0x7FFF 7FFF 7FFF 7FFF
				29	0x4555 4555 4555 5555	61	0x7FFF 7FFF 7FFF FFFF
30	0x4555 5555 4555 5555	62	0x7FFF FFFF 7FFF FFFF
				31	0x4555 5555 5555 5555	63	0x7FFF FFFF FFFF FFFF
32	0x5555 5555 5555 5555	64	0xFFFF FFFF FFFF FFFF

Table 1: frame rate control register table

105: and updating the frame rate control register and the frame rate control backup register by using the FCB value, and enabling a counter n to be 1.

And finishing the updating process of the frame rate control register. It should be noted that, for the repeated execution period T of the update process of the frame rate control register, if the value of T is too small, the value of the frame rate control register may be updated too frequently, which increases the resource consumption of the system; if the value of T is too large, the precision of frame rate control is reduced, and the real-time performance of the frame rate control is poor. The value of T is typically at least greater than the time required for the image sensor to output a B frame. In this example, T is 2 seconds.

When a new image frame output by the image sensor is received, the following frame rate control flow is executed:

106: judging the specific judgment bit of the current frame rate control register, and if the judgment bit value is 1, executing step 107; if the determination bit value is 0, go to step 108;

in this embodiment, the determination Bit is the Least Significant Bit (LSB) of the frame rate control register.

107: the currently received image frame is released, namely the image frame is output to an image processing module for further processing; jumping to 109;

108: discarding a currently received image frame;

109: making a counter n equal to n + 1; the frame rate control register is shifted to the right by one bit;

110: if n is greater than B, executing the next step; otherwise, the flow is finished;

111: restoring the original value of the frame rate control register by using a frame rate control backup register; let n equal 1.

Because the ratio of the total number of bits of the frame rate control register value with the median of 1 to the total number of bits (length) of the frame rate control register value is the frame passing rate used by the frame rate control method, the frame rate control register value, i.e. the frame passing rate, can be adjusted in real time according to the change of the Fsensor and/or the Ftarget by repeatedly executing the updating process of the frame rate control register with the period of T; in the frame rate control process, the received new image frame is determined to be discarded or released according to the lowest bit of the current frame rate control register, and the frame rate control register is shifted to the right by one bit; when the number of the received image frames is larger than the number of bits of the frame rate control register, the original value of the frame rate control register is recovered and reused.

In addition, if the bit distribution of the value 1/0 is not uniform, the frame rate control register may cause continuous frame loss, which may affect the continuity of the image to some extent. For example, if the upper 32 bits of the frame rate control register value are 1 and the lower 32 bits are 0, 32 frames will be continuously discarded after the frame rate control register is updated by using the value, which has a certain influence on the continuity of the image. If the frame rate control register value is set to 101010.. which contains 32 binary values of 1, the continuity of the image will be guaranteed. Therefore, it is preferable that each frame rate control register value in the frame rate control register table satisfies the uniformity distribution requirement in addition to the condition (3). If the frame rate control register value meeting the requirement of uniformity distribution is used, the problem that continuous frame loss affects the image quality can be avoided.

Fig. 2 is a flowchart of a method for controlling a real-time frame rate according to a second embodiment of the present invention. As shown in fig. 2, the real-time control of the frame rate includes the following steps:

and (3) statistical process:

201: counting the Fcurrent value of the actual output frame rate (namely the release frame rate of the frame rate control unit) in real time;

the actual output frame rate is the frame rate of the released image frame after frame rate control.

And repeatedly executing the updating process of the frame rate control register by taking T as a period:

202: judging whether a frame rate control factor updating condition is met, if so, executing the next step; otherwise, the frame rate control factor updating process is finished.

In this embodiment, the frame rate control factor updating condition is as follows:

(4) fcurrent > Ftarget; or

(5) Fcurrent < Ftarget, and FC < B;

203: updating a frame rate control factor;

note that the current frame rate control factor is FC _ OLD,

if Fcurrent/Ftarget <1/4, FC is 4 × FC _ OLD;

if 1/4 ≦ Fcurrent/Ftarget <1/2, FC ═ 2 × FC _ OLD;

if 1/2 ≦ Fcurrent/Ftarget <3/4, FC ═ 4/3 × FC _ OLD;

if 3/4 is not more than Fcurrent/Ftarget <1, then FC is FC _ OLD + 1;

if 1< Fcurrent/Ftarget ≦ 4/3, FC — OLD-1;

if 4/3< Fcurrent/Ftarget ≦ 2, FC ═ 3/4 × FC _ OLD;

if 2< Fcurrent/Ftarget ≦ 4, FC — 1/2 × FC _ OLD;

if 4< Fcurrent/Ftarget, FC is 1/4 × FC _ OLD.

If FC > B is calculated according to the formula, making FC equal to B; if FC <1, let FC be 1; if FC is not an integer, then a round-down operation is performed on it.

The above method for updating the frame rate control factor adopts a section updating method, that is, when the comparison relationship between fcurrent and ftarget is in a certain section, FC _ OLD is used to update FC according to a corresponding formula. It should be noted that the interval used for updating the frame rate control factor and the corresponding calculation formula are not unique, and may be adjusted according to the actual situation of the system.

Note that although the update formula of the frame rate control factor used in the present embodiment is greatly different in form as compared with the first embodiment, their purpose is completely the same. The analysis was as follows:

since Fcurrent ≈ Fsensor × FC _ OLD/B,

branching: if Fcurrent/Ftarget <1/4, FC is 4 × FC _ OLD; for example, the update formula branch becomes:

if FC _ OLD/B <1/4 × fttarget/Fsensor, FC is 4 × FC _ OLD, that is, when the FC _ OLD/B value is too small, a new FC is used so as to satisfy:

FC/B<Ftarget/Fsensor。

the update formula of the first embodiment is: FC ═ Ftarget × B/Fsensor, that is, the new FC satisfies:

FC/B＝Ftarget/Fsensor。

that is, the update principle of FC is: the new frame rate control factor is used such that its ratio to B is closer to or equal to the ratio of Ftarget to Fsensor than the frame rate control factor used previously.

204: and performing table lookup operation by using the updated frame rate control factor FC, and acquiring a corresponding frame rate control register value FCB from the frame rate control register table.

205: updating a frame rate control register using the FCB value;

when a new image frame output by the image sensor is received, the following frame rate control flow is executed:

206: judging the specific judgment bit of the current frame rate control register, and if the judgment bit value is 1, executing step 207; if the determination bit value is 0, go to step 208;

the decision bit may be the lowest order bit, the highest order bit or any other designated bit of the frame rate control register.

207: the currently received image frame is released, namely, the image frame is sent to an image processing module for processing;

208: discarding a currently received image frame;

209: performing cyclic shift operation on the frame rate control register;

in this embodiment, the frame rate control register is a ring shift register, and the circular shift operation is to shift a bit left/right and place the shifted bit into the lowest bit/highest bit (MSB) of the frame rate control register. Of course, the circular shift operation can be performed using any register.

The operation of adding 1 to the counter in step 109 and the operation of restoring the original value of the frame rate control register in steps 110 and 111 in the first embodiment can be omitted by performing the circular shift operation.

Based on the basic principle of the present invention, the present invention can also be changed based on the above-mentioned embodiments, for example:

using the most significant bit of the frame rate control register as a decision bit in step 106, while shifting the frame rate control register one bit to the left in step 109;

in addition, in the above embodiment, 1 is used as the release frame identifier, 0 is used as the discard frame identifier, and when the determination bit of the frame rate control register is 1, the current frame is released; 0 may also be used as a clear frame identification. Meanwhile, each frame rate control register value in the frame rate control register table should be modified correspondingly, and the condition (3) should also be modified as follows: the sum of the number of bits with a value of 0 is equal to the corresponding frame rate control factor FC.

The present invention will be described in detail with reference to the accompanying drawings and embodiments.

Fig. 3 is a schematic structural diagram of a real-time frame rate control apparatus according to an embodiment of the invention. As shown in fig. 3, the real-time frame rate control apparatus for performing frame rate control on an image frame output from an image sensor includes: the device comprises a counting unit, a frame rate control factor updating unit, a frame rate control register, a frame rate control backup register and a frame rate control unit. Wherein,

a counting unit for counting the output frame rate Fsensor value of the image sensor and the output frame rate Fcurrent value of the frame rate control unit in real time;

the frame rate control factor updating unit is used for acquiring the Fsensor value from the counting unit, judging the updating condition of the frame rate control factor and updating the FC value when the updating condition of the frame rate control factor is met;

the frame rate control factor updating condition is one of the following conditions:

1) fsensor × FC/B > Ftarget; or

2) Fsensor × FC/B < Ftarget, and FC < B; or

3) Fcurrent > Ftarget; or

4) Fcurrent < Ftarget, and FC < B;

further, the frame rate control factor updating unit updates FC using the formula and the constraint operation in step 103 or step 203.

A frame rate control register updating unit, configured to obtain an FC value from the frame rate control factor updating unit, update the frame rate control register and the frame rate control backup register using a frame rate control register value with a length of B, where the number of released frame identifiers is the same as that of FC, and simultaneously set a counter value n to 1;

the frame rate control unit is used for judging the distinguishing bit of the current frame rate control register when receiving an image frame: if the discrimination bit is the identification of releasing the frame, releasing the frame; otherwise, the frame is discarded; after the judgment is finished, the frame rate control register is subjected to cyclic shift operation;

in another embodiment, the frame rate control unit is configured to determine the decision bit of the current frame rate control register when an image frame is received: if the discrimination bit is the identification of releasing the frame, releasing the frame; otherwise, the frame is discarded; after the judgment is finished, making n equal to n + 1; shifting the frame rate control register; and when n > B, restoring the original value of the frame rate control register by using the frame rate control backup register, and enabling n to be 1.

Claims (10)

1. A real-time frame rate control method is characterized in that a frame rate control factor FC is periodically updated according to a frame rate control factor updating principle, and a frame rate control register is updated by using a frame rate control register value which contains the same number of released frame identifications as the FC and has the length of B; and sequentially and circularly using each bit of the frame rate control register as a discrimination bit to respectively discriminate each received image frame: when the distinguishing bit corresponding to the image frame is a releasing frame mark, releasing the frame; otherwise, the frame is discarded;

the frame rate control factor updating principle is as follows: using a new frame rate control factor to make the ratio of the new frame rate control factor to B equal to the ratio of Ftarget to Fsensor, or making the ratio of the frame rate control factor to B before updating closer to the ratio of Ftarget to Fsensor; ftarget and Fsensor are respectively a target frame rate and an image sensor output frame rate; the clear frame is identified as either 1 or 0.

2. The method as claimed in claim 1, wherein the method comprises a frame rate control register update procedure performed periodically, the frame rate control register update procedure comprises the following steps:

A) if the frame rate control factor updating condition is met, executing the next step, otherwise, ending the frame rate control register updating process;

B) updating the FC value according to the frame rate control factor updating principle;

C) obtaining a frame rate control register value through table lookup, and enabling the number of released frame identifications contained in the value to be equal to the FC value;

D) updating a frame rate control register by using the value of the frame rate control register;

the frame rate control factor updating condition is one of the following conditions:

1) fsensor × FC/B > Ftarget; or

2) Fsensor × FC/B < Ftarget, and FC < B; or

3) Fcurrent > Ftarget; or

4) Fcurrent < Ftarget, and FC < B; wherein Fcurrent is the release frame rate.

3. The real time frame rate control method as claimed in claim 2, wherein the FC value is updated in the step B) using one of the following formulas and a constraint operation:

the formula I is as follows: FC ═ Ftarget × B/Fsensor;

the formula II is as follows: if Fcurrent/Ftarget <1/4, FC is 4 × FC _ OLD;

if 1/4 ≦ Fcurrent/Ftarget <1/2, FC ═ 2 × FC _ OLD;

if 1/2 ≦ Fcurrent/Ftarget <3/4, FC ═ 4/3 × FC _ OLD;

if 3/4 is not more than Fcurrent/Ftarget <1, then FC is FC _ OLD + 1;

if 1< Fcurrent/Ftarget ≦ 4/3, FC — OLD-1;

if 4/3< Fcurrent/Ftarget ≦ 2, FC ═ 3/4 × FC _ OLD;

if 2< Fcurrent/Ftarget ≦ 4, FC — 1/2 × FC _ OLD;

if 4< Fcurrent/Ftarget, FC is 1/4 × FC _ OLD;

wherein, FC _ OLD is a frame rate control factor before updating;

the frame rate control factor obtained by using the above calculation formula is further subjected to the following constraint operation:

if FC > B, let FC be B; if FC <1, let FC be 1; if FC is not an integer, then a round-down operation is performed on it.

4. The method as claimed in claim 1, wherein the method comprises a frame rate control process, when an image frame is received, performing the following operations:

a) judging the discrimination bit of the current frame rate control register: if the distinguishing position is a releasing frame mark, releasing the image frame; otherwise, discarding the image frame;

b) performing cyclic shift operation in a specified direction on the frame rate control register;

the discrimination bit corresponds to the lowest order or the highest order or any other designated position of the frame rate control register.

5. The method as claimed in claim 2, wherein the method comprises a frame rate control process, when an image frame is received, performing the following operations:

a') judging the discrimination bit of the current frame rate control register: if the discrimination bit is the identification of releasing the frame, releasing the frame; otherwise, the frame is discarded;

b') letting counter n be n + 1; performing shift operation in a designated direction on the frame rate control register;

c') if n is greater than B, using the frame rate control backup register to restore the original value of the frame rate control register; let n equal to 1;

the step D) is followed by the following steps: updating a frame rate control backup register using the frame rate control register value; and let n equal to 1;

the distinguishing bit is the lowest bit of the frame rate control register, and the shifting operation is right shifting by 1 bit; or the distinguishing bit is the highest bit of the frame rate control register, and the shifting operation is left shifting by 1 bit.

6. A real-time frame rate control apparatus for performing frame rate control on an image frame output from an image sensor, the apparatus comprising: the device comprises a counting unit, a frame rate control factor updating unit, a frame rate control register and a frame rate control unit; wherein,

the statistical unit is used for carrying out real-time statistics on the output frame rate Fsensor of the image sensor;

the frame rate control factor updating unit is used for acquiring the Fsensor value from the counting unit and periodically updating the frame rate control factor FC according to a frame rate control factor updating principle;

the frame rate control register updating unit is used for acquiring an FC value from the frame rate control factor updating unit and updating a frame rate control register by using a frame rate control register value which contains the same number of released frame identifications as the FC and has the length of B;

a frame rate control unit, configured to sequentially and cyclically use each bit of the frame rate control register as a discrimination bit to discriminate each image frame received from the image sensor: when the distinguishing bit corresponding to the image frame is a releasing frame mark, releasing the frame; otherwise, the frame is discarded;

the frame rate control factor updating principle is as follows: using a new frame rate control factor to make the ratio of the new frame rate control factor to B equal to the ratio of Ftarget to Fsensor, or making the ratio of the frame rate control factor to B before updating closer to the ratio of Ftarget to Fsensor; ftarget and Fsensor are respectively a target frame rate and an image sensor output frame rate; the clear frame is identified as either 1 or 0.

7. The apparatus of claim 6, wherein the frame rate control factor updating unit is further configured to determine a frame rate control factor updating condition, and update the FC value when the frame rate control factor updating condition is satisfied; the frame rate control factor updating condition is one of the following conditions:

1) fsensor × FC/B > Ftarget; or

2) Fsensor × FC/B < Ftarget, and FC < B; or

3) Fcurrent > Ftarget; or

4) Fcurrent < Ftarget, and FC < B; wherein, Fcurrent is the output frame rate of the frame rate control unit;

the counting unit is also used for counting the output frame rate Fcurrent of the frame rate control unit in real time.

8. The apparatus of claim 7, wherein the frame rate control factor updating unit updates the FC value using a constraint operation and one of the following formulas:

the formula I is as follows: FC ═ Ftarget × B/Fsensor;

the formula II is as follows: if Fcurrent/Ftarget <1/4, FC is 4 × FC _ OLD;

if 1/4 ≦ Fcurrent/Ftarget <1/2, FC ═ 2 × FC _ OLD;

if 1/2 ≦ Fcurrent/Ftarget <3/4, FC ═ 4/3 × FC _ OLD;

if 3/4 is not more than Fcurrent/Ftarget <1, then FC is FC _ OLD + 1;

if 1< Fcurrent/Ftarget ≦ 4/3, FC — OLD-1;

if 4/3< Fcurrent/Ftarget ≦ 2, FC ═ 3/4 × FC _ OLD;

if 2< Fcurrent/Ftarget ≦ 4, FC — 1/2 × FC _ OLD;

if 4< Fcurrent/Ftarget, FC is 1/4 × FC _ OLD;

wherein, FC _ OLD is the frame rate control factor before updating;

the frame rate control factor obtained by using the above calculation formula is further subjected to the following constraint operation:

if FC > B, let FC be B; if FC <1, let FC be 1; if FC is not an integer, then a round-down operation is performed on it.

9. The apparatus of claim 6, wherein the frame rate control unit determines the decision bit of the current frame rate control register when receiving an image frame: if the discrimination bit is the identification of releasing the frame, releasing the frame; otherwise, the frame is discarded; after the judgment is finished, the frame rate control register is subjected to cyclic shift operation;

the discrimination bit corresponds to the lowest order or the highest order or any other designated position of the frame rate control register.

10. The apparatus of claim 6, further comprising a frame rate control backup register; the frame rate control register updating unit is also used for updating a frame rate control backup register by using the same value when the frame rate control register is updated, and enabling a counter value n to be 1; the frame rate control unit judges the discrimination bit of the current frame rate control register when receiving an image frame: if the discrimination bit is the identification of releasing the frame, releasing the frame; otherwise, the frame is discarded; after the judgment is finished, making n equal to n + 1; shifting the frame rate control register; when n is greater than B, the frame rate control backup register is used for recovering the original value of the frame rate control register, and n is made to be 1;

the distinguishing bit is the lowest bit of the frame rate control register, and the shifting operation is right shifting by 1 bit; or the distinguishing bit is the highest bit of the frame rate control register, and the shifting operation is left shifting by 1 bit.

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