CN100533521C - Display system line extraction abnormal display cancelling method and its circuit - Google Patents
Display system line extraction abnormal display cancelling method and its circuit Download PDFInfo
- Publication number
- CN100533521C CN100533521C CNB2006101630013A CN200610163001A CN100533521C CN 100533521 C CN100533521 C CN 100533521C CN B2006101630013 A CNB2006101630013 A CN B2006101630013A CN 200610163001 A CN200610163001 A CN 200610163001A CN 100533521 C CN100533521 C CN 100533521C
- Authority
- CN
- China
- Prior art keywords
- display
- circuit
- line
- signal
- display system
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention relates to a method for eliminating the abnormal display of the thread drawing phenomenon for a display system and a circuit thereof, which comprise the following steps: an image data line is input into a driving circuit and the driving circuit grasps the image data line to be deleted and the time pulse signal displayed by the image data line to be deleted on a display is eliminated; the circuit enables the signal for a grid driving integrated circuit to which a control switching element corresponds. The invention utilizes the driving circuit to generate a control waveform so as to effectively eliminate a plurality of displayed data lines, thereby converting the format of an image system into the format of another different image system. The invention can effectively reduce the interference caused by the grounding disturbance of the circuit and ensure that the panel avoids generating the bad phenomenon after the thread drawing.
Description
Technical field
The present invention relates to a kind of line extraction abnormal display cancelling method and circuit thereof of abnormal show removing method and circuit thereof, particularly a kind of display system of display system.
Background technology
The simulated data form that drive system received of flat display panel front end is the data layout of television system, the reception interface of its analog signal is generally AV terminal (YC mixes signal) and S terminal (YC separates signal), and the data layout that present television system is suitable for has three kinds of international standards, National Television System Committee (NTSC) (National Television StandardsCommittee, NTSC), sweep trace phase cross-over (Phase Alternating Line, PAL) and color in proper order with the memory (Sequential Color Avec Memory, SECAM).
Front-end driven system in the small-medium size flat-panel screens supports NTSC and two kinds of transmission standards of PAL more, the NTSC system transmits 30 picture frames (frame) in per second, scheme (field) for totally 60,525 data lines of each picture frame, that is 262.5 data lines in each figure field, odd number and even data line transmit with interlace mode; And the PAL system transmits 25 picture frames in per second, totally 50 figure, and 625 data lines of each picture frame, that is 312.5 data lines in each figure field, odd number and even data line also transmit with interlace mode.
In the known technology, one sequential control circuit (Timing Controller) is arranged in the driving circuit of flat display panel front end, it can decipher the data layout of television system the valid data of back gained at the process decoding scheme, reasonably be distributed on the panel, the data (simulated data) that also are exactly on the axle sometime are dispensed to (panel demonstration) on another time shaft.See also shown in the 1st figure, sequential control circuit with the data allocations of analog signal to the resolution panel of 480*234, when simulation system is the NTSC system, 262.5 data lines in each figure field, sequential control circuit is got wherein effective 240 data lines and is delivered to panel on each odd number and even number picture frame, and cooperate simulated panel in grid-driving integrated circuit (Gate IC) last 3 and following 3 design rules that do not connect, correctly demonstrate 234 vertical resolution, and the frequency of panel video data is 60Hz, so the video data of simulated panel is to become picture frame to show the figure field stimulation, therefore not being applied in needs to show highdensity literal field, as information display.
In addition, when front end system is the PAL system, according to normal design, its control integrated circuit need be different from the allocation scheme of NTSC system in addition, but for the NTSC/PAL system compatibility and save the calculation core logic door of integrated circuit, and the time of every data line of PAL system be 64 μ s, with every the data line times 63.49 μ s of NTSC system much at one, therefore the quickest and easy method is exactly that the data that will transmit in the PAL system extract 100, that is each figure field extracts 50.Therefore when the simulated panel front end system switches to the PAL system by the NTSC system, must take out line, and the frequency of panel video data can be reduced to 50Hz.
Please refer to Fig. 2 A and be the sequential chart under the demonstration of NTSC pattern, and Fig. 2 B is the known sequential chart that is switched to the controlling signal variation of PAL pattern by Fig. 2 A, by two figure as can be known in the time will extracting data H9, can be with controlling signal (the Source IC Start Pulse of these data, STH) eliminate, and send controlling signal (the Output Enable Input For DataDriver of last data H8, OEH) postpone, and the grid-driving integrated circuit that will control last data H8 correspondence is opened signal CLKV (Gate IC Clock) and is also eliminated, then data H9 can be not crawled and can not be presented on the panel, last data H8 can delay demonstration, and the data line that also is about to the H9 representative extracts.
Known, the framework that above-mentioned data line extracts the analog source electrode drive integrated circult (Source IC) of method in driving circuit as shown in Figure 3, comprise bit shift register (Shift Register) 03, analog sample and holding circuit 02 and output buffer 01, the charge-discharge system of equivalent electrical circuit shown in Fig. 4 A and Fig. 4 B of its output terminal action.Mutual exclusion switch SW 1 and SW2 in CPH (Sampling And ShiftingClock Pulse For Data Driver) the signal controlling analog sampling circuit, when 1 conducting of mutual exclusion switch SW, analog source electrode drive integrated circult sampling (sampling) n bar data, data voltage also begins inner capacitor C 1 charging, and its charging size is according to the relation decision of the data signals DATA and the ground connection signal AVSS (Ground ForAnalog Circuit) of sampling; At this moment, n-1 data voltage on the capacitor C 2 keeps (holding) to live originally, and inputs to unity gain operational amplifier 102, via 100 chargings of 102 pairs of pixel electrodes of unity gain operational amplifier; When output enable OE (Output Enable) signal is controlled outside switch (Switch) switching, mutual exclusion switch SW 2 conductings in the analog source electrode drive integrated circult, n+1 the data voltage of then taking a sample, and to capacitor C 2 chargings, at this moment, n data voltage on the capacitor C 1 maintains originally, and inputs to unity gain operational amplifier 102, via 100 chargings of 102 pairs of pixel electrodes of unity gain operational amplifier, export n bar data.
According to above-mentioned, its action of taking out line is shown in Fig. 5 A and Fig. 5 B; As shown in FIG., when mutual exclusion switch SW 22 conductings in the CPH signal controlling analog sampling circuit, the data voltage of sampling video data H7, at this moment, the data voltage of video data H6 on the capacitor C 11 is held, and input to unity gain operational amplifier 202, and via 200 chargings of 202 pairs of pixel electrodes of unity gain operational amplifier, output video data H6; When output enable OE signal is controlled outside switch and is switched, mutual exclusion switch SW 21 conductings in the analog source electrode drive integrated circult, then the take a sample data voltage of video data H8, and to capacitor C 11 chargings, at this moment, the data voltage of the video data H7 on the capacitor C 21 maintains originally, and inputs to unity gain operational amplifier 202, via 200 chargings of 202 pairs of pixel electrodes of unity gain operational amplifier, output video data H7; Then, in order to extract video data H9, output enable OE signal remains unchanged, outside switch is failure to actuate, understandable, the mutual exclusion switch SW 21 of this moment is kept conducting, continue the data voltage of sampling video data H8, and to capacitor C 21 lasting chargings, at this moment, the data voltage of the video data H7 of script is repeated to maintain on the capacitor C 21, and repeat pixel electrode 200 chargings, to continue output video data H7, pass through up to the video data H9 that desires to extract, regular event is replied by output enable OE signal side.That is to say, it is that preceding data H8 of the data of desiring to extract delayed demonstration that sequential control circuit is taken out the line algorithm, that is the data that equal to extract in advance show after passing through again, when preceding data desiring to extract data are delayed video data H8, signal AVSS disturbance promptly can impact the voltage of sampling, because it is of a specified duration that the voltage of this data line is retained in other data line of time ratio of circuit, signal AVSS disturbance promptly can cause bigger influence to the voltage of this line, make the lines of taking out the line position obviously differ from other lines, cause display frame unusual, as shown in Figure 6.
Summary of the invention
In order to address the above problem, one of the object of the invention is to provide a kind of line extraction abnormal display cancelling method and circuit thereof of display system, between the different images display system, utilize analog drive circuit to produce control waveform, effectively several video data lines are extracted, so the format conversion of an image system can be become the form of another different image system.
One of the object of the invention is that the time pulse signal that the image data line is presented on the display is eliminated, and the image data line that delete is driven can be presented on the display module of display after circuit grasps, and also is about to this data line and takes out.
One of the object of the invention is in the analog drive circuit of display, can not be retained in the source electrode driven integrated circuit behind the image data line that extraction will be deleted, and keep the duration of charging of each this image data line identical, and the line inversion driving pattern of this display, effectively reduce the interference of circuit ground disturbance, make panel avoid producing to take out the bad phenomenon behind the line.
In order to achieve the above object, the line extraction abnormal display cancelling method of the display system of one embodiment of the invention comprises: many image data lines are inputed to one drive circuit; Driving circuit grasps the first image data line that will delete; Elimination is presented at time pulse signal on the display with the first image data line, and time pulse signal is opened signal for the pairing grid-driving integrated circuit of on-off element element of the control first image data line; Making the output enable input scan drive signal (OEV) changes identical with the duration of charging that keeps each image data line; Making common electrode drive signal (VCOM) changes to keep the line inversion driving pattern of display with data signals; And continue to grasp the second image data line that to delete and the step of repeated elimination time pulse signal.
In order to achieve the above object, the line phenomenon abnormal show of taking out of the display system of one embodiment of the invention is eliminated circuit, comprises: a videl signal code translator, and in order to receiving a videl signal, and this videl signal of data decoding; Time schedule controller is in order to produce an one source pole drive integrated circult controlling signal and a grid-driving integrated circuit controlling signal; One parameter selector is in order to provide the videl signal code translator a plurality of decoding parameters; One phase-locked loop provides time schedule controller a required system frequency; And one direct current/DC converting circuit, provide the line phenomenon abnormal show of taking out of display system to eliminate circuit one working power.
By above-mentioned technical characterictic, beneficial effect of the present invention shows as: when switching the PAL system model, control waveform after the compensation can grasp the data of desiring to take out as usual, the last data that extracted that do not show, so not having any data can be retained in the source electrode driven integrated circuit and just lose with the time of waiting for a line, effectively reduce the interference of circuit ground signal (AVSS) disturbance, make panel avoid producing to take out the bad phenomenon behind the line.
Below the accompanying drawing shown in cooperating by specific embodiment illustrate in detail, when the purpose that is easier to understand this creation, technology contents, characteristics and the effect reached thereof.
Description of drawings
Figure 1 shows that the image data of known NTSC system is dispensed to the synoptic diagram of 480*234 resolution panel.
Fig. 2 A is the sequential chart under known ntsc mode shows.
The sequential chart that Fig. 2 B changes for the controlling signal that is switched to the PAL system model by Fig. 2 A.
Figure 3 shows that the configuration diagram of known analog source electrode driven integrated circuit circuit.
Fig. 4 A and Fig. 4 B are depicted as the equivalent electrical circuit of the output terminal action of Fig. 3.
Fig. 5 A and Fig. 5 B are depicted as the action that known source electrode driven integrated circuit is taken out line.
Figure 6 shows that the known caused picture abnormal show of the line technology figure that takes out.
The image data that Figure 7 shows that one embodiment of the invention display is taken out line method.
Figure 8 shows that analog drive circuit used in the present invention.
Figure 9 shows that drive waveforms of the present invention.
Symbol description among the figure
01 output buffer
02 analog sample and holding circuit
03 bit shift register
10 analog drive circuits
11 videl signal code translators
12 time schedule controllers
13 phase-locked loops
14 parameter selectors
15 DC/DC conversion circuit
16 panel modules
100,200 pixel electrodes
102,202 unity gain operational amplifiers
S11 imports the data line of an image signal to one drive circuit
The S12 driving circuit grasps the image data line of desire deletion
S13 eliminates the time pulse signal of image data displaying
S14 grasps next image data line
S15 image output signal is to display
Embodiment
The image data that Figure 7 shows that one embodiment of the invention display is taken out line method, and its step comprises: step S11 inputs to one drive circuit with the data line of an image signal, and the analog drive circuit in the display receives the image signal of a PAL form; Step S12 driving circuit grasps the image data line that will delete, has more several image data lines because of the PAL system transmits the image data line than NTSC system, so must calculate extra image data line; Step S13 eliminates extra image data line is presented at time pulse signal on the display, the waveform of driving circuit utilization control time pulse signal and eliminate extra image data line is presented at time pulse signal on the display, and this clock pulse signal is opened signal for the pairing grid-driving integrated circuit of on-off element of control image data line; The next image data line that will delete of step S14 continuation extracting and repeating step S13 are to the image data line of the last item desire deletion; And step S15 the image output signal is to display in regular turn at last, display is a flat-panel screens.
According to above-mentioned, eliminate the image data line be presented on this display time pulse signal simultaneously, the output enable input scan is driven signal (Output Enable Input For Scan Driver, OEV) variation is identical with the duration of charging that keeps each image data line, and (Common Electrode Driving Signal VCOM) changes to keep the line inversion driving pattern of display with data (DATA) signal to make common electrode drive signal.
In addition, when the input end of flat-panel screens receives the television signal of PAL system, take out the line bad phenomenon in order to improve, the present invention utilizes the method for drive controlling waveform to eliminate this phenomenon, the system architecture of its generation drive controlling waveform as shown in Figure 8, it is an analog drive circuit 10, comprises: a videl signal code translator 11 (Video Decoder) can be used for the data decoding of videl signal, and can receive a normal video signal; Time schedule controller 12 produces required source electrode driven integrated circuit and the grid-driving integrated circuit controlling signal of panel; One parameter selector 14 (Parameter Selector) provides videl signal code translator 11 in the required decoding parameter of different video system; One phase-locked loop 13 (Phase Locked Loop circuit, PLL circuit) provides time schedule controller 12 required system frequency; And one direct current/DC converting circuit 15 provides total system and panel module 16 required working power; Wherein, flat-panel screens can be light emitting diode (Light Emitting Diode, LED) display, rear-projection display device (LiquidCrystal on Silicon, LCoS), LCD (Liquid Crystal Display, LCD), plasma display (Plasma Display Panel, PDP) or organic electro-luminescent display (Organic Light Emitting Diode, OLED).
Moreover, the present invention is applied to compensate the sequential of taking out behind the line with the time schedule controller control waveform, make drive waveforms as shown in Figure 9, in the time data H8 will being extracted, the time pulse signal CLKV that the grid-driving integrated circuit of these data of control H8 correspondence is opened signal eliminates, then data H8 can want data presented the same as system grabs with other, but different with other data is that data H8 can not shown by panel, also being about to these data takes out, the output enable input scan drives the variation of signal OEV then for keeping the duration of charging unanimity of every data line, and the variation that common electrode drives signal VCOM and data signals DATA then is the line inversion driving pattern that keeps panel.
Comprehensively above-mentioned, the present invention is when switching the PAL system model, control waveform after the compensation can grasp the data of desiring to take out as usual, the last data that extracted that do not show, so not having any data can be retained in the source electrode driven integrated circuit and just lose with the time of waiting for a line, effectively reduce the interference of circuit ground signal (AVSS) disturbance, make panel avoid producing to take out the bad phenomenon behind the line.
Above-described embodiment only is explanation technological thought of the present invention and characteristics, its purpose makes the personage who has the knack of this skill can understand content of the present invention and is implementing according to this, when can not with qualification claim of the present invention, promptly the equalization of doing according to disclosed spirit generally changes or modifies, and must be encompassed in the claim of the present invention.
Claims (11)
1. the line extraction abnormal display cancelling method of a display system comprises:
Many image data lines are inputed to one drive circuit;
This driving circuit grasps the first image data line that will delete;
Elimination is presented at time pulse signal on the display with this first image data line, and this time pulse signal is opened signal for the pairing grid-driving integrated circuit of on-off element of this first image data line of control;
Make the output enable input scan drive signal and change, identical with the duration of charging that keeps each this image data line;
Common electrode driving signal and data signals are changed to keep the line inversion driving pattern of this display; And
The second image data line that the continuation extracting will be deleted and the step of this time pulse signal of repeated elimination.
2. the line extraction abnormal display cancelling method of display system as claimed in claim 1, wherein said image data line is the image scan line that sweep trace phase cross-over system is exported.
3. the line extraction abnormal display cancelling method of display system as claimed in claim 1, wherein this driving circuit is controlled the waveform of this time pulse signal and is eliminated this first image data line is presented at action on the display.
4. the line extraction abnormal display cancelling method of display system as claimed in claim 1 more comprises the image signal of last output one system format.
5. the line extraction abnormal display cancelling method of display system as claimed in claim 4, wherein this system format is NTSC's ntsc format.
6. the line extraction abnormal display cancelling method of display system as claimed in claim 1, wherein this display system is a flat-panel screens.
7. the line extraction abnormal display cancelling method of display system as claimed in claim 6, wherein this flat-panel screens is light emitting diode indicator, rear-projection display device, LCD, plasma display or organic electro-luminescent display.
8. the line phenomenon abnormal show of taking out of a display system is eliminated circuit, comprises:
One videl signal code translator, in order to receiving a videl signal, and this videl signal of data decoding;
Time schedule controller is in order to produce an one source pole drive integrated circult controlling signal and a grid-driving integrated circuit controlling signal;
One parameter selector is in order to provide this videl signal code translator a plurality of decoding parameters;
One phase-locked loop provides this time schedule controller a required system frequency; And
One direct current/DC converting circuit provides the working power that line phenomenon abnormal show is eliminated circuit of taking out of this display system.
9. the line phenomenon abnormal show of taking out of display system as claimed in claim 8 is eliminated circuit, and wherein this display system is a flat-panel screens.
10. the line phenomenon abnormal show of taking out of display system as claimed in claim 9 is eliminated circuit, and wherein this flat-panel screens is light emitting diode indicator, rear-projection display device, LCD, plasma display or organic electro-luminescent display.
11. the line phenomenon abnormal show of taking out of display system as claimed in claim 8 is eliminated circuit, wherein this DC/DC conversion circuit more can provide the working power of this display system.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101630013A CN100533521C (en) | 2006-11-28 | 2006-11-28 | Display system line extraction abnormal display cancelling method and its circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101630013A CN100533521C (en) | 2006-11-28 | 2006-11-28 | Display system line extraction abnormal display cancelling method and its circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101192363A CN101192363A (en) | 2008-06-04 |
| CN100533521C true CN100533521C (en) | 2009-08-26 |
Family
ID=39487323
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006101630013A Expired - Fee Related CN100533521C (en) | 2006-11-28 | 2006-11-28 | Display system line extraction abnormal display cancelling method and its circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100533521C (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR102517738B1 (en) * | 2016-12-29 | 2023-04-04 | 엘지디스플레이 주식회사 | Display device, driving controller, and driving method |
-
2006
- 2006-11-28 CN CNB2006101630013A patent/CN100533521C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101192363A (en) | 2008-06-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN103035297B (en) | Shift register | |
| CN110010092B (en) | Display interface device | |
| KR101048994B1 (en) | Organic electroluminescence display device and driving method thereof | |
| CN103680378B (en) | Time schedule controller, display device and driving method thereof | |
| CN108257559A (en) | Display panel with gate drivers | |
| CN105390116B (en) | Gate driving circuit | |
| CN105206242A (en) | Drive circuit, driving method thereof, and display panel | |
| CN105374331A (en) | Gate driver on array (GOA) circuit and display by using the same | |
| CN103578394A (en) | Gate driving circuit and display device using the same | |
| CN102469329A (en) | Stereoscopic image display and power control method thereof | |
| CN104599654B (en) | Chromacoder and method, signal generating system and display device | |
| CN101533597B (en) | Driving method of scanning line of plane monitor | |
| CN107195278A (en) | A kind of display methods of display panel, display panel and display device | |
| CN102280093A (en) | Display panel and driving method of grid driving circuit and gate driving circuit thereof | |
| CN104637430B (en) | Gate driving circuit and display device | |
| CN104361876A (en) | Driving method, driving circuit and display device | |
| US20140191936A1 (en) | Driving Module and Driving Method | |
| CN101123075A (en) | Display apparatus drive device and driving method | |
| CN103903577A (en) | Display device and driving method thereof, and data processing and output method of time sequence control circuit | |
| CN109599070A (en) | Liquid crystal display device and its control method | |
| CN103794170A (en) | Display device including reset controlling unit and method of driving the same | |
| CN100399411C (en) | Device for driving image display equipment and method for designing the device | |
| CN101667388A (en) | Pixel array and driving method thereof and flat plane display | |
| CN100444222C (en) | PDP data driver, PDP driving method, plasma display device, and control method for the same | |
| CN101097691A (en) | LCD driving mechanism and method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090826 Termination date: 20191128 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |