CN100531392C - Hardware implementation method for H.264 block elimination effect filter - Google Patents
Hardware implementation method for H.264 block elimination effect filter Download PDFInfo
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Abstract
The invention relates to a hardware implementation method for a H264 de-blocking effect filter in the technical field of digital video coding and decoding. The invention uses a sub-regional storage approach for pixel information which de-blocks current filter macro-block pixel information and reference macro-block pixel information with 4*4 unit and stores information in two separate single-port memory areas in turn, therefore, synchronous reading and writing can be realized in filter process. Compared with double-port storage device solution with synchronous reading and writing, the invention can effectively save hardware resources; compared with storage device solution with single-port, the invention greatly improves parallel speed and data processing speed on the condition of unchanged hardware resource consumption.
Description
Technical field
The present invention relates to the method in a kind of digital video technology field, specifically is a kind of hardware implementation method of H.264 block elimination effect filter.
Background technology
H.264 be the common a kind of video coding international standard form worked out of the IEC of ISO/ International Power association of International Standards Organization by international telecommunication standardization ITU-T of department and formulation MPEG.H.264 the original intention of standard generation is exactly to formulate a new video encoding standard, to realize high compression ratio, high picture quality, the good network adaptability of video.H.264 MPEG-4 AVC (" advanced video coding of active images expert group-4 ") or be called MPEG-4 Part10 simultaneously is otherwise known as.H.264 be a kind of compression algorithm, and be to produce visible block structure once in a while that blocking effect is the common artificial flaw of present compression algorithm based on the characteristics of the compression algorithm of block encoding based on block encoding.H.264 defined a self adaptation block elimination effect filter, the intensity of filtering is by several syntactic element controls.The absolute difference at if block edge is relatively big, and the possibility that the artificial flaw of piece occurs is just very big, therefore need carry out respective handling.Yet if the difference amplitude is very big, the error of coded quantization process can not explain that the edge has reflected the actual sample value of source image probably, does not need to handle.Through Filtering Processing, reduced blocking effect, and the quality of image is unaffected substantially, so subjective quality improves greatly.If not filtering, same subjective quality need have more the code check of 5%-10%.
By prior art documents, in " An In-Place Architecture for The Deblocking Filterin H.264/AVC " (a suitable H.264/AVC block elimination effect filter structural design) that people such as discovery Chao-Chung Cheng are delivered on Circuits andSystems II, relate to a kind of H.264 block elimination effect filter method for designing, the operating efficiency of this method filter is very high, the cost of for this reason paying is exactly to use the internal storage of a twoport, compare with the single port memory of same capability, expense increases greatly; Also find in the retrieval, in " Architecture design for deblocking filter in H.264/JVT/AVC " (H.264/JVT/AVC block elimination effect filter structural design) that people such as Y.-W.Huang deliver on Proc.of Multimedia and Expo, relate to H.264 block elimination effect filter method for designing of another kind, though this method on-chip memory of single port, but filtration efficiency is very low, can't realize high-definition real-time encoding and decoding substantially.
Summary of the invention
The present invention is directed to the deficiencies in the prior art, provide a kind of based on the hardware implementation method of block elimination effect filter H.264.The present invention has saved hardware resource effectively with respect to the memory device solution that twoport can read while write; With respect to the memory device solution of a single port, consuming under the identical situation of hardware resource, improved the degree of concurrence and the Pixel Information processing speed of block elimination effect filter greatly.
The present invention is achieved by the following technical solutions, the present invention has adopted a kind of method for the storage of Pixel Information subregion, is the unit piecemeal with current filtered macroblock Pixel Information and reference macroblock Pixel Information according to 4 * 4, alternately be stored in two independently in the single port storage area, thereby in filtering, realize reading while write Pixel Information.The present invention includes following steps:
The first step obtains filtering current macro parameters needed;
Second step obtained the needed reference pixel information of the current luminance macroblock of filtering, was that unit alternately is stored in the appropriate address of two storage areas with 4 * 4;
The 3rd step, utilize two storage areas and two transposition modules to current luminance macroblock filtering, the Pixel Information of exporting is waited in the Pixel Information and the filtering that need in the filtering to keep in afterwards, is that unit alternately is temporarily stored in the appropriate address of two storage areas with 4 * 4;
In the 4th step, the filtered luminance pixel information that is temporarily stored in two memory blocks is exported by former position of image splicing;
The 5th step obtained the needed reference pixel information of filtering current chroma macro block, was that unit alternately is stored in the appropriate address of two storage areas with 4 * 4;
The 6th step, utilize two memory blocks and two transposition modules to the current chroma macro block filtering, with filtering Pixel Information afterwards, be that unit alternately is temporarily stored in the appropriate address of two storage areas in the filtering with 4 * 4;
In the 7th step, the filtered chroma pixel information that is temporarily stored in two storage areas is exported in proper order by former position of image.
In the described first step, filtering current macro parameters needed comprises frame field information, the boundary threshold index information of current macro, top and left side reference macroblock, the boundary intensity of each 4 * 4 block boundary of current macro.These parameters were calculated each parameter good the existence in the filter before each macro block filtering by an independently module calculating acquisition.
In described second step and the 5th step, for luminance macroblock filtering, the rightmost four that the reference pixel information that needs has the current macro left side to face macro block mutually is listed as totally 64 pixels, and current macro top bottom four lines totally 64 pixels of believing macro block.For chrominance macroblock filtering, the rightmost two that the reference pixel information of needs has the current macro left side to face macro block mutually is listed as totally 16 pixels, and bottom two capable totally 16 pixels of macro block are believed in the current macro top.
During described the 3rd step and the 6th went on foot, the data storage method of original pixels information was position of image is laterally faced mutually four 8 and is spliced into 32 bits than characteristics, is stored in each memory cell.In filtering with horizontal (vertically) two 4 * 48 points of same delegation (row) facing mutually of position of image, i.e. filtering in two 32 Bit data while input filters.For each 4 * 4, filter sequence is a first vertical edges horizontal sides again, and the first left side is the right again, and first top is following again.
In described the 3rd step and the 6th step, the effect of two transposition modules is to be that the piece of 4 * 4 pixels is by being converted to by column split storage by the row packet memory, perhaps by being converted to by going packet memory by the column split storage with size.Thereby satisfy the needs that horizontal and vertical different Pixel Information puts in order in the filtering.
In described the 4th step and the 7th step, according to the different requirements of interface definition, the data in the storage area can be exported filtered Pixel Information according to 32 bits and two kinds of bit wides of 64 bits.When exporting according to 32 bit bit wides, two storage areas are according to alternately output of position of image; When exporting according to 64 bit bit wides, two storage area while reading of data are spliced into the output of 64 bits.
As from the foregoing, H.264 the hardware implementation method that provides of the present invention utilizes in the block-eliminating effect filtering 4 * 4 and the correlation of access time between the piece on every side, uses the method for data qualification storage, has saved resource effectively.Method in people's papers such as the present invention and Chao-Chung Cheng relatively under the identical situation of filtration efficiency, for the requirement of the memory single port that becomes by twoport, has been saved hardware resource; With method in people's paper such as Y.-W.Huang relatively, be all at memory under the situation of single port, significantly improved the operating efficiency of filter.
Description of drawings
Fig. 1 is the H.264 block elimination effect filter system architecture diagram that the embodiment of the invention adopts;
Fig. 2 is luminance macroblock and reference pixel storage schematic diagram;
Fig. 3 is chrominance macroblock and a reference pixel storage schematic diagram under the 4:2:0 pattern;
Wherein: blank parts and dash area are stored in respectively on two sheets among the SRAM;
Fig. 4 is a macro-block level brightness boundary filtering order, according to the ascending order filtering schematic diagram of numbering;
Fig. 5 is a macro-block level colourity boundary filtering order under the 4:2:0 pattern, according to the ascending order filtering schematic diagram of numbering;
Fig. 6 is a transposition register internal structure schematic diagram;
Specific implementation
Below in conjunction with accompanying drawing embodiments of the invention are elaborated: present embodiment is being to implement under the prerequisite with the technical solution of the present invention, provided detailed execution mode and concrete operating process, but protection scope of the present invention is not limited to following embodiment.
As shown in Figure 1, the H.264 block elimination effect filter system architecture diagram that the embodiment of the invention adopts is a block elimination effect filter in the dashed rectangle, comprises with lower module:
Master controller goes by control that other modules and Pixel Information flow to the control that realizes the filtering of whole block elimination effect filter in the piece efficient filter;
Two modules of transposition register A and transposition register B realize the matrix transpose operation to 4 * 4 Pixel Information, to cater to the needs of the horizontal and vertical filtering of pictorial information;
Pixel memories A and pixel memories B realize that with SRAM on the sheet of two single port bit wide is 32 bits (4 pixels), and the every degree of depth is 48, and size is a current macro block pixels, and the top, half of left side reference pixel summation.
The current macro block pixels input port, the reference pixel input port, the pixel output port, three Pixel Information switching ports connect an external memory storage respectively, and bit wide is respectively 32 bits, 64 bits, 64 bits.Current macro block pixels information and reference pixel information enter filter by current macro block pixels input port and reference pixel input port, export by the pixel output port after the filtering.
The filtering parameter input port connects the FIFO (first-in first-out buffer) that bit wide is 6 bits.Before each macro block filtering, with frame field information, the boundary threshold index information of the needed current macro of filtering, top and left side reference macroblock, the parameters such as boundary intensity of each 4 * 4 block boundary of current macro pass to block elimination effect filter by the filtering parameter input port.Wherein, each 1 bit of the frame field information of the left side and current macro is merged into a word transmission.The top, each 6 bit of the boundary threshold index of the left side and current macro, transmission separately.Totally 32 of 4 * 4 block boundary intensity, each 3 bit, per two combine transmission.
As shown in Figure 2, be luminance macroblock and reference pixel storage scheme figure, blank parts and dash area are stored in respectively on two sheets among the SRAM, and when luminance macroblock filtering, with current macro block pixels information, reference pixel information is that unit divides with 4 * 4.After rearranging, deposit two correspondence positions in the pixel memories respectively in.4 * 4 that shade indicates among the figure deposit pixel memories A in, and blank 4 * 4 of indicating deposit pixel memories B in.Storage like this makes all to be stored in the different pixel memories with each 4 * 4 Pixel Information of facing mutually that therefore in filtering, the read-write operation of Pixel Information can not clash in the pixel memories.
As shown in Figure 3, also by 4 * 4 divisions, processing method is identical with luminance macroblock for the current macro block pixels information of chrominance macroblock and reference pixel information.The reference pixel information that it should be noted that chrominance macroblock is two row, but not four row of brightness.
The transposition module is connected by structure shown in Figure 6 by one group of register, and it is the register of 8 bits that each square is represented bit wide.4 * 4 Pixel Information have vertical output more earlier by horizontal input register, have just finished the operation of transposition.When vertically exporting, another 4 * 4 Pixel Information vertically can be imported, the operation of transposition has been finished in laterally output with the mode of streamline again.
In the filtering, current macro block pixels information is according to Fig. 4, and order enters filter successively shown in 5.Earlier carry out vertical filtering, enter filter other end inlet again, carry out vertical filtering, enter the transposition register file afterwards, make transposition and calculate, be stored on the sheet in the corresponding address space of SRAM with four pixels in the right with four pixels in the left side; When doing horizontal filtering, the pixel behind the transposition is read the SRAM from sheet, respectively do horizontal filtering with 4 of tops and at following 4, filtered pixel enters the transposition register file again, deposits in behind the transposition and waits for output on the sheet among the SRAM.Filter calculates to be needed to postpone four cycles, uses streamline mechanism in whole filtering, guarantees on average in one to two cycle output, one row's filtering pixel.
During output,, form the data of 64 bits and write as in the external memory storage with two 4 * 4 splicings (they must be to be stored in respectively in the different on-chip memories) of laterally facing mutually.Read reference pixel and other module application during in order to later other macro block filterings.
H.264 above-mentioned hardware implementation method utilizes in the block-eliminating effect filtering 4 * 4 and the correlation of access time between the piece on every side, uses the method for data qualification storage, has saved resource effectively.With two degree of depth is 48, and bit wide is SRAM on the single port sheet of 32 bits, has reached the efficient of a macro block of 300cycle decoding.Method in people's papers such as the present invention and Chao-Chung Cheng relatively, under the identical situation of filtration efficiency (300cycle/MB), memory is become SRAM on the sheet of two single port by SRAM on the sheet of a twoport, saved hardware resource; With method in people's paper such as Y.-W.Huang relatively, be all at SRAM on the sheet under the situation of single port, significantly improved operating efficiency (people's method: 878cycle/MB such as Y.-W.Huang, the present invention: 300cycle/MB) of filter.
Claims (7)
1. hardware implementation method of block elimination effect filter H.264, it is characterized in that, adopted a kind of for the subregional storage means of Pixel Information, is the unit piecemeal with current filtered macroblock Pixel Information and reference macroblock Pixel Information with 4 * 4, alternately be stored in two independently in the single port storage area, thereby in filtering, realize reading and writing simultaneously
Comprise the steps:
The first step obtains filtering current macro parameters needed;
Second step obtained the needed reference pixel information of the current luminance macroblock of filtering, was that unit alternately is stored in the appropriate address of two storage areas with 4 * 4;
The 3rd step, utilize two storage areas and two transposition modules to current luminance macroblock filtering, the Pixel Information of exporting is waited in the Pixel Information and the filtering that need in the filtering to keep in afterwards, is that unit alternately is temporarily stored in the appropriate address of two storage areas with 4 * 4;
In the 4th step, the filtered luminance pixel information that is temporarily stored in two memory blocks is exported by former position of image splicing;
The 5th step obtained the needed reference pixel information of filtering current chroma macro block, was that unit alternately is stored in the appropriate address of two storage areas with 4 * 4;
The 6th step, utilize two memory blocks and two transposition modules to the current chroma macro block filtering, with filtering Pixel Information afterwards, be that unit alternately is temporarily stored in the appropriate address of two storage areas in the filtering with 4 * 4;
The 7th step, the filtered chroma pixel information that is temporarily stored in two storage areas is exported in proper order by former position of image, be that data in the storage area are exported filtered Pixel Information according to 32 bits and two kinds of bit wides of 64 bits, when exporting according to 32 bit bit wides, two storage areas are according to alternately output of position of image; When exporting according to 64 bit bit wides, two storage area while reading of data are spliced into the output of 64 bits.
2. the hardware implementation method of H.264 block elimination effect filter as claimed in claim 1, it is characterized in that, in the described first step, filtering current macro parameters needed comprises frame field information, the boundary threshold index information of current macro, top and left side reference macroblock, the boundary intensity of each 4 * 4 block boundary of current macro, these parameters were calculated each parameter good the existence in the filter before each macro block filtering by an independently module calculating acquisition.
3. the hardware implementation method of H.264 block elimination effect filter as claimed in claim 1, it is characterized in that, in described the 3rd step, the piece that two transposition modules are 4 * 4 pixels with size is stored by being converted to by column split by the row packet memory, perhaps be converted to by the row packet memory, thereby satisfy the needs that horizontal and vertical different Pixel Information puts in order in the filtering by storing by column split.
4. as the hardware implementation method of claim 1 or 3 described H.264 block elimination effect filters, it is characterized in that in described the 3rd step, for each 4 * 4, filter sequence is a first vertical edges horizontal sides again, the first left side is the right again, and first top is following again.
5. the hardware implementation method of H.264 block elimination effect filter as claimed in claim 1, it is characterized in that, in described the 6th step, the piece that two transposition modules are 4 * 4 pixels with size is stored by being converted to by column split by the row packet memory, perhaps be converted to by the row packet memory, thereby satisfy the needs that horizontal and vertical different Pixel Information puts in order in the filtering by storing by column split.
6. as the hardware implementation method of claim 1 or 5 described H.264 block elimination effect filters, it is characterized in that in described the 6th step, for each 4 * 4, filter sequence is a first vertical edges horizontal sides again, the first left side is the right again, and first top is following again.
7. the hardware implementation method of H.264 block elimination effect filter as claimed in claim 1, it is characterized in that, in described the 4th step, data in the storage area are exported filtered Pixel Information according to 32 bits and two kinds of bit wides of 64 bits, when exporting according to 32 bit bit wides, two storage areas are according to alternately output of position of image; When exporting according to 64 bit bit wides, two storage area while reading of data are spliced into the output of 64 bits.
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| CN103209324A (en) * | 2012-01-17 | 2013-07-17 | 张民 | Method of applying edge offset |
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| JP2010288079A (en) * | 2009-06-11 | 2010-12-24 | Sony Corp | Image processing apparatus and image processing method |
| KR101757947B1 (en) * | 2009-10-05 | 2017-07-13 | 톰슨 라이센싱 | Methods and apparatus for adaptive filtering of prediction pixels for chroma components in video encoding and decoding |
| CN101841722B (en) * | 2010-06-08 | 2011-08-31 | 上海交通大学 | Detection method of detection device of filtering boundary strength |
| CN101883285A (en) * | 2010-07-06 | 2010-11-10 | 西安交通大学 | VLSI (Very Large Scale Integration) structural design method of parallel pipeline deblocking filter |
| CN101924938B (en) * | 2010-08-11 | 2012-09-05 | 上海交通大学 | Method for processing adjacent block information in video decoding macro-block prediction and boundary filtering |
| CN102131098B (en) * | 2011-04-02 | 2016-03-30 | 深圳市中兴微电子技术有限公司 | The block-removal filtering method of video image and device |
| CN104253998B (en) * | 2014-09-25 | 2017-05-10 | 复旦大学 | Hardware on-chip storage method of deblocking effect filter applying to HEVC (High Efficiency Video Coding) standard |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN103209324A (en) * | 2012-01-17 | 2013-07-17 | 张民 | Method of applying edge offset |
| CN103209324B (en) * | 2012-01-17 | 2018-01-02 | 杰尼普Pte有限公司 | A kind of method for applying edge compensation |
| US10063859B2 (en) | 2012-01-17 | 2018-08-28 | Infobridge Pte. Ltd. | Method of applying edge offset |
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