CN100531043C - Clock impulse signal frequency controlling method and network exchanger therewith - Google Patents
Clock impulse signal frequency controlling method and network exchanger therewith Download PDFInfo
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- CN100531043C CN100531043C CNB031238459A CN03123845A CN100531043C CN 100531043 C CN100531043 C CN 100531043C CN B031238459 A CNB031238459 A CN B031238459A CN 03123845 A CN03123845 A CN 03123845A CN 100531043 C CN100531043 C CN 100531043C
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Abstract
The network interchanger consists of the several output/input ports, a clock pulse signal generator and an interlinking state detector. The controlling method includes following steps. Based on the number of output/input ports transferring data actually in the output/input ports and/or the existing circumstance of data transmission rate of these output/input ports, the interlinking state detector outputs a control signal to the clock pulse signal generator accordingly. The clock pulse signal generator changes the frequency of the output clock pulse signal in order to respond the change of the control signal.
Description
Technical field
The invention relates to a kind of clock pulse signal control method for frequency and use the network switch of this method, particularly a kind of meeting changes the control method and the corresponding network switch of forceful pulse signal frequency along with the state of all I/O ports.
Background technology
See also Fig. 1, it is the built-in function block schematic diagram of a network switch 1 at present commonly used, find out by knowing among the figure, it mainly has a control chip 10, and this control chip 10 has switch fabric circuitry 100 (Switch Matrix), several medium access controllers 101 (Media Access controller, MAC), unit such as embedded internal memory 102 and phase-locked loop clock pulse signal generator 103, wherein this phase-locked loop gate generator 103 is to produce the required clock pulse signal in other unit of chip internal with reference to an external clock pulse produces source 11.
And owing to network switch is that the network node (for example personal computer) that supplies multi-section to have the network card interface connects, therefore each medium access controller 101 is linked to the entity apparatus 12 of a corresponding I/O port, by this entity apparatus 12, medium access controller 101 can be reached transfer of data by its corresponding network node.Though but the network card frequency range of each network node might be also inequality, with present common network card frequency range specification, each entity apparatus 12 can be linked to the network card of three kinds of possibility frequency ranges (10/100/1000Mb/s) or be in the state that does not link.But, carry out required total frequency range simultaneously in order to meet all possible high-speed transfer, the producer just can only may list the highest of each I/O port in consideration by frequency range, and then assesses out the clock pulse signal frequency that this phase-locked loop gate generator 103 is produced.For instance, with common network switch with 24 I/O ports, wherein there are two I/O ports can support three kinds of transmission rates (10/100/1000Mb/s), other 22 I/O ports then can be supported two kinds of transmission rates (10/100Mb/s), therefore the designer utilizes the frequency of 103 output clock pulse signals of phase-locked loop gate generator, must meet required when all I/O ports all operate in the highest frequency range (i.e. 2 1000Mb/s and 22 100Mb/s), therefore, phase-locked loop commonly used gate generator 103 just need be fixed lasting output one high-frequency clock pulse signal (for example frequency is 100M/s) and use for other unit of chip internal, make control chip 10 ongoing operations meet its highest default demand in a fast state, but so will cause network switch to be in high hot state always and consumed power excessive, and then produce the shortcoming of easy standby and power consumption, and how to improve this shortcoming, for developing main purpose of the present invention.
Summary of the invention
The present invention is a kind of clock pulse signal control method for frequency, be applied on the network switch, this network switch has several I/O ports and a clock pulse signal generator, and this control method comprises the following step: carry out the I/O port quantity of transfer of data and corresponding output one controls signal to this clock pulse signal generator according to actual in the described I/O port; And this clock pulse signal generator responds the variation of this control signal and changes the frequency of its output clock pulse signal.
According to above-mentioned conception, clock pulse signal control method for frequency of the present invention, the total quantity that wherein actual I/O port quantity of carrying out transfer of data is I/O port deducts the I/O port quantity that is not connected with network node.
According to above-mentioned conception, clock pulse signal control method for frequency of the present invention, wherein this clock pulse signal generator is the increase of this actual I/O port quantity of carrying out transfer of data of response and increase the frequency of institute's output clock pulse signal.
According to above-mentioned conception, clock pulse signal control method for frequency of the present invention, wherein this clock pulse signal generator is the minimizing of this actual I/O port quantity of carrying out transfer of data of response and reduce the frequency of institute's output clock pulse signal.
Another aspect of the invention is a kind of clock pulse signal control method for frequency, be applied on the network switch, this network switch has several I/O ports and a clock pulse signal generator, and this control method comprises the following step: according to the virtual condition of described I/O port message transmission rate and corresponding output one controls signal to this clock pulse signal generator; And this clock pulse signal generator responds the variation of this control signal and changes the frequency of its output clock pulse signal.
According to above-mentioned conception, clock pulse signal control method for frequency of the present invention, the virtual condition of wherein said I/O port message transmission rate is the summation of actual transfer rate that is connected with the I/O port of network node.
According to above-mentioned conception, clock pulse signal control method for frequency of the present invention, wherein this clock pulse signal generator be this actual transfer rate of response summation increase and increase the frequency of institute's output clock pulse signal.
According to above-mentioned conception, clock pulse signal control method for frequency of the present invention, wherein this clock pulse signal generator respond this actual transfer rate summation minimizing and reduce the frequency of institute's output clock pulse signal.
Another aspect of the invention is a kind of network switch, be applied to the signal transmission of several network nodes, it comprises: several I/O ports, and it connects for described network node; One clock pulse signal generator, it produces a clock pulse signal for the utilization of the assembly in the network switch; An and connecting state detector, signal is connected to described I/O port, its actual connecting state according to described I/O port and described network node is exported one and is controlled signal to this clock pulse signal generator, and then changes the frequency of this clock pulse signal generator output clock pulse signal.
According to above-mentioned conception, network switch of the present invention, wherein this clock pulse signal generator is a phase-locked loop clock pulse signal generator.
According to above-mentioned conception, network switch of the present invention, wherein this connecting state detector one actually links the frequency that quantity changes this clock pulse signal generator output clock pulse signal according to what the total quantity of described I/O port deducted that the I/O port quantity gained that is not connected with network node causes.
According to above-mentioned conception, network switch of the present invention, wherein this connecting state detector changes the frequency of this clock pulse signal generator output clock pulse signal according to the summation of the actual transfer rate of the I/O port that is connected with network node.
Compared with prior art, advantage of the present invention is clearly.Because the number of meeting basis of the present invention I/O port just in use and the real-time Transmission speed of I/O port just in use, therefore the frequency of the clock pulse signal can the enable clock pulse generator exported of the present invention, as long as can adjust to the demand that enough meets at that time, and in advance the clock pulse signal frequency is adjusted to as the prior art for another example might demand the upper limit.Whereby, when the actual demand frequency was lower than the demand upper frequency limit, the present invention just can pass through to reduce frequency, and then reduces temperature and reduce power consumption.
Description of drawings
The present invention makes it to obtain deep understanding by following graphic and detailed description.
Fig. 1: the built-in function block schematic diagram of a network switch at present commonly used;
Fig. 2: the network switch function block schematic diagram that the inventive method was applied to;
Fig. 3: the first preferred embodiment steps flow chart schematic diagram of discharge control method that the present invention develops;
Fig. 4: the second preferred embodiment steps flow chart schematic diagram of discharge control method that the present invention develops.
Embodiment
See also Fig. 2, it is the network switch function block schematic diagram that the inventive method is applied to, wherein network switch 2 mainly has a control chip 20, and this control chip 20 has switch fabric circuitry 200 (Switch Matrix), several medium access controllers 201 (MAC), unit such as embedded internal memory 202 and phase-locked loop clock pulse signal generator 203, wherein this phase-locked loop gate generator 203 produces source 21 with a connecting state detector 204 and the required clock pulse signal in generation other unit of chip internal with reference to an external clock pulse.Wherein connecting state detector 204 is that signal is connected to each medium access controller 201 (MAC), so as to learning the connecting state of the I/O port that each medium access controller 201 (MAC) and its corresponding entity device 22 are formed.For instance, with common network switch with 24 I/O ports, wherein have two I/O ports can support three kinds of transmission rates (10/100/1000Mb/s), other 22 I/O ports then can be supported two kinds of transmission rates (10/100Mb/s).Though must possessing to have, control chip 20 can deal with required processing speed when all I/O ports all operate in the highest frequency range (i.e. 2 1000Mb/s and 22 100Mb/s), but actual user mode seldom is so busy, because 24 I/O ports can not stuck with usually fully, disposing transmission rate only has the personal computer of the network card of 10Mb/s still to exist in a large number, and transmission rate is that the personal computer of the network card of 1000Mb/s is also popularized as yet.So, the present invention utilizes a connecting state detector 204 to detect the actual connecting state of all I/O ports, and control signal to this phase-locked loop clock pulse signal generator 203 according to actual connecting state, and then can flexibly adjust the frequency of 203 output clock pulse signals of this phase-locked loop clock pulse signal generator, and then reach the shortcoming of avoiding Gao Re excessive with power consumption.
See also Fig. 3 again, it is the first preferred embodiment steps flow chart schematic diagram of discharge control method that the present invention develops, and comprises five base program 31-34.This control method comprises the following step: this connecting state detector carries out the virtual condition of the I/O port quantity of transfer of data and/or described I/O port message transmission rate according to actual in the described I/O port and corresponding output one controls signal to this clock pulse signal generator; And this clock pulse signal generator responds the variation of this control signal and changes the frequency of its output clock pulse signal.Wherein mainly be to carry out the total quantity of I/O port is deducted the I/O port quantity Calculation action that is not connected with network node every a scheduled time, and then draw an actual I/O port quantity of carrying out transfer of data, with common network switch with 24 I/O ports, common 24 I/O ports can not stuck with usually fully, therefore actual I/O port quantity of carrying out transfer of data is 0 to 24 all possible, and just can correspondence go out an operating frequency, and then send one and control signal to this clock pulse signal generator and make its output clock pulse signal operate in this operating frequency according to this quantity.Thus, above-mentioned network switch 2 just can flexibly be adjusted the frequency of 203 output clock pulse signals of this phase-locked loop clock pulse signal generator according to actual connecting state, and then reaches the shortcoming of avoiding Gao Re excessive with power consumption.Change the practice of the frequency of output clock pulse signal as for phase-locked loop clock pulse signal generator 203, cause the assembly operated according to this clock pulse signal to produce mistake for avoiding crossing play because of short time internal cause frequency change, phase-locked loop clock pulse signal generator 203 should be walked unhurriedly and be carried out the change of frequency progressively.
See also Fig. 4 again, it is the second preferred embodiment steps flow chart schematic diagram of discharge control method that the present invention develops, and comprises four base program 41-44.Wherein mainly be to calculate every the summation that a scheduled time is carried out the actual transfer rate of the actual I/O port that is connected with network node, and then draw possible the maximum data treating capacity of network switch at that time, with common network switch with 24 I/O ports, usually can all not operate on the highest frequency range by each I/O port, therefore the actual transmission rate summation S that carries out transfer of data is S=M*0+N*10+O*100+P*1000, and M+N+O+P=24, and just can correspondence go out an operating frequency, and then send one and control signal to this clock pulse signal generator and make its output clock pulse signal operate in this operating frequency according to this summation S.Thus, above-mentioned network switch 2 just can flexibly be adjusted the frequency of 203 output clock pulse signals of this phase-locked loop clock pulse signal generator according to actual connecting state, and then reaches the shortcoming of avoiding Gao Re excessive with power consumption.
In sum, the present invention is according to information such as the actual connecting state of all I/O ports and actual transmission speed thereof, and then can flexibly adjust the frequency of this phase-locked loop clock pulse signal generator institute output clock pulse signal, and then reach the shortcoming of avoiding Gao Re excessive with power consumption.So the present invention is by the equivalent modifications that those skilled in the art did, in scope of patent protection of the present invention.
Claims (10)
1. a clock pulse signal control method for frequency is applied on the network switch, and this network switch has several I/O ports and a clock pulse signal generator, and this control method comprises the following step:
Carry out the I/O port quantity of transfer of data and corresponding output one controls signal to this clock pulse signal generator according to actual in the described I/O port; And
This clock pulse signal generator responds the variation of this control signal and changes the frequency of its output clock pulse signal.
2. clock pulse signal control method for frequency as claimed in claim 1, the total quantity that wherein actual I/O port quantity of carrying out transfer of data is I/O port deducts the I/O port quantity that is not connected with network node.
3. clock pulse signal control method for frequency as claimed in claim 1, wherein this clock pulse signal generator is the increase of this actual I/O port quantity of carrying out transfer of data of response and increase the frequency of institute's output clock pulse signal.
4. clock pulse signal control method for frequency as claimed in claim 1, wherein this clock pulse signal generator responds the minimizing of this actual I/O port quantity of carrying out transfer of data and reduces the frequency of institute's output clock pulse signal.
5. a clock pulse signal control method for frequency is applied on the network switch, and this network switch has several I/O ports and a clock pulse signal generator, and this control method comprises the following step:
According to the virtual condition of described I/O port message transmission rate and corresponding output one controls signal to this clock pulse signal generator; And
This clock pulse signal generator responds the variation of this control signal and changes the frequency of its output clock pulse signal.
6. clock pulse signal control method for frequency as claimed in claim 5, the virtual condition of wherein said I/O port message transmission rate are the summation of actual transfer rate that is connected with the I/O port of network node.
7. clock pulse signal control method for frequency as claimed in claim 6, wherein this clock pulse signal generator be this actual transfer rate of response summation increase and increase the frequency of institute's output clock pulse signal.
8. clock pulse signal control method for frequency as claimed in claim 6, wherein this clock pulse signal generator be this actual transfer rate of response summation minimizing and reduce the frequency of institute's output clock pulse signal.
9. a network switch is applied to the signal transmission of several network nodes, and it comprises:
Several I/O ports, it connects for described network node;
One connecting state detector, signal is connected to described I/O port, and it exports a control signal according to the actual connecting state between described I/O port and described network node; And
One clock pulse signal generator, it uses for the assembly in the network switch at this this clock pulse signal according to the frequency that changes a clock pulse signal that is produced from this control signal of this connecting state detector.
10. network switch as claimed in claim 9, wherein this clock pulse signal generator is a phase-locked loop clock pulse signal generator.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031238459A CN100531043C (en) | 2003-05-14 | 2003-05-14 | Clock impulse signal frequency controlling method and network exchanger therewith |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB031238459A CN100531043C (en) | 2003-05-14 | 2003-05-14 | Clock impulse signal frequency controlling method and network exchanger therewith |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1457174A CN1457174A (en) | 2003-11-19 |
| CN100531043C true CN100531043C (en) | 2009-08-19 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB031238459A Expired - Lifetime CN100531043C (en) | 2003-05-14 | 2003-05-14 | Clock impulse signal frequency controlling method and network exchanger therewith |
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| Country | Link |
|---|---|
| CN (1) | CN100531043C (en) |
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- 2003-05-14 CN CNB031238459A patent/CN100531043C/en not_active Expired - Lifetime
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| CN1457174A (en) | 2003-11-19 |
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