CN100530298C - Slot type plasma display panel holding driving method and circuit thereof - Google Patents
Slot type plasma display panel holding driving method and circuit thereof Download PDFInfo
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- CN100530298C CN100530298C CNB2007100212912A CN200710021291A CN100530298C CN 100530298 C CN100530298 C CN 100530298C CN B2007100212912 A CNB2007100212912 A CN B2007100212912A CN 200710021291 A CN200710021291 A CN 200710021291A CN 100530298 C CN100530298 C CN 100530298C
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Abstract
This invention relates to a maintaining and driving method and a circuit for SMPDP, in which, the driving circuit is composed of a voltage control driving circuit, a positive voltage maintaining voltage pulse generator, a positive voltage energy resuming keeping circuit, a negative voltage maintenance voltage pulse generator, a negative voltage energy resuming and keeping circuit, a line IC chip protection circuit, a PDP high voltage line driving IC chip, and the output of the PDP high voltage line driving IC chip is connected with the SMPDP.
Description
Technical field
The present invention relates to a kind of plasma display panel and safeguard driving method and circuit thereof; especially a kind of groove type plasma display panel (SMPDP) of capable IC chip protection circuit that adopted is kept driving method and circuit, and specifically a kind of groove type plasma display panel is kept driving method and circuit thereof.
Background technology
The plasma panel display (PDP) that early 1990s rises, with its digitizing, giant-screen, high resolving power, high definition, wide visual angle and thin thickness, advantage such as in light weight is subjected to extensive concern.
Existing P DP screen all adopts three electrode AC plasma plate displays (AC-PDP) at present, 3 orthogonal thereto shapes of electrode are distributed on the front-back baseboard, discharge is then carried out between two substrates, horizontal distribution and is kept electrode (X electrode) and scan electrode (Y electrode) on the prebasal plate, both are called as show electrode together, the addressing electrode (A electrode) that on metacoxal plate, vertically distributing, X electrode and Y electrode be parallel to each other and with A electrode quadrature.In AC-PDP showed, in the phase of keeping, X electrode and Y electrode alternately added high pressure, made the unit generation discharge that has accumulated the wall electric charge in address period.Thereby realize the demonstration of image.
The structure of existing groove type plasma display panel mainly is made of metacoxal plate 101, aperture plate plate 103 and prebasal plate 102.Metacoxal plate 101 comprises back substrate glass substrate 104, film first electrode 105 (row electrode, addressing electrode) that forms on back substrate glass substrate 104, the insulation course 106 that forms on back substrate glass substrate 104; Prebasal plate 102 comprises preceding substrate glass substrate 108, form on preceding substrate glass substrate 108 lower surfaces with metacoxal plate 101 on second electrode 109 (column electrode, scan electrode) of 105 one-tenth spatial vertical quadratures of first electrode, the dielectric layer 110 that on the lower surface of second electrode 109, forms, the diaphragm 111 that on preceding substrate glass substrate 108 and dielectric layer 110, forms; Column electrode and row electrode are in vertical distribution after forward and backward substrate assembling is finished; The aperture plate plate 103 that is clipped between the front-back baseboard 101,102 is current-carrying plates (public electrode) that comprise the grid hole array, and it can be a sheet metal, can also be the dielectric-slab that the surface plates metal conducting layer.Mesh on the aperture plate plate is corresponding one by one with the position, point of crossing of column electrode and row electrode, fills the required working gas with certain air pressure in grid hole, just becomes the discharge cell space of this plasma display screen.As shown in Figure 3, Figure 4.
What type of drive in groove type plasma display panel (SMPDP) adopted is two electrodes, is respectively to keep electrode (X electrode), the interchange subtend discharge mode of the addressing electrode on the metacoxal plate 101 (A electrode) on the prebasal plate 102.X electrode and A electrode quadrature in SMPDP shows, in the phase of keeping, only add the positive and negative high pressure that replaces and make address period accumulate the unit generation discharge of wall electric charge, thereby realize that image shows on the X electrode.
The visual display drive method of existing groove type plasma display panel adopts is that the bipolarity energy regains and keeps voltage pulse circuit, this circuit regains at the positive and negative energy of realization and keeps in the pulse voltage process, row IC chip does not stop under the control of Control of Voltage driving circuit will go the output terminal of IC chip and communicate with the high-voltage power supply earth terminal of capable IC chip with the high-voltage power supply end of row IC chip respectively, therefore row IC chip is bigger in the high-frequency loss of the phase of keeping, cause the heating of capable IC chip, make the reliability decrease of SMPDP plasma display panel.
Summary of the invention
The objective of the invention is can't guaranteed problem at existing SMPDP plasma display panel reliability, provide a kind of row IC chip that can reduce to keep driving method, a kind of corresponding maintenance driving circuit is provided simultaneously at the groove type plasma display panel of the frequency of operation of the phase of keeping.
Technical scheme of the present invention is:
A kind of groove type plasma display panel is kept driving method, it is characterized in that: make the output terminal of keeping the field effect transistor M6 in the phase voltage control circuit connect the drain electrode of field effect transistor M11 and the input end of the field effect transistor T2 in the PDP horizontal high voltage driving IC chip respectively; Make the output terminal of keeping the field effect transistor M3 in the phase voltage control circuit connect the source electrode of field effect transistor M11 and the input end of the field effect transistor T1 in the PDP horizontal high voltage driving IC chip respectively; The output terminal of field effect transistor M9, M10 in the negative voltage energy recovery holding circuit connects the negative pole of fast recovery diode D5 positive pole, D6 respectively, the positive pole of fast recovery diode D5 negative pole, D6 connects inductance L 2, and the other end of inductance L 2 connects the source electrode of field effect transistor M4, the drain electrode of M5, the source electrode of M6 respectively; The positive voltage energy recovers the negative pole of the output termination fast recovery diode D3 of the field effect transistor M7 in the holding circuit, the positive pole of the output termination fast recovery diode D4 of field effect transistor M8, the positive pole of the negative pole of fast recovery diode D4 and fast recovery diode D3 connects inductance L 1, and the other end of inductance L 1 connects the drain electrode of field effect transistor M2, the source electrode of M1, the drain electrode of M3 respectively; At the high-voltage power supply end of the earth terminal of the capable driving IC chip of PDP high pressure and the capable driving IC chip of a PDP high pressure field effect transistor M11 in parallel and make it to be in open mode, reduce the switch number of times of row IC chip in the phase of keeping, avoid the capable IC chip heating situation that high-frequency loss causes, keep the reliability of driving circuit with raising; Utilize column electrode to produce compound erasing pulse at erasing period at last, make the row electrode all keep ground state in phase of keeping and erasing period.
Driving circuit of the present invention is:
A kind of groove type plasma display panel is kept driving circuit; it is characterized in that by Control of Voltage driving circuit 1; positive voltage is kept voltage impulse generator 2; the positive voltage energy recovers holding circuit 3; negative voltage is kept voltage impulse generator 4; the negative voltage energy recovers holding circuit 5; row IC chip protection circuit 6; the capable driving IC chip 7 of PDP high pressure is formed; positive voltage is kept 2 one input ends of voltage impulse generator; the positive voltage energy recovers the input end of holding circuit 3; negative voltage is kept an input end of voltage impulse generator 4; the negative voltage energy recovers the input end of holding circuit 5; the output terminal that the input end of row IC chip protection circuit 6 and an input end of the capable driving IC chip 7 of PDP high pressure are corresponding with Control of Voltage driving circuit 1 respectively links to each other; an output termination positive voltage of row IC chip protection circuit 6 is kept the output terminal of voltage impulse generator 2 and an input end of the capable driving IC chip 7 of PDP high pressure; another output termination negative voltage of row IC chip protection circuit 6 is kept the output terminal of voltage impulse generator 4 and another input end of the capable driving IC chip 7 of PDP high pressure; the output that the positive voltage energy recovers holding circuit 3 connects another input end that positive voltage is kept voltage impulse generator 2; the output termination negative voltage of negative voltage energy recovery holding circuit 5 is kept another input end of voltage impulse generator 4; positive voltage is kept the output terminal of voltage impulse generator 2 and output terminal that negative voltage is kept voltage impulse generator 4 also links to each other the output terminal access slot type plasma display panel 8 of the capable driving IC chip 7 of PDP high pressure with capable driving IC chip 7 corresponding input end of PDP high pressure.
Described Control of Voltage driving circuit 1 is made up of programmable logic chip and field effect transistor chip for driving, the pulse signal that programmable logic chip produces produces the pulse signal of the field effect transistor work in follow-up each circuit that can drive: XEFH after the field effect transistor chip for driving is amplified, XEFL, XHU, XPZH, XPZL, XFU, XNEL, XNEH, XAEH, XAEL, XSU, they are respectively and just keep the Control of Voltage pulse signal, just keeping the voltage control wave that makes zero, open the M3 control wave, the negative voltage control wave that makes zero of keeping, the negative Control of Voltage pulse signal of keeping, open the M6 control wave, positive voltage storage capacitor charging start signal, positive voltage storage capacitor discharge start signal, negative voltage storage capacitor charging start signal, negative voltage storage capacitor discharge start signal, open the M11 control wave.
Described positive voltage is kept voltage impulse generator 2 and is made up of field effect transistor M1, M2, M3, positive voltage is kept the input of voltage impulse generator 2 and is drawn the output that the output that connects Control of Voltage driving circuit 1 is the field effect pipe driving chip from the grid of M1, M2, M3, export XEFH, XEFL, XHU respectively by the field effect transistor chip for driving under the control of programmable logic chip and give corresponding field effect transistor M1, M2, M3, its output is drawn the earth terminal that connects the capable driving IC chip 7 of PDP high pressure respectively and the source terminal of field effect transistor M11 from the source electrode of M3.
Described positive voltage energy recovers holding circuit 3 by field effect transistor M3, M7, M8, inductance L 1, diode D3, D4, capacitor C 1 is formed, the positive voltage energy recovers the input of holding circuit 3 from M3, M7, the grid of M8 is drawn the output that the output that connects Control of Voltage driving circuit 1 is the field effect pipe driving chip, under the control of programmable logic chip, export XHU respectively by the field effect transistor chip for driving, XNEL, the XNEH pulse signal is given corresponding field effect transistor M4, M7, M8, its output is drawn from the end of L1 and is connect positive voltage respectively and keep field effect transistor M2 the voltage impulse generator 2, the source electrode of the drain electrode of M3 and field effect transistor M1 is drawn the earth terminal that connects the capable driving IC chip 7 of PDP high pressure respectively and the source terminal of field effect transistor M11 from the source electrode of field effect transistor M3 again.
Described negative voltage is kept voltage impulse generator 4 and is made up of field effect transistor M4, M5, M6, negative voltage is kept the input of voltage impulse generator 4 and is drawn the output that the output that connects Control of Voltage driving circuit 1 is the field effect pipe driving chip from the grid of M4, M5, M6, export XPZH, XPZL, XFU respectively by the field effect transistor chip for driving under the control of programmable logic chip and give corresponding field effect transistor M4, M5, M6, its output is drawn the power end that connects the capable driving IC chip 7 of PDP high pressure respectively and the drain electrode end of field effect transistor M11 from the drain electrode of M6.
Described negative voltage energy recovers holding circuit 5 by field effect transistor M6, M9, M10, inductance L 2, diode D5, D6, capacitor C 2 is formed, the negative voltage energy recovers the input of holding circuit 5 from M6, M9, the grid of M10 is drawn the output that the output that connects Control of Voltage driving circuit 1 is the field effect pipe driving chip, under the control of programmable logic chip, export XFU respectively by the field effect transistor chip for driving, XAEH, the XAEL pulse signal is given corresponding field effect transistor M6, M9, M10, its output is drawn from the end of L2 and to be connect the drain electrode that negative voltage is kept source electrode and the field effect transistor M5 of the field effect transistor M4 the voltage impulse generator 4 respectively, draws the power end that connects the capable driving IC chip 7 of PDP high pressure respectively and the drain electrode end of field effect transistor M11 from the drain electrode of field effect transistor M6 again.
Described capable IC chip protection circuit 6 is made up of field effect transistor M11; the input of row IC chip protection circuit 6 is drawn the output that the output that connects Control of Voltage driving circuit 1 is the field effect pipe driving chip from the grid of M11; export the XSU pulse signal respectively by the field effect transistor chip for driving under the control of programmable logic chip and give corresponding field effect transistor M11, the output source electrode of field effect transistor M11 connects the source terminal of the earth terminal and the field effect transistor M3 of the capable driving IC chip 7 of PDP high pressure respectively.
The driving method essence that groove type plasma display panel of the present invention (SMPDP) is kept driving circuit is that the positive voltage in keeping driving circuit is kept voltage impulse generator and negative voltage is kept on the driving method of voltage impulse generator, at the earth terminal of the capable driving IC chip of PDP high pressure and high-voltage power supply end field effect transistor M11 in parallel of the capable driving IC chip of PDP high pressure, make the former output terminal of keeping the field effect transistor M6 in the phase voltage control circuit directly and the input end of the field effect transistor T2 in the PDP horizontal high voltage driving IC chip join, the output terminal that changes the field effect transistor M6 in keeping the phase voltage control circuit now into connects the drain electrode of field effect transistor M11 and the input end of the field effect transistor T2 in the PDP horizontal high voltage driving IC chip respectively, the former output terminal of keeping the field effect transistor M3 in the phase voltage control circuit directly and the input end of the field effect transistor T1 in the PDP horizontal high voltage driving IC chip join, the output terminal that changes the field effect transistor M3 in keeping the phase voltage control circuit now into connects the source electrode of field effect transistor M11 and the input end of the field effect transistor T1 in the PDP horizontal high voltage driving IC chip respectively, the negative voltage energy recovers the field effect transistor M9 in the holding circuit, the output terminal of M10 connects fast recovery diode D5 positive pole respectively, the negative pole of D6, fast recovery diode D5 negative pole, the positive pole of D6 connects inductance L 2, and the other end of inductance L 2 connects the source electrode of field effect transistor M4 respectively, the drain electrode of M5, the source electrode of M6; The positive voltage energy recovers the negative pole of the output termination fast recovery diode D3 of the field effect transistor M7 in the holding circuit, the positive pole of the output termination fast recovery diode D4 of field effect transistor M8, the positive pole of the negative pole of fast recovery diode D4 and fast recovery diode D3 connects inductance L 1, and the other end of inductance L 1 connects the drain electrode of field effect transistor M2, the source electrode of M1, the source electrode of M3 respectively.
The pulse driving circuit of keeping at groove type plasma display panel, grooved plasma display screen by the prebasal plate that is printed on column electrode, be printed on the metacoxal plate of row electrode and have the sheet metal of a large amount of mesh or dielectric-slab that the surface is coated with metal conducting layer is formed, display mode is to arrange the experimental process field in the time that shows a two field picture, each son field is by sweep time, keep phase and erasing period and form, finish igniting sweep time successively full frame each pixel; Adopted bipolar energy recovering to keep driving circuit mode and groove type plasma display panel (SMPDP) to keep the driving method of driving circuit in the phase of keeping to groove type plasma display panel, bipolar energy recovering keeps driving circuit according to the positive-negative polarity of keeping pulse, produce the positive and negative pulse waveform that replaces, make the pixel of being lighted a fire keep gas discharge state and luminous in sweep time; The driving method that groove type plasma display panel (SMPDP) is kept driving circuit is just to realize originally, negative energy regains to be kept in the pulse voltage process, former capable IC chip does not stop under the control of Control of Voltage driving circuit will go the working method that the output terminal of IC chip communicates with the high-voltage power supply earth terminal of capable IC chip with the high-voltage power supply end of row IC chip respectively, changing into will be at the earth terminal of the capable driving IC chip of PDP high pressure and high-voltage power supply end field effect transistor M11 in parallel of the capable driving IC chip of PDP high pressure, and be in open mode, reduce the switch number of times of row IC chip in the phase of keeping, avoid the capable IC chip heating situation that high-frequency loss causes, improved the reliability of keeping driving circuit of groove type plasma display panel (SMPDP).
The phase of keeping has adopted the bipolar energy recovering to groove type plasma display panel to keep the driving circuit scheme, two independently charging and discharge circuits are kept in the driving circuit in utilization, inner capacity plate antenna Cp of circuit and energy recover capacitor C 1 or C2 passes through external inductors L series connection, keeping driving circuit is to utilize Cp, L, series connection between C1 or the C2 responds and discharges and recharges to inner capacity plate antenna, promptly the energy that recovers to discharge capacitor C 1 or the C2 from energy is used for to inner capacity plate antenna Cp charging, and the energy that discharges among the capacity plate antenna Cp also temporarily is stored among energy recovery capacitor C 1 or the C2 internally.The realization energy recovers.And produce the positive and negative bipolarity that replaces and keep pulse waveform, make the pixel of being lighted a fire keep gas discharge state and luminous in sweep time, erasing period will utilize a composite wave-shape to finish neutralization to the discharge space charged particle.In the phase of keeping, to just realize originally, negative energy regains to be kept in the pulse voltage process, former capable IC chip does not stop under the control of Control of Voltage driving circuit will go the working method that the output terminal of IC chip communicates with the high-voltage power supply earth terminal of capable IC chip with the high-voltage power supply end of row IC chip respectively, changing into will be at the earth terminal of the capable driving IC chip of PDP high pressure and high-voltage power supply end field effect transistor M11 in parallel of the capable driving IC chip of PDP high pressure, and be in open mode, reduce the switch number of times of row IC chip in the phase of keeping, avoid the capable IC chip heating situation that high-frequency loss causes, improved the reliability of keeping driving circuit of groove type plasma display panel (SMPDP).Erasing period utilizes column electrode to produce compound erasing pulse, and the row electrode all keeps the working method of ground state at the phase of keeping and erasing period.
Fundamental purpose of the present invention is for the high-voltage power supply end of the earth terminal of the capable driving IC chip of PDP high pressure in keeping the phase voltage control circuit and the capable driving IC chip of PDP high pressure field effect transistor M11 in parallel, make the output terminal of the field effect transistor M6 in keeping the phase voltage control circuit connect the source electrode of field effect transistor M11 respectively and the input end of the field effect transistor T2 in the PDP horizontal high voltage driving IC chip joins, the output terminal of field effect transistor M3 connects the drain electrode of field effect transistor M11 respectively and the input end of the field effect transistor T1 in the PDP horizontal high voltage driving IC chip joins; In the phase of keeping, reduce the switch number of times of row IC chip, the capable IC chip of avoiding high-frequency loss the to cause situation of generating heat has improved the reliability of keeping driving circuit of groove type plasma display panel (SMPDP).
Beneficial effect of the present invention:
Because the visual display drive method of existing groove type plasma display panel adopts is that the bipolarity energy regains and keeps voltage pulse circuit, this circuit regains at the positive and negative energy of realization and keeps in the pulse voltage process, row IC chip does not stop under the control of Control of Voltage driving circuit will go the output terminal of IC chip and communicate with the high-voltage power supply earth terminal of capable IC chip with the high-voltage power supply end of row IC chip respectively, therefore row IC chip is bigger in the high-frequency loss of the phase of keeping, cause the heating of capable IC chip, make the reliability decrease of SMPDP plasma display panel.And keep driving circuit at groove type plasma display panel (SMPDP), at the earth terminal of the capable driving IC chip of PDP high pressure and high-voltage power supply end field effect transistor M11 in parallel of the capable driving IC chip of PDP high pressure, make the output terminal of the field effect transistor M6 in keeping the phase voltage control circuit connect the source electrode of field effect transistor M11 respectively and the input end of the field effect transistor T2 in the PDP horizontal high voltage driving IC chip joins, the output terminal of field effect transistor M3 connects the drain electrode of field effect transistor M11 respectively and the input end of the field effect transistor T1 in the PDP horizontal high voltage driving IC chip joins; In the phase of keeping, reduce the switch number of times of row IC chip, the capable IC chip of avoiding high-frequency loss the to cause situation of generating heat has improved the reliability of keeping driving circuit of groove type plasma display panel (SMPDP).
Description of drawings
Fig. 1 is that groove type plasma display panel of the present invention (SMPDP) is kept the driving circuit structure block diagram.
Fig. 2 is the electrical schematic diagram of groove type plasma display panel of the present invention (SMPDP) driving circuit.
Fig. 3 is the structural representation of conductive grid sheet type plasma display board.
Fig. 4 is a conductive grid sheet type plasma display screen electrode relative position distribution synoptic diagram.
VS is just keeping potential pulse voltage among Fig. 2; VXG is the negative potential pulse voltage of keeping.
Embodiment
Keep driving method and circuit is further described below in conjunction with drawings and Examples to of the present invention.
A kind of groove type plasma display panel safeguards that driving method is to make the output terminal of keeping the field effect transistor M6 in the phase voltage control circuit connect the source electrode of field effect transistor M11 and the input end of the field effect transistor T2 in the PDP horizontal high voltage driving IC chip respectively; The drain electrode and the input end of the field effect transistor T1 in the PDP horizontal high voltage driving IC chip, the output terminal of field effect transistor M9, M10 in the negative voltage energy recovery holding circuit that make the output terminal of keeping the field effect transistor M3 in the phase voltage control circuit meet field effect transistor M11 respectively connect the negative pole of fast recovery diode D5 positive pole, D6 respectively, the positive pole of fast recovery diode D5 negative pole, D6 connects inductance L 2, and the other end of inductance L 2 connects the source electrode of field effect transistor M4, the drain electrode of M5, the source electrode of M6 respectively; The positive voltage energy recovers the negative pole of the output termination fast recovery diode D3 of the field effect transistor M7 in the holding circuit, the positive pole of the output termination fast recovery diode D4 of field effect transistor M8, the positive pole of the negative pole of fast recovery diode D4 and fast recovery diode D3 connects inductance L 1, and the other end of inductance L 1 connects the drain electrode of field effect transistor M2, the source electrode of M1, the source electrode of M3 respectively; At the high-voltage power supply end of the earth terminal of the capable driving IC chip of PDP high pressure and the capable driving IC chip of a PDP high pressure field effect transistor M11 in parallel and make it to be in open mode, reduce the switch number of times of row IC chip in the phase of keeping, avoid the capable IC chip heating situation that high-frequency loss causes, keep the reliability of driving circuit with raising; Simultaneously at the high-voltage power supply end field effect transistor M11 in parallel of the earth terminal of the capable driving IC chip of PDP high pressure and the capable driving IC chip of PDP high pressure and make and be in open mode, reduce row IC chip at the switch number of times of the phase of keeping, the capable IC chip of avoiding high-frequency loss the to cause situation of generating heat; Utilize column electrode to produce compound erasing pulse at erasing period at last, make the row electrode all keep ground state in phase of keeping and erasing period.
Keep driving circuit shown in Fig. 1-4.
A kind of groove type plasma display panel (SMPDP) is kept driving circuit, and it is mainly kept voltage impulse generator 2, positive voltage energy by Control of Voltage driving circuit 1, positive voltage and recovers holding circuit 3, negative voltage and keep voltage impulse generator 4, negative voltage energy and recover holding circuit 5, row IC chip protection circuit 6, the capable driving IC chip 7 of PDP high pressure (SMPDP screen) and form.Positive voltage is kept 2 one input ends of voltage impulse generator; the positive voltage energy recovers the input end of holding circuit 3; negative voltage is kept an input end of voltage impulse generator 4; the output terminal that the input end that the negative voltage energy recovers the input end of holding circuit 5 and the capable driving IC chip 7 of PDP high pressure is corresponding with Control of Voltage driving circuit 1 respectively links to each other; the output terminal with Control of Voltage driving circuit 1 links to each other in three input ends of row IC chip protection circuit 6; one links to each other with a output terminal that positive voltage is kept voltage impulse generator 2; another links to each other with the output terminal that negative voltage is kept voltage impulse generator 4; an input end of the capable driving IC chip 7 of output termination PDP high pressure of row IC chip protection circuit 6; the output that the positive voltage energy recovers holding circuit 3 connects another input end that positive voltage is kept voltage impulse generator 2; the output termination negative voltage of negative voltage energy recovery holding circuit 5 is kept another input end of voltage impulse generator 4; positive voltage is kept another output terminal of voltage impulse generator 2 and another output terminal that negative voltage is kept voltage impulse generator 4 also links to each other with capable driving IC chip 7 corresponding input end of PDP high pressure; the X electrode of the output terminal groove type plasma display panel 8 of the capable driving IC chip 7 of PDP high pressure, as shown in Figure 1.
The Control of Voltage pulse that Control of Voltage driving circuit 1 is made up of programmable logic chip (model can be EP1S25F672C7) and field effect transistor chip for driving (model can be IR2113) produces and drives field effect transistor pulse signal " XEFH; XEFL; XHU; XPZH; XPZL; XFU, XNEL, XNEH, XAEH, XAEL, XSU "; correspondence meets each field effect transistor " M1 respectively, M2, M3, M4, M5, M6, M7, M8, M9, M10, M11 " grid; according to different time constants; control the unlatching and the closure time of each field effect transistor, guarantee the realization of the novel tact circuit function of plasma display panel (PDP).
The effect that the positive voltage energy recovers holding circuit 3 and negative voltage energy recovery holding circuit 5 is that needed bipolarity is kept pulse voltage when keeping the SMPDP screen to light; Guarantee the PDP screen after firing pulse, the bright state of quilt point bright spot holding point on the PDP screen.
Positive voltage is kept voltage impulse generator 2 and negative voltage, and to keep voltage impulse generator 4 (be bipolarity energy regain keep voltage pulse circuit 2,4) be the voltage of keeping for variation being provided for the PDP equivalent capacity, and PDP keeps to drive and generally comprises a charge-discharge circuit and a voltage control circuit.And the PDP equivalent capacity is by dull and stereotyped size decision.
The circuit diagram of present embodiment as shown in Figure 2.
Wherein:
Control of Voltage driving circuit 1 mainly is made up of programmable logic chip and field effect transistor chip for driving, the pulse signal that programmable logic chip produces produces the pulse signal of the field effect transistor work in follow-up each circuit that can drive: XEFH after the field effect transistor chip for driving is amplified, XEFL, XHU, XPZH, XPZL, XFU, XNEL, XNEH, XAEH, XAEL, XSU, they are respectively and just keep the Control of Voltage pulse signal, just keeping the voltage control wave that makes zero, open the M3 control wave, the negative voltage control wave that makes zero of keeping, the negative Control of Voltage pulse signal of keeping, open the M6 control wave, positive voltage storage capacitor charging start signal, positive voltage storage capacitor discharge start signal, negative voltage storage capacitor charging start signal, negative voltage storage capacitor discharge start signal, open the M11 control wave.
Positive voltage is kept voltage impulse generator 2 and mainly is made up of field effect transistor M1, M2, M3, M11, positive voltage is kept the input of voltage impulse generator 3 and is drawn the output that the output that connects voltage control circuit 1 is the field effect pipe driving chip from the grid of M1, M2, M3, M11, export XEFH, XEFL, XHU, XSU respectively by the field effect transistor chip for driving under the control of programmable logic chip and give corresponding field effect transistor M1, M2, M3, M11, its output is drawn the earth terminal that connects PDP high drive IC chip 7 respectively and the source terminal of field effect transistor M11 from the source electrode of M3.
The positive voltage energy recovers holding circuit 3 mainly by field effect transistor M3, M7, M8, M11, inductance L 1, diode D3, D4, capacitor C 1 is formed, the positive voltage energy recovers the input of holding circuit 4 from M3, M7, M8, the grid of M11 is drawn the output that the output that connects voltage control circuit 1 is the field effect pipe driving chip, under the control of programmable logic chip, export XHU respectively by the field effect transistor chip for driving, XNEL, XNEH, the XSU pulse signal is given corresponding field effect transistor M4, M7, M8, M11, its output is drawn from the end of L1 and is connect positive voltage respectively and keep field effect transistor M2 the voltage impulse generator 2, the source electrode of the drain electrode of M3 and field effect transistor M1 is drawn the earth terminal that connects PDP high drive IC chip 7 respectively and the source terminal of field effect transistor M11 from the source electrode of field effect transistor M3 again.
Negative voltage is kept voltage impulse generator 4 and mainly is made up of field effect transistor M4, M5, M6, M11, negative voltage is kept the input of voltage impulse generator 4 and is drawn the output that the output that connects voltage control circuit 1 is the field effect pipe driving chip from the grid of M4, M5, M6, M11, export XPZH, XPZL, XFU, XSU respectively by the field effect transistor chip for driving under the control of programmable logic chip and give corresponding field effect transistor M4, M5, M6, M11, its output is drawn the power end that connects PDP high drive IC chip 7 respectively and the drain electrode end of field effect transistor M11 from the drain electrode of M6.
The negative voltage energy recovers holding circuit 5 mainly by field effect transistor M6, M9, M10, M11, inductance L 2, diode D5, D6, capacitor C 2 is formed, the negative voltage energy recovers the input of holding circuit 4 from M6, M9, M10, the grid of M11 is drawn the output that the output that connects voltage control circuit 1 is the field effect pipe driving chip, under the control of programmable logic chip, export XFU respectively by the field effect transistor chip for driving, XAEH, XAEL, the XSU pulse signal is given corresponding field effect transistor M6, M9, M10, M11, its output is drawn from the end of L2 and is connect negative voltage respectively and keep field effect transistor M4 the voltage impulse generator 4, the drain electrode of the source electrode of M5 and field effect transistor M5.Draw the power end that connects PDP high drive IC chip 7 respectively and the drain electrode end of field effect transistor M11 from the drain electrode of field effect transistor M6 again.
Row IC chip protection circuit 6 mainly is made up of field effect transistor M11; the input of row IC chip protection circuit 6 is drawn the output that the output that connects voltage control circuit 1 is the field effect pipe driving chip from the grid of M11; export the XSU pulse signal respectively by the field effect transistor chip for driving under the control of programmable logic chip and give corresponding field effect transistor M11, the output source electrode of field effect transistor M11 connects the earth terminal of PDP high drive IC chip 7 and the source terminal of field effect transistor M3 respectively.Drain electrode connects the power end of PDP high drive IC chip 7 and the drain electrode end of field effect transistor M6 respectively.
The course of work of the present invention is:
The principle of work that groove type plasma display panel (SMPDP) is kept the driving circuit driving method is as follows:
In the phase of keeping, adopted bipolar energy recovering to keep driving circuit, made that the power consumption when the groove type plasma display panel image shows is minimized.
Keep to drive and include two independently charging and discharge processes.Inner capacity plate antenna Cp of circuit and energy recover capacitor C 1 or C2 passes through external inductors L series connection, keeping driving circuit is to utilize the inner capacity plate antenna Cp of circuit, external inductors L, energy recovers series connection between capacitor C 1 or the C2 and responds and discharge and recharge to inner capacity plate antenna, promptly the energy that recovers to discharge capacitor C 1 or the C2 from energy is used for to inner capacity plate antenna Cp charging, and the energy that discharges among the capacity plate antenna Cp also temporarily is stored among energy recovery capacitor C 1 or the C2 internally.Utilize this method to realize that energy recovers exactly.
The course of work that bipolar energy recovering is kept driving circuit is as follows:
At first keep in the phase process whole, by voltage control circuit field effect transistor M11 is in opening stage always, guarantee to be in short-circuit condition between the power end of PDP high drive IC chip and the earth terminal, and the output terminal of control PDP high drive IC communicates with the high-voltage power supply of PDP high drive IC or the power ground end of PDP high drive IC communicates.To reduce power end and the voltage difference between the earth terminal and the switch number of times of PDP high drive IC chip.
Positive voltage energy recovery sustain driving circuit discharges and recharges capacity plate antenna Cp and is divided into 4 processes:
Before t0, field effect transistor M2, M3 are opened, and other Mos switches all are switched off.Output voltage V p equals 0.
In the t0-t1 process, at first M2 is switched off, and M3, M8 are opened, except that M11 and other Mos switches all are switched off, so just formed a LC loop.The voltage of just keeping on the pulse voltage storage capacitor C1 equals Vs/2, and by 1 pair of Cp charging of inductance L, last Vp is charged to Vs in the t1-t2 process.After output voltage V p equals Vs, open M1 earlier, turn off M8 again.
In the t2-t3 process, the Cp discharge, switch M1 turns off, and M7 opens.The discharge current of Cp flow through M3, L1, diode D3 and M7 arrive C1, and C1 just is recharged like this.Cp discharges always and equals Vs/2 up to output voltage V p.
In the t3-t4 process, M7 turns off, and M2 opens.And other Mos on off states are all constant, and output voltage V p equals 0.
The negative voltage energy recovering holding circuit discharged and recharged Cp is divided into 4 processes equally:
Before t5, field effect transistor M4, M6 are opened, and other Mos switches all are switched off.Output voltage V p equals 0.
In the t4-t5 process, at first M4 is switched off, and M10 is opened, except that M11 and other Mos switches all are switched off, so just formed a LC loop.The negative voltage of keeping on the pulse voltage storage capacitor C2 equals V
XG/ 2, by 2 pairs of Cp chargings of inductance L, last output voltage V p is charged to V in the T5-T6 process
XGP equals V in output voltage V
XGAfter, open M5 earlier, turn off M10 again.
In the t6-t7 process, the Cp discharge, switch M5 turns off, and M9 opens.The discharge current of Cp flow through M6, L2, diode D5 and M9 arrive C2, and C2 just is recharged like this.Cp discharges always and equals V up to output voltage V p
XG/ 2.
In the t7-t0 process, turn off M9, open M4, and other Mos on off states are all constant, output voltage V p equals 0.
Above-mentioned Cp is equivalent to the equivalent capacity of entire display panel.
Claims (8)
1, a kind of groove type plasma display panel is safeguarded driving method, it is characterized in that: make the output terminal of keeping the field effect transistor M6 in the phase voltage control circuit connect the drain electrode of field effect transistor M11 and the input end of the field effect transistor T2 in the PDP horizontal high voltage driving IC chip respectively; Make the output terminal of keeping the field effect transistor M3 in the phase voltage control circuit connect the source electrode of field effect transistor M11 and the input end of the field effect transistor T1 in the PDP horizontal high voltage driving IC chip respectively; The output terminal of field effect transistor M9, M10 in the negative voltage energy recovery holding circuit connects the negative pole of fast recovery diode D5 positive pole, D6 respectively, the positive pole of fast recovery diode D5 negative pole, D6 connects inductance L 2, and the other end of inductance L 2 connects the source electrode of field effect transistor M4, the drain electrode of M5, the source electrode of M6 respectively; The positive voltage energy recovers the negative pole of the output termination fast recovery diode D3 of the field effect transistor M7 in the holding circuit, the positive pole of the output termination fast recovery diode D4 of field effect transistor M8, the positive pole of the negative pole of fast recovery diode D4 and fast recovery diode D3 connects inductance L 1, and the other end of inductance L 1 connects the drain electrode of field effect transistor M2, the source electrode of M1, the drain electrode of M3 respectively; At the high-voltage power supply end of the earth terminal of the capable driving IC chip of PDP high pressure and the capable driving IC chip of a PDP high pressure field effect transistor M11 in parallel and make it to be in open mode, reduce the switch number of times of row IC chip in the phase of keeping, avoid the capable IC chip heating situation that high-frequency loss causes, keep the reliability of driving circuit with raising.Utilize column electrode to produce compound erasing pulse at erasing period at last, make the row electrode all keep ground state in phase of keeping and erasing period.
2; a kind of groove type plasma display panel of the described method of claim 1 that adopts is kept driving circuit; it is characterized in that by Control of Voltage driving circuit (1); positive voltage is kept voltage impulse generator (2); the positive voltage energy recovers holding circuit (3); negative voltage is kept voltage impulse generator (4); the negative voltage energy recovers holding circuit (5); row IC chip protection circuit (6); the capable driving IC chip of PDP high pressure (7) is formed; positive voltage is kept (2) input ends of voltage impulse generator; the positive voltage energy recovers the input end of holding circuit (3); negative voltage is kept an input end of voltage impulse generator (4); the negative voltage energy recovers the input end of holding circuit (5); the input end of row IC chip protection circuit (6) and corresponding with Control of Voltage driving circuit (1) the respectively output terminal of an input end of the capable driving IC chip of PDP high pressure (7) link to each other; an output termination positive voltage of row IC chip protection circuit (6) is kept the output terminal of voltage impulse generator (2) and an input end of the capable driving IC chip of PDP high pressure (7); another output termination negative voltage of row IC chip protection circuit (6) is kept the output terminal of voltage impulse generator (4) and another input end of the capable driving IC chip of PDP high pressure (7); the output that the positive voltage energy recovers holding circuit (3) connects another input end that positive voltage is kept voltage impulse generator (2); the output termination negative voltage of negative voltage energy recovery holding circuit (5) is kept another input end of voltage impulse generator (4); positive voltage is kept the output terminal of voltage impulse generator (2) and output terminal that negative voltage is kept voltage impulse generator (4) also links to each other the output terminal access slot type plasma display panel (8) of the capable driving IC chip of PDP high pressure (7) with the capable driving IC chip of PDP high pressure (7) corresponding input end.
3, groove type plasma display panel according to claim 2 is kept driving circuit, it is characterized in that described Control of Voltage driving circuit (1) is made up of programmable logic chip and field effect transistor chip for driving, the pulse signal that programmable logic chip produces produces the pulse signal of the field effect transistor work in follow-up each circuit that can drive: XEFH after the field effect transistor chip for driving is amplified, XEFL, XHU, XPZH, XPZL, XFU, XNEL, XNEH, XAEH, XAEL, XSU, they are respectively and just keep the Control of Voltage pulse signal, just keeping the voltage control wave that makes zero, open field effect transistor M3 control wave, the negative voltage control wave that makes zero of keeping, the negative Control of Voltage pulse signal of keeping, open field effect transistor M6 control wave, positive voltage storage capacitor charging start signal, positive voltage storage capacitor discharge start signal, negative voltage storage capacitor charging start signal, negative voltage storage capacitor discharge start signal, open field effect transistor M11 control wave.
4, groove type plasma display panel according to claim 2 is kept driving circuit, it is characterized in that described positive voltage keeps voltage impulse generator (2) by field effect transistor M1, M2, M3 forms, positive voltage is kept the input of voltage impulse generator (2) from field effect transistor M1, M2, the grid of M3 is drawn the output that the output that connects voltage control circuit 1 is the field effect pipe driving chip, under the control of programmable logic chip, export XEFH respectively by the field effect transistor chip for driving, XEFL, XHU gives corresponding field effect transistor M1, M2, M3, its output is drawn the earth terminal that connects PDP high drive IC chip (7) respectively and the source terminal of field effect transistor M11 from the source electrode of field effect transistor M3.
5, groove type plasma display panel according to claim 2 is kept driving circuit, it is characterized in that described positive voltage energy recovers holding circuit (3) by field effect transistor M3, M7, M8, inductance L 1, diode D3, D4, capacitor C 1 is formed, the positive voltage energy recovers the input of holding circuit (3) from field effect transistor M3, M7, it is the output of field effect pipe driving chip that the grid of M8 is drawn the output that connects Control of Voltage driving circuit (1), under the control of programmable logic chip, export XHU respectively by the field effect transistor chip for driving, XNEL, the XNEH pulse signal is given corresponding field effect transistor M3, M7, M8, the output that the positive voltage energy recovers holding circuit (3) is drawn the negative pole that meets diode D3 respectively and the positive pole of diode D4 from the source electrode of the drain electrode of field effect transistor M7 and field effect transistor M8, the tie point of the negative pole of the positive pole of diode D3 and diode D4 connects an end of inductance L 1, the other end of inductance L 1 is drawn and is met field effect transistor M2 respectively, the source electrode of the drain electrode of M3 and field effect transistor M1 is drawn the earth terminal that connects PDP high drive IC chip (7) respectively and the source terminal of field effect transistor M11 from the source electrode of field effect transistor M3 again.
6, groove type plasma display panel according to claim 2 is kept driving circuit, it is characterized in that described negative voltage keeps voltage impulse generator (4) by field effect transistor M4, M5, M6 forms, negative voltage is kept the input of voltage impulse generator (4) from field effect transistor M4, M5, it is the output of field effect pipe driving chip that the grid of M6 is drawn the output that connects voltage control circuit (1), under the control of programmable logic chip, export XPZH respectively by the field effect transistor chip for driving, XPZL, XFU gives corresponding field effect transistor M4, M5, M6, its output is drawn the power end that connects PDP high drive IC chip (7) respectively and the drain electrode end of field effect transistor M11 from the drain electrode of field effect transistor M6.
7, groove type plasma display panel according to claim 2 is kept driving circuit, it is characterized in that described negative voltage energy recovers holding circuit (5) by field effect transistor M6, M9, M10, inductance L 2, diode D5, D6, capacitor C 2 is formed, the negative voltage energy recovers the input of holding circuit (5) from field effect transistor M6, M9, it is the output of field effect pipe driving chip that the grid of M10 is drawn the output that connects Control of Voltage driving circuit (1), under the control of programmable logic chip, export XFU respectively by the field effect transistor chip for driving, XAEH, the XAEL pulse signal is given corresponding field effect transistor M6, M9, M10, field effect transistor M9, the output of M10 meets diode D5 respectively, D6, diode D5, the output of D6 connects an end of inductance L 2, the other end of inductance L 2 is drawn and is met field effect transistor M4 respectively, the drain electrode of the source electrode of M6 and field effect transistor M5 is drawn the power end that connects PDP high drive IC chip (7) respectively and the drain electrode end of field effect transistor M11 from the drain electrode of field effect transistor M6 again.
8; groove type plasma display panel according to claim 2 is kept driving circuit; it is characterized in that described capable IC chip protection circuit (6) is made up of field effect transistor M11; it is the output of field effect pipe driving chip that the input of row IC chip protection circuit (6) is drawn the output that connects voltage control circuit (1) from the grid of field effect transistor M11; under the control of programmable logic chip, export the XSU pulse signal respectively by the field effect transistor chip for driving and give corresponding field effect transistor M11; the output source electrode of field effect transistor M11 connects the source terminal of the earth terminal and the field effect transistor M3 of PDP high drive IC chip (7) respectively, and drain electrode connects the power end of PDP high drive IC chip (7) and the drain electrode end of field effect transistor M6 respectively.
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| CNB2007100212912A CN100530298C (en) | 2007-04-26 | 2007-04-26 | Slot type plasma display panel holding driving method and circuit thereof |
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| CNB2007100212912A CN100530298C (en) | 2007-04-26 | 2007-04-26 | Slot type plasma display panel holding driving method and circuit thereof |
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