CN100525116C - Serial-to-parallel conversion circuit, and semiconductor display device employing the same - Google Patents

Abstract

In a serial-to-parallel conversion (SPC) circuit for digital data which converts the digital data serially inputted, into parallel digital data, and which outputs the parallel digital data; clock signals at frequencies which are, at the highest, 1/2 of the frequency of the input digital data are employed for operating the SPC circuit, whereby the SPC circuit is improved in power dissipation, stability and reliability.

Description

The semiconductor display device of serial-to-parallel change-over circuit and this change-over circuit of use

The application is to be January 28, application number in 2000 the dividing an application for the application of " serial-to-parallel change-over circuit and use the semiconductor display device of this change-over circuit " that be 200410055695X, denomination of invention the applying date.

Technical field

The present invention relates to serial digital data is converted to serial-to-parallel conversion (SPC) circuit of parallel digital data.The invention still further relates to the semiconductor device that comprises this SPC circuit.

Background technology

Input signal is that the example of the semiconductor device of numerical data is an active-matrix liquid crystal display device.In recent years, active-matrix liquid crystal display device is made of a plurality of TFTs (thin-film transistor), and TFT is formed by polysilicon, and this active-matrix liquid crystal display device is unitarily formed active matrix circuit that is useful on displayed image and the drive circuit that is used to drive this active matrix circuit.

The serial-to-parallel that is used for numerical data is changed the input (hereinafter referred to as " input digital data ") of (SPC) circuit receiving digital data as input signal, and will (pulse length can be extended any multiple by the temporary transient pulse length that prolongs input digital data, but prevailing is to prolong n doubly, and wherein alphabetical n represents that minimum is 2 natural number) numerical data of revising flows to the source signal line drive circuit of active-matrix liquid crystal display device.The pulse length of input digital data temporarily is extended for n and is not doubly had other influence, just the frequency of input digital data can be reduced to 1/n.

The SPC circuit that is used for numerical data has importance as described below.The numerical data that inputs to active-matrix liquid crystal display device is usually at tens MHz, but for meeting recently more high definition, the more high-resolution and the demand of multi-grayscale more, can be in the numerical data of 100 and tens MHz by unitized.

In any case, be included in the performance that TFT in the source signal line drive circuit of active-matrix liquid crystal display device has the numerical data that is not enough to handle this upper frequency, and they can not be operated or have any problem on reliability.Therefore the frequency of supplied with digital signal must be reduced to the degree that the source signal line drive circuit can ideally be operated.About this point, the function that is used for the SPC circuit of numerical data is to reduce the frequency of input digital data.Incidentally, compare with the source signal line drive circuit, the scale of SPC circuit that is used for numerical data is less, and the clock signal in the SPC circuit is difficult for becoming " blunt " (as the signal delay in the rising or the decline of clock signal pulse), therefore can be at higher speed drive SPC circuit.

As mentioned above, the SPC circuit that is used for numerical data can be driven quickly than source signal line drive circuit etc.But for meet recently concerning high definition more, more high-resolution and more the reliability and stability of the demand of multi-grayscale the faster operation of SPC circuit say so disadvantageous in a way.

The example of the SPC circuit that is used for numerical data that has been used by the inventor is the open disclosed SPC circuit that is used for numerical data of No.11-231798 (1999) of Japanese patent application that transfers the same assignee of the application up to now.Corresponding U.S. Patent Application Serial 09/206297 of this Japanese patent application and the open No.0921517A of european patent application special permission.

The described example SPC circuit that is used for numerical data need be in the clock signal of the frequency identical with the frequency of input digital data for its operation.For example, for the serial input digital data with 80MHz converts eight parallel digital datas to, carry the clock signal of 80MHz for usually this SPC circuit.It is this that to operate on power consumption, stability, the reliability etc. be problematic.

Summary of the invention

The present invention makes in view of the above problems, and the purpose of this invention is to provide new serial-to-parallel conversion (SPC) circuit that is used for numerical data, and the power consumption of this circuit, stability and reliability are all excellent.

Brief description is according to SPC circuit of the present invention and the structure that comprises the semiconductor display device of this SPC circuit.

According to the present invention, serial-to-parallel conversion (SPC) circuit that is used for numerical data will be (m2 with the digital data conversion of mHz serial input ^-y) Hz 2 ^yParallel digital data also exports 2 ^yParallel digital data (wherein alphabetical m represents positive number, and alphabetical y represents natural number) is used for a plurality of clock signal operations of the serial-to-parallel change-over circuit of numerical data with the highest (m/2) Hz.

In this way, SPC circuit of the present invention allows that being used in the highest is the clock signal operation of 1/2 frequency of the frequency of the numerical data that will import.

In addition, in this manual, often limit the frequency of clock signal and digital signal, but they should be the approximate frequencies that covers equivalent frequency.

And according to the present invention, serial-to-parallel conversion (SPC) circuit that is used for numerical data will be (m2 with the digital data conversion of mHz serial input ^-y) Hz 2 ^yParallel digital data also exports 2 ^yParallel digital data (wherein alphabetical m represents positive number, and alphabetical y represents natural number), the serial-to-parallel change-over circuit that is used for numerical data is with the highest (m/2) Hz and minimum (m2 ^-y) a plurality of clock signals operation of Hz.

In addition, according to the present invention: serial-to-parallel conversion (SPC) circuit that is used for numerical data will be (m2 with every digital data conversion of the x bit digital data of mHz serial input ^-y) Hz 2 ^yParallel digital data also exports 2 ^yParallel digital data (wherein alphabetical m represents positive number, and alphabetical x and y represent natural number); The serial-to-parallel change-over circuit that is used for numerical data comprises x SPC/ position circuit, every numerical data of described x bit digital data inputs to this x SPC/ position circuit, each described SPC position circuit comprises the first order to y level circuit, and y level circuit is 2 of the serial input ^Y-1The frequency of numerical data reduces half, and this 2 ^Y-1Digital data conversion is 2 ^yParallel digital data.

In addition, according to the present invention: serial-to-parallel conversion (SPC) circuit that is used for numerical data is (m2 to every digital data conversion of the x bit digital data of importing with the mHz serial ^-y) Hz 2 ^yParallel digital data also exports 2 ^yParallel digital data (wherein alphabetical m represents positive number, and alphabetical x and y represent natural number); The serial-to-parallel change-over circuit that is used for numerical data comprises x SPC/ position circuit, every numerical data of described x bit digital data inputs to this x SPC/ position circuit, each described SPC/ position circuit comprises the elementary cell of quantity by formula given below (1) expression, quantity is half by the frequency inverted of the numerical data of each serial input of the described elementary cell of formula (1) expression, and the digital data conversion that serial is imported is two parallel digital datas.

$\underset{k=1}{\overset{y}{\mathrm{\Σ}}}{2}^{k-1}---\left(1\right)$

In addition, according to the present invention: a kind of semiconductor display device has the serial-to-parallel change-over circuit that pixel TFTs wherein is arranged in the active matrix circuit of rectangular, the source signal line drive circuit that drives this active matrix circuit and gate signal line drive circuit and is used for numerical data, and wherein this serial-to-parallel change-over circuit that is used for numerical data is (m2 to the digital data conversion with mHz serial input ^-y) Hz 2 ^yParallel digital data also exports 2 ^yParallel digital data (wherein alphabetical m represents positive number, and alphabetical y represents natural number); This semiconductor display device is operated with a plurality of clock signals of the highest (m/2) Hz.

In addition, according to the present invention: a kind of semiconductor display device has the serial-to-parallel change-over circuit that pixel TFT wherein is arranged in the active matrix circuit of rectangular, the source signal line drive circuit that drives this active matrix circuit and gate signal line drive circuit and is used for numerical data, and wherein this serial-to-parallel change-over circuit that is used for numerical data is (m2 to the digital data conversion with mHz serial input ^-y) Hz 2 ^yParallel digital data also exports 2 ^yParallel digital data (wherein alphabetical m represents positive number, and alphabetical y represents natural number); This semiconductor display device the highest (m/2) Hz and minimum (m2 ^-y) a plurality of clock signals operation of Hz.

In addition, according to the present invention: a kind of semiconductor display device has the serial-to-parallel change-over circuit that pixel TFTs wherein is arranged in the active matrix circuit of rectangular, the source signal line drive circuit that drives this active matrix circuit and gate signal line drive circuit and is used for numerical data, and wherein this serial-to-parallel change-over circuit that is used for numerical data is (m2 to the every digital data conversion with the x bit digital data of mHz serial input ^-y) Hz 2 ^yParallel digital data is also exported this parallel digital data (wherein alphabetical m represents positive number, and alphabetical y represents natural number); The serial-to-parallel change-over circuit that is used for numerical data comprises x SPC/ position circuit, every numerical data of described x bit digital data inputs to this x SPC/ position circuit, each described SPC/ position circuit comprises the first order to y level circuit, and y level circuit is 2 of the serial input ^Y-1The frequency of numerical data reduces half, and this 2 ^Y-1Digital data conversion is 2 ^yParallel digital data.

In addition, according to the present invention: a kind of semiconductor display device has the serial-to-parallel change-over circuit that pixel TFT wherein is arranged in the active matrix circuit of rectangular, the source signal line drive circuit that drives this active matrix circuit and gate signal line drive circuit and is used for numerical data, and wherein this serial-to-parallel change-over circuit that is used for numerical data is (m2 to everybody digital data conversion with the x bit digital data of mHz serial input ^-y) Hz 2 ^yParallel digital data also exports 2 ^yParallel digital data (wherein alphabetical m represents positive number, and alphabetical y represents natural number); The serial-to-parallel change-over circuit that is used for numerical data comprises x SPC/ position circuit, every numerical data of described x bit digital data inputs to this x SPC/ position circuit, each described SPC/ position circuit comprises the elementary cell of quantity by formula given below (1) expression, quantity is reduced to 1/2 by the frequency of the numerical data of each serial input of the described elementary cell of formula (1) expression, and the digital data conversion that serial is imported is two parallel digital datas.

$\underset{k=1}{\overset{y}{\mathrm{\Σ}}}{2}^{k-1}---\left(1\right)$

Description of drawings

Fig. 1 is the calcspar of serial-to-parallel conversion (SPC) circuit that is used for numerical data among the embodiment 1;

Fig. 2 is the clock generator in the SPC circuit of expression embodiment 1 and the schematic diagram of the circuit layout of SPC/ position circuit;

Fig. 3 is the schematic diagram of circuit layout of the SPC elementary cell in the SPC circuit of expression embodiment 1;

Fig. 4 A, 4B and 4C are the schematic diagrames of circuit layout of the D-latch cicuit in the SPC circuit of expression embodiment 1;

Fig. 5 is the sequential chart of operation that is used to explain the SPC circuit of embodiment 1;

Fig. 6 is the calcspar that is used for serial-to-parallel conversion (SPC) circuit of numerical data among the embodiment 2:

Fig. 7 is the clock generator in the SPC circuit of expression embodiment 2 and the schematic diagram of the circuit layout of SPC/ position circuit;

Fig. 8 is that the numerical data in the SPC circuit of expression embodiment 2 rearranges the schematic diagram of the circuit layout of switch;

Fig. 9 is the sequential chart of operation that is used to explain the SPC circuit of embodiment 2;

Figure 10 adopts the serial-to-parallel that is used for numerical data according to the present invention to change the calcspar of the active-matrix liquid crystal display device of (SPC) embodiment of circuit 3;

Figure 11 A-11E is the cutaway view of example of the technology of the expression active-matrix liquid crystal display device of making embodiment 3;

Figure 12 A, 12B and 12C are the cutaway views of example of the technology of the expression active-matrix liquid crystal display device of making embodiment 3;

Figure 13 A, 13B and 13C are the cutaway views of example of the technology of the expression active-matrix liquid crystal display device of making embodiment 3;

Figure 14 A, 14B and 14C are the cutaway views of example of the technology of the expression active-matrix liquid crystal display device of making embodiment 3;

Figure 15 A-15E is the cutaway view of example of the technology of the expression active-matrix liquid crystal display device of making embodiment 4;

Figure 16 A, 16B and 16C are the schematic diagrames of example of the technology of the expression active-matrix liquid crystal display device of making embodiment 4;

Figure 17 A and 17B are respectively the example schematic diagrames of representing wherein to be equipped with the projecting apparatus of the active matrix type semiconductor display device that adopts SPC circuit of the present invention;

Figure 18 A-18E is respectively an example schematic diagram of representing wherein to be equipped with the electronic equipment of the active matrix type semiconductor display device that adopts SPC circuit of the present invention;

Figure 19 is the oscillogram of expression by the work wave of the SPC circuit of the present invention of the manufacturing of the manufacturing process among the embodiment 3;

Figure 20 A, 20B and 20C are respectively the oscillogram of expression by the work wave of the SPC circuit of the present invention of the manufacturing of the manufacturing process among the embodiment 3;

Figure 21 is the curve chart of expression TFT characteristic;

Figure 22 represents to comprise the demonstration example according to the active-matrix liquid crystal display device of the SPC circuit that is used for digital of digital video data of the present invention;

Figure 23 represents to adopt the demonstration example that respectively comprises according to the projecting apparatus of the active-matrix liquid crystal display device of the SPC circuit that is used for digital of digital video data of the present invention;

Figure 24 is the curve chart that applies voltage-transmissison characteristic that the no threshold value of expression is mixed anti ferroelectric liquid crystal;

Figure 25 A and 25B are respectively top plan view and the cutaway view (embodiment 9) of expression according to the structure of the example of the EL plate of active array type of the present invention;

Figure 26 A and 26B are respectively the top plan view and the cutaway views (embodiment 10) of structure of another example of expression active matrix EL plate of the present invention;

Figure 27 is the cutaway view (embodiment 11) of another example of active matrix EL plate of the present invention;

Figure 28 A and 28B are respectively the top plan view and the circuit diagrams (embodiment 11) of the example of the active matrix EL plate shown in Figure 27;

Figure 29 is the cutaway view (embodiment 12) of the another example of active matrix EL plate of the present invention; With

Figure 30 A, 30B are respectively the circuit diagrams (embodiment 13) of explaining the different examples of active matrix EL plate of the present invention with 30C.

Embodiment

Now introduce serial-to-parallel conversion (SPC) circuit that is used for numerical data according to of the present invention in conjunction with the embodiments.But SPC circuit of the present invention should not be limited to the following examples.

(embodiment 1)

Change an embodiment of (SPC) circuit below with reference to Fig. 1 introduction serial-to-parallel that is used for numerical data according to the present invention.In Fig. 1, the circuit layout of the SPC circuit that is used for 8 bit digital data in this example is shown with the form of calcspar.The SPC circuit that is used for 8 bit digital data in this example becomes parallel to 8 (DIGITAL DATA-1 (LSB) is to DIGITAL DATA-8 (MSB)) digital data conversion with 80MHz serial input, and exports eight parallel digital datas of every 10MHz.

In this routine SPC circuit shown in Figure 1, symbol CLK_GEN_L and CLK_GEN_R represent clock generating circuit, and each clock generating circuit produces a plurality of clock signals that the SPC circuit working needs.This clock generating circuit CLK_GEN_L and CLK_GEN_R can be the parts of SPC circuit of the present invention or its external circuit.In this example, the clock signal of 40MHz (CK40) and be input to each clock generating circuit CLKGEN_L and the CLK_GEN_R as the inversion clock signal (CK40B) of the inversion signal of last signal outside from the SPC circuit.In this mode, the frequency of clock signal can be the numerical data of outside input frequency (being 80MHz in this example) 1/2.This is one of characteristics of SPC circuit of the present invention.

In addition, reset signal (RES) is presented to clock generating circuit CLK_GEN_L and CLK_GEN_R.The operation of the SPC circuit that this is routine is to import startup by the pulse of reset signal.

Produce the clock signal of 20MHz and 10MHz on the basis of the 40MHz clock signal that each clock generating circuit CLK_GEN_L and CLK_GEN_R externally import, and the SPC/ position circuit that the clock signal that produces and its inversion clock signal conveys will be explained to the back.Transmit the clock signal of 40MHz from the output node CK40_O of each clock generator CLK_GEN_L shown in Figure 1 and CLK_GEN_R, and transmit its inversion clock signal from output node CK40B_O.In addition, the clock signal of carrying 20MHz from the output node CK20_O of each generator, and carry its inversion clock signal from output node CK20B_O.In addition, from the clock signal that the output node CK10_O of each generator transmits 10MHz, transmit its inversion clock signal from output node CK10B_O.

Incidentally, adopt two clock generator CLK_GEN_L and CLK_GEN_R in this example, but also can only adopt one of them.

SPC/ position circuit is the circuit of a position of corresponding numerical data.In this example, 8 SPC/ position circuit (SPC/ position-1 circuit is to SPC/ position-8 circuit) have been comprised at the SPC circuit that is used for numerical data.Because the numerical data that this routine SPC processing of circuit is 8 (DIGITALDATA-1 (LSB) is to DIGITALDATA-8 (MSB)), so the bit data of numerical data (DIGITALVIDEO-1 is to DIGITALVIDEO-8) is input to SPC/ position-1 circuit respectively to SPC/ position-8 circuit.

On clock signal (CK40, CK40B, CK20, CK20B, CK10 and the CK10B) basis of carrying from clock generator CLK_GEN, SPC/ position circuit will become parallel and export 8 parallel digital datas with 10MHz with the digital data conversion of every 80MHz serial input.

Here, introduce SPC/ position circuit with reference to Fig. 2 as this routine SPC circuit part.Fig. 2 represents clock generator CLK_GEN_L and SPC/ position-1 circuit in this routine SPC circuit, and wherein the lowest order of numerical data (DIGITAL DATA-1) is input to SPC/ position-1 circuit.Incidentally, SPC/ position-1 circuit with shown in Figure 2 is identical basically for the SPC/ position circuit of difference input digital data (DIGITAL DATA-2 is to DIGITAL DATA-8).

As shown in Figure 2, in this example, SPC/ position-1 circuit has first order circuit (1 grade), second level circuit (2 grades) and tertiary circuit (3 grades).

SPC/ position-1 circuit comprises seven SPC elementary cells.More particularly, first order circuit comprises a SPC elementary cell, and second level circuit comprises two SPC elementary cells, and tertiary circuit comprises four SPC elementary cells.

The clock signal of the 40MHz (CK40) of self-clock generator CLK_GEN_L or CLKGEN_R and its inversion clock signal (CK40B) since the SPC elementary cell of first order circuit is carried.The numerical data of 80MHz is input to the input node (IN) of the SPC elementary cell of the first order from the outside of SPC circuit.The 8-bit digital data of the 80MHz of lowest order (DIGITAL DATA-1) are input to the input node (IN) of SPC elementary cell of the first order circuit of SPC/ position-1 circuit shown in Figure 2 from the outside.Each corresponding input node (IN) of two SPC elementary cells that the numerical data of 40MHz is transferred to second level circuit from the output node OUT1 and the OUT2 of the SPC elementary cell of first order circuit.

The clock signal of the 20MHz (CK20) of self-clock generator CLK_GEN_L or CLK_GEN_R and its inversion clock signal (CK20B) since two SPC elementary cells of second level circuit are transferred.Each corresponding input node (IN) of four elementary cells that the 20MHz numerical data is transported to tertiary circuit from the output node OUT1 and the OUT2 of the SPC elementary cell of second level circuit.

Four SPC elementary cells of tertiary circuit are transferred with 10MHz (CK10) clock signal and its inversion clock signal (CK10B) from clock generator CLK_GEN_L or CLK_GEN_R.The numerical data of carrying 10MHz from the output node OUT1 and the OUT2 of each SPC elementary cell of tertiary circuit.

In addition, also in the circuit of SPC/ position-8, carry out operation same as described above, therefore from the output node OUT1 of each SPC elementary cell of the tertiary circuit of all SPC/ position circuit and the numerical data that OUT2 transmits 10MHz at SPC/ position-2 circuit of input residue seven bit digital data (DIGITALDATA-2 is to DIGITALDATA-8) respectively.

Here, introduce the circuit layout of the SPC elementary cell of the SPC/ position circuit that constitutes this routine SPC circuit with reference to Fig. 3.In Fig. 3, the circuit layout of a SPC elementary cell is shown with block diagram form.In this example, any SPC elementary cell all has layout as shown in Figure 3.But, because the frequency of operation difference of the SPC elementary cell of circuit at different levels, so they preferably are made of the transistor that different qualities is arranged.

In SPC elementary cell shown in Figure 3, symbol H-DL and L-DL represent to be called the latch cicuit of " D-latch cicuit ".Latch cicuit H-DL is the D-latch cicuit that pins input signal (IN) when the input and latch signal is Hi (height), and latch cicuit L-DL is the D-latch cicuit that pins input signal (IN) when the input and latch signal is Lo (low).

Here, introduce D latch cicuit H-DL in this example and the circuit layout of L-DL with reference to Fig. 4 A, 4B and 4C.But also allow and adopt the D latch cicuit beyond those circuit shown in Fig. 4 A, 4B and the 4C.

D-latch cicuit H-DL is shown among Fig. 4 A, and D-latch cicuit L-DL is shown among Fig. 4 B.Each latch cicuit H-DL and L-DL comprise two clock negative circuits and a negative circuit." clock negative circuit " is the negative circuit of working on the clock signal of input and its inversion clock basis of signals.The circuit layout of the clock negative circuit in this example is shown among Fig. 4 C.

Clock signal (CK) and its inversion clock signal (CKB) are input among each D-latch cicuit H-DL and the L-DL.In this example, the latch signal among clock signal (CK) corresponding D-latch cicuit H-DL and the L-DL.In addition, when clock signal (CK) was Hi, D-latch cicuit H-DL pinned from the input signal of input node IN reception and from output node OUT and carries output signal.On the other hand, when clock signal (CK) was Lo, D-latch cicuit L-DL pinned from the input signal of input node IN reception and from output node OUT and carries output signal.

Here, see figures.1.and.2 and the sequential chart of Fig. 5 is introduced the operation of the SPC circuit that is used for numerical data in this example in detail.In the sequential chart of Fig. 5, show as the 40MHz clock signal (CK40) that is input to the signal of clock generator CLK_GENL and CLK_GEN_R (also being the 40MHz clock signal that is input to SPC/ position circuit from clock generator CLKGEN_L and CLK_GEN_R), its inversion signal (CK40B) and reset signal (RES).

In addition, also show 20MHz clock signal (CK20) and the 10MHz clock signal (CK10) that is input to SPC/ position circuit from clock generator CLK_GEN among Fig. 5.

But also show the serial 8-bit digital data of 80MHz lowest order (A, B, C ... A ', B ', C ' ... and A ", B ", C " ...), these numerical datas flow to SPC/ position-1 circuit respectively to SPC/ position-8 circuit.In addition, the data length of a digital data sets (for example data set A) is 12.5nsec.

In addition, be shown in the sequential chart of Fig. 5 from the output node OUT100 of each SPC/ position circuit and the digital signal of OUT200 (1 grade), its output node OUT110, OUT120, OUT210 and OUT220 (2 grades) and output node OUT111 (PAO), OUT112 (PEO), OUT121 (PCO), OUT122 (PGO), OUT211 (PBO), OUT212 (PFO), OUT221 (PDO) and OUT222 (PHO) (3 grades) conveying.

Shown in the sequential chart of Fig. 5, every grade SPC elementary cell is reduced to 1/2 (in other words, it is the twice of data length) with the frequency of input digital data, and input digital data sequentially is converted to two parallel digital signals.

More particularly, at first, 1 grade of SPC elementary cell of each SPC/ position circuit will become the parallel digital data of 40MHz with the digital data conversion of 80MHz serial input, and these parallel digital datas are transferred to the correspondence input node (IN) of two SPC elementary cells of 2 grades respectively from output node OUT100 and OUT200.For example, 1 grade SPC elementary cell will convert two parallel digital datas (data length respectively is A and the B of 25nsec) of 40MHz with the numerical data (data length respectively is A and the B of 12.5nsec) of 80MHz serial input to.

Secondly, two SPC elementary cells of 2 grades of each SPC/ position circuit will become the parallel digital data of 20MHz with the digital data conversion of 40MHz serial input, and they are transferred to four SPC elementary cells of 3 grades from output node OUT110 and OUT120 and OUT210 and OUT220 respectively.For example, 2 grades SPC elementary cell will convert two parallel digital datas (data length respectively is A and the C of 50nsec) of 20MHz with the numerical data (data length respectively is A and the C of 25nsec) of 40MHz serial input to.

In addition, four SPC elementary cells of 3 grades of each SPC/ position circuit will become the parallel digital data of 10MHz with the digital data conversion of 20MHz serial input, and they are respectively from output node OUT111 (PAO) and OUT112 (PEO), output node OUT121 (PCO) and OUT122 (PGO), OUT211 (PBO) and OUT212 (PFO) and OUT221 (PDO) and OUT222 (PHO) transmission.For example, 3 grades SPC elementary cell will convert two parallel digital datas (data length respectively is A and the E of 100nsec) of 10MHz with the numerical data (data length respectively is A and the E of 50nsec) of 20MHz serial input to.

Thereby the numerical data of this 10MHz is respectively from output node PAO, PBO, PCO, PDO, PEO, PFO, PGO and PHO transmission.

Carry out aforesaid operations in all SPC/ position circuit, the result makes the 8 bit digital data transaction of the 80MHz of serial input become 8 parallel 8-bit digital data of 10MHz.

Incidentally, the front by the agency of relate to the embodiment that the serial-to-parallel change-over circuit that is used for numerical data of the present invention becomes the 8-bit digital data transaction of 80MHz 8 parallel 8-bit digital data conditions of 10MHz.But, be not limited thereto applicable to serial-to-parallel change-over circuit of the present invention.

The serial-to-parallel change-over circuit that is used for numerical data according to the present invention can become (m2 with the digital data conversion with mHz serial input ^-y) Hz 2 ^yIndividual parallel digital data is so that the output parallel digital data.Here, alphabetical m represents positive number, and alphabetical y represents natural number.Should be appreciated that in this case, serial-to-parallel change-over circuit of the present invention can be operated with a plurality of clock signals that are equal to or less than (m/2) Hz.

Here, be up to (m/2) Hz for the frequency that a plurality of clock signal adopted, minimum is (m2 ^-y) Hz.

In addition, be under the situation of x position in the numerical data that will be handled by serial-to-parallel change-over circuit of the present invention, the SPC/ position circuit of every numerical data of input x bit digital data is made up of to x SPC/ position circuit of SPC/ position-x circuit SPC/ position-1 circuit.In addition, each SPC/ position circuit comprises a plurality of SPC elementary cells, and its quantity is represented by formula given below (1).Here, alphabetical x represents that minimum is 2 natural number.

[formula 1]

$\underset{k=1}{\overset{y}{\mathrm{\Σ}}}{2}^{k-1}---\left(1\right)$

In more detail, first order circuit comprises a SPC elementary cell, and second level circuit comprises two SPC elementary cells, and k level circuit comprises 2 ^K-1Individual SPC elementary cell, y level circuit comprises 2 ^Y-1Individual SPC elementary cell.Here, alphabetical k represent 1 to the y natural number of (comprise 1 and y).

Every numerical data of x bit digital data inputs to corresponding SPC/ position circuit.The k level circuit of each SPC/ position circuit is 2 of the serial input ^K-1The frequency of numerical data reduces half, and k level circuit is 2 of the serial input ^K-1Individual numerical data converts 2 to ^kIndividual parallel digital data.2 ^kIndividual parallel digital data outputs to the corresponding SPC elementary cell as (k+1) level circuit of back level.Incidentally, the corresponding bit digital data of the rank circuit transmission of final stage are as the output of SPC circuit.

As mentioned above, the serial-to-parallel change-over circuit that is used for numerical data according to the present invention is not subjected to any frequency, its bit quantity of numerical data and cuts apart the restriction of quantity.

And serial-to-parallel change-over circuit of the present invention only need be up to half the clock signal of frequency of the frequency of the numerical data that will import.Therefore, compare with the circuit of prior art, the stability of serial-to-parallel change-over circuit of the present invention, reliability and power consumption are more excellent.

(embodiment 2)

Introduce another embodiment that is used for serial-to-parallel conversion (SPC) circuit of numerical data according to of the present invention now.SPC circuit in this example is that the SPC circuit among the embodiment 1 has been added the function that rearranges numerical data.Remaining structure is identical with embodiment's 1.

Referring now to Fig. 6,, wherein shows the circuit layout of the SPC circuit that is used for numerical data in this example with calcspar.In this example, the same with embodiment 1, also handle the numerical data of 8-position.The same with the SPC circuit among the embodiment 1, the SPC circuit that is used for 8-bit digital data in this example will convert 8 parallel digital datas that walk abreast and export every 10MHz to the 8-bit digital data (DIGITAL DATA-1 (LSB) is to DIGITAL DATA-8 (MSB)) of 80MHz serial input.

As shown in Figure 6 in this routine SPC circuit, be used to embody numerical data that numerical data rearranges function and rearrange input node LRR_L and the LRB_L that signal (LR) and inversion signal (LRB) thereof flow to each SPC/ position circuit.

Here, introduce SPC/ position circuit with reference to Fig. 7 as this routine SPC network component.Fig. 7 represents SPC/ position-1 circuit of the lowest order (DIGITAL DATA-1) of clock generator CLK GEN L in this routine SPC circuit and input digital data.Incidentally, each SPC/ position circuit of input digital data (DIGITALDATA-2 is to DIGITALDATA-8) is identical with the SPC/ position circuit shown in Fig. 6 basically respectively.

As shown in Figure 7, in this example, SPC/ position-1 circuit comprises that 7 SPC elementary cells and 8 numerical datas rearrange switch SW _ LR.Identical among the connection of 7 SPC elementary cells and the embodiment 1.

Here, the circuit diagram that rearranges switch SW _ LR of the numerical data in this example is shown among Fig. 8.In this example, switch SW _ LR comprises two analog switches, and each analog switch is made of P-channel transistor (PchTr) and N-channel transistor (Nch Tr).Numerical data in this example rearranges switch SW _ LR can carry the signal of importing node P1 or input node P2 according to signal LR that receives as input and LRB from output node P3.

When keeping LR=Hi (height) and LRB=Lo (low), numerical data rearranges switch SW _ LR is input to node P1 from node P3 numerical data.On the other hand, when keeping LR=Lo and LRB=Hi, numerical data rearranges switch SW _ LR is input to node P2 from node P3 numerical data.

Introduce the operation of the SPC circuit that is used for numerical data in this example below with reference to the sequential chart of Fig. 9.Identical up to the output signal of the SPC elementary cell of the signal of output node OUT111, OUT112, OUT121, OUT122, OUT211, OUT212, OUT221 and the OUT222 of the SPC of tertiary circuit elementary cell and embodiment 1 therefore can be with reference to embodiment 1.

The SPC elementary cell of the tertiary circuit of each SPC/ position circuit will become the parallel digital data of 10MHz with the digital data conversion of 20MHz serial input, and they are respectively from output node OUT111 and OUT112, OUT121 and OUT122, OUT211 and OUT212 and OUT221 and OUT222 transmission.

When being input to signal that numerical data rearranges switch SW _ LR when being LR=Hi and LRB=Lo, these switches input to the numerical data of node P1 from node P3.Therefore shown in the sequential chart of Fig. 9, respectively from output node PAO, PEO, PCO, PGO, PBO, PFO, PDO and PHO transmission of digital data A, E, C, G, B, F, D and H.

When being input to signal that numerical data rearranges switch SW _ LR when being LR=Lo and LRB=Hi, these switches input to the numerical data of node P2 from node P3.Therefore as the sequential chart of Fig. 9 shown in draw together with bracket, respectively from output node PAO, PEO, PCO, PGO, PBO, PFO, PDO and PHO transmission of digital data H, D, F, B, G, C, E and A.

In all SPC/ position circuit, carry out aforesaid operations, the result, the 80MHz8-bit digital data of serial input are converted into 8 parallel 8-bit digital data of 10MHz.

In this mode, input to the signal LR that numerical data rearranges switch SW _ LR by control, can rearrange will be from the numerical data of serial-to-parallel change-over circuit output.

In this example, input to the signal LR that numerical data rearranges switch, rearrange the numerical data that to change the output of (SPC) circuit from serial-to-parallel by control.But can also adopt such method: rearranging in advance will be from the numerical data of the outside input of SPC circuit, and the data that this is rearranged input to the SPC circuit then.This method is particularly useful for the scheme that numerical data rearranges switch that do not comprise in the SPC circuit of embodiment 1.

(embodiment 3)

In this example, the serial-to-parallel of introducing in the foregoing description 1 or 2 that is used for numerical data is changed the situation that (SPC) circuit is applicable to the drive circuit that is used for active-matrix liquid crystal display device.

Referring to Figure 10, wherein show the block schematic diagram of the active-matrix liquid crystal display device in this example.Numeral 1001 expression source signal line drive circuit A, and mark 1002 expression source signal line drive circuit B.Mark 1003 expression gate signal line drive circuits.In addition, mark 1004 expression active matrix circuits.With mark 1005 expression be the SPC circuit that is used for numerical data, this circuit has in front that the numerical data described in the embodiment 2 rearranges function.

Source signal line drive circuit A1001 comprises shift register circuit (have 240 grades * 2 shift register circuit) 1001-1, latch cicuit 1 (pinning the latch cicuit of 960 * 8 numerical datas) 1001-2, latch cicuit 2 (pinning the latch cicuit of 960 * 8 numerical datas) 1001-3, select circuit 1 (selecting the selection circuit of 240 numerical datas) 1001-4, D/A (digital-to-analog) change-over circuit (change 240 numerical datas and be called the D/A change-over circuit of " DAC ") 1001-5 and select circuit 2 (selecting the selection circuit of 240 numerical datas) 1001-6.In addition, this drive circuit A1001 also comprises buffer circuit and level shift circuit (not shown).In addition, for ease of explanation, should comprise level shift circuit among the DAC1001-5.

Clock signal (CK) and starting impulse (SP) input to shift register circuit 1001-1.What input to latch cicuit 1 (1001-2) is its frequency has been reduced to 10MHz by SPC circuit 1005 8 parallel 8-bit digital data.Latch signal inputs to latch cicuit 2 (1001-3).Select signal to input to and select circuit 1 (1001-4).What input to D/A change-over circuit 1001-5 is high potential power voltage (DC_VIDEOH), low potential power source voltage (DC_VIDEO_L), offset power source voltage (DC VIDEO_M) and reset pulse (ResA and ResB).In addition, select signal to input to and select circuit 2 (1001-6).

The structure of source signal line drive circuit B1002 is identical with the structure of source signal line drive circuit A1001.Incidentally, source signal line drive circuit A1001 flows to the odd number source signal line with vision signal (grayscale voltage signal), and source signal line drive circuit B1002 flows to the even number source signal line with vision signal.

In addition, in this routine active-matrix liquid crystal display device, two source signal line drive circuit A and B are arranged to for the former of circuit layout thereby vertically keep therebetween active matrix circuit 1004.But, if can a source signal line drive circuit can only be set from the viewpoint of circuit layout.

Simultaneously, gate signal line drive circuit 1003 comprises (all not shown) such as shift register circuit, buffer circuit, level shift circuits.

Active matrix circuit 1004 has the pixel that quantity is 1920 * 1080 (levels * vertical).Pixel TFTs (thin-film transistor) distributes to each pixel.Source signal line and gate signal line are electrically connected to source region and the grid of each pixel TFTs respectively.In addition, pixel capacitors is electrically connected with the drain region of each pixel TFT.Each pixel TFT control of video signal (grayscale voltage) is to the conveying of the pixel capacitors that is electrically connected with it.This vision signal (grayscale voltage) flows to each pixel capacitors, and described voltage puts on and is clipped in pixel capacitors and to the liquid crystal between the electrode, drives liquid crystal thus.

In this example, the 8-bit digital data of 80MHz input to serial-to-parallel conversion (SPC) circuit 1005 from the outside of liquid crystal display device.SPC circuit 1005 is changed the 8-bit digital data of the 80MHz of outside input, and 8 parallel digital datas of 10MHz are flowed to source signal line drive circuit A and B.

Here, next will introduce the operation of the active-matrix liquid crystal display device in this example.

At first, explain the operation of source signal line side drive circuit A1001.Clock signal (CK) and starting impulse (SP) input to shift register circuit 1001-1.This shift register circuit 1001-1 produces timing signal continuously on the basis of clock signal (CK) and starting impulse (SP), and by (not shown) such as buffer circuits this timing signal is continuously delivered to late-class circuit.

Timing signal from shift register circuit 1001-1 is cushioned bufferings such as circuit.Conveying has very big load capacitance (parasitic capacitance) with each source signal line of timing signal, and this is attached thereto because of a large amount of circuit or element and causes.Buffer circuit is set, so that prevent the rising of each timing signal or descend owing to heavy load electric capacity becomes " blunt ".

Then, the timing signal that is cushioned circuit buffering flows to latch cicuit 1 (1001-2).This latch cicuit 1 (1001-2) has 960 grades of sub-latch cicuits, and each sub-latch cicuit is handled 8-bit digital data.When carrying with timing signal, latch cicuit 1 (1001-2) is accepted the 8-bit digital data of presenting from SPC circuit 1005 of the present invention continuously and is held them in wherein.

Time cycle of sub-latch cicuit that numerical data is written into all grades of latch cicuit 1 (1001-2) fully is called as " line-scanning period ".In other words, at forward forward under the scan condition, the time interval of the time point the when line-scanning period is EO in the sub-latch cicuit that numerical data is write the rightest one-level of time point when the operation the sub-latch cicuit of the first from left level of numerical data write lock storage circuit 1 (1001-2) is begun.In fact, will add that sometimes the time cycle that the above line scan period obtains is called " line-scanning period " horizontal flyback period.

After a line-scanning period finishes, be consistent with the operation timing of shift register circuit 1001-1, latch signal flows to latch cicuit 2 (1001-3).At this moment, the numerical data that is written into and remains in the latch cicuit 1 (1001-2) flows to latch cicuit 2 (1001-3) simultaneously, and they are written into and remain in the sub-latch cicuit of all grades of latch cicuit 2 (1001-3).

On the timing signal basis from shift register circuit 1001-1, the numerical data of transmitting from SPC circuit 1005 of the present invention is write to the latch cicuit 1 (1001-2) of the numerical data that latch cicuit 2 (1001-3) transmission keeps once more continuously.

During the line-scanning period of second round, D/A change-over circuit (DAC) 1001-5 is selected and flowed to the selected circuit 1 of numerical data (1001-4) that is written into and remains in the latch cicuit 2 (1001-3) continuously.In this example, select circuit 1 (1001-4) to have son and select circuit, each son is selected corresponding four source signal lines of circuit.

Illustrate in passing,, can also adopt disclosed selection circuit in the open No.11-167373 (1999) of the Japanese patent application that transfers the same assignee of the application about selecting circuit.Corresponding U.S. Patent Application Serial 09/162230 of this Japanese patent application and the open No.0938074A of european patent application special permission.

According to the selection signal of input, a line-scanning period (horizontal scanning period) per 1/4 selects circuit 1 (1001-4) to select and the numerical data of corresponding four source signal lines of output.

In the selection circuit 1 (1001-4) of this example, son of per quart source signal line is set selects circuit.Like this, be transported to per 1/4 time of a selected line-scanning period of 8-bit digital data of corresponding source signal line from latch cicuit 2 (1001-3).

The 8-bit digital data delivery that selected circuit 1 (1001-4) is selected is given DAC1001-5.In this example, can adopt any D/A change-over circuit, disclosed D/A change-over circuit is favourable in transferring the assignor's identical with the application Japanese patent application No.10-344732 (1998) but adopt.

With with the identical mode of aforementioned selection circuit 1 (1001-4), per 1/4 scan period, select and flow to source signal line from the selected circuit 2 of analogue data (grayscale voltage) (1001-6) of D/A change-over circuit 1001-5 output.

The analogue data that flows to source signal line is transported to the source region of the pixel TFTs of the active matrix circuit 1004 that is connected with source signal line.

Source signal line drive circuit B1002 has the identical structure with aforementioned source signal line drive circuit A1001.This drive circuit B1002 flows to the even number source signal line with analogue data.

Gate signal line drive circuit 1003 comprises conveying with the buffer circuit (not shown) from the timing signal of shift register (not shown), and timing signal is transferred to corresponding gate signal line (scan line).The gate electrode that is used for the pixel TFTs of a horizontal line is connected to each gate signal line, and all pixel TFTs that need be used for a horizontal line are opened simultaneously.Therefore, the buffer circuit of employing has high current capacity.

In this mode, corresponding pixel TFTs is switched by the sweep signal from gate signal line drive circuit 1003, and they are transferred with the analogue data (grayscale voltage) from source signal line drive circuit A (1001) and B (1002), drive liquid crystal molecule thus.

When serial-to-parallel conversion (SPC) circuit that is used for numerical data according to the present invention is applicable to the active-matrix liquid crystal display device the same with this example, can handle the numerical data of upper frequency.

To introduce the example of the technology of making the active-matrix liquid crystal display device that comprises the SPC circuit of the present invention described in this example below.In this example, introduce liquid crystal display device by way of example, wherein a plurality of TFTs are formed on the substrate with insulating surface, and on same substrate, form active matrix circuit, source signal line drive circuit, gate signal line drive circuit, SPC circuit of the present invention and other peripheral circuit.The technology that is used for making this example is shown in Figure 11 A-11E, Figure 12 A-12C, Figure 13 A-13E and Figure 14 A-14C.Incidentally, to introduce such state in the example below: wherein active matrix circuit pixel TFT is formed with CMOS (complementary MOS transistor) circuit simultaneously, and this cmos circuit is the basic circuit of other circuit (source signal line drive circuit, gate signal line drive circuit, SPC circuit and other peripheral circuit).And, the manufacturing step that comprises the situation of a grid about each P-channel TFT and N-channel TFT in cmos circuit will be introduced in the example below, but cmos circuit can be made equally based on the TFTs of the TFTs that respectively comprises a plurality of grids such as double grid type or three grid types.In addition, introduced pixel TFT in the example below, but also can replace with TFT such as single grid type, three grid types as double grid N-channel TFT.

Referring now to Figure 11 A.At first, preparation quartz substrate 5001 is as the substrate with insulating surface.Can use silicon substrate to replace quartz substrate with heat oxide film.But also can adopt such method, wherein amorphous silicon film once is formed on the quartz substrate, and thermal oxidation becomes dielectric film fully.In addition, allow that employing is formed with quartz substrate, ceramic substrate or the silicon substrate of silicon nitride film as dielectric film.Form basilar memebrane 5002 then.In this example, silica (SiO ₂) be used for basilar memebrane 5002.Form amorphous silicon film 5003 at next step.Adjust amorphous silicon film 5003, make its final thickness (considering the thickness that the film attenuation obtains after thermal oxidation) can be 10 to 75nm (being preferably 15) to 45nm, more preferably 25nm.

Incidentally, when forming amorphous silicon film 5003, the impurity concentration in the controlling diaphragm is very important fully.In the case of this example, in amorphous silicon film 5003, C (carbon), N (nitrogen) and O (oxygen) are impurity, and they can hinder amorphous film crystallization afterwards.The concentration of control impurity C and N is so that it is 5 * 10 ¹⁸Atoms/cm ³Below (be at most 5 * 10 usually ¹⁷Atoms/cm ³, preferably be at most 2 * 10 ¹⁷Atoms/cm ³), and the concentration of impurity O (oxygen) is controlled in 5 * 10 ¹⁹Atoms/cm ³Below (be at most 1 * 10 usually ¹⁸Atoms/cm ³, preferably be at most 5 * 10 ¹⁷Atoms/cm ³).Reason is, the impurity that exists with higher concentration produces injurious effects and causes the quality of crystalline film to descend crystallization afterwards.In this manual, the concentration of impurity element is defined as the minimum value of the measurement result of SIMS (ion microprobe) in the film.

For obtaining said structure, the low pressure hot CVD stove that uses in this example should be dry-cleaned processing usually, so that clean film formation chamber.Dry-cleaning can be carried out in this way, makes ClF that is: ₃(chlorine fluoride) gas flows in being heated to about 200-400 ℃ stove with 100 to 300sccm, and then the fluorine that produces with thermal decomposition cleans film formation chamber.

In addition, the inventor has been found that temperature is arranged on 300 ℃ and ClF in stove ₃The flow set of gas can be removed fully in 4 hours and is about the thick adhesive substance (mainly being made up of silicon) of 2 μ m under the situation of 300sccm.

And the concentration of the hydrogen in the amorphous silicon film 5003 is unusual important parameters, hydrogen content is being suppressed at when very low, can produce the film of well-crystallized.Therefore, it is favourable utilizing the low pressure hot CVD to form amorphous silicon film 5003.Can also pass through to optimize film formed condition and using plasma CVD.

Next, carry out the crystallisation step of amorphous silicon film 5003.Can adopt among the open No.7-130652 (1995) of Japanese patent application disclosed technology as the method for crystallization.Corresponding U.S. Patent No. 5643826 of this Japanese patent application and U.S. Patent No. 5923962.Though can depend on method, can advantageously adopt the technology contents described in the embodiment 2 of this Japanese patent application (details see Japanese patent application open No.8-78329 (1996)) in this example in any of the embodiment 1 described in this Japanese patent application and 2.

Disclosed technology is among the open No.8-78329 of Japanese patent application, and at first forming thickness is the mask insulating film 5004 that is used to select the zone of 150nm, and this film will mix with catalyst elements.Mask insulating film 5004 has a plurality of openings, so that introduce catalyst elements.The position of crystal region can be determined by these openings.

In addition, as the catalyst elements that promotes amorphous silicon film 5003 crystallizations, by using the resulting substrate of solution (ethanolic solution of nickel acetate) 5005 spin-applied that contains nickel.Except nickel element, cobalt (Co), iron (Fe), palladium (Pd), germanium (Ge), platinum (Pt), copper (Cu), gold (Au) etc. are any can be as catalyst elements (Figure 11 B).

And, also can adopt the ion that utilizes Etching mask to inject or plasma doping for doping step with catalyst elements.In this case, the growth distance that reduces each the regional footprint area that will mix and control each the cross growth zone that will introduce the back is favourable.Therefore, this technology is very effective for constituting microcircuit.

Finish with after the doping step of catalyst elements, at 450 ℃ the substrate that obtains is carried out dehydrogenation and handled about one hour.Afterwards, by under 500-960 ℃ (being generally 550-650 ℃), in inert atmosphere, nitrogen atmosphere or oxygen atmosphere, the substrate that obtains being heat-treated 4 hours-24 hours, make amorphous silicon film 5003 crystallizations.In this example, heat treatment is to have carried out in blanket of nitrogen 12 hours under 600 ℃.

In this case, preferentially carry out the crystallization of amorphous silicon film 5003 from appearing at the nucleus the catalyst elements Ni doped regions 5004, form crystal region 5007 thus, each crystal region is by constituting with the polysilicon film of the parallel growth of substrate plane of substrate 5001 basically.Crystal region 5007 is called as " lateral growth region ".Because lateral growth region has the discrete crystal of assembling with relative uniform state, therefore has the advantage (Figure 11 C) of crystallinity excellence as a whole.

Incidentally, also can make amorphous silicon film 5003 crystallizations, and not adopt mask insulating film 5004 by apply its whole surface with nickel acetate solution.

With reference to Figure 11 D, wherein show the technology of absorbing catalyst element.At first, with the mix selection part of the substrate obtain of phosphonium ion.The doping of using doping agent phosphorus is to carry out in the state that forms mask insulating film 5004.Then, with only mix those parts 5008 (these parts should be called " phosphorus doping district 5008 ") of the polysilicon film 5007 that not masked dielectric film 5004 covers of doping agent phosphorus.In this case, the thickness of accelerating voltage that should optimal selection mixes and the mask 5004 that is made of oxide-film is in order to avoid doping agent phosphorus passes mask insulating film 5004.Though mask insulating film 5004 not necessarily must be an oxide-film, oxide-film is favourable, even this is because it directly also can not constitute the reason of pollution with any active layer catalytic oxidation film.

The dosage of doping agent phosphorus can be 1 * 10 ¹⁴Ions/cm ²To 2 * 10 ¹⁵Ions/cm ²The order of magnitude.In the example of present embodiment, doping agent phosphorus can utilize ion doping equipment with 2 * 10 ¹⁵Ions/cm ²Dosage introduce.

In addition, the accelerating voltage of ion doping is arranged on 10keV.By the accelerating voltage of 10keV, doping agent phosphorus can pass the thick mask insulating film of 150nm hardly.

With reference to Figure 11 E.Then, in 600 ℃ blanket of nitrogen, the substrate that obtains is carried out thermal annealing 1-12 hour (being 12 hours in this example), remove elemental nickel thus.Therefore, shown in the arrow among Figure 11 E, elemental nickel is pulled through to the doping agent phosphorus direction.600 ℃ temperature, phosphorus atoms can move in film 5007 hardly, but nickle atom can move the distance that waits about hundreds of μ m at least.Therefore, be appreciated that phosphorus is to be suitable for one of element of removing in nickel most.

Introduce the step of composition polysilicon film 5007 below with reference to Figure 12 A.In this case, should prevent to stay the phosphorus doping district 5008 that wherein absorbs elemental nickel.In this way, obtain as the active layer 5009,5010 and 5011 that contains the polysilicon film of elemental nickel hardly.So the active layer 5009,5010 and 5011 as polysilicon film that obtains is used as the active layer of TFTs afterwards.

With reference to Figure 12 B, using the thickness that is made of the dielectric film that contains silicon is the gate insulating film 5012 stack active layers 5009,5010 and 5011 of 70nm.In addition, in oxidizing atmosphere, heat-treat 800-1100 ℃ (being preferably 950-1050 ℃), thus active layer 5009,5010 and 5011 and gate insulating film 5012 between the interface form the heat oxide film (not shown).

In addition, can make correspondence require gate insulating film 5012 attenuation of part of the SPC circuit of the present invention, drive circuit etc. of high speed operation in this way, that is: after forming this gate insulating film 5012, partly remove gate insulating film, further form gate insulating film then.

In addition, can be used to remove the heat treatment (being used to remove the technology of catalyst elements) of catalyst elements in this stage.In this case, make heat treated atmosphere contain halogen, and obtain to utilize halogen to remove the degassing effect of catalyst elements.Wherein, in order to obtain the degassing effect on the halogen basis satisfactorily, the temperature that is preferably in more than 700 ℃ is heat-treated.In the temperature below 700 ℃ and 700 ℃, obviously handle halogen compounds in the atmosphere and become and be difficult to decompose, therefore can not obtain degassing effect.In this case, can be used as the gas that contains halogen usually is to be selected from least a in the following halogen contained compound: HCl, HF, NF ₃, HBr, Cl ₂, ClF ₃, BCl ₂, F ₂And Br ₂In this step, under the situation of for example using compound H Cl, should consider that remove the elemental nickel in the active layer under the effect of chlorine, thereby form volatile nickel chloride, this nickel chloride will be evaporated in the atmosphere.In addition, using halogen to remove under the situation of technology of catalyst elements, this technology should be carried out after removing mask insulating film 5004 He before the active layer composition.In addition, be preferably in the degassing process that is used for catalyst elements after the composition of active layer.And any this technology can be in conjunction with carrying out.

Then, forming its main component is the unshowned metal film of aluminium, and is patterned into the prototype of grid afterwards.In this example, the thickness of the aluminium film that contains 2wt% scandium (Sc) of formation is 400nm.

Perhaps, the polysilicon film of the impurity that can give conduction type with having mixed forms grid.

Next form porous anodic oxide film 5013-5020, non-porous anode oxide film 5021-5024 and grid 5025-5028 by disclosed technology among the open No.7-135318 (1995) of Japanese patent application.(Figure 12 B).The corresponding U.S. Patent application No.5648277 of this Japanese patent application.

Obtain in this way after the state of Figure 12 B, be used as the mask etch gate insulating film 5012 of grid 5025-5028 and porous anodic oxide film 5013-5020.Then, remove porous anodic oxide film 5013-5020 to obtain the state of Figure 12 C.In addition, the label 5029-5032 among Figure 12 C represents above-mentioned processing gate insulating film afterwards.

Referring now to Figure 13 (A), wherein show the step of mixing with the impurity element that applies a kind of conduction type.For the N-channel-type, impurity element can be P (phosphorus) or As (arsenic), and for the P-channel-type, impurity element can be B (boron) or Ga (gallium).

In this example, each the doping impurity step that is used to form N-raceway groove and P-channel TFT s is divided into two sub-steps.

At first, be used to form the doping impurity step of N-channel TFT s.Under the high accelerating voltage of about 80keV, use first substep of the foreign matter of phosphor doping of adopting in this example, form n thus ^-The district.Repair and adjust this n-district, make it present 1 * 10 ¹⁸To 1 * 10 ¹⁹Aroms/cm ³Phosphorus concentration.

In addition, under the low accelerating voltage of about 10keV, use second substep of doping impurity, form the n+ district thus.In this case, because accelerating voltage is lower, gate insulating film 5029-5032 is used as mask.In addition, adjust n ⁺The district makes it be presented to the sheet resistance that mostly is 500 Ω (preferably being at most 300 Ω).

Form source region 5033 and drain region 5034, its low concentration impurity district 5037 and its channel formation region 5040 of the N-channel TFT that constitutes cmos circuit by above-mentioned steps.And adjustment constitutes source region 5035 and drain region 5036, its low concentration impurity district 5038 and its channel formation region 5041,5042 (Figure 13 A) of the N-channel TFT of pixel TFT.

In addition, in the state shown in Figure 13 A, the active layer of the P-channel TFT of formation cmos circuit is identical with the structure of N-channel TFT.

Then shown in Figure 13 B, provide the Etching mask 5043 that covers N-channel TFT s, the substrate that mixes and obtain with the foreign ion (adopting boron in this example) that applies the P type.

The same with the abovementioned steps with doping impurity, this step also is divided into two sub-steps.But,, therefore introduce the B ion with several times high concentration with the aforementioned concentration of P ion doping because the N channel-type needs transoid to become the P channel-type.

The source region 5045 and drain region 5044, its low concentration impurity district 5046 and its channel formation region 5047 (Figure 13 B) that constitute the P-channel TFT of cmos circuit have so just been formed.

In addition, form under the situation of grid, can utilize the known side wall construction that is used to form the low concentration impurity district at polysilicon film with the impurity that applied conduction type of having mixed.

Then, the combination activator impurity ion by furnace annealing, laser annealing, lamp annealing etc.Simultaneously, repair the damage of the active layer that causes by the doping step.

Referring now to Figure 13 C,, form the stack membrane of forming by silicon oxide film and silicon nitride film, as first interlayer dielectric 5048, this film has contact hole.Then, form source electrode and drain electrode 5049-5053.In addition, can also adopt organic resin film as first interlayer dielectric 5048.

Below with reference to Figure 14 A, 14B and 14C.Then, form second interlayer dielectric 5054 of silicon nitride film.At next step, forming the thickness of being made by organic resin film is the 3rd interlayer dielectric 5056 of 0.5-3 μ m.What be used for organic resin film can be any of polyimides, acrylic resin, poly-Imidamide (polyimidoamide) etc.The advantage of above-mentioned organic resin film is: the method that forms film is easy to, and this film is easy to thicken, and can reduce parasitic capacitance, the flatness excellence on film surface owing to the little dielectric constant of organic resin.In addition, also can adopt organic resin film except above-mentioned.

Then, corrosion part the 3rd interlayer dielectric 5056 forms black matrix 5055 in the drain electrode 5053 of pixel TFT, and wherein second interlayer dielectric 5054 is inserted in black matrix 5055 and drains between 5053.In this example, Ti (titanium) is used for black matrix 5055.In addition, in this example, between pixel TFT and black matrix 5055, form storage (retention) electric capacity 5058.

Then, in second interlayer dielectric 5054 and the 3rd interlayer dielectric 5056, form contact hole, and formation thickness is the pixel capacitors 5057 of 120nm.Here, because this example has been introduced the active-matrix liquid crystal display device of transmission-type, therefore adopt the conducting film of the conduct formation pixel capacitors 5057 such as nesa coating of ITO (tin indium oxide).

Then, heating entire substrate 1-2 hour makes its complete hydrogenation in 350 ℃ nitrogen atmosphere, thus the dangling bonds in the compensate film (especially in the active layer).In addition, use is carried out hydrogenation by the hydrogen that gas is converted into plasma generation.

Finished the active matrix substrate through above-mentioned steps, wherein cmos circuit and PEL (picture element) matrix circuit are formed on the same substrate.

Next be presented in the technology of making active-matrix liquid crystal display device on the basis of the active matrix substrate by above-mentioned steps preparation.

Form oriented film 5059 on the active matrix substrate in Figure 14 B state.In this example, polyimides is used for oriented film 5059.Prepare substrate then.To substrate is by glass substrate 5060, by nesa coating is made electrode 5061 and oriented film 5062 are constituted.

In this example, oriented film 5062 is polyimide films.Form after the oriented film, processing rubs.In addition, in this example, the polyimides with wide relatively pre-tilt (pretilt) angle is used for oriented film.

Then, utilize active matrix substrate that seal member (not shown), sept (not shown) etc. will carry out above-mentioned steps and be in the same place by known unit number of assembling steps substrate is fixed to one another.Subsequently, between two substrates, inject liquid crystal 5063, and seal resulting structure fully with the sealant (not shown).In this example, nematic liquid crystal is used as liquid crystal 5063.

Finished the active array type transmission liquid crystal display spare as shown in Figure 14 C then.

In addition, can use laser beam (being generally excimer pulsed laser beam) to replace the method for crystallising of the amorphous silicon film described in this example to make the amorphous silicon film crystallization.

In addition, use the soi structure (SOI substrate) of " Smart Cut ", " SIMOX ", " ELTRAN " etc. to replace polysilicon film, can finish another technology well.

Introduce the operating result of the active-matrix liquid crystal display device in this example below with reference to Figure 19, Figure 20 A, 20B and 20C.Figure 19 is illustrated in the oscillogram that obtains when the serial-to-parallel of operating in this example that is used for numerical data is changed (SPC) circuit.

Shown in Figure 19 is output waveform from the clock signal of clock generator CLK_GEN_L or CLK_GEN_R.Among the figure, symbol Ref1 represents the output waveform of clock signal C K40_O (about 40MHz), and symbol Ref2 represents the output waveform of clock signal C K20_O (about 20MHz), and symbol Ref3 represents the output waveform of clock signal C K10_O (about 10MHz).In addition, symbol Ref5 represents reset pulse (RES), and symbol Ref4 represents the signal waveform that the reset pulse in the actual measurement SPC circuit obtains.

Figure 20 A, 20B and 20C represent the output waveform in the circuit of SPC/ position-1, and wherein the lowest order digit digital data in the 8-bit digital data inputs to this SPC/ position-1 circuit.

Figure 20 A shows the numerical data of the clock signal C K40 of about 40MHz (Ref1) of SPC elementary cell of the first order (1 grade) that inputs to SPC/ position-1 circuit and 80MHz (Ref2) and respectively from two parallel digital datas of the 40MHz (Ref3 and Ref4) of the output node OUT100 of above-mentioned SPC elementary cell and OUT200 transmission.And, also show reset pulse (Ref5).

The numerical data of 80MHz (Ref2) flows to the input node IN of SPC/ position-1 circuit.This 80MHz numerical data is a serial digital data, and from leftmost pulse, they have level Hi (height), Lo (low), Lo, Hi, Lo, Lo, Hi and Hi successively.In addition, the situation that this 80MHz serial digital data is corresponding this, promptly in the sequential chart in Fig. 5, be expert at data A, D, G and the H of DIGITAL DATA of expression is level Hi, and other data are level Lo.

From the numerical data (Ref3 and Ref4) of output node OUT100 and OUT200 transmission, the frequency that can see the numerical data (Ref2) of input is reduced to 1/2 (about 40MHz) and converts the state of two parallel digital datas (Ref3 and Ref4) to from respectively.About Hi data A, D, G and the H of row DIGITAL DATA order, can know with reference to the sequential chart of Fig. 5 and to see this state from output node OUT100 and OUT200 transmission.

Figure 20 B represents to be input to the numerical data of the clock signal C K20 of about 20MHz (Ref1) of SPC elementary cell of the second level (2 grades) of SPC/ position-1 circuit and 40MHz (Ref2) and respectively from two parallel digital datas (Ref3 and Ref4) of the 20MHz of the output node OUT110 of above-mentioned SPC elementary cell and OUT120 transmission.But also show reset pulse (Ref5).

In Figure 20 B, from numerical data (Ref3 and Ref4) by output node OUT110 and OUT120 transmission, can see such state, wherein the frequency of Shu Ru numerical data (Ref2) is reduced to half (about 20MHz) and is converted to two parallel digital datas (Ref3 and Ref4).

In addition, Figure 20 C represents to input to the numerical data of the clock signal C K10 of about 10MHz (Ref1) of SPC elementary cell of the third level (3 grades) of SPC/ position-1 circuit and 20MHz (Ref2) and respectively from two parallel digital datas of the 10MHz (Ref3 and Ref4) of output node OUT111 and OUT112 transmission.But also show reset pulse (Ref5).

In Figure 20 C, from respectively from the numerical data (Ref3 and Ref4) of output node OUT111 and OUT112 transmission, can see such state, wherein the frequency of Shu Ru numerical data (Ref2) is reduced to 1/2 (about 10MHz) and is converted to two parallel digital datas (Ref3 and Ref4).

As mentioned above, although the frequency of the numerical data of input is the upper frequency of about 80MHz, serial-to-parallel conversion (SPC) circuit that is used for numerical data according to the present invention presents stable operation.In addition, the highest frequency of operation of the SPC circuit of this time making of the present invention is 140MHz (numerical data of input is 140MHz, and clock signal is 70MHz).

(embodiment 4)

In this example introduction is used to make another example of the technology of active-matrix liquid crystal display device, wherein said active-matrix liquid crystal display device comprise described in top embodiment 3 according to serial-to-parallel conversion (SPC) circuit that is used for numerical data according to the present invention.And in this example, have a plurality of TFTs of formation on the substrate of insulating surface, and on same substrate, forming active matrix circuit, source signal line drive circuit, gate signal line drive circuit, SPC circuit of the present invention and other peripheral circuit.Introduce negative circuit referring now to Figure 15 A-15E and Figure 16 A-16C as the basic arrangement of cmos circuit.

Referring now to Figure 15 A-15E.Can adopt glass substrate, plastic, ceramic substrate etc. as substrate 6001.Can also adopt silicon substrate or metal substrate, be typically at the bottom of the stainless steel lining, its surface is formed with dielectric film, as silicon oxide film or silicon nitride film.Certainly, also can use quartz substrate.

Substrate 6001 surface that will form TFTs is thereon gone up and is formed the basilar memebrane 6002 that is made of silicon nitride film and by the film formed basilar memebrane 6003 of silica.These basilar memebranes form with plasma CVD or sputter, and are provided with to prevent that any impurity that TFTs is harmful to is diffused into the semiconductor layer from substrate 6001.For this reason, can to form the thickness that is made of silicon nitride film be 20-100nm, be generally the basilar memebrane 6002 of 50nm, and to form the thickness that is made of silicon oxide film simultaneously be 50-500nm, be generally the glue-line film 6003 of 150-200nm.

Certainly, can also only form basilar memebrane 6002 that constitutes by silicon nitride film or the basilar memebrane 6003 that constitutes by silicon oxide film.In this example, consider the reliability of TFTs, what wish most is double-decker.

Wish to form to such an extent that the semiconductor layer that contacts with glue-line film 6003 is by making with the crystalline semiconductor of following manner manufacturing, described mode is: by the solid state growth method based on laser crystallization or thermal annealing, make the amorphous semiconductor crystallization that forms as plasma CVD, decompression CVD or sputter by film formation method.Can also apply by above-mentioned film and form the crystallite semiconductor that method forms.Here spendable semi-conducting material comprises silicon (Si), germanium (Ge), silicon-germanium alloy and carborundum.In addition, also can use compound semiconductor materials, as GaAs.

It is thick that this semiconductor layer forms 10-100nm, is typically 50nm.The hydrogen that contains 10-40 atom % ratio by the amorphous semiconductor film of plasma CVD generation.About this point, by before crystallisation step, carrying out heat treatment step, wish amorphous semiconductor film is carried out dehydrogenation at 400-500 ℃, making hydrogen content is 5 atom % or still less.In addition, can form amorphous silicon film with other formation method, as sputter or vapour deposition.In this case, should fully reduce impurity element such as oxygen and the nitrogen that is contained in the film.

In addition, owing to can form basilar memebrane and amorphous semiconductor film, therefore can form basilar memebrane 6002, basilar memebrane 6003 and second half conductor layer continuously with identical film formation method.Form after each film, their surface does not contact with atmosphere, therefore can prevent surface contamination.As a result, can eliminate and cause one of reason that the TFTs characteristic disperses.

Make the step of amorphous semiconductor membrane crystallization can be dependent on the known technology of laser crystallization or thermal crystalline.Can adopt crystalline semiconductor film based on the thermal crystalline technology of using catalyst elements.In addition, when the crystalline semiconductor film that is formed by the thermal crystalline technology that adopts catalyst elements being carried out the gettering step so that remove catalyst elements, can obtain excellent TFT characteristic.

According to the known patterning process that utilizes first photomask, cover the crystalline semiconductor film that so forms with resist film, and utilize dry etching that it is patterned into first island semiconductor layer (active layer) 6005 and second island semiconductor layer (active layer) 6004.

Then, cover second island semiconductor layer 6004 and first island semiconductor layer 6005 with gate insulating film 6006, wherein the main component of gate insulating film 6006 is silica or silicon nitride.Can form the gate insulating film 6006 (Figure 15 A) that thickness is 10-200nm, preferred 50-150nm with plasma CVD or sputtering method.

In addition, use second photomask to form the Etching mask 6007 and 6008 of the channel formation region that covers second island semiconductor layer 6004 and first island semiconductor layer 6005.In this case, can in the zone that forms wiring, form Etching mask 6009.

Subsequently, by mixing, form the step of second impurity range with the impurity element that applies the n-conduction type.As impurity element, be known as phosphorus (P), arsenic (As), antimony (Sb) etc., these impurity are given n-conduction type to crystal semiconductor material.Adopt element phosphor in this example, but can adopt the ion doping that uses hydrogen phosphide (PH3) to be used for mixing.In this step, with this element doping lower floor semiconductor layer, so the accelerating voltage of ion doping is arranged on certain high voltage of 80keV because element phosphor passes gate insulating film 6006.The concentration that is introduced into the element phosphor in the semiconductor layer as dopant preferably is arranged on 1 * 10 ¹⁶-1 * 10 ¹⁹Atoms/cm ³In the scope.Here this concentration is set to 1 * 10 ¹⁸Atoms/cm ³Like this, just in semiconductor layer, formed with element phosphor doped regions 6010,6011.Here the part of second impurity range of Xing Chenging is used as LDD district (Figure 15 B).

For removing Etching mask, can use available alkaline decomposing solution on the market, also be effective but use ashing in this example.Ashing is a kind of like this method, the plasma of promptly in oxidizing atmosphere, growing, and make the resist of sclerosis be exposed to plasma, so that remove resist.In this example, it is effective adding steam to oxygen in described atmosphere.

Subsequently, on gate insulating film 6006 surfaces, form first conductive layer 6012.It is that the electric conducting material that is selected from the element of Ta, Ti, Mo and W forms that first conductive layer 6012 is to use main component.In addition, the thickness of first conductive layer 6012 is arranged on 10-100nm, preferred 150-400nm (Figure 15 C).

For example can adopt in the following compounds any: WMo, TaN, MoTa and WSi _x(wherein keeping 2.4＜x＜2.7).

Compare with element al or Cu, the resistivity of electric conducting material such as Ta, Ti, Mo or W is higher.But, in this example, undoubtedly can use these electric conducting materials, thereby, obtain about 100cm with respect to the area of the circuit that will make ²Maximum area.

Then, use the 3rd photomask to form Etching mask 6013,6014,6015 and 6016.Etching mask 6013 is used to form the grid of P channel TFT, and Etching mask 6015 and 6016 is respectively applied for formation grating routing and its grid bus.In addition, form the Etching mask 6014 that covers first island semiconductor layer, 6005 whole surfaces, it is used for detecting at next step the mask of the impurity of introducing semiconductor layer.

Remove the unwanted part of first conductive layer by dry etching, form second grid 6017, grating routing 6019 and grid bus 6020 thus.In this example, ashing is effective for eliminating the residue that stays after the corrosion.

Subsequently, with remaining intac Etching mask 6013,6014,6015 and 6016, form the step of the 3rd impurity range by this way, wherein will form the part of second island semiconductor layer 6004 of p-channel TFT therein with the impurity element doping that applies the p-conduction type.What be known as this impurity element is boron (B), aluminium (Al) and gallium (Ga), and they can give the p conduction type.In this example, adopt impurity element boron, and with diborane (B ₂H ₆) the realization ion doping.And in this case, the accelerating voltage of ion doping is set to 80keV, so that with 2 * 10 ²⁰Atoms/cm ³Concentration introduce element boron.So just formed shown in Figure 15 D with element boron with the 3rd impurity range 6021,6022 of high-concentration dopant.

After the step of Figure 15 D is removed Etching mask, use the 4th photomask to form Etching mask 6023,6024 and 6025.The 4th photomask is used as the grid that forms the n-channel TFT, and forms first grid 6026 with dry etching.In this case, form first grid 6026 so that pass gate insulating film and 6010,6011 stacks (Figure 15 E) of part second impurity range.

In addition, remove fully after Etching mask 6023,6024 and 6025, use the 5th photomask to form Etching mask 6029,6030 and 6031 (referring to Figure 16 A).Form Etching mask 6030 so as to cover first grid 6026 and with 6010,6011 stacks of part second impurity range.In other words, Etching mask 6030 is used for determining the side-play amount in each LDD district.

Here, can use Etching mask 6030 to remove the part gate insulating film, peel off the surface portion of the semiconductor layer that will form first impurity range thus in advance.For this situation, can use the next step of the impurity element doping of bestowing the n-conduction type effectively.

Then, form the step of first impurity range by mixing with the impurity element of bestowing the n-conduction type.Therefore form first impurity range 6032 that is used as the source region and first impurity range 6033 that is used as the drain region.In this example, use hydrogen phosphide (PH ₃) ion doping be used for mixing.And in this step, with this element doping lower floor semiconductor layer, so the accelerating voltage of ion doping is arranged on higher 80keV because element phosphor passes gate insulating film 6006.Concentration height in the step that the concentration ratio of the P elements in these zones mixes with first impurity element of bestowing the n-conduction type, it preferably is set to 1 * 10 ¹⁹-1 * 10 ²¹Atoms/cm ³In this example, this concentration is set to 1 * 10 ²⁰Atoms/cm ³(Figure 16 A).

Subsequently, on the surface of gate insulating film 6006, first and second grids 6026,6017, grating routing 6027 and grid bus 6028, form first interlayer dielectric 6034 and second interlayer dielectric 6035.First interlayer dielectric 6034 is silicon nitride films, and its thickness is 50nm.On the other hand, second interlayer dielectric 6035 is silicon oxide films, and its thickness is 950nm.

Here first interlayer dielectric 6034 of the silicon nitride film of Xing Chenging is that to be used to heat-treat step necessary.This film for prevent first and second grids 6026,6017, grating routing 6027 and grid bus 6028 oxidized be effectively.

Need be used to activate the heat treatment step of the impurity element of giving n-conduction type and p-conduction type and introducing with independent concentration.This step can be by with the thermal annealing of electrothermal furnace, finish with the laser annealing of aforementioned excimer laser or with the short annealing (RTA) of Halogen lamp LED.Laser annealing can be at low substrate heating temperature activator impurity element, but being difficult to activate is hidden in the impurity element in the zone below the grid.Thereby, adopt thermal annealing in this example.Condition in this case is a blanket of nitrogen, and heating-up temperature is 300-700 ℃, preferred 350-550 ℃.Heat treatment is to carry out under 450 ℃ 2 hours in this example.

At heat treatment step, can in blanket of nitrogen, add the hydrogen of 3-90% in advance.In addition, finish after the heat treatment step, preferably carry out step of hydrogenation, this step of hydrogenation be in the atmosphere that contains 3-100% hydrogen, 150-500 ℃, be preferably under 300-450 ℃ the temperature and carried out 2-12 hour.Perhaps, can carry out hydrogen plasma under 150-500 ℃, preferred 200-450 ℃ underlayer temperature handles.For any situation, hydrogen can compensate to be stayed in the semiconductor layer or the defective at its interface, improves the characteristic of TFTs thus.

Then, use the 6th photomask, cover first interlayer dielectric 6034 and second interlayer dielectric 6035, and be formed by etching and have the source region of leading to each TFTs and the contact hole in drain region with predetermined Etching mask.In addition, form second conductive layer, and form source electrode 6036,6037 and drain 6038 by the pattern step that adopts the 7th photomask.In this example, second conductive layer that is used for electrode forms three-decker, and wherein utilize sputter to form the thick Ti film of 100nm continuously, contain Ti and thickness Al film and the thick Ti film of 150nm for 300nm, but not shown.

For above-mentioned steps, form the p-channel TFT with autoregistration, form the n-channel TFT with non-autoregistration.

The n-channel TFT of cmos circuit is formed with channel formation region 6042, first impurity range 6045,6046 and second impurity range 6043,6044.Wherein, second impurity range 6043,6044 respectively by with zone (GOLD district) 6043a, the 6044a of grid stack and not with zone (LDD district) 6043b, the 6044b formation of grid stack.In addition, first impurity range 6045 is as the source region, and first impurity range 6046 is as the drain region.

On the other hand, the p-channel TFT is formed with channel formation region 6039 and the 3rd impurity range 6040,6041.In addition, the 3rd impurity range 6040 as source region the 3rd impurity range 6041 as drain region (Figure 16 B).

In addition, Figure 16 C represents the top plan view of negative circuit, and part shown in C-C ' the sectional structure corresponding diagram 16B of the B-B ' sectional structure of the A-A ' sectional structure of TFT part, grating routing part and grid bus portion.In this example, grid, grating routing and grid bus are formed by first conductive layer.

In Figure 15 A-15E and Figure 16 A-16C, show n-channel TFT and p-channel TFT and complementally be combined in wherein cmos circuit, but also can make the nmos circuit that adopts n-channel TFT s, active matrix circuit etc. equally.

With with embodiment 3 in the identical method active matrix substrate that will so prepare manufacture active-matrix liquid crystal display device.

(embodiment 5)

In the active-matrix liquid crystal display device of the foregoing description 3 and 4, be used as display mode based on the TN pattern of nematic liquid crystal, but also can adopt other display mode.

In addition, can use the ferroelectric liquid crystals of no threshold value anti ferroelectric liquid crystal or fast response time to constitute active-matrix liquid crystal display device.

For example, can adopt disclosed liquid crystal in following document: by people such as H.Furue disclosed in SID in 1998 " Charateristic and Driving Scheme of Polymer-Stabilized MonostableFLCD Exhibiting Fast Response Time and High Contrast Ratio with Gray-ScaleCapability "; People such as T.Yoshida disclosed in SID digest, 841 in 1997 " A Full-ColorThresholdless Antiferroelectric LCD Exhiting Wide Viewing Angle with FastResponse Time "; By people such as S.Inui J.Mater.Chem 1996 6 (4), in the 671-673 page or leaf disclosed " Thresholdless antiferroelectric in liquid crystals and its application todisplays "; With U.S. Patent No. 5594569.

The liquid crystal that presents antiferroelectric phase in a certain temperature range is called " anti ferroelectric liquid crystal ".Mixed liquid crystal with anti ferroelectric liquid crystal comprises the liquid crystal that is called " no threshold value is mixed anti ferroelectric liquid crystal ", and it presents transmissivity along with electric field continually varying electro-optic response characteristic.Have been found that no threshold value mixes anti ferroelectric liquid crystal and comprise that the liquid crystal and the driving voltage that present so-called " V-arrangement electro-optic response characteristic " are about ± liquid crystal of 2.5V (element thickness is about 1-2 μ m).

To this, Figure 24 shows the example that the no threshold value that presents the V-arrangement electro-optic response is mixed " light transmission with apply voltage " characteristic of anti ferroelectric liquid crystal.The axis of ordinates of curve shown in Figure 24 is represented transmissivity, and abscissa represents to apply voltage.In addition, it is parallel that the axis of homology of the polarizer on the entrance side of liquid crystal display device is arranged to basically to mix with no threshold value the normal direction of smectic layer of anti ferroelectric liquid crystal, and wherein said direction is in fact consistent with the frictional direction of liquid crystal display device.In addition, the axis of homology of the polarizer of display device outlet side is arranged to basically vertical with the axis of homology of the polarizer of entrance side.

As can be seen from Figure 24, when adopting this no threshold value to mix anti ferroelectric liquid crystal, can realize that low voltage drive and tonal gradation show.Even mixing anti ferroelectric liquid crystal in the no threshold value of this low voltage drive is used to comprise under the situation of active-matrix liquid crystal display device of serial-to-parallel conversion (SPC) circuit that is used for numerical data of the present invention, also can reduce the output voltage of DAC (D/A change-over circuit), thereby can reduce the operating power voltage of DAC, and can make the working power voltage of driver be set to lower.Thereby can realize the low-power consumption and the high reliability of active-matrix liquid crystal display device.

Therefore, under the situation of the TFT that adopts its LDD district (low concentration impurity district) relative narrower (for example 0-500nm or 0-200nm), it also is effective using the no threshold value mixing anti ferroelectric liquid crystal of above-mentioned low voltage drive.

Usually, no threshold value is mixed anti ferroelectric liquid crystal and is presented significantly spontaneous polarization, and self has big dielectric constant.Therefore, mix anti ferroelectric liquid crystal in no threshold value and be used under the situation of liquid crystal display device, the pixel of display device needs the storage capacitance of big relatively value.The no threshold value of using is mixed anti ferroelectric liquid crystal and is preferably had spontaneous polarization.

Incidentally, owing to realized low voltage drive, therefore can reduce the power consumption of active-matrix liquid crystal display device by adopting above-mentioned no threshold value to mix anti ferroelectric liquid crystal.

In addition, any liquid crystal with electro-optical characteristic as shown in figure 24 can be used as the display medium according to liquid crystal display device of the present invention.

In addition, apply voltage according to it and can modulate the active matrix type semiconductor display device that any other display medium of its optical characteristics may be used to comprise SPC circuit of the present invention.For example, can adopt electroluminescent cell.

In addition, except TFT, also can use the active element as the active matrix circuit that constitutes active-matrix liquid crystal display device such as MIM element.

And, though introduced the TFTs of top gate type in the foregoing description 3 and 4, comprise that the active matrix type semiconductor display device (being generally liquid crystal display device) of SPC circuit of the present invention can be made of the TFTs of bottom gate type such as reverse interleaved type.

(embodiment 6)

The employing active matrix type semiconductor display device (comprising active-matrix liquid crystal display device) that is used for serial-to-parallel conversion (SPC) circuit of numerical data according to the present invention has a lot of application.In this example, semiconductor device or the device that the active matrix type semiconductor display device that adopts SPC circuit of the present invention wherein respectively is housed will be introduced.

Above-mentioned semiconductor device or device are: video camera, static video camera, projecting apparatus, head-mounted display, apparatus for vehicle navigation, personal computer, portable data assistance (as movable computer or pocket telephone), or the like.These examples are shown among Figure 17 A and 17B and Figure 18 A-18E.

Figure 17 A represents front type projecting apparatus, and it is made of main body 10001, active matrix type semiconductor display device 10002 (being generally liquid crystal display device), light source 10003, optical system 10004 and phosphor screen 10005.In addition, though the front type projecting apparatus that comprises single semiconductor display device has been shown among Figure 17 (A), can have realized more high-resolution and more the front type projecting apparatus of high definition by three active-matrix liquid crystal display devices of combination (light among corresponding color R, G and the B respectively).

Figure 17 B represents back side type projecting apparatus, and wherein label 10006 is represented main bodys, and label 10007 is active matrix type semiconductor display devices, and label 10008 is light sources, and label 10009 is reflectors, and label 10010 is phosphor screens.In Figure 17 B, back side type projecting apparatus comprises three active matrix type semiconductor display devices (light among corresponding color R, G and the B respectively).

Figure 18 A has showed pocket telephone, and it is made of main body 11001, voice output 11002, acoustic input dephonoprojectoscope 11003, active matrix type semiconductor display device 11004, console switch 11005 and antenna 11006.

Figure 18 B has showed video camera, and it is by main body 12001, active matrix type semiconductor display device 12002, acoustic input dephonoprojectoscope 12003, console switch 12004, battery 12005 and image received device 12006.

Figure 18 C represents movable computer, is made of main body 13001, camera head 13002, image received device 13003, console switch 13004 and active matrix type semiconductor display device 13005.

Figure 18 D represents head-mounted display, is made of main body 14001, active matrix type semiconductor display device 14002.

Figure 18 E represents portable notebook (electronic memo), is made of main body 15001, active matrix type semiconductor display device 15002,15003, storage medium 15004, console switch 15005 and antenna 15006.

(embodiment 7)

In this example, the example of the active-matrix liquid crystal display device that comprises serial-to-parallel conversion (SPC) circuit that is used for numerical data of the present invention will introduce be made.In addition, in this example, carried out and the substantially the same technology of Production Example described in the embodiment 3, therefore no longer specified.

In the example of present embodiment, in the state of Figure 11 A, do not adopt mask insulating film 5004 with the whole surface of nickel acetate solution coating amorphous silicon film 5003, the same with the step of mixing with catalyst elements.

After finishing the step of mixing, at 450 ℃ the substrate that obtains is carried out dehydrogenation and handled about one hour with catalyst elements.Then, by in inert atmosphere, nitrogen atmosphere or oxygen atmosphere, under 500-960 ℃ of (550-650 ℃ usually) temperature, the substrate that obtains being heat-treated 4-24 hour, make amorphous silicon film 5003 crystallizations.In this example, heat treatment is to carry out in blanket of nitrogen 8 hours at 590 ℃.

Then, be used to remove the heat treatment (being used to remove the technology of catalyst elements) of catalyst elements.In the case of this example, make heat treated atmosphere contain halogen, and obtain to utilize halogen to remove the gettering effect of catalyst elements.Here, heat-treat in order to realize gettering effect satisfactorily, to be preferably under the temperature more than 700 ℃ based on halogen.In the temperature that is equal to or less than 700 ℃, the halogen compounds of obviously handling in the atmosphere will be difficult to decompose, and therefore can not realize the gettering effect.What in this case, can be used as the gas that contains halogen usually is to be selected from following at least a in the halogen compounds of containing: as HCl, HF, NF ₃, HBr, Cl ₂, ClF ₃, BCl ₂, F ₂And Br ₂In the example, gettering process is to contain O in the present embodiment ₂With under 950 ℃, carry out in the atmosphere of HCl, form heat oxide film simultaneously.

Form gate insulating film subsequently.In the example of present embodiment, the thickness of gate insulating film is set to the final thickness of about 50nm.

Can be about other step with reference to embodiment 3.

The characteristic of the TFTs that is obtained by the manufacturing process of present embodiment is listed in the following table 1.

Table 1

L/W＝6.8/7.6[μm]	Nch	Pch
			Ion[μa]	227	91.5
Ioff[pA]	3.10	11.8
			Ion/Ioff[dec.]	7.86	6.89
Vth[V]	0.44	-0.56
			S value [V/dec.]	0.08	0.10
μFE(max)[cm 2/Vs]	314	131
			*μFE(max)[cm 2/Vs]	425	262

In the table 1, L/W represents (channel length/channel width), Ion represents (ON electric current), Ioff represents (OFF electric current), Ion/Ioff represents (common logarithm of ratio between ON electric current and the OFF electric current), Vth is (threshold voltage), and the S value is (subthreshold voltage swing), and μ FE is (field-effect mobility).In addition, ^*μ FE represents the μ FE of the TFT of channel length L=50 μ m.

Figure 21 represents the curve of the TFT characteristic that the manufacturing process by present embodiment obtains.Among the figure, Vg represents gate voltage, and Id represents leakage current, and Vd represents drain voltage.

(embodiment 8)

In this example, the example that introduction is comprised the active-matrix liquid crystal display device of making according to serial-to-parallel conversion (SPC) circuit that is used for digital of digital video data according to the present invention and by the inventor.

Listed in the following table 2 and comprised the technical indicator of making by the inventor according to SPC circuit active-matrix liquid crystal display device of the present invention.

Table 2

The display Diagonal Dimension	2.6 inch
		The quantity of pixel	1920×1080
Pixel size	30(H)×30(V)μm
		The aperture ratio	46％
The input data	8
		Power supply (logic)	5V
Input digital data speed	80MHz
		The frequency of data driver	10MHz
The frequency of scanner driver	8.1kHz
		Addressing mode	Be listed as anti-phase
Contrast	>100

" data driver " in the table 2 and " scanner driver " are represented source signal line drive circuit and gate signal line drive circuit respectively.In the example of present embodiment, the anti-phase demonstration of source signal line is as addressing mode.

Figure 22 is illustrated in the active-matrix liquid crystal display device that is used for serial-to-parallel conversion (SPC) circuit of digital of digital video data (8) according to of the present invention that comprises described in this example.

In addition, Figure 23 shows the described in this example demonstration example that respectively comprises according to the front type projecting apparatus of the active-matrix liquid crystal display device of the SPC circuit that is used for digital of digital video data (8) of the present invention of employing.About this front type projecting apparatus, can be with reference to embodiment 6.

From Figure 22 and 23 as can be seen, although the high-resolution of 1980 * 1080 pixels comprises that the active-matrix liquid crystal display device of SPC circuit of the present invention has realized that very high definition shows and very fine tonal gradation shows.

(embodiment 9)

To introduce the example that utilizes the present invention to make EL (electroluminescence) display panel in this example.

Figure 25 A is the top plan view that adopts EL display panel of the present invention.Referring to Figure 25 A, label 4010 expression substrates, label 4011 expression pixel units, label 4012 expression source drive circuits, label 4013 expression grid side drive circuit.Each drive circuit is guided to FPC (flexible print wiring) 4017 (also can referring to Figure 25 B) through wiring 4014,4015 and 4016, and is connected with external equipment.

In this case, coating member 7010, seal member (being also referred to as " case member ") 7000 (Figure 25 B) and gas-tight seal parts (second seal member) 7001 are arranged to center at least pixel unit, and preferably around drive circuit and pixel unit.

In addition, Figure 25 B shows the sectional structure of the EL display panel of present embodiment.On substrate 4010 and glue-line film 4021, be formed for the TFTs 4022 of drive circuit (refer to n-channel TFT and p-channel TFT here and be combined in wherein cmos circuit) and be used for the TFT4023 of pixel unit (refer to just be used for the TFT of control flows) here to the electric current of EL element.These TFTs can have known configurations (top gate structure or bottom grating structure).

The present invention can be used for drive circuit TFTs4022 and pixel unit TFT4023.

When using the present invention to finish drive circuit TFTs4022 and pixel unit TFT4023, on the interlayer dielectric of making by resin material (leveling film) 4026, form the pixel capacitors 4027 that constitutes and be connected by nesa coating with the electric leakage of pixel unit TFT4023.The compound of indium oxide and tin oxide (being called " ITO ") or the compound of indium oxide and zinc oxide can be used for nesa coating.In addition, form after the pixel capacitors 4027, deposit dielectric film 4028 also makes it be formed with opening on pixel capacitors 4027.

Then form EL layer 4029.By the known EL material of combination in any, can make this EL layer 4029 be configured as sandwich construction or single layer structure (hole injection layer, hole transmission layer, luminescent layer, electron transfer layer and electron injecting layer).Its structure can be determined by known technology.In addition, the EL material is classified as low molecular material and macromolecule (polymer) material.Under the situation of using low molecular material, can utilize vapour deposition, and under the situation of using macromolecular material, can utilize simple method, as spin coating, common printed or ink jet printing.

In this example, the EL layer is to form by the vapour deposition that utilizes shadow mask.Each pixel that can send the luminescent layer (red light luminescent layer, green luminescence layer and blue light-emitting) of different wavelengths of light is to adopt shadow mask to form, and realizes colored the demonstration thus.Also can adopt the scheme of color conversion apparatus (CCM) and colour filter combination and the scheme of white-light emitting layer and colour filter combination, and can adopt any of these methods.Certainly, can also constitute the EL display panel of bill coloured light.

Form after the EL layer 4029, cover with negative electrode 4030.Wish to remove to greatest extent in advance and be present in moisture and the oxygen in the border between negative electrode 4030 and the EL layer 4029.Thereby, need such measure, promptly form EL layer 4029 and negative electrode 4030 in a vacuum continuously, perhaps in inert atmosphere, form EL layer 4029, form negative electrode 4030 then, and do not make the substrate that obtains be exposed to atmosphere.In this example, can adopt the film forming device of multi-chamber system (Set of tools system) to finish the formation of above-mentioned film.

In addition, in this example, negative electrode 4030 can adopt the sandwich construction of being made up of LiF (lithium fluoride) film and Al (aluminium) film.Specifically, utilize vapour deposition on EL layer 4029, to form the LiF film of thickness, and cover with the Al film of thickness 300nm for 1nm.Certainly, also can use known cathode material MgAg electrode, in addition, negative electrode 4030 is connected with the wiring 4016 of zone in 4031.This wiring 4016 is the voltage supply lines that are used for applying predetermined voltage to negative electrode 4030, and is connected with FPC4017 by conductive paste material 4032.

For the wiring 4016 in negative electrode 4030 and the zone 4031 is electrically connected, need in interlayer dielectric 4026 and dielectric film 4028, form contact hole.Can be in advance when corrosion interlayer dielectric 4026 (when being formed for the contact hole of pixel capacitors) and when corrosion dielectric film 4028 (when forming opening before forming the EL layer), form these contact holes.Perhaps, when corrosion dielectric film 4028, also can corrode interlayer dielectric 4026 with the set form.In this case, if interlayer dielectric 4026 and dielectric film 4028 are made of the same resin material, then can make contact hole form favourable shape.

Form the passivating film 7013, filling component 7014 and the coating member 7010 that cover the EL element surface that so forms.

In addition, between coating member 7010 and substrate 4010, seal member 7000 is set, so that surround the EL element part, and at the seal member 7000 outside gas-tight seal parts (second seal member) 7001 that form.

In this case, filling component 7014 also is as the adhesive that is used for bonding coating member 7010.That can be used as filling component 7014 is PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral resin) or EVA (ethylene vinylacetate).When in filling component 7014, adding drier in advance, can advantageously keep moisture sorption effect.

In addition, can contain sept in the filling component 7014.In this case, the bulk material that can select to be made by BaO makes sept itself have moisture absorption as sept thus.

Under the situation that adopts sept, passivating film 7013 can relaxation sept pressure.Also allow the resin molding of the relaxation sept pressure that setting and passivating film 7013 separate etc.

What can be used as coating member 7010 is glass plate, aluminium sheet, corrosion resistant plate, FRP (fiberglass reinforced plastics) plate, PVF (polyvinyl fluoride) film, Mylar film, polyester film or acrylic acid (acrylic) film.In addition, use at filling component 7014 under the situation of PVB or EVA material, adopt that to have the thin slice that the thick aluminium foil of tens μ m is clipped in the structure between PVF film or the Mylar film be favourable.

But,, require coating member 7010 to have light transmission features according to the direction of light of sending from EL element (radiation direction of light).

In addition, wiring 4016 gaps of passing between seal member 7000 and gas-tight seal parts 7001 and the substrate 4010 are electrically connected to FPC4017.Though here by the agency of wiring 4016, other wiring 4014,4015 is passed below seal member 7000 and gas-tight seal parts 7001 and is electrically connected with FPC4017, with connect up 4016 the same.

(embodiment 10)

In this example, introduce the example of the EL layer of the structure of using manufacturing of the present invention to be different from embodiment 9 with reference to Figure 26 A and 26B.In these figure, the label identical with 25B with Figure 25 A represented identical part, and omitted the explanation about them.

Figure 26 A is the top plan view of the EL display panel in the present embodiment, has illustrated among Figure 26 B along the cutaway view of the A-A ' planar interception shown in Figure 26 A.

Carry out up to forming passivating film 7013 so that cover the step of EL element surface step according to embodiment 9.

In addition, filling component 7014 is set so that cover EL element.This filling component 7014 also is used as the adhesive that is used for bonding coating member 7010.That can be used as filling component 7014 is PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral resin) or EVA (ethylene vinylacetate).When in filling component 7014, adding drier in advance, can advantageously keep moisture sorption effect.

In addition, can contain sept in the filling component 7014.In this case, the bulk material that can select to be made by BaO etc. makes sept itself have moisture absorption as sept thus.

Under the situation that adopts sept, passivating film 7013 can relaxation sept pressure.Also allow the resin molding of the relaxation sept pressure that setting and passivating film 7013 separate etc.

What can be used as coating member 7010 is glass plate, aluminium sheet, corrosion resistant plate, FRP (fiberglass reinforced plastics) plate, PVF (polyvinyl fluoride) film, Mylar film, polyester film

Or acrylic film.In addition, use at filling component 6004 under the situation of PVB or EVA material, adopt that to have the thin slice that the thick aluminium foil of tens μ m is clipped in the structure between PVF film or the Mylar film be favourable.

But,, require coating member 7010 to have light transmission features according to the direction of light of sending from EL element (radiation direction of light).

Then, use filling component 7014 bonding coating members 7010, installation frame parts 7011 are so that cover the side surface (exposed surface) of filling component 7014 afterwards.With seal member (being used as adhesive) 7012 bonding frame partss 7011.In this case, preferably adopt light-cured resin to be used for seal member 7012.But, if the thermal resistance of EL layer allow, can use thermosetting resin.In addition, requiring seal member 7012 is the materials that prevent that as far as possible moisture and oxygen from entering.Can also in seal member 7012, add drier.

In addition, wiring 4016 gaps of passing between seal member 6002 and the substrate 4010 are electrically connected with FPC4017.Though by the agency of wiring 4016, other wiring 4014,4015 is passed below seal member 7012 and is electrically connected with FPC 4017, with connect up 4016 the same.

(embodiment 11)

In this example, figure 27 illustrates the more detailed sectional structure of the pixel unit of EL display panel, its top plan view has been shown in Figure 28 A, in Figure 28 B, circuit diagram has been shown.Owing to used general reference marker among Figure 27, Figure 28 A and Figure 28 B, so their references mutually.

In Figure 27, use N-channel TFT s to form the switching TFT 5302 that is arranged on the substrate 3501.Though adopted double-gate structure in this example, therefore itself structure and manufacturing process and aforementioned not too big difference no longer describe in detail.But in fact, double-gate structure is the structure of two TFTs series connection, and its advantage is the amplitude that can reduce the OFF electric current.In addition, TFT3502 has double-gate structure in this example, but also can adopt single grid structure or adopt three grid structures or have the multi-gate structure of a large amount of grid.And, can utilize P-channel TFT s to form TFT 3502.

Simultaneously, use the N-channel TFT to form Current Control TFT3503.In this case, the leak routing 35 of switch 3502 is electrically connected with the grid 37 of Current Control TFT3503 by wiring 36.In addition, the wiring by mark 38 expressions is and the grid 39a of switching TFT 3502, the grating routing that 39b is electrically connected.

Because Current Control TFT3503 is used for the element that control flows is crossed the magnitude of current of EL element, a large amount of electric currents flow through TFT, so this TFT is the element of degenerating owing to heat and hot carrier very easily.Therefore it is effectively adopting following structure: wherein the LDD district is arranged on leakage one side of Current Control TFT, so that by gate insulating film and grid stack.

In addition, the Current Control TFT3503 shown in this example is single grid structure, but also can be the multi-gate structure that a plurality of TFTs are connected in series.In addition, allow also and adopt such structure that promptly a plurality of TFTs are connected in parallel, so that channel formation region is divided into a plurality of zones, thus can be with the high efficiency radiations heat energy.A kind of means that this structure is degenerated as opposing heat are effectively.

And shown in Figure 28 A, the wiring that is used as the grid 37 of Current Control TFT3503 is passed by the leak routing of the dielectric film in the zone of mark 3504 expressions with Current Control TFT3503 and is superposeed.In this case, in zone, form capacitor by mark 3504 expressions.Capacitor 3504 is used to keep put on the voltage of the grid of Current Control TFT3503.In addition, leak routing 40 is connected with current feed line (power voltage line) 3506, and always keeps predetermined voltage to put on wiring 40.

Switching TFT 3502 and Current Control TFT3503 and 41 stacks of first passivating film, and first passivating film 41 also superposes with the leveling film 42 that is made of resin insulating film.Utilize 42 levelings of leveling film because the hierarchic structure that TFTs forms is very important.Because it is the back EL layer that will form is very thin, therefore very poor luminous owing to existing any hierarchic structure to occur sometimes.Thereby, wish these hierarchic structures of leveling before forming pixel capacitors, so that the EL layer can form flat as far as possible surface.

The pixel capacitors (negative electrode of EL element) that mark 43 expression is constituted and is connected with the electric leakage of Current Control TFT3503 by the conducting film of high reflectance.Low-resistance conducting film, as aluminium alloy film, tin-copper alloy film or silver alloy film, perhaps the stack membrane of these films all can be used as pixel capacitors 43.Certainly, can also adopt laminated construction with any other conducting film.

In addition, in the memory bank 44a that constitutes by dielectric film (preferably resin), groove (corresponding pixel) that 44b limits, form luminescent layer 45.Incidentally, though only show a pixel here, can form the luminescent layer of corresponding each color R (red), G (green), B (indigo plant) respectively.The organic EL Material that is used for luminescent layer is pi-conjugated polymer system material.Above-mentioned typical polymer system material is that the inferior ethene of polyparaphenylene (PPV) is, polyvinylcarbazole (PVK) is, gathers fluorine system etc.

In addition, PPV is that organic EL Material comprises many types.Can adopt at for example H.Shenk, H.Becker, O.Gelsen, E.Kluge, W.Kreuder, and H.Spreitzer: " Plolymers for LightEmitting Diodes ", Euro Display, Proceedings, 1999, any material described in the open No.10-92576 (1998) of pp.33-37 and Japanese patent application.

Luminescent layer as reality is used can use cyano group polyphenylene 1 for the luminescent layer that glows, the 2-ethenylidene, the luminescent layer of green light can use polyphenylene 1, the 2-ethenylidene, the luminescent layer of blue light-emitting can use polyphenylene 1,2-ethenylidene or poly-alkyl phenylene.The thickness of each luminescent layer can be set to 30-150nm (preferred 40-100nm).

But just for the example of the adoptable organic EL Material of luminescent layer, luminescent layer is not limited to above-mentioned material to above-mentioned material.Can form EL layer (can luminous and make carrier mobility) by combination in any luminescent layer, charge transport layer and electric charge injection layer so that luminous layer.

For example, in this example by the agency of adopt the example of polymer system material as luminescent layer, but also can use low molecule organic EL Material.Can also use inorganic material such as carborundum to be used for charge transport layer or electric charge injection layer.Well known materials can be used as organic EL Material and inorganic material.

In this example, the EL layer has laminated construction, wherein luminescent layer 45 and hole injection layer 46 stacks that are made of PEDOT (polythiophene) or PAni (polyaniline).Hole injection layer 46 superposes with the anode 47 that nesa coating constitutes.Under this routine situation, the upper surface side of the light directive EL display panel that produces by luminescent layer 45 (TFT upward to), so anode must can transmit light.The compound of the compound of indium oxide and tin oxide or indium oxide and zinc oxide can be used for nesa coating.But, owing to after the hole injection layer that forms luminescent layer and low thermal resistance, form anode, so this nesa coating should be the material that can form under minimum as far as possible temperature.

When forming anode 47, just finished EL element 3505.In addition, here the capacitor that " EL element 3503 " expression is formed by pixel capacitors (negative electrode) 43, luminescent layer 45, hole injection layer 46 and anode 47.Because the area of pixel capacitors 43 conforms to the area of the pixel shown in Figure 28 A basically, therefore whole pixel is used as EL element.Thereby the utilization ratio of light is very high, and can obtain image demonstration clearly.

Simultaneously, in this example, anode 47 also superposes with second passivating film 48.Silicon nitride film or oxygen silicon nitride membrane can be used as second passivating film 48.Second passivating film 48 makes EL element and external isolation, and has the function and the effect of inhibition gas from the organic EL Material effusion that prevents that organic EL Material from degenerating owing to oxidation.Like this, can improve the reliability of EL display panel.

As mentioned above, the pixel unit that EL display panel according to the present invention has the pixel by structure shown in Figure 27 to constitute, and the Current Control TFTs that comprises the very low switching TFT s of OFF electric current and can avoid hot carrier to inject.Thereby can obtain to have high reliability and can produce the EL display panel that high quality image shows.

Using this routine EL display panel also is effective as the display unit of each electronic equipment among the embodiment 6.

(embodiment 12)

To be presented in the structure that the structure of EL element 3505 is squeezed in the pixel unit described in the embodiment 11 in this example.With reference to Figure 29.Incidentally, only be part EL element and Current Control TFT owing to be different from the place of the structure of Figure 27, therefore the explanation of having omitted other parts.

Referring to Figure 29, form Current Control TFT3503 with the P-channel TFT.

In this example, nesa coating is used as pixel capacitors (anode) 50.Specifically, this conducting film is made of the compound of indium oxide and zinc oxide.Certainly, can also use the conducting film of making by the compound of indium oxide and tin oxide.

After the memory bank 51a and 51b that formation is made by dielectric film; Form the luminescent layer of making by polyvinylcarbazole 52 with the solution coating.Luminescent layer 52 can order superpose with the electron injecting layer of being made by acetylacetonate potassium (being called " acacK ") 53 with by the negative electrode 54 that aluminium alloy is made.In the case, negative electrode 54 also is used as passivating film.So just finished EL element 3701.

In the case of this example, the light directive that is produced by luminescent layer 52 is formed with the substrate of TFTs, as shown by arrows.

Using this routine EL display panel also is effective as each electronic equipment among the embodiment 6.

(embodiment 13)

In this example, introduce the situation that pixel structure has structure shown in the circuit diagram that is different from Figure 28 B with reference to Figure 30 A, 30B and 30C.In this example, the source wiring of mark 3801 expression switching TFT 3802, the grating routing of mark 3803 expression switching TFT 3802, mark 3804 expression Current Control TFT, mark 3805 expression capacitors, mark 3806,3808 expression power delivery lines, mark 3807 expression EL element.

Example corresponding power pipeline 3806 shown in Figure 30 A public situation between two pixels.That is, these routine characteristics are that two pixels form with respect to power delivery line 3806 linear symmetric.In this case, can reduce the quantity of power delivery line, therefore can further improve the definition of pixel unit.

In addition, the example corresponding power pipeline 3808 shown in Figure 30 B is arranged to the situation parallel with grating routing 3803.In addition, in the structure of Figure 30 B, power delivery line 3808 and grating routing 3803 are arranged to not superpose mutually.But if form this two wiring in different layers, they can be arranged to pass the dielectric film form of stack mutually.In this case, power delivery line 3808 and grating routing 3803 can have public footprint area, make the definition of pixel unit higher.

In addition, the characteristics of example shown in Figure 30 C are that power delivery line 3808 usefulness and the same way as in Figure 30 B structure be arranged to parallelly with grating routing 3803, and two pixels form with respect to power delivery line 3808 linear symmetric.Power delivery line 3808 be arranged to grating routing 3808a, 3803b in a stack also be effective.In this case, can reduce the quantity of power delivery line, thereby the definition of pixel unit is further improved.

In addition, this routine structure can with the structure combination in any of embodiment 9 or 10.The EL display panel that use has this routine pixel structure also is effective as the display unit of each electronic equipment among the embodiment 6.

(embodiment 14)

In embodiment 11, among Figure 28 A and the structure shown in the 28B of institute's reference, provide capacitor 3504, but also can save capacitor 3504 in order to keep putting on the voltage of Current Control TFT3503.Under the situation of embodiment 11, Current Control TFT3503 comprises and is arranged to pass the LDD district that gate insulating film is superposeed by grid.Usually, in each overlap-add region, can form the parasitic capacitance that is called " gate capacitance ".These routine characteristics are effectively to utilize parasitic capacitance to replace capacitor 3504.

The size of parasitic capacitance depends on the stack area between grid and each the LDD district.Therefore can determine by the length that is included in each the LDD district in the overlap-add region.

In embodiment 13, can save capacitor 3805 equally in each structure of Figure 30 A, the 30B of institute's reference and 30C.

In addition, this routine structure can with the structure combination in any of embodiment 9-13.The EL display panel that use has this routine pixel structure also is effective as the display unit of each electronic equipment among the embodiment 6.

The present invention has following effect.

It is half the clock signal of frequency of the frequency of the numerical data that will input that serial-to-parallel conversion (SPC) circuit that is used for numerical data according to the present invention only needs the highest. Therefore, compare with the change-over circuit of prior art, stability and the reliability of SPC circuit of the present invention are more excellent.

And the serial-to-parallel change-over circuit that is used for numerical data with prior art is compared, the element of SPC circuit of the present invention and the quantity of wiring still less, area is less. Therefore can make the size of the active matrix type semiconductor display device that adopts SPC circuit of the present invention less.

Claims (24)

1. serial-to-parallel change-over circuit comprises:

Be used to produce the clock generator of first clock signal to i clock signal; And

First order circuit is to i level circuit, and wherein each grade circuit comprises and contains transistorized latch circuit,

Wherein, first order circuit will become x2 with the digital data conversion of x Hz serial input to i level circuit ^-iThe 2i of a Hz parallel digital data,

Wherein, j clock signal is imported into j level circuit,

Wherein, first clock signal is x/2Hz to the highest frequency of i clock signal,

Wherein, the contained characteristics of transistor of j level circuit is different from the contained characteristics of transistor of k level circuit,

Wherein, alphabetical i represents natural number,

Wherein, alphabetical j represents to be no more than the natural number of n,

Wherein, alphabetical k represents the natural number that is not less than j and is no more than n, and

Wherein, alphabetical x represents positive number.

2. serial-to-parallel change-over circuit as claimed in claim 1, wherein, the frequency of j clock signal in the described i clock signal is for x.2 ^-jHz.

3. serial-to-parallel change-over circuit as claimed in claim 1, wherein, described latch circuit is the D-latch circuit that contains the clock inverter.

4. serial-to-parallel change-over circuit as claimed in claim 1 also comprises 2 ⁱIndividual being used for to described 2 ⁱThe numerical data that individual parallel digital data rearranges rearranges switch.

5. one kind comprises the display unit according to the serial-to-parallel change-over circuit of claim 1.

6. one kind comprises the equipment according to the display unit of claim 5, wherein, described equipment is one that selects from the group that comprises front type projecting apparatus, back side type projecting apparatus, pocket telephone, video camera, mobile computer, head mounted display and e-book.

7. serial-to-parallel change-over circuit comprises:

Be used to produce the clock generator of first clock signal to i clock signal; And

First order circuit is to i level circuit,

Wherein j level circuit comprises 2 ^J-1Individual SPC elementary cell, each SPC elementary cell comprise and contain transistorized latch circuit,

Wherein, first order circuit will become x2 with the digital data conversion of x Hz serial input to i level circuit ^-i2 of Hz ⁱIndividual parallel digital data,

Wherein, j clock signal is imported into j level circuit,

Wherein, first clock signal is x/2Hz to the highest frequency of i clock signal,

Wherein, the contained characteristics of transistor of j level circuit is different from the contained characteristics of transistor of k level circuit,

Wherein, alphabetical i represents natural number,

Wherein, alphabetical j represents to be no more than the natural number of n,

Wherein, alphabetical k represents the natural number that is not less than j and is no more than n, and

Wherein, alphabetical x represents positive number.

8. serial-to-parallel change-over circuit as claimed in claim 7, wherein, the frequency of j clock signal in the described i clock signal is for x.2 ^-jHz.

9. serial-to-parallel change-over circuit as claimed in claim 7, wherein, described latch circuit is the D-latch circuit that contains the clock inverter.

10. serial-to-parallel change-over circuit as claimed in claim 7 also comprises 2 ⁱIndividual being used for to described 2 ⁱThe numerical data that individual parallel digital data rearranges rearranges switch.

11. one kind comprises the display unit according to the serial-to-parallel change-over circuit of claim 7.

12. one kind comprises the equipment according to the display unit of claim 11, wherein, described equipment is one that selects from the group that comprises front type projecting apparatus, back side type projecting apparatus, pocket telephone, video camera, mobile computer, head mounted display and e-book.

13. a serial-to-parallel change-over circuit comprises:

N SPC/ position circuit, wherein each SPC/ position circuit comprises:

Be used to produce the clock generator of first clock signal to i clock signal; And

First order circuit is to i level circuit, and wherein each grade circuit comprises and contains transistorized latch circuit,

Wherein, first order circuit will convert x2 to in the n bit digital data of x Hz serial input to i level circuit ^-i2 of Hz ⁱIndividual parallel one-bit digital data,

Wherein, j clock signal is imported into j level circuit,

Wherein, first clock signal is x/2Hz to the highest frequency of i clock signal,

Wherein, the contained characteristics of transistor of j level circuit is different from the contained characteristics of transistor of k level circuit,

Wherein, alphabetical n represents natural number,

Wherein, alphabetical i represents natural number,

Wherein, alphabetical j represents to be no more than the natural number of n,

Wherein, alphabetical k represents the natural number that is not less than j and is no more than n, and

Wherein, alphabetical x represents positive number.

14. serial-to-parallel change-over circuit as claimed in claim 13, wherein, the frequency of j clock signal in the described i clock signal is for x.2 ^-jHz.

15. serial-to-parallel change-over circuit as claimed in claim 13, wherein, described latch circuit is the D-latch circuit that contains the clock inverter.

16. each the SPC/ position circuit in the serial-to-parallel change-over circuit as claimed in claim 13, wherein said n SPC/ position circuit comprises 2 ⁱIndividual being used for to described 2 ⁱThe numerical data that individual parallel one-bit digital data rearrange rearranges switch.

17. one kind comprises the display unit according to the serial-to-parallel change-over circuit of claim 13.

18. one kind comprises the equipment according to the display unit of claim 17, wherein, described equipment is one that selects from the group that comprises front type projecting apparatus, back side type projecting apparatus, pocket telephone, video camera, mobile computer, head mounted display and e-book.

19. a serial-to-parallel change-over circuit comprises:

N SPC/ position circuit, wherein each SPC/ position circuit comprises:

Be used to produce the clock generator of first clock signal to i clock signal; And

First order circuit is to i level circuit,

Wherein j level circuit comprises 2 ^J-1Individual SPC elementary cell, wherein each SPC elementary cell comprises and contains transistorized latch circuit,

Wherein, first order circuit will convert x2 to in the n bit digital data of x Hz serial input to i level circuit ^-i2 of Hz ⁱIndividual parallel one-bit digital data,

Wherein, j clock signal is imported into j level circuit,

Wherein, first clock signal is x/2Hz to the highest frequency of i clock signal,

Wherein, the contained characteristics of transistor of j level circuit is different from the contained characteristics of transistor of k level circuit,

Wherein, alphabetical n represents natural number,

Wherein, alphabetical i represents natural number,

Wherein, alphabetical j represents to be no more than the natural number of n,

Wherein, alphabetical k represents the natural number that is not less than j and is no more than n, and

Wherein, alphabetical x represents positive number.

20. serial-to-parallel change-over circuit as claimed in claim 19, wherein, the frequency of j clock signal in the described i clock signal is for x.2 ^-jHz.

21. serial-to-parallel change-over circuit as claimed in claim 19, wherein, described latch circuit is the D-latch circuit that contains the clock inverter.

22. each the SPC/ position circuit in the serial-to-parallel change-over circuit as claimed in claim 19, wherein said n SPC/ position circuit comprises 2 ⁱIndividual being used for to described 2 ⁱThe numerical data that individual parallel one-bit digital data rearrange rearranges switch.

23. one kind comprises the display unit according to the serial-to-parallel change-over circuit of claim 19.

24. one kind comprises the equipment according to the display unit of claim 23, wherein, described equipment is one that selects from the group that comprises front type projecting apparatus, back side type projecting apparatus, pocket telephone, video camera, mobile computer, head mounted display and e-book.

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