CN100523921C - Pixel sampling circuit of active matrix display device - Google Patents
Pixel sampling circuit of active matrix display device Download PDFInfo
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- CN100523921C CN100523921C CNB2005101080930A CN200510108093A CN100523921C CN 100523921 C CN100523921 C CN 100523921C CN B2005101080930 A CNB2005101080930 A CN B2005101080930A CN 200510108093 A CN200510108093 A CN 200510108093A CN 100523921 C CN100523921 C CN 100523921C
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Abstract
A pixel sampling circuit of active matrix display is featured as utilizing wire pair mode to transmit data of scanning line to display face plate and coordinating with display face plate to carry out reverse driving for displaying picture.
Description
Technical field
The invention relates to a kind of pixel sampling circuit, and particularly relevant for a kind of pixel sampling circuit of active matrix display device.
Background technology
TV signal adopts staggered video picture mode (interlacing) mostly, just each picture (frame) of TV signal is made up of an odd number figure field (odd field) and an even number figure field (evenfield), and the sweep trace of one of them figure field crisscrosses between the sweep trace of another figure field.
Fig. 1 illustrates the synoptic diagram into staggered video picture formula TV signal.Please refer to Fig. 1, is example with the ntsc television system for example, and a picture has 525 sweep traces, but after deduction was used to return the sweep trace of speeding, the effective scanning line that really contains image data was 484, respectively with 1,2,3 ..., 482,483 and 484 signs.And a picture is made up of an odd number Tu Chang and an even number figure place, wherein odd number figure field comprise this picture be denoted as 1,3,5 ..., 481 and 483 sweep trace, even number figure field comprise this picture be denoted as 2,4,6 ..., 482 and 484 sweep trace.
Fig. 2 illustrates to adopting LCD to play the synoptic diagram of TV signal.In fact, the type of drive of the display panel of general LCD is for activating each bar sweep trace of (enable) display panels (scan line) in regular turn, and when a certain sweep trace activated, send into corresponding data by the data line (data line) of display panels, this data can be a certain the data that effective scanning line comprised of above-mentioned odd number figure field or even number figure field.
Please refer to Fig. 2, wherein X, Y represent the data line of display panel of LCD and the label of sweep trace respectively, and T represents the label of the sweep trace data of TV signal.When the display panels that has 240 sweep traces when utilization showed above-mentioned picture (being that its odd number figure field and even number figure field have 242 sweep trace data respectively) with 484 sweep trace data, its broadcast mode was odd number figure field and the even number figure field that alternately shows each picture.For example, elder generation shows that the odd number figure field of first picture shows the even number figure field of first picture again on display panels, next the odd number figure field that shows second picture shows the even number figure field of second picture again, so alternately shows the odd number figure field and the even number figure field of each picture.
In known techniques, in order to increase resolution, the general practice is the number of scanning lines increase with display panels, the display panels that for example will have 240 sweep traces increases to 480 sweep traces, and most common form is that sweep trace is originally increased in the right mode of line, and for example the odd number figure field data line label that transmits originally is { 1 in proper order, 3,5,7,9,11 ... }, after passing through the right processing of line again, can be adjusted into { 1,1,3,3,5,5,7,7,9,9,11,11, ..., that is represent that the data of same group of data line repeats to transmit twice.Certainly, even number figure increases its sweep trace with identical line to mode, so to improve the resolution of display panels.
Please refer to Fig. 3, it illustrates is in the known techniques, and in the display panel of LCD, the circuit diagram of one group of pixel sampling circuit wherein below describes with the load mode of the sweep trace data of odd number figure field.In this circuit, be utilize gauge tap 301～307 conducting whether, transmit the sweep trace data of odd number figure field in regular turn continuously.For example, when data line will transmit first group of sweep trace data earlier, it is first conducting switch 301, first group of sweep trace data can be stored in the capacitor C 1, follow actuating switch 303 again, the first group of sweep trace data transmission that is stored in capacitor C 1 gone out, and the switch 307 of this moment is an open-circuit condition, therefore can't transmits second group of sweep trace data this moment.Otherwise, in the time will transmitting next group sweep trace data, utilize the above-mentioned mode gauge tap 305 and the action of switch 307 to reach equally.
As previously mentioned, when right mode increases the resolution of display panels if desire is utilized line, must in above-mentioned pixel sampling circuit, increase extra memory body more in addition, to store the sweep trace data that is increased.Moreover, suppose in the process of continuous Alternation Display odd number figure field and even number figure field, when just in time same data line having been applied identical bias voltage, in fact liquid crystal is continuously applied unidirectional electric field, so also can cause liquid crystal torque characteristic variation maybe can't reverse, also can cause simultaneously the shown picture that goes out of display panels to have the phenomenon generation of flicker (flicker).
Summary of the invention
Purpose of the present invention is exactly that a kind of pixel sampling circuit of active matrix display device is being provided, and does not need to use extra memory body and complicated algorithm, promptly can allow the capable inversion driving of display panels, and increases the resolution of display frame.
The present invention proposes a kind of pixel sampling circuit of active matrix display device, and in order to provide a data line required pixel signal, this pixel sampling circuit comprises the first pixel sampling unit and the second pixel sampling unit.Wherein, the first pixel sampling unit receives N group pixel signal with first polarity and the N group pixel signal with second polarity, and the N of the N group pixel signal of exporting first polarity according to a clock pulse signal and second polarity organize the pixel signal the two one of.
In addition, the second pixel sampling unit receives N+1 group pixel signal with first polarity and the N+1 group pixel signal with second polarity, and the N+1 of the N+1 group pixel signal of exporting first polarity according to time pulse signal and second polarity organize the pixel signal the two one of.Wherein, N is a positive integer, and the first above-mentioned polarity is opposite with the polarity of second polarity.Pixel sampling circuit then be according to time pulse signal receive in regular turn and transmit N group pixel signal and N+1 organize pixel the two one of.
Described according to preferred embodiment of the present invention, the first above-mentioned pixel sampling unit comprises first storage element, second storage element, the first gauge tap group.Wherein, first storage element receives and stores the N group pixel signal of first polarity.Wherein, second storage element receives and stores the N group pixel signal of second polarity.And the first gauge tap group couples first storage element and second storage element, in order to the N of the N group pixel signal of control output first polarity and second polarity organize the pixel signal the two one of.
Described according to preferred embodiment of the present invention, the second above-mentioned pixel sampling unit comprises the 3rd storage element, the 4th storage element, the second gauge tap group.Wherein, the 3rd storage element receives and stores the N+1 group pixel signal of first polarity.The 4th storage element receives and stores the N+1 group pixel signal of second polarity.And the second gauge tap group couples the 3rd storage element and the 4th storage element, in order to the N+1 of the N+1 group pixel signal of control output first polarity and second polarity organize the pixel signal the two one of.
Described according to preferred embodiment of the present invention, each above-mentioned group storage element comprises first switch and storage unit.Wherein, the plain signal of the first termination reproduced image of first switch, and first end of storage unit couples second end of first switch, second end then is coupled to ground.Wherein, above-mentioned storage unit is an electric capacity.
Described according to preferred embodiment of the present invention, above-mentioned time pulse signal is that M is during the cycle, first storage element and second storage element store the N group pixel signal of first polarity and the N group pixel signal of second polarity respectively, wherein, first switch in first storage element and second storage element is a conducting state, and M is a positive integer.
Described according to preferred embodiment of the present invention, above-mentioned time pulse signal is M+1 during the cycle, and the first gauge tap group couples first storage element, and time pulse signal is M+2 during the cycle, and the first gauge tap group is coupled to second storage element.
Described according to preferred embodiment of the present invention, the first above-mentioned gauge tap group comprises second switch and the 3rd switch.First end of second switch couples second end of first switch of first storage element, and second end of second switch couples second end of first switch of second storage element.First end of the 3rd switch couples the 3rd end of second switch, and second end is exported N group pixel signal.
Wherein, when the clock pulse signal is this M+1 during the cycle, first end and the 3rd end of second switch are conducting state, and when the clock pulse signal is this M+2 during the cycle, second end of second switch and the 3rd end are conducting state.And when the clock pulse signal be M+1 cycle and M+2 during the cycle, the 3rd switch is a conducting state.And the second gauge tap group is an open-circuit condition.
Described according to preferred embodiment of the present invention, above-mentioned time pulse signal is M+2 during the cycle, and the 3rd storage element and the 4th storage element store N+1 group pixel signal with first polarity and the N+1 group pixel signal with second polarity respectively.First switch of the 3rd storage element and the 4th storage element is a conducting state.When the clock pulse signal is M+3 during the cycle, the second gauge tap group couples the 3rd storage element, and when the clock pulse signal be M+4 during the cycle, the second gauge tap group is coupled to the 4th storage element.
Described according to preferred embodiment of the present invention, the second above-mentioned gauge tap group comprises second switch and the 3rd switch.Wherein first end of second switch couples second end of first switch of the 3rd storage element, and second end of second switch couples second end of first switch of the 4th storage element.First end of the 3rd switch couples the 3rd end of second switch, and second end is exported N+1 group pixel signal.
When the clock pulse signal is M+3 during the cycle, first end of the 4th switch and the 3rd end are conducting state.And time pulse signal is M+4 during the cycle, and second end of the 4th switch and the 3rd end are conducting state.When the clock pulse signal is M+3 cycle and M+4 during the cycle, the 5th switch is a conducting state, and the first gauge tap group is an open-circuit condition.
The present invention because of adopt line to mode with the sweep trace data transmission of picture to display panels, and display panels can also be gone inversion driving, so promptly can not need to use extra memory body and complicated algorithm, just can increase the resolution of display frame.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 illustrates the synoptic diagram into staggered video picture formula TV signal.
Fig. 2 illustrates to adopting LCD to play the synoptic diagram of staggered video picture formula TV signal.
It is in the known techniques that Fig. 3 illustrates, in the display panel of LCD, and the circuit diagram of one group of pixel sampling circuit wherein.
It is according in the present invention's one preferred embodiments that Fig. 4 illustrates, the pixel sampling circuit figure of active matrix display device.
It is according in the pixel sampling circuit in the preferred embodiment of the present invention that Fig. 5 illustrates, the synoptic diagram of the work period of its inner each switch room.
301～307,401～408: switch
421～424: storage unit
431～435: end points
441,443: the pixel sampling unit
451,452: the gauge tap group
461～464: storage element
C1, C2: electric capacity
X: the data line of display panels
Y: the sweep trace of display panels
T: the sweep trace data of TV signal
+: (polarity is) on the occasion of
-: (polarity is) negative value
Embodiment
Please refer to Fig. 4, it illustrates is according in the present invention's one preferred embodiments, the pixel sampling circuit figure of active matrix display device.As shown in FIG., above-mentioned pixel sampling circuit has comprised the first pixel sampling unit 441 and the second pixel sampling unit 443.Wherein, the first pixel sampling unit 441 comprises first storage element 461, second storage unit 462, and the first gauge tap group 451.And the second pixel sampling unit 443 comprises the 3rd storage element 463, the 4th storage unit 464, and the second gauge tap group 452.
Wherein, in each above-mentioned group storage element, more comprise one group of switch and one group of storage unit.For example, in the first pixel sampling unit 441, comprise first switch 401 and first storage unit 421 in first storage element 461, and comprise the second switch 402 and second storage unit 422 in second storage element 462.And the element that is comprised in the second pixel sampling unit 443 is then identical with first pixel cell 441, does not repeat them here.
In addition, in each above-mentioned group gauge tap group, other comprises two groups of gauge tap.Wherein, in the first gauge tap group 451, first end of the 3rd switch 403 couples second end of first switch 401, its second end is coupled to second end of second switch 402, first end of the 4th switch 404 then is the 3rd end that couples the 3rd switch 403, second end then is the output terminal 435 that is coupled to pixel sampling circuit, in order to export the above-mentioned pixel signal that is stored in the storage element.
In the second gauge tap group 452, first end of minion pass 407 couples second end of the 5th switch 405, its second end is coupled to second end of the 6th switch 406, first end of octavo pass 408 then is the 3rd end that couples minion pass 407, second end then is the output terminal 435 that is coupled to pixel sampling circuit, in order to export the above-mentioned pixel signal that is stored in the storage element.
In the present embodiment, in first storage element 461 in the first pixel sampling unit 441, first end 431 of first switch 401 receives the N group pixel signal of first polarity, and first end 432 of second switch 402 then is the N group pixel signal that receives second polarity.And first end of first storage unit 421 is coupled to second end of first switch 401, and first end of second storage unit 422 then is second end that is coupled to second switch 402, and second end of each group storage unit then is to be coupled to ground.
In addition, in the second pixel sampling unit 443 in the present embodiment, its each interelement relation object that couples is similar to the first pixel sampling unit 441, is not giving unnecessary details at this.Wherein, different is, first end 433 of the 5th switch 405 is the N+1 group pixel signals that receive first polarity, and first end 434 of the 6th switch 406 then is the N+1 group pixel signal that receives second polarity.
Wherein, in the present embodiment, storage unit 421～424 aims to provide a memory function, and for example, when first switch 401 was conducting state, first storage element 421 promptly can store the pixel signal of first polarity.And in the present embodiment, storage element is to be replaced by electric capacity, and any element that can carry memory function, all applicable in the present embodiment.
In the present embodiment, first polarity just in time is opposite with the polarity of second polarity, for example, first polarity be on the occasion of, and second polarity is negative value; Perhaps, first polarity is negative value, and second polarity be on the occasion of.Suppose in the odd number figure field and even number figure field of continuous Alternation Display, if it is just in time identical to the bias voltage that data line applied, but because first polarity just in time is opposite with the polarity of second polarity, therefore when showing different figure fields picture continuously, can make display panel carry out inversion driving, take place liquid crystal is continuously applied the problem of folk prescription to electric field avoiding.。
Please refer to Fig. 5, it illustrates is according to the sampling of the pixel in the preferred embodiment of the present invention, the synoptic diagram of the work period of its inner each switch room.Wherein, for convenience of description, in this synoptic diagram, when switch list is shown high levels, promptly represents conducting state, and when switch is low level, promptly be expressed as open-circuit condition, below promptly cooperate the embodiment among Fig. 4 to describe.
When clock pulse signal during in cycle 1, first switch 401 is a conducting state with second switch 402, therefore first storage unit 421 is that to begin to receive and write down polarity be positive N group pixel signal, and second storage unit 422 also begins to receive and write down polarity simultaneously and is negative N group pixel signal.
When clock pulse signal during in cycle 2 and cycle 3, the 4th switch 404 is all conducting state, and it then is closed condition that octavo closes 408.When time pulse signal was the cycle 3, first end of the 3rd switch 403 was coupled to the 3rd end, and 4 o'clock cycles, second end of the 3rd switch 403 then was to be coupled to the 3rd end.Therefore, the cycle 2, having only polarity is that positive N group pixel signal can transmit, and the cycle 3, then is to transmit polarity to be negative N group pixel signal.
In addition, when clock pulse signal the time in cycle 3, the 5th switch 405 and the 6th switch 406 are conducting states, therefore to begin to receive and write down polarity be positive N+1 group pixel signal to the 3rd storage unit 423, and the 4th storage unit 424 also begins to receive and write down polarity simultaneously and is negative N+1 group pixel signal.
In cycle 2 and cycle 3, when clock pulse signal during in cycle 4 and cycle 5, it is conducting state that octavo closes 408 with respect to time pulse signal, and the 4th switch 404 then is a closed condition.And when time pulse signal was the cycle 4, first end of minion pass 407 was coupled to the 3rd end, and 5 o'clock cycles, second end of minion pass 407 then was to be coupled to the 3rd end.Therefore, the cycle 4, having only polarity is that positive N+1 group pixel signal can transmit, and the cycle 5, then is to transmit polarity to be negative N+1 group pixel signal.
According to above-mentioned explanation, close in the previous cycle of 408 conductings at the 4th switch 404 and octavo, storage unit 421～424 can upgrade self stored data earlier, and then two time pulse signals that get off are in the cycle, transmit the pixel signal of two opposed polarities respectively, the memory cell that does not so promptly need to add again other stores the data of pixel signal.
And in general active matrix display device,, can receive the data line signal of odd number figure field and the data line signal of even number figure field as illustrated in the known techniques.In the above-described embodiment, this pixel sampling circuit can be in each group displayed map field, wherein the sample circuit of one group of data line.Use disclosed pixel sampling circuit among the present invention, promptly the display frame of odd number figure field and even number figure field alternately can be shown on the display.
In addition, if the data number of sweep trace is during more than the displayable sweep trace number of display, for example, if when the active matrix display device of 240 sweep traces of tool shows the odd number figure field (or even number figure field) of 242 sweep trace data of tool, need cast out two sweep trace data inevitably, generally speaking, be to adopt to cast out end to end two or other and cast out mode, but just the result is little to the picture influence of integral body.
In sum, the present invention because of adopt line to mode with the sweep trace data transmission of picture to display panels, display panels can be gone inversion driving, does not also need to use extra memory body and complicated algorithm simultaneously, promptly can increase the resolution of display frame.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limiting the present invention, anyly has the knack of this skill person, without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the claim person of defining.
Claims (20)
1, a kind of pixel sampling circuit of active matrix display device in order to provide a data line required pixel signal, is characterized in that this pixel sampling circuit comprises:
One first pixel sampling unit, the N group pixel signal and N group pixel signal that have one first polarity in order to reception with one second polarity, and this N of this N group pixel signal of exporting this first polarity according to a clock pulse signal and this second polarity organize pixel signal the two one of, the described first pixel sampling unit comprises:
One first storage element is in order to receive and to store this N group pixel signal of this first polarity;
One second storage element is in order to receive and to store this N group pixel signal of this second polarity;
And
One first gauge tap group couples this first storage element and this second storage element, in order to this N of this N group pixel signal of this first polarity of control output and this second polarity organize pixel signal the two one of; And
One second pixel sampling unit, the N+1 group pixel signal and N+1 group pixel signal that have this first polarity in order to reception with this second polarity, and this N+1 of this N+1 group pixel signal of exporting this first polarity according to this time pulse signal and this second polarity organize pixel signal the two one of, this second pixel sampling unit comprises:
One the 3rd storage element is in order to receive and to store this N+1 group pixel signal of this first polarity;
One the 4th storage element is in order to receive and to store this N+1 group pixel signal of this second polarity; And
One second gauge tap group couples the 3rd storage element and the 4th storage element, in order to this N+1 of this N+1 group pixel signal of this first polarity of control output and this second polarity organize pixel signal the two one of,
Wherein said each those storage element comprise:
One first switch, first end of this first switch is in order to receive this pixel signal; And
One first storage unit, first end of this storage unit couples second end of this first switch,
Second end is coupled to ground,
The described first gauge tap group comprises:
One second switch, first end of this second switch couples second end of this first switch of this first storage element, and second end of this second switch couples second end of this first switch of this second storage element; And
One the 3rd switch, first end of the 3rd switch couples the 3rd end of this second switch, and second end is exported this N group pixel signal,
Wherein, N is a positive integer, and this first polarity is opposite with the polarity of this second polarity, this pixel sampling circuit receive in regular turn and transmit according to this time pulse signal this N group pixel signal and this N+1 organize pixel the two one of.
2, the pixel sampling circuit of active matrix display device according to claim 1 is characterized in that wherein said storage unit is an electric capacity.
3, the pixel sampling circuit of active matrix display device according to claim 1, it is characterized in that wherein when this time pulse signal be that a M is during the cycle, this first storage element and this second storage element store this N group pixel signal of this first polarity and this N group pixel signal of this second polarity respectively, wherein, M is a positive integer.
4, the pixel sampling circuit of active matrix display device according to claim 3 is characterized in that this first switch in wherein said first storage element and this second storage element is a conducting state.
5, the pixel sampling circuit of active matrix display device according to claim 4 is characterized in that wherein said time pulse signal is the M+1 during cycle, and this first gauge tap group couples this first storage element.
6, the pixel sampling circuit of active matrix display device according to claim 5 is characterized in that wherein said time pulse signal is the M+2 during cycle, and this first gauge tap group couples this second storage element.
7, the pixel sampling circuit of active matrix display device according to claim 6 is characterized in that wherein said time pulse signal is this M+1 during the cycle, and first end of this second switch and the 3rd end are conducting state.
8, the pixel sampling circuit of active matrix display device according to claim 6 is characterized in that wherein said time pulse signal is this M+2 during the cycle, and second end of this second switch and the 3rd end are conducting state.
9, the pixel sampling circuit of active matrix display device according to claim 6 is characterized in that wherein said time pulse signal is this M+1 cycle and this M+2 during the cycle, and the 3rd switch is a conducting state.
10, the pixel sampling circuit of active matrix display device according to claim 6 is characterized in that wherein said time pulse signal is this M+1 cycle and this M+2 during the cycle, and this second gauge tap group is an open-circuit condition.
11, the pixel sampling circuit of active matrix display device according to claim 6, it is characterized in that wherein said time pulse signal is this M+2 during the cycle, the 3rd storage element and the 4th storage element store this N+1 group pixel signal of this first polarity respectively and this N+1 of this second polarity organizes pixel signal.
12, the pixel sampling circuit of active matrix display device according to claim 11 is characterized in that this first switch of wherein said the 3rd storage element and the 4th storage element is a conducting state.
13, the pixel sampling circuit of active matrix display device according to claim 12 is characterized in that wherein said time pulse signal is the M+3 during phase, and this second gauge tap group couples the 3rd storage element.
14, the pixel sampling circuit of active matrix display device according to claim 13 is characterized in that wherein said time pulse signal is the M+4 during cycle, and this second gauge tap group couples the 4th storage element.
15, the pixel sampling circuit of active matrix display device according to claim 14 is characterized in that the wherein said second gauge tap group comprises:
One the 4th switch, first end of the 4th switch couples second end of this first switch of the 3rd storage element, and second end of the 4th switch couples second end of this first switch of the 4th storage element; And
One the 5th switch, first end of the 5th switch couples the 3rd end of this second switch, and second end is exported this N+1 group pixel signal.
16, the pixel sampling circuit of active matrix display device according to claim 15 is characterized in that wherein said time pulse signal is this M+3 during the cycle, and first end of the 4th switch and the 3rd end are conducting state.
17, the pixel sampling circuit of active matrix display device according to claim 15 is characterized in that wherein said time pulse signal is this M+4 during the cycle, and second end of the 4th switch and the 3rd end are conducting state.
18, the pixel sampling circuit of active matrix display device according to claim 15 is characterized in that wherein said time pulse signal is this M+3 cycle and this M+4 during the cycle, and the 5th switch is a conducting state.
19, the pixel sampling circuit of active matrix display device according to claim 18 is characterized in that wherein said time pulse signal is this M+3 cycle and this M+4 during the cycle, and this first gauge tap group is an open-circuit condition.
20, the pixel sampling circuit of active matrix display device according to claim 1, it is characterized in that wherein said first polarity on the occasion of, and this second polarity is negative value.
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| CNB2005101080930A CN100523921C (en) | 2005-09-29 | 2005-09-29 | Pixel sampling circuit of active matrix display device |
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| CNB2005101080930A CN100523921C (en) | 2005-09-29 | 2005-09-29 | Pixel sampling circuit of active matrix display device |
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| CN100523921C true CN100523921C (en) | 2009-08-05 |
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