CN100521657C - Method for allocating bandwidth dynamically to design on-chip network - Google Patents
Method for allocating bandwidth dynamically to design on-chip network Download PDFInfo
- Publication number
- CN100521657C CN100521657C CNB2007101177155A CN200710117715A CN100521657C CN 100521657 C CN100521657 C CN 100521657C CN B2007101177155 A CNB2007101177155 A CN B2007101177155A CN 200710117715 A CN200710117715 A CN 200710117715A CN 100521657 C CN100521657 C CN 100521657C
- Authority
- CN
- China
- Prior art keywords
- virtual channel
- buffering area
- bandwidth
- output
- moderator
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The invention features the following: setting up a arbitrator on the sending end; the input of the arbitrator is connected to the buffer area; setting up an empty flag indicating signal at buffer area; if the empty flag indicating signal is '0', it means empty; if the empty flag indicating signal is '1', it means non-empty; setting up a shunt, and its each data output end is connected to the receiving buffer area of each virtual channel; setting up a full-flag indicating signal at receiving buffer area; if it is '0', it means full; if it is '1', it means non-full; the indicating signals in each sending or receiving buffer area are sent to multi AND gates whose amounts are same with the amounts of buffer areas; when a certain AND gate outputs a '1', it means that a certain virtual channel requests a bandwidth, and the arbitrator allocates the bandwidth for it.
Description
Technical field
The invention belongs to integrated circuit (IC) design, relate in particular to on-chip interconnect network design field.
Background technology
Integrated circuit advances according to Moore's Law always, single-chip integrated IP (Intellectual Property) piece number more and more, traditional on-chip interconnect structure based on bus is in increasing limitation of aspect performance place such as bandwidth, power consumption, reliability, autgmentabilities, and chip-on communication has been substituted the bottleneck that is calculated to be to integrated circuit (IC) design.(Network-on-Chip NoC) as a key technology in integrated circuit (IC) design field, has been used to solve chip-scale and has increased the on-chip interconnect problem of being brought network-on-chip.
Because the network-on-chip resource-constrained is also relatively responsive to transmission delay, the worm channel routing mode is adopted in the most recommendations of the researchers of network-on-chip at present.In the worm channel routing mode, packet is cut into a string data microplate (basic data transmission unit), and the microplate string transmits in network in the mode of flowing water then, therefore greatly reduces transmission delay.First microplate of packet is called as a microplate, has only it just to comprise routing iinformation.Other microplates of packet are just immediately following transmitting in network in the back of a microplate.In case a microplate is blocked, wait in other microplate original places, so routing node allows to use less buffering area.
In the worm channel routing mode, because packet can take the buffering area of several routers simultaneously, therefore two problems that may occur are: 1) link utilization is low; 2) deadlock.By physical link being divided into some Virtual Channels, can effectively improving link utilization and avoid deadlock.
A plurality of Virtual Channels are shared a physical link, and bandwidth that must each Virtual Channel of reasonable distribution could guarantee effective utilization of physical link bandwidth.Figure 1 shows that traditional timeslot-based fixed-bandwidth distribution method, in the method, the bandwidth of physical link is fixed and distributes to four Virtual Channels, when certain transmission Virtual Channel buffering area does not have data or receives the Virtual Channel buffering area to have expired, all cause this Virtual Channel time slot can't transmit data, the bandwidth of distributing to this Virtual Channel will be wasted.Therefore, the fixed-bandwidth distribution method can not well be utilized the bandwidth of physical link.
Summary of the invention
The objective of the invention is to propose a kind of distribution method of dynamic bandwidth that can overcome the shortcoming of fixed-bandwidth distribution method.
The invention is characterized in, contain following steps successively:
Step (1). initialization
At transmitting terminal, set a moderator, be provided with N data input at the moderator input, read the enable signal output for N, N is the number that Virtual Channel sends buffering area, and each Virtual Channel sends buffering area and is provided with: a data output, and one read the enable signal input; Send the corresponding data input pin of buffering area with this Virtual Channel in the data output end that each Virtual Channel sends buffering area and the described moderator and link to each other, each Virtual Channel send buffering area read read the enable signal output accordingly with this Virtual Channel transmission buffering area in enable signal input and the described moderator and link to each other; The bandwidth that each Virtual Channel sends the data of buffering area output is kW, and W is the physical link total bandwidth, and k accounts for the ratio of physical link total bandwidth, 0≤k≤1 for the bandwidth of each Virtual Channel transmission buffering area institute dateout; In addition, also send buffering area at each Virtual Channel and be provided with an empty sign index signal, this signal is " 0 ", represents that described Virtual Channel sends buffering area for empty, and this signal is " 1 ", represents that described Virtual Channel sends buffering area for not empty;
At receiving terminal, set a splitter, be provided with N data output and the individual enable signal output of writing of N at the splitter output, N is the number that Virtual Channel receives buffering area, the number that described Virtual Channel receives buffering area equates with the number that Virtual Channel sends buffering area, and each Virtual Channel reception buffering area all is provided with a data input and one and writes the enable signal input; In addition, receive buffering area at each Virtual Channel and be provided with a full scale will index signal, this signal is " 0 ", and it is full to represent that described Virtual Channel receives buffering area, and this signal is " 1 ", represents that described Virtual Channel receives buffering area for discontented;
In addition, at transmitting terminal, also be provided with N AND circuit, two inputs of each AND circuit send the sky sign index signal output of buffering area with described Virtual Channel respectively and the full scale will index signal output of Virtual Channel reception buffering area links to each other, and the output of each AND circuit links to each other with the signal input end of the MUX of moderator;
Step (2). carry out the Bandwidth Dynamic Allocation method successively according to the following steps:
Step (2.1). described moderator is provided with a Virtual Channel cue mark, and this Virtual Channel cue mark is initialized as Virtual Channel d;
Step (2.2). in first link clock cycle, this moderator begins search at the next Virtual Channel of initialization Virtual Channel, till finding out some AND circuit and being output as " 1 ", this moment expression should have the corresponding bandwidth request with the Virtual Channel that links to each other with door that is output as " 1 ", distributed to corresponding Virtual Channel bandwidth and transmitted the data of corresponding Virtual Channel; Otherwise,, then, do not transmit any data in this clock cycle link idle if do not find the Virtual Channel that bandwidth request is arranged;
Step (2.3). for later any one link clock cycle, moderator all the indicated next Virtual Channel of Virtual Channel cue mark set by step (2.2) described method begin search.
The present invention has guaranteed all can effectively utilize the physical link bandwidth at any time.
Description of drawings
Fig. 1. traditional fixed-bandwidth distribution method.
Fig. 2. in the Bandwidth Dynamic Allocation method in 1 allocated bandwidth constantly.
Fig. 3. in the Bandwidth Dynamic Allocation method in 2 allocated bandwidth constantly.
Fig. 4. the implementing procedure figure of Bandwidth Dynamic Allocation method.
Fig. 5. the moderator workflow diagram.
Embodiment
At the shortcoming of fixed-bandwidth distribution method on allocated bandwidth, we have proposed distribution method of dynamic bandwidth, this method sends the full situation of sky of Virtual Channel buffering area and reception Virtual Channel buffering area in each clock cycle according to each, dynamically physical link bandwidth mean allocation is given to send the not empty and discontented Virtual Channel of reception buffering area of buffering area.For example: in 1 (as shown in Figure 2) of the moment, the transmission buffering area of a, b, c, four Virtual Channels of d not empty (have data etc. to be transmitted), receive buffering area and all be discontented with (can receive data), then a, b, four Virtual Channels of c, d are assigned to 1/4 physical link bandwidth respectively in the moment 1.Yet, in 2 (as shown in Figure 3) of the moment, the transmission buffering area of a Virtual Channel is empty (do not have data etc. to be transmitted), the reception buffering area of c Virtual Channel is full (can not receive data), the transmission buffering area of b, d Virtual Channel is not empty and receive buffering area and all be discontented with, then in the moment 2, b, d Virtual Channel are assigned to 1/2 physical link bandwidth respectively, and do not distribute to a, any bandwidth of c Virtual Channel.Guaranteed that like this physical link bandwidth all can be used effectively at any time.
Execution mode as shown in Figure 4, at transmitting terminal, Dynamic Bandwidth Allocation realizes by a moderator.The transmission buffering area of Virtual Channel is provided with an empty sign index signal, and is empty with " 0 " expression, not empty usefulness " 1 " expression.The reception buffering area of Virtual Channel is provided with a full scale will index signal, and is full of " 0 " expression, discontented with " 1 " expression.The full scale will index signal that Virtual Channel is sent the sky sign index signal of buffering area and receive buffering area with the result as the bandwidth request signal of this Virtual Channel.Whether moderator distributes to this Virtual Channel bandwidth by the bandwidth request signal deciding of judging each Virtual Channel, when Virtual Channel bandwidth request signal is " 1 ", represent that this Virtual Channel has bandwidth request, then moderator is distributed to this Virtual Channel bandwidth, otherwise, when this signal was " 0 ", moderator was not distributed to this Virtual Channel bandwidth.
The concrete workflow of moderator is as shown in Figure 5 (with four Virtual Channel a, b, c, d is an example): moderator is provided with a Virtual Channel cue mark, this last clock cycle of mark indication sends the Virtual Channel of data, be initialized as Virtual Channel d, in each clock cycle, moderator begins search from the next Virtual Channel of the Virtual Channel of Virtual Channel cue mark indication, till finding the Virtual Channel that bandwidth request is arranged, send for the data of the Virtual Channel that searches labelled (Virtual Channel under this label designation data) and with it then, simultaneously the Virtual Channel cue mark is updated to the Virtual Channel that sends data in this clock cycle.Still do not find the Virtual Channel that bandwidth request is arranged if searched for all Virtual Channels, then do not send data in this clock cycle, the Virtual Channel cue mark is constant.
At receiving terminal, splitter receives the label of data according to each, deposits data in corresponding Virtual Channel buffering area.
In sum, distribution method of dynamic bandwidth has been avoided the traditional fixed-bandwidth distribution method shortcoming of waste bandwidth in some cases, has guaranteed all can effectively utilize the physical link bandwidth at any time.
Claims (2)
1. be used for a kind of Bandwidth Dynamic Allocation method of designing network on chip, it is characterized in that, contain following steps successively:
Step (1). initialization
At transmitting terminal, set a moderator, be provided with N data input at the moderator input, read the enable signal output for N, N is the number that Virtual Channel sends buffering area, and each Virtual Channel sends buffering area and is provided with: a data output, and one read the enable signal input; Send the corresponding data input pin of buffering area with this Virtual Channel in the data output end that each Virtual Channel sends buffering area and the described moderator and link to each other, each Virtual Channel send buffering area read read the enable signal output accordingly with this Virtual Channel transmission buffering area in enable signal input and the described moderator and link to each other; The bandwidth that each Virtual Channel sends the data of buffering area output is kW, and W is the physical link total bandwidth, and k accounts for the ratio of physical link total bandwidth, 0≤k≤1 for the bandwidth of each Virtual Channel transmission buffering area institute dateout; In addition, also send buffering area at each Virtual Channel and be provided with an empty sign index signal, this signal is " 0 ", represents that described Virtual Channel sends buffering area for empty, and this signal is " 1 ", represents that described Virtual Channel sends buffering area for not empty;
At receiving terminal, set a splitter, be provided with N data output and the individual enable signal output of writing of N at the splitter output, N is the number that Virtual Channel receives buffering area, the number that described Virtual Channel receives buffering area equates with the number that Virtual Channel sends buffering area, and each Virtual Channel reception buffering area all is provided with a data input and one and writes the enable signal input; In addition, receive buffering area at each Virtual Channel and be provided with a full scale will index signal, this signal is " 0 ", and it is full to represent that described Virtual Channel receives buffering area, and this signal is " 1 ", represents that described Virtual Channel receives buffering area for discontented;
In addition, at transmitting terminal, also be provided with N AND circuit, two inputs of each AND circuit send the sky sign index signal output of buffering area with described Virtual Channel respectively and the full scale will index signal output of Virtual Channel reception buffering area links to each other, and the output of each AND circuit links to each other with the signal input end of the MUX of moderator;
Step (2). carry out the Bandwidth Dynamic Allocation method successively according to the following steps:
Step (2.1). described moderator is provided with a Virtual Channel cue mark, and this Virtual Channel cue mark is initialized as Virtual Channel d;
Step (2.2). in first link clock cycle, this moderator begins search at the next Virtual Channel of initialization Virtual Channel, till finding out some AND circuit and being output as " 1 ", this moment expression should have the corresponding bandwidth request with the Virtual Channel that links to each other with door that is output as " 1 ", distributed to corresponding Virtual Channel bandwidth and transmitted the data of corresponding Virtual Channel; Otherwise,, then, do not transmit any data in this clock cycle link idle if do not find the Virtual Channel that bandwidth request is arranged;
Step (2.3). for later any one link clock cycle, moderator all the indicated next Virtual Channel of Virtual Channel cue mark set by step (2.2) described method begin search.
2. a kind of Bandwidth Dynamic Allocation method that is used for designing network on chip according to claim 1 is characterized in that described N=4.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2007101177155A CN100521657C (en) | 2007-06-22 | 2007-06-22 | Method for allocating bandwidth dynamically to design on-chip network |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CNB2007101177155A CN100521657C (en) | 2007-06-22 | 2007-06-22 | Method for allocating bandwidth dynamically to design on-chip network |
Publications (2)
Publication Number | Publication Date |
---|---|
CN101075959A CN101075959A (en) | 2007-11-21 |
CN100521657C true CN100521657C (en) | 2009-07-29 |
Family
ID=38976785
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2007101177155A Expired - Fee Related CN100521657C (en) | 2007-06-22 | 2007-06-22 | Method for allocating bandwidth dynamically to design on-chip network |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN100521657C (en) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN101227297B (en) * | 2007-12-21 | 2010-06-02 | 清华大学 | Method for ensuring service quality for designing network on chip |
CN101252513B (en) * | 2008-04-07 | 2010-09-29 | 哈尔滨工业大学 | On-chip network band width resource scheduling method for ensuring service quality |
CN101267315B (en) * | 2008-04-18 | 2011-01-26 | 清华大学 | An irregular topology structure generation method for chip network |
CN101789892B (en) * | 2010-03-11 | 2012-05-09 | 浙江大学 | All-node virtual-channel network-on-chip ring topology data exchange method and system |
CN102291314B (en) * | 2011-09-06 | 2015-04-01 | 厦门大学 | Center flow control method and device for network on chip |
CN109639585A (en) * | 2017-10-09 | 2019-04-16 | 中兴通讯股份有限公司 | Flow control methods, device, the network equipment and computer readable storage medium |
-
2007
- 2007-06-22 CN CNB2007101177155A patent/CN100521657C/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CN101075959A (en) | 2007-11-21 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US7940788B2 (en) | System for transmitting data within a network between nodes of the network and flow control process for transmitting the data | |
CN100521657C (en) | Method for allocating bandwidth dynamically to design on-chip network | |
CN101383712B (en) | Routing node microstructure for on-chip network | |
Dobkin et al. | QNoC asynchronous router | |
US20060136681A1 (en) | Method and apparatus to support multiple memory banks with a memory block | |
CN1798102A (en) | Arbitrating virtual channel transmit queues in a switched fabric network | |
EP1370939A1 (en) | Communications system and method with non-blocking shared interface | |
CN104158738A (en) | Network-on-chip router with low buffer area and routing method | |
CN113114593B (en) | Dual-channel router in network on chip and routing method thereof | |
CN103532807A (en) | Technology for PCIE (Peripheral Component Interface Express) data service quality management | |
US20210359958A1 (en) | Hierarchical switching fabric and deadlock avoidance method for ultra high radix network routers | |
US20110268137A1 (en) | Communication within an integrated circuit including an array of interconnected programmable logic elements | |
KR20240024188A (en) | network interface device | |
CN106445869B (en) | A kind of high-speed data exchange method based on FPGA and PCIe | |
Kim et al. | Solutions for real chip implementation issues of NoC and their application to memory-centric NoC | |
Ghidini et al. | Lasio 3D NoC vertical links serialization: Evaluation of latency and buffer occupancy | |
Song et al. | Asynchronous spatial division multiplexing router | |
CN101702714B (en) | Method, system, and apparatus for a credit based flow control in a computer system | |
CN103530188B (en) | It is a kind of can dynamic configuration RAM resource pools multi-channel chip | |
Sun et al. | DCBuf: a high-performance wireless network-on-chip architecture with distributed wireless interconnects and centralized buffer sharing | |
CN100541461C (en) | Data handling system and the method that is used for interconnect arbitration | |
Duan et al. | Research on Double-Layer Networks-on-Chip for Inter-Chiplet Data Switching on Active Interposers | |
Pande et al. | Performance optimization for system-on-chip using network-on-chip and data compression | |
CN101576867B (en) | Extended universal asynchronous serial interface method, device and system | |
US20060155959A1 (en) | Method and apparatus to provide efficient communication between processing elements in a processor unit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C17 | Cessation of patent right | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090729 Termination date: 20120622 |