CN100520981C - Balance symmetric type read-out amplifier circuit for nonvolatile memory - Google Patents

Abstract

The invention is a balance symmetrical reading amplifying circuit for fixed memory, it includes: at least a difference amplifier and two data wires which connects the two ends of the amplifier; the character is: the bit lines of the memorizing unit array are divided into odd and even number bit line; sets odd and even series multiplier circuits to each bit line, the odd and even number bit line connects with odd and even bit data wires throgh odd and even series multiplizer; at least two odd/even bit character lines which connects all the control ends of the odd/even multiplier circuit; at least a parallel emulational bit line whose resistance matches with bit line at the proper place of memorizing unit array, it connects with a refernece current source and two even/odd emulational series multiplier circuits, the emulational bit lines connects with odd/even data wires through odd. even emulational series multiplizer circuits.

Description

A kind of balanced, symmetrical formula that is used for nonvolatile memory is read amplifying circuit

Technical field

The present invention relates to a kind of auxiliary circuit of semiconductor memory, more particularly, is the balanced, symmetrical formula input circuit about the data sense amplifier of the ROM (read-only memory) of electrically erasable preface.

Background technology

As everyone knows, volatile storage, for example dynamic RAM (DRAMs) and static RAM (SRAMs) but stored datas all, in case but the chip dead electricity, the data of being stored are all lost.Opposite with it, nonvolatile memory, for example, ROM (read-only memory) (ROMs), EPROM (EPROMs) and electrically-programmable erasable read-only memory (EEPROMs) still can keep the data (data that promptly write) of being stored after the chip dead electricity.Therefore, nonvolatile memory is particularly suitable for the portable product that uses powered battery and require low-power consumption, and EEPROMs is also particularly useful to requiring programmable system.EEPROMs comprises optional conventional EEPROMs of byte (it contains byte selection transistor conventional EEPROMs) and lighting formula EEPROMs as shown in Figure 2 as shown in Figure 1.

A conventional EEPROM one basic unit of storage among Fig. 1 comprises that one selects a floating grid transistor 102 of transistor 101 and series connection with it.Constitute a byte 100 by 8 such basic units of storage, a byte selects the control grid 104 of 103 pairs of floating grid transistors 102 of transistor that bias voltage CG is provided, the source electrode of floating grid transistor all connects a common junction CS, storage unit at EEPROM is in different operation modes, for example programming, wipe with read operation during, common junction CS is offset to varying level, all unit select transistor 101 and byte to select the grid of transistor 103 all to be connected to word line WL node, the drain electrode of each storage unit connects respective bit line BL0-BL7, and is communicated with each storage unit respectively.Conventional EEPROM allows each storage unit by selecting transistor that each byte is programme, lighting formula EEPROM (Fig. 2) 200 normally is made of floating grid transistor 201, for therefore the area that reduces storage unit also dwindles chip size and select transistor with selection transistor and byte as conventional EEPROM.The grid of all floating grid transistors all connects a common word line WL and all is connected a public power node CS with all source electrodes, the drain electrode of each storage unit connects corresponding bit line BL0-BL7, is similar to the data that every bit line BL0-BL7 of conventional EEPROM allows each each storage unit of self-access.Lighting formula EEPROM is not owing to select the floating grid transistor to isolate a plurality of storage unit, so require to finish erase operation simultaneously in many storage unit, usually be referred to as section and wipe (sector erase), the storage element array is called cell group (also being called " section " or " square " sometimes).

Comprise very little memory cell array in the semiconductor memory, electronic data just is stored in these storage unit, because these data-signals are generally very little, so need sensor amplifier to amplify these data-signals from these storage unit, sensor amplifier adopts differential amplifier usually, at one end input data signal and at its other end input contrast signal.Common solution is to utilize the physical characteristics of the array of coupling consecutive storage unit, improves the sensitivity that detects these data-signals by a neutrodyne circuit.

Fig. 3 A and Fig. 3 B are existing a kind of schematic diagrams that is used for the balanced type sensing circuit of semiconductor storage unit.As shown in the figure, memory device 300 comprises a cell group 302 and a corresponding cell group 304 down on one, and they are connected to a sense amplifier groups 310.Can be chosen by word line and bit line by two cell group 302,304 that memory cell array constitutes, those bit lines of choosing indicate with label 306 in the drawings.When a word line was energized, to the bit line data-signal of packing into, the word line of excitation was called selected word line, consults number in the figure 308.

The memory cell array of choosing 302 is all passed through multiplier circuit 312 with all bit lines of unchecked memory cell array 304 and is connected one group of sensor amplifier 310, these sensor amplifiers 310 are mounted in two memory cell arrays 302, between 304, at Fig. 3 A, in the physical circuit of 3B, one group of four bit line 306 connects a certain sensor amplifier 310 through a certain multiplier circuit 312, the mlultiplying circuit 312 of memory cell array under this sensor amplifier 310 is gone up the multiplier circuit 312 of memory cell array and is connected by following data line 316 by last data line 314 connections.

One balanced type is read amplifying circuit and is realized by two matched impedances accurately that input end provided of sensor amplifier 310.Here it is when no matter when choosing memory cell array 302 or choosing down memory cell array 304, all passes through the multiplier circuit 312 of two upper and lower memory cell arrays 302,304 among excitation Fig. 3 A and Fig. 3 B and realize.

The erase operation time of EEPROM device is than long, usually consume more time than read operation, because erase operation can consume a large amount of time, so the read cycle may be the length that is difficult to accept, in order to allow the EEPROM device to carry out read operation continuously, normally the storage array of EEPROMs is divided into many cell group and realizes the read-while-write function at lighting formula eeprom memory spare, another cell group is write (wipe and programme) data while promptly read a certain cell group.

The balanced type sensing circuit, effective at DRAMs and SRAMs, be applied to conventional EEPROMs and lighting formula EEPROMs, although these read only memory devices have a plurality of cell group, but have problem.A reason is generally will use high voltage to EEPROM storage unit write data, and provides balanced loaded cell group may be in programming or erase status, and therefore, the performance of reading of EEPROMs goes with SRAMs not as DRAMs usually.Solution is to end write operation, in this case, provides balanced loaded cell group just to take time out to and provide matched load for the cell group in read operation just from write operation.U.S. Pat 6,052,308 provide a technical solution, promptly use the balanced type sensing circuit in order to overcome lighting formula EEPROM and the mistake that relates to is wiped problem, must set up the circuit of videoing again and again.

Usually be called " cross and wipe " being in " exhausting attitude " storage unit (depteted), under this state, lighting formula EEPROM storage unit is behind erase operation, and floating grid is to fill positive electricity in essence, and storage unit plays a part a depletion mode transistor.Erase operation normally is added to positive high voltage voltage the source electrode of lighting formula EEPROM storage unit and finishes, and electronics is removed from floating grid in erase operation.The result, depletion type " cross wipe " lighting formula EEPROM storage unit can not remain on a certain level with the control grid and turn-off, the storage unit that " exhausts attitude " will import undesirable leakage current, and this leakage current can destroy the balance of two cell group that compare.

For this problem is described, Fig. 4 has described United States Patent (USP) 6,052,308 disclosed desirable balanced type sensing circuits that are used for EEPROM, this sensor amplifier 400 has a first input end (+) and one second input end (-), according at the difference between current shown in these two input ends, this sensor amplifier 400 produces a DATA signal.This first input end (+) is connected to data line 402, one mlultiplying circuits 404 and a last memory cell array bit line 406 on one; Two storage unit Q400 and Q402 are connected to memory cell array bit line 406, this second input end (-) and this first input end (+) balance, and be connected to data line 408, one multiplier circuits 404 and once memory cell array bit line 410.Two storage unit Q404 and Q406 are connected to down memory cell array bit line 410.Storage unit (Q400 among Fig. 4 A, Q402, Q404 and Q406) all be EEPROM storage unit as shown in Figure 1 " monocrystal triode " (1-T), " tandem transistor " that be presented at the EEPROM storage unit among Fig. 2 (2-T) can be arranged in the same way into the balance sensing circuit.

Structure and accessing operation that Fig. 4 B explanation is identical with Fig. 4 A, but count nonideal effect, these nonideal effects are in the situation generation that the attitude storage unit occurs exhausting.The circuit structure of Fig. 4 B comes mark with the label symbol identical with Fig. 4 A.Suppose that following memory cell array (Q404 and Q406) has been subjected to erase operation before storage unit Q402 sense data, this erase operation has placed storage unit Q404 and has exhausted attitude.Soft programming (soft program) operation behind the original erase operation can correcting storing unit Q404, will make this soft programming to finish but end erase operation in order to allow read memory cell Q402.

Shown in Fig. 4 B, storage unit Q402 is in and exhausts attitude and therefore flow out an electric current I data, second input end (-) with reference to current source 412 couplings connection sensor amplifier, and cause at second input end (-) outflow electric current I ref, yet, different with the ideal situation of Fig. 4 A, in Fig. 4 B, be in and exhaust attitude storage unit Q404 no matter its control grid is whether low level also flows out electric current I dep, the result, second input end (-) outflow one of this sensor amplifier equals the electric current of Iref+Idep, and its direction is opposite with electric current I ref.This may cause the data read operation to spend the oversize time (low yields) or in the worst case, full of prunes data-signal occur.

Being in the storage unit that exhausts attitude among the lighting formula EEPROM can be proofreaied and correct by soft programming and (also be referred to as " correct (repair) ", " treatment (heal) " and " fine and close (compaction) "), soft programming injects in a small amount, and negative charge makes storage unit play a part enhancement device again to floating grid.Concerning the cell group of the lighting formula EEPROM that finishes erase operation and corrective operations, storage unit individually has some little leakage currents under high running temperature, because the repairing that these storage unit may be subjected to is many not enough, though these little leakage currents can not read problem on a large scale, at high temperature will reduce to read the range of tolerable variance of amplifying circuit and cause low yields.

United States Patent (USP) 6,052,308 introduce a kind of circuit and four cell group of videoing again solves above-mentioned about wiping---end and exhaust the problem of attitude storage unit, as shown in Figure 5, the method is the cell group that the cell group of will wipe videos another replacement more different with it.

In Fig. 5, four cell group 502A-502D are arranged, each cell group is connected to corresponding multiplier circuit 504A-504D, these multiplier circuits provide the connecting path of the storage unit in their cell group of difference correspondence, for example, provide connection to be positioned at the storage unit of cell group 502A by multiplier circuit 504A, how cell group 502A-502D can divide into groups to be connected sense amplifier groups 506 according to them with multiplier circuit 504A-504D, as shown in Figure 5, multiplier circuit 504A and 504B are (and therefore, cell group 502A and 502B) be connected to sense amplifier groups 506 by some data line 508A that go up, like this, cell group 502A and 502B can regard cell group and multiplier circuit 504A as, and 504B can regard superior musical instruments used in a Buddhist or Taoist mass circuit as.Under balance mode, multiplier circuit 504C is connected sense amplifier groups 506 with 504D by following data line 508B, and cell group 502C and 502D can regard cell group down as, and multiplier circuit 504C and 504D can regard multiplier circuit down as.Should be appreciated that noun is upper and lower to be the annexation of definition to this sense amplifier groups, should not be regarded as according to corresponding concrete direction.The providing by reference current source circuit 510 with reference to electric current of each amplifier in sense amplifier groups 506 is provided.

Column address signal COLADD is produced by column address, and determines that the column address of cell group 502A-502D of choosing is connected to corresponding data line 508A or 508B.When read access is operated, produce cell group decoded signal BNK and a pair of multiplier circuit 504A-504D is connected.The a pair of multiplier circuit 504A～504D that connects will comprise a superior musical instruments used in a Buddhist or Taoist mass circuit 504A or 504B and once multiplier circuit 504C or 504D, this circuit causes reading simultaneously a pair of cell group, a cell group is last cell group, and the another cell group is following cell group.This situation provides two input impedance of balance for sense amplifier groups 504.Which will depend on selected row address and image signal REMAP again to cell group is selected.When the cell group data were provided, image signal REMAP did not determine where to organize cell group 502A-502D and extracts data-signal again, and has only determined the cell group of balanced impedance effect.After wiping termination, the REMAP signal is produced by the arbitrary partly cell group 502A through wiping that determines address realm-502D.During read operation, this address scope is compared with the address of the cell group 502A that plays the balanced impedance effect-502D, if do not match, the REMAP signal is under an embargo also because of there being the pre-cell group 502A that plays a balanced impedance effect-502D read operation of determining then to proceed routinely.Yet, if coupling, wipe end before the REMAP signal activation, this shows that erase operation just carries out in as balanced loaded cell group at one.Another cell group 502A-502D as an alternative will be selected as balanced load.

There is following shortcoming in above-mentioned prior art:

1. require termination playing the erase operation of the cell group of balanced load effect, make the loss of data that is stored in the balanced load cell group, these data reload needs and rewrite, the waste processing time.

2. particularly in product, fail to solve the little leakage problem of the storage unit of fully not correcting as the high-temperature operation of automotive electronics generic request.Therefore in " rectifications ", " soft programming ", or during " compression (densification) " processing has stricter requirement to the threshold voltage of control store unit.

3. data line passes through four cell group and connects multiplier circuits and cause lead-in wire long, has increased the input capacitive load of sensor amplifier, has therefore reduced the speed of read operation, influences the performance of storer;

4. the solution of multiple memory cell group is not suitable for the little memory device of area, when a little storage array is divided into the multiple memory cell group, owing to used extra multiplier circuit and decoding scheme, just can pay the expensive cost of chip area.

Summary of the invention

How overcoming existing four the above-mentioned shortcomings of prior art, is technical matters to be solved by this invention, the object of the present invention is to provide a kind of balanced, symmetrical formula that is used for nonvolatile memory to read amplifying circuit for this reason, so that:

1. when a certain cell group is carried out read operation, the present invention allows other cell group not wipe to end and write operation continuously, in the cell group that plays the balanced load effect, still preserve original and data message that newly write, do not need to save a large amount of overwriting data time to balanced loaded cell group write data again;

2. eliminate the little leakage problem of the storage unit of fully not wiping fully.

3. the present invention is applicable to the memory device of single cell group and a plurality of cell group;

4. do not pass through the data line of the length of a plurality of cell group, to improve read operation speed and to reach higher yields.Technical scheme of the present invention is as follows:

A kind of balanced, symmetrical formula that is used for nonvolatile memory is read amplifying circuit, comprising:

At least one differential amplifier, it has two input ends;

Have two data lines at least, one be odd multiple according to line, another is even position datawire, connects two input ends of this differential amplifier respectively; Be characterized in:

Memory cell array has a cell group at least, and the bit line in the cell group is divided into odd bit lines and even bitlines;

Corresponding each root bit line is established a row multiplier circuit, and is defined as odd column multiplier circuit and even column multiplier circuit, and odd bit lines connects odd multiple according to line through the odd column multiplier circuit, and even bitlines connects even position datawire through the even column multiplier circuit;

Be provided with at least two group array selecting signals, one group is strange, idol position word-line signal, another group is strange, the even control line signal of emulation, wherein, strange position word-line signal connects the control end of all odd column multiplier circuits, idol position word-line signal connects the control end of all even column multiplier circuits, and the strange control line signal of emulation connects the control utmost point of odd number emulation row multiplier circuit, and emulation idol control line signal connects the control utmost point of even number emulation row multiplier circuit;

At least establish the emulation bit line of a parallel and impedance and bit line coupling at the appropriate location of memory cell array, and corresponding connected one with reference to current source, and an odd number emulation row multiplier circuit and an even number emulation row multiplier circuit, this emulation bit line connects odd multiple according to line through odd number emulation row multiplier circuit, and connects even position datawire through even number emulation row multiplier circuit.

Further, the emulation bit line of described at least one parallel and impedance and bit line coupling is laid in an end margin or the array central authorities of memory cell array;

Described memory cell array is an independent matrix, the bit line of storage unit is wherein alternately arranged with strange, idol, row multiplier circuit is correspondingly also alternately arranged with strange, idol, and the bit line behind corresponding row multiplier circuit also alternately connects strange accordingly, even position datawire respectively;

Described storage array is an independent matrix, storage unit bit line wherein is divided into very, idol group bit line is alternately arranged, correspondingly, the row multiplier circuit is also alternately arranged with strange, idol group, and the bit line behind corresponding row multiplier circuit also alternately connects odd multiple according to line, even position datawire with strange, idol group respectively;

Described storage unit is strange, idol group bit line means with 2 or 4 or 8 positions, 16 or 32 strange, idol group bit lines that bit line constitutes;

Described 2 strange, even data lines are laid along the edge of said memory cell array;

According to the present invention, the balanced, symmetrical formula that is used for nonvolatile memory is read amplifying circuit, be characterized in: described memory cell array comprises two cell group that structure is identical, this differential amplifier and two strange, even position datawires that connect two input end are laid between these two cell group, and the storage unit bit line in these two cell group connects odd multiple respectively according to line and even position datawire through corresponding row multiplier circuit; Described storage unit bit line is alternately arranged with strange, even number, and correspondingly, strange, idol alternately connects odd multiple according to line and even position datawire;

Storage unit bit line in described two cell group is divided into identical strange, idol to be organized bit line and alternately arranges, and strange, even group bit line is connected odd multiple according to line and even position datawire through corresponding odd column multiplier circuit or even column multiplier circuit;

Have more ground, between described two storage unit, 8 differential amplifiers are set, and there are 16 strange, even position datawires alternately to arrange, form 8 pairs of strange, idol group data lines successively, every group of data line connects a corresponding differential amplifier respectively, and lays 4 strange, corresponding strange, even number emulation row multiplier circuits respectively at the two ends of each cell group; 4 strange, even emulation bit lines that one end of each cell group is laid connect strange, the even position datawire on 2 close differential amplifiers, and 8 bit lines of the odd number group in strange, the even cell group are connected according to line with 8 odd multiples successively, and 8 bit lines of even number set are connected with 8 even position datawires successively; Described 4 parameters that connect 4 emulation bit lines respectively can be by the replacing with reference to current source an of current mirror type according to current sources, or be divided into two groups, and every group connects a current mirror type with the reference current source;

At the described central portion that is located at 4 of each cell group two ends strange, even number emulation bit lines and can be laid in described cell group accordingly with reference to current source and row multiplier circuit; Described is the current mirror type power supply with reference to current source, and whenever believe adjacent 2 or 4 or 8 emulation bit lines connect a current mirror type with reference to current source;

Strange, idol group bit line in described each cell group comprises by 2 or 4 or 16 or 32 strange, idol group bit lines that bit line constitutes.

Advantage of the present invention is:

1. because the sensing circuit of balanced, symmetrical of the present invention has accurate input impedance matching and reads detectability, therefore, be applicable to low-voltage, the EEPROM and the lighting formula eeprom memory spare of high-speed and big operating temperature range;

2. when certain cell group was being carried out read operation, the present invention allowed other cell group not end, and continues erase operation;

3. the present invention eliminates not the fully little leakage current of eraseable memory unit fully, therefore, has improved read operation speed and product qualification rate at high temperature;

4. the present invention can be used for the single memory cell group and is used for two or more cell group, and the memory device that is applicable to different layout density;

5. owing to there is not the data line of the length of a plurality of cell group of process, therefore, can improves read rate, and/or can obtain higher product yields.

6. the present invention's cell group or cell group that engages in parallel of can be used for connecting and engaging;

7. in a plurality of cell group,, littler charge pump can be used, therefore chip area can be reduced owing to reduce the charge pump load.

Description of drawings

Fig. 1 is the circuit theory diagrams of the byte that 8 storage unit constitute among the conventional EEPROM.

Fig. 2 is the circuit theory diagrams of a byte of 8 storage unit formations among the existing lighting formula EEPROM.

Fig. 3 A and Fig. 3 B are existing a kind of balance sensing circuit schematic diagrams that is used for semiconductor storage unit.

Fig. 4 A is the ideal operation situation synoptic diagram of existing a kind of eeprom memory balanced type sensing circuit.

Fig. 4 B is the imperfect working condition synoptic diagram of existing a kind of eeprom memory balanced type sensing circuit.

Fig. 5 is the eeprom memory balanced type sensing circuit schematic diagram of prior art.

Fig. 6 is the balanced type symmetry sensing circuit synoptic diagram of single groups of memory cells of the present invention.

Fig. 7 is the balanced type symmetry sensing circuit synoptic diagram that series connection engages two cell group that has of the present invention.

Fig. 8 is that the another kind of row multiplier circuit decoding among the present invention enables schematic diagram.

Fig. 9 is the byte decoding scheme synoptic diagram on two cell group among the present invention.

Figure 10 is that the present invention is at the embodiment of engagement type eeprom memory spare in parallel synoptic diagram.

Figure 11 is the embodiment synoptic diagram that another layout with reference to current source Iref is provided with of reading among the present invention.

Embodiment

Provide preferred embodiment of the present invention according to Fig. 6～Figure 11, and described in detail in conjunction with the accompanying drawings, enable to illustrate better architectural feature of the present invention, function characteristics.

Better embodiment of the present invention can be used for the electric erasable of general electric erasable and programmable read-only memory (EEPROM) or lighting formula and the sensing circuit of programmable read-only memory (Flash EEPROM), these EEPROMs can be an independent devices or an in-line memory, comprise the part as large scale integrated circuit such as microprocessor or microcontroller.

A semiconductor memory cell array is made up of many same memory cell, and these identical storage unit are organized into row (word line) and row (bit line).In the manufacturing process of semiconductor devices, require to make equably these storage unit.But, in order to reduce the proximity effect of illumination technology in the semiconductor fabrication, along border several emulation bit lines of increase and several matter of common practices that the emulation word line is a semiconductor fabrication of memory cell array.The purpose of these emulation bit lines and word line be make edges at two ends at this storage array produce with memory cell array in storage unit have identical physical characteristics, the present invention utilizes these emulation bit lines and the data line that increases in addition constitute with memory cell array in carrying out access storage unit have the impedance load that is complementary.

The better embodiment of Fig. 6 demonstration illustrates and with common tags symbol 600 expression with block scheme.Fig. 6 describes the EEPROM cell group of a serial connection.Better embodiment can realize that these implementations will be described with a plurality of storage unit and/or juncture in parallel in Fig. 7～Figure 11.

In Fig. 6, in order to eliminate the proximity effect of illumination process, single cell group 600 is surrounded by desired emulation bit line 602C-E and emulation word line (not shown), whole bit line 602A-B of memory cell array are divided into two groups, be odd bit lines 602A and even bitlines 602B, two emulation bit line 602C-D are used to provide balanced impedance, and the impedance load of two emulation bit line 602C-D is accurately identical with the impedance of memory cell array bit line 602A-B.

Read with reference to current source Iref-ODD and Iref-EVEN for two and be connected emulation bit line 602C-D respectively.The logic state that is used to be determined at the storage unit of choosing in the storage unit word group with reference to electric current.

Two data lines 604A and 604B replace a common data lines along the memory cell array edge placement, and all bit lines all pass through row multiplier circuit 603A-D and connect data line.Multiplier circuit is divided into odd number group 603A and even number set 603B.All odd bit lines 602A connect odd multiple according to line 604A, and all even bitlines 602B connect even bit data line 604B; Equally, very bit emulator bit line 602C is connected with even bit emulator line 602D by even column multiplier circuit 603 according to line 604A by odd column multiplier circuit 603C connection odd multiple and connects even position datawire 604B.Odd multiple is connected second input end (-) of sensor amplifier with even position datawire according to the first input end (+) of line connection sensor amplifier.

The decoding column address is to produce the promptly strange position word-line signal COLADD-ODD of four array selecting signals, idol position word-line signal COLADD-EVEN, the strange control signal DUMMY-ODD of emulation and emulation idol control signal DUMMY-EVEN, and even bit address and odd bits address can be selected with the lowest address position in the column address.For example, on a certain odd bit lines 602A, reading the situation of a storage unit, strange position word-line signal COLADD-ODD will connect a certain odd column multiplier circuit 603A, so that odd bit lines 602A is connected odd multiple according to line 604A, and an idol position word-line signal COLADD-EVEN will disconnect even bitlines 602B and even position datawire 604B.In the case, emulation idol control signal DUMMY-EVEN will connect even bit emulator row multiplier circuit 603D, this even number emulation bit line 602D will be connected to even position datawire 604B, the impedance ratio that the multiplier circuit 603D of even number emulation bit line 602D and it will provide matched impedance and this odd bit lines 602A and multiplier circuit 603A thereof selects signal to choose with reference to current source Iref-EVEN by another.This selects signal and emulation idol control signal DUMMY-EVEN to encourage simultaneously with reference to current source Iref-EVEN.Sensor amplifier is determined logic situation and logical signal DATA of output of this storage unit comparing with reference to electric current and memory cell current.

Equally, on an even bitlines 602B, read the situation of a storage unit, idol position word-line signal COLADD-EVEN will connect a certain even column multiplier circuit 603B, a certain even bitlines 602B is connected to even position datawire 604B, and a strange position word-line signal COLADD-ODD will disconnect odd bit lines 602A and odd multiple according to line 604A, in the case, the strange control signal DUMMY-ODD of emulation will connect strange bit emulator row multiplier circuit 603C, odd number emulation bit line 602C will connect odd multiple according to line 604A, the impedance ratio that odd number emulation bit line 602C and its multiplier circuit 603C will provide matched impedance and certain even bitlines 602B and multiplier circuit 603B thereof, select signal to be chosen with reference to current source Iref-ODD by another, this selects signal and the strange control signal DUMMY-ODD of this emulation to move simultaneously with reference to current source Iref-ODD, sensor amplifier is relatively with reference to electric current and memory cell current, measure logic states of memory unit and export a logical signal DATA, outer logic circuit will be according to the logic state of the lowest address bit reversal DATA of for example column address, and this state is exported to the external data impact damper.

In addition, also to point out, two strange, even number emulation bit line 602C in the present embodiment, 602D and being attached thereto connect two is with reference to current source Iref-ODD, Iref-EVEN, and two central parts strange, that even column multiplier circuit 603C, 603D can be laid in memory cell array, particularly, also can replace two strange, even number emulation bit lines and replace two with reference to current source Iref-ODD, Iref-EVEN with reference to current source by an emulation bit line by one.

Fig. 7 is the better embodiment of EEPROMs memory device that is used to have the series connection of two cell group.

Represent with general labeling symbol 700.Present embodiment more is applicable to high density EEPROMs device, in Fig. 7, two cell group 701A, 701B is by word line (not shown) and bit line 702A0-1,702B0-1,702C-E constitutes, but 702C-E is the emulation bit line, odd bit lines 702A0-1 connects odd multiple according to line 704A by odd column multiplier circuit 703A0-1 respectively, and even bitlines 702B0-1 connects even position datawire 704B by even column multiplier circuit 703B0-1 respectively.The mode of last cell group 701A picture described in Fig. 6 chosen and read.When going up cell group in elected, being used for down, all the row multiplier circuit 703A1 and the 703B1 of cell group use signal COLADD-ODD1 and signal COLADD-EVEN1 to disconnect.Therefore, the impedance of following storage unit and last storage unit are isolated and can not caused any readout error.In order to read down cell group, an odd bit lines 702A1 for example, certain odd column multiplier circuit 703A1 is connected by signal COLADD-ODD1, and signal COLADD-EVEN1, COLADD-ODD0 and COLADD-EVEN0 are disconnected, at one time, signal DUMMY-EVEN connects and emulation row multiplier circuit 703D, emulation bit line 702D will connect even position datawire 704B, even number emulation bit line 702D and multiplier circuit 703D thereof will provide impedance ratio that matched impedance and certain odd bit lines 702A1 and multiplier circuit 703A1 thereof provided, select signal to choose with reference to current source Iref-EVEN by another, this selects signal and signal DUMMY-EVEN to connect simultaneously, sensor amplifier will compare reference electric current and memory cell current, measure the logic state and the output logic signal DATA of storage unit.

On the contrary, in order to choose an even bitlines 702B1, a certain digit pair is counted multiplier circuit 703B1 and is connected by signal COLADD-EVEN1, and signal COLADD-ODD1, COLADD-ODD0 and COLADD-EVEN0 disconnect, meanwhile, signal DUMMY-ODD connects emulation row multiplier circuit 703C, and emulation bit line 702C will connect odd multiple according to line 704A.Odd multiple will provide impedance ratio that matched impedance and certain digit pair digit line 702B1 and multiplier circuit 703B1 thereof provided according to line 702C and multiplier circuit 703C thereof, select signal to choose with reference to current source Iref-ODD by another, this selects signal and signal DUMMY-ODD to connect simultaneously separately.This sensor amplifier will the current ratio of reference electric current and storage unit be measured the logic state and the output logic signal DATA of storage unit.One outer logic circuit is basis, the logic state of the lowest address bit reversal DATA of column address for example, and this state delivered to the external data impact damper.

If an advantage of preferred embodiment as shown in Figure 7 is that certain cell group is read, other cell group needn't be ended erase operation.For example, read if go up cell group 701A, as long as signal COLADD-EVEN1 and COLADD-ODD1 disconnect, the erase operation on following cell group 701B just can be proceeded.

This row multiplier circuit 703A1 and 703B1 will be this time cell group and data line 704A, and 704B isolates, and allow to go up that the cell group read operation continues and not disturbed.

The another one advantage that cell group is divided into little cell group is to reduce the load of charge pump.Because bit line is the pith of charge pump capacitive and current loading with the high-voltage switch gear that is connected (interconnection) with them, so relatively Duan bit line is the load that can reduce charge pump.

Employed two strange, even number emulation bit line 703C in the present embodiment, 703D, two are strange, idol is with reference to electric current stream Iref-ODD, Iref-EVEN and strange, even column emulation multiplier circuit 703C, 703D can be laid in the central part of cell group, particularly, can replace two strange, even number emulation bit lines by an emulation bit line, with replace two strange, idols with reference to current source Iref-ODD, Iref-EVEN by one with reference to current source.

Fig. 6 and Fig. 7 describe better embodiment in detail.Fig. 8～Figure 11 will describe the example of other several conversion.

Fig. 8 display column multiplier circuit is selected another interpretation method of signal COLADD-ODD and COLADD-EVEN, and with 800 expressions of general labeling symbol.Present embodiment is the EEPROM memory cell array that is used for serial interface.Different with the mode of alternately deciphering between each even bitlines and the odd bit lines, this method is divided into a byte with per 8 bit lines 802A-B, all bytes are appointed as odd bytes 802A and even bytes 802B, signal COLADD-ODD and COLADD-EVEN decoding is ranked that multiplier circuit is connected to certain of odd bytes 802A respectively or certain multiplier circuit of even bytes 802B is connected, and the advantage of sort circuit is to reduce the switch number of times of multiplier circuit when reading thereby reduce switching current.Similarly, per two bytes, per four bytes, per 16 bytes, even per 32 bytes or the like, can further be divided into one group together.

Fig. 9 is presented at the method that realizes byte decoding on two cell group, represents with general labeling symbol 900.This better embodiment be used for the EEPROM cell group of two serial interfaces, as in the single cell group of Fig. 8, per 8 bit lines 902A0-1 and 902B0-1 are divided into a byte.All bytes are specified and are odd bytes 902A0-1 and even bytes 902B0-1.To signal COLADD-ODD0-1 and COLADD-EVEN0-1 decoding respectively certain multiplier circuit of odd bytes 902A0-1 is connected or certain multiplier circuit of dual numbers byte 902B0-1 is connected, for example, under the situation of a certain odd bit lines 902A0 of memory cell array 901A, signal COLADD-ODD0 will connect among the odd column multiplier circuit 903A on choosing.All other row multiplier circuit selects signal COLADD-ODD1 and COLADD-EVEN0-1 not selected, in the identical time, emulation array selecting signal DUMMY-EVEN connects even emulation row mlultiplying circuit 903D, like this, provide impedance ratio that build-out resistor and even bit data count 904B, select signal to choose with reference to current source Iref-EVEN by another, sensor amplifier compares the data message on the present two data lines 904A-B, and according to the state output logic status signal DATA of the storage unit of choosing.Correspondingly, even storage unit in last cell group or the strange and even storage unit in following cell group can be chosen in the same manner.In per two bytes described in Fig. 8, per four bytes, per 16 bytes, even per 32 bytes or the like, can further be divided into one group of example that can be applicable to two cell group equally together.

Better embodiment can implement too to the eeprom memory spare that parallel connection engages.Figure 10 describes the example that can realize 8 storage unit of access simultaneously at the eeprom memory spare of parallel interface.And represent with common label symbol 1000.Memory device is divided into two cell group, promptly go up cell group 1000A and following cell group 1000B, per 8 bit lines are a byte, bit line is divided into odd bytes 1002A0-1 and even bytes 1002B0-1,16 emulation bit line 1002C-D, four emulation bit lines of the every end of cell group, edge along cell group is arranged, the emulation bit line is divided into odd number emulation bit line 1002C and even number emulation bit line 1002D, read with reference to current source Iref-ODD and Iref-EVEN for 16 and all be connected odd number emulation bit line 1002C and even number emulation bit line 1002D respectively, bit line all passes through row multiplier circuit 1003A0-1 with the emulation bit line and is connected odd multiple with 1003B0-1 according to line 1004A and even position datawire 1004B.Emulation row multiplier circuit is all selected by signal DOMMY-ODD and DOMMY-EVEN and is connected; The row multiplier circuit is selected by signal COLADD-ODD0-1 and COLADD-EVEN0-1 respectively and is connected.

As an example, under the selected situation of last storage unit 1003A08 root odd bit lines, the prefactor COLADD-ODD0 of column address decoding and decoding will connect the row multiplier 1003A0 of a certain bit byte, the data message of storage unit will be presented on odd multiple according on the line 1004A, emulation row prefactor DUMMY-EVEN connects and makes to read with reference to electric current and is presented on the even position datawire 1004B, all other column address prefactor COLADD-ODD1 and COLADD_EVEN0-1, and DUMMY-ODD disconnects.Odd multiple is connected the first input end and second input end of 8 sensor amplifier SA with even position datawire according to line.According to the logic state of getting the storage unit of depositing, these sensor amplifier output logic signal DATA or DATA, these sensor amplifiers can be laid between two cell group.

Another conversion of preferred embodiment comprises the position of reading with reference to current source, can be laid in diverse location or a plurality of positions around cell group with reference to current source, as shown in figure 11, by general labeling 1100 indications, quantity and installation position with reference to current source Iref can be selected according to the size of memory cell array, purpose be for reduce memory cell current and with reference to the difference between the current source to realize optimum matching.Corresponding emulation row multiplier circuit can select signal DUMMY-ODD00-11 and DUMMY-EVEN00-11 to choose by emulation row multiplier circuit according to the position of reference current source.

At last, also to point out, in the above-described embodiments, also can be according to the size of memory cell array, if promptly columns (bit line) is more, then for helping whole machine balancing, emulation bit line then all can be located at the central portion (the emulation bit line is parallel with the row bit line) of memory cell array accordingly with reference to current source Iref and emulation row multiplier circuit.Particularly, the quantity of emulation bit line, all can be reduced according to actual conditions with reference to the number of current source, for example, use the current mirror then can be, even four, eight with reference to current source replacing by a current mirror type with reference to current source with two shown in the figure with reference to current source as the reference current source.

Though the present invention has made detailed description, and in Fig. 6-11, describe several embodiment and various combination, do not broken away from the various modifications that spirit of the present invention is made, substituted and conversion, surely belonged to the desired protection domain of claim of the present invention.

Claims (18)

1. a balanced, symmetrical formula that is used for nonvolatile memory is read amplifying circuit, comprising:

At least one differential amplifier, it has two input ends;

Have two data lines at least, one be odd multiple according to line, another is even position datawire, connects two input ends of this differential amplifier respectively; It is characterized in that:

A. memory cell array has a cell group at least, and the bit line in the cell group is divided into odd bit lines and even bitlines;

B. corresponding each root bit line is established a row multiplier circuit, and be defined as odd column multiplier circuit and even column multiplier circuit, odd bit lines connects odd multiple according to line through the odd column multiplier circuit, and even bitlines connects even position datawire through the even column multiplier circuit;

C. be provided with at least two group array selecting signals, one group is strange, idol position word-line signal, another group is strange, the even control line signal of emulation, wherein, strange position word-line signal connects the control end of all odd column multiplier circuits, idol position word-line signal connects the control end of all even column multiplier circuits, and the strange control line signal of emulation connects the control utmost point of odd number emulation row multiplier circuit, and emulation idol control line signal connects the control utmost point of even number emulation row multiplier circuit;

D. establish the emulation bit line of a parallel and impedance and bit line coupling at least at the appropriate location of memory cell array, and corresponding connected one with reference to current source and an odd number emulation row multiplier circuit and an even number emulation row multiplier circuit, this emulation bit line connects odd multiple according to line through odd number emulation row multiplier circuit, and connects even position datawire through even number emulation row multiplier circuit.

2. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 1 is read amplifying circuit, it is characterized in that: the emulation bit line of described at least one parallel and impedance and bit line coupling is laid in an end margin or the array central authorities of memory cell array.

3. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 1 or 2 is read amplifying circuit, it is characterized in that: described memory cell array is an independent matrix, the bit line of storage unit is wherein alternately arranged with strange, idol, row multiplier circuit is correspondingly also alternately arranged with strange, idol, and the bit line behind corresponding row multiplier circuit also alternately connects strange accordingly, even position datawire respectively.

4. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 1 or 2 is read amplifying circuit, it is characterized in that: described storage array is an independent matrix, storage unit bit line wherein is divided into very, idol group bit line is alternately arranged, correspondingly, the row multiplier circuit is also alternately arranged with strange, idol group, and the bit line behind corresponding row multiplier circuit also alternately connects odd multiple according to line, even position datawire with strange, idol group respectively.

5. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 4 is read amplifying circuit, it is characterized in that: described storage unit is strange, idol group bit line means with 2 or 4 or 8 or 16 or 32 strange, idol group bit lines that bit line constitutes.

6. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 1 or 2 is read amplifying circuit, it is characterized in that: described 2 strange, even position datawires are laid along the edge of said memory cell array.

7. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 5 is read amplifying circuit, it is characterized in that: described 2 strange, even position datawires are laid along the edge of said memory cell array.

8. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 3 is read amplifying circuit, it is characterized in that: described 2 strange, even position datawires are laid along the edge of said memory cell array.

9. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 4 is read amplifying circuit, it is characterized in that: described 2 strange, even position datawires are laid along the edge of said memory cell array.

10. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 1 or 2 is read amplifying circuit, it is characterized in that: described memory cell array comprises two cell group that structure is identical, this differential amplifier and two strange, even position datawires that connect two input end are laid between these two cell group, and the storage unit bit line in these two cell group connects odd multiple respectively according to line and even position datawire through corresponding row multiplier circuit.

11. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 10 is read amplifying circuit, it is characterized in that: described storage unit bit line is alternately arranged with strange, even figure place, correspondingly, strange, idol alternately connects odd multiple according to line and even position datawire.

12. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 10 is read amplifying circuit, it is characterized in that: the storage unit bit line in described two cell group is divided into identical strange, idol to be organized bit line and alternately arranges, and strange, even group bit line is connected odd multiple according to line and even position datawire through corresponding odd column multiplier circuit with the even column multiplier circuit.

13. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 12 is read amplifying circuit, it is characterized in that: described strange, even group bit line is organized bit line for strange, the idol that are made of a byte 8 bit lines.

14. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 13 is read amplifying circuit, it is characterized in that: between described two storage unit, 8 differential amplifiers are set, and there are 16 very, the idol position datawire is alternately arranged, form 8 pairs successively very, idol group data line, every group of data line connects a corresponding differential amplifier respectively, and lays 4 respectively very at the two ends of each cell group, idol emulation bit line is connected these 4 respectively very with 4, idol emulation bit line strange, even number is with reference to current source and corresponding strange, even number emulation row multiplier circuit; 4 strange, even emulation bit lines that one end of each cell group is laid connect strange, the even position datawire on 2 close differential amplifiers, and 8 bit lines of the odd number group in strange, the even cell group are connected according to line with 8 odd multiples successively, and 8 bit lines of even number set are connected with 8 even position datawires successively.

15. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 14 is read amplifying circuit, it is characterized in that: described connect 4 of 4 emulation bit lines respectively can replacing with reference to current source by a current mirror type with reference to current source, or be divided into two groups, every group connect a current mirror type with reference to current source.

16. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 14 is read amplifying circuit, it is characterized in that: at the described central portion that is located at 4 of each cell group two ends strange, even number emulation bit lines respectively and can be laid in described cell group accordingly with reference to current source and row multiplier circuit.

17. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 16 is read amplifying circuit, it is characterized in that: described is the current mirror type power supply with reference to current source, and every adjacent 2 or 4 or 8 emulation bit lines connect a current mirror type with reference to current source.

18. the balanced, symmetrical formula that is used for nonvolatile memory as claimed in claim 12 is read amplifying circuit, it is characterized in that: described strange, even group bit line comprises by 2 or 4 or 16 or 32 strange, idol group bit lines that bit line constitutes.

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