CN100520973C - Semiconductor integrated circuit device - Google Patents

Abstract

A programmable logic device unit, a non-volatile memory unit which stores data for programming the programmable logic device unit in a part of data storage area thereof and a control circuit which controls the non-volatile memory unit to allow the data stored in a part of the data storage area to be read at power-on time and supplied to the programmable logic device unit are integrally provided on a semiconductor chip. Based on the program data, the programmable logic device unit forms an interface for allowing the non-volatile memory unit to operate as at least one of a register, a flash memory, a random access memory, and a read-only memory.

Description

Semiconductor device

Technical field

The present invention relates to a kind of semiconductor device that is built-in with Nonvolatile memery unit (unit) and programmable logic device (PLD) unit.

Background technology

Now, popularizing and be manufactured on the business activity that is mounted with the semi-conductor chip of system LSI unit around the Nonvolatile memery unit that constitutes by NAND type flash memory etc.But the system LSI unit causes the specification difference because of client waits, and must change interface etc. according to specification.For this reason, must cause the cost of development height in the time of will having manufacturing to each production template and not possess the such problem of versatility.

In addition, in Japanese documentation 1, disclose a kind of flash memory cells is integrated on the semi-conductor chip with FPGA unit, CPU, RAM etc. and the data storage of the FPGA unit that will be used for programming at this device of the static latch of SRAM, anti-fuse, non-volatile memory cells (cell) etc.

[patent documentation 1] spy opens the 2003-218212 communique

Summary of the invention

Consider above-mentioned these situations and implemented the present invention, the objective of the invention is to, provide a kind of after making semi-conductor chip, can also easily constitute circuit, and cost of development is low and have a conductor integrated circuit device of high universalizable with the various functions except Nonvolatile memery unit.

The semiconductor device of a kind of form of the present invention comprises:

Integrated programmable logic device (PLD) unit on semi-conductor chip;

Integrated on above-mentioned semi-conductor chip, will be used for above-mentioned programmable logic device (PLD) unit is carried out the Nonvolatile memery unit that data programmed is kept at a part of zone of data storage area; And

Control above-mentioned Nonvolatile memery unit, when energized, read out in data of preserving in the above-mentioned part zone of above-mentioned data storage area and the control circuit that supplies to above-mentioned programmable logic device (PLD) unit.

According to the present invention, can provide a kind of and after making semi-conductor chip, can also easily constitute circuit, and cost of development is low and have a semiconductor device of high universalizable with the various functions except Nonvolatile memery unit.

Description of drawings

Fig. 1 is the planimetric map of semi-conductor chip of the semiconductor device of first embodiment of the invention.

Fig. 2 is the synoptic diagram of the address space of the flash memory cells among Fig. 1.

The circuit diagram of an example of the circuit structure when Fig. 3 is the data storage area sense data of the flash memory cells of expression from Fig. 1.

Fig. 4 is the synoptic diagram of an example of the circuit structure when writing routine data in the data storage area of the flash memory cells among Fig. 1.

Fig. 5 is the synoptic diagram of another example of the circuit structure when writing routine data in the data storage area of the flash memory cells among Fig. 1.

Fig. 6 is the synoptic diagram of another example of the address space of the flash memory cells among Fig. 1.

Fig. 7 is the synoptic diagram of an example of the circuit structure when changing the size of data storage area of the flash memory cells among Fig. 1.

Fig. 8 is the synoptic diagram of an example when changing the size of data storage area of the flash memory cells among Fig. 1.

Fig. 9 is the synoptic diagram of another example when changing the size of data storage area of the flash memory cells among Fig. 1.

Figure 10 is the synoptic diagram of another example when changing the size of data storage area of the flash memory cells among Fig. 1.

Figure 11 is the synoptic diagram of another example when changing the size of data storage area of the flash memory cells among Fig. 1.

Figure 12 is the synoptic diagram of another example when changing the size of data storage area of the flash memory cells among Fig. 1.

Figure 13 is the block scheme of expression as the concrete configuration example of the FPGA unit of an example of the programmable logic device (PLD) unit among Fig. 1.

Figure 14 is the block scheme of expression as the concrete configuration example of the CPLD unit of an example of the programmable logic device (PLD) unit among Fig. 1.

Figure 15 is the circuit diagram of structure of the part of storage unit (cell) array in the flash memory cells in the presentation graphs 1.

Figure 16 is the circuit diagram of another structure of the interior memory cell array of the flash memory cells in the presentation graphs 1.

Figure 17 is the planimetric map of the various configuration statuses of flash memory cells in the presentation graphs 1 and FPGA unit.

Figure 18 is the planimetric map of semi-conductor chip of the semiconductor device of second embodiment of the present invention.

The circuit diagram of an example of the circuit structure when Figure 19 is the data storage area sense data of the flash memory cells of expression from Figure 18.

Figure 20 is the synoptic diagram of an example of the circuit structure when writing routine data in the data storage area of the flash memory cells among Figure 18.

Figure 21 is the synoptic diagram of another example of the circuit structure when writing routine data in the data storage area of the flash memory cells among Figure 18.

Figure 22 is the planimetric map of semi-conductor chip of the semiconductor device of the 3rd embodiment of the present invention.

The circuit diagram of an example of the circuit structure when Figure 23 is the data storage area sense data of the flash memory cells of expression from Figure 22.

Figure 24 is the synoptic diagram of an example of the circuit structure when writing routine data in the data storage area of the flash memory cells among Figure 22.

Figure 25 is the synoptic diagram of another example of the circuit structure when writing routine data in the data storage area of the flash memory cells among Figure 22.

Figure 26 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 27 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 28 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 29 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 30 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 31 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 32 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 33 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 34 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 35 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 36 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 37 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 38 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 39 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 40 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 41 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 42 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 43 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 44 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 45 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 46 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 47 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 48 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 49 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 50 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 51 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 52 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 53 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 54 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 55 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Figure 56 is the block scheme of the object lesson of the circuit that expression is used among Fig. 1, the FPGA unit among Fig. 8, among Figure 22 is realized.

Symbol description

10... semi-conductor chip, 11... Nonvolatile memery unit, 12... programmable logic device (PLD) unit, 13... outside terminal, 14... control circuit, 15... interface, 16... address area initialization circuit, 17... error correction circuit, 18... multiplexer.

Embodiment

Below, with reference to the accompanying drawings and utilize embodiment to describe.

Fig. 1 is the planimetric map of semi-conductor chip of the semiconductor device of first embodiment of the invention.On semi-conductor chip 10, be integrated with and have storage unit (cell) array that constitutes by a plurality of Nonvolatile programmable elements and the Nonvolatile memery unit 11 and the programmable logic device (PLD) unit 12 of peripheral circuit.

Peripheral part at semi-conductor chip 10 is formed with a plurality of outside terminals 13 that are used for carrying out between this semi-conductor chip 10 and the external device (ED) various exchanges data and supply line voltage.

And, on semi-conductor chip 10, be formed with the control circuit (not shown) of control Nonvolatile memery unit 11.When energized, this control circuit is read the data in a part of data storage area that is stored in Nonvolatile memery unit 11, and supplies to programmable logic device (PLD) unit 12.

In the semiconductor device of present embodiment, an example as Nonvolatile memery unit 11, be formed with NAND type flash memory cells 11, as programmable logic device (PLD) unit 12, be formed with the FPGA unit of (field programmable gate array, the Field Programmable Gate Array) structure that has FPGA.But, as Nonvolatile memery unit 11, except NAND type flash memory cells, also can form any one flash memory cells of NOR type and AND type, mram cell (unit) with mram cell (cell), have at least a in the FeRAM unit (unit) of FeRAM unit (cell), and, as programmable logic device (PLD) unit 12, except the FPGA unit, also can form and have CPLD (compound programmable logic element, ComplexProgrammable Logic Device) the CPLD unit of structure, DFA (D Fabric Array) (TM) and the unit of other PLD structure.

In the semiconductor device of present embodiment, form FPGA unit 12 in the mode of surrounding flash memory cells 11.

The address space of the flash memory cells 11 in Fig. 2 presentation graphs 1.In flash memory cells 11, be set with two data memory block A and B.In the data storage area A of the higher level address of address space side, preserve routine data.In the data storage area B of subordinate's address side, preserve and be used for FPGA unit 12 is carried out data programmed (program).

In the semiconductor device of above-mentioned this structure, in the data storage area of flash memory cells 11 B, preserve in advance and be used for the routine data programmed in FPGA unit 12.Carry out as follows from data storage area B sense data: for example, as shown in Figure 3, during energized, by the action of control circuit 14 control flash memory cells 11, read out in the routine data of preserving the data storage area B from flash memory cells 11, and supply to FPGA unit 12.In FPGA unit 12, carry out the operation that is called configuration (Configuration), form the circuit of function with responder data.At this, the circuit that uses FPGA unit 12 to realize is various interface circuit and various control circuit, clock generator and the computing circuit etc. of flash memory cells 11.

In present FPGA,, can use SRAM usually as the device of save routine data.Because SRAM uses the volatibility programmable element to constitute, during dump, the storage data in the SRAM will disappear, and during power-on, must supply with routine data to FPGA once more, to form circuit once more once more.

With respect to this, in the semiconductor device of present embodiment, because will be used for that FPGA unit 12 is carried out data programmed is kept at flash memory cells 11, also can keep data even cut off the electricity supply, once more during power-on, read the routine data among the data storage area B that is stored in flash memory cells 11, and supply to FPGA unit 12.That is, when each power supply is under the opening, use FPGA unit 12 can realize having and the circuit of identical function in the past.

In addition, in the semiconductor device of present embodiment, by changing the routine data of in the data storage area of flash memory cells 11 B, preserving, can after the manufacturing of semi-conductor chip, use FPGA unit 12 easily to realize circuit with various functions.Its result can realize having the semiconductor device of high universalizable.And, owing to do not need as in the past to each production mask, so can make cost of development cheap.

The programmed element that is arranged in the flash memory cells 11 is non-volatile programmed element, can write data.The example of the circuit structure when routine data write flash memory cells 11 then, is described.

Fig. 4 is an example of the circuit structure of expression when writing routine data among the data storage area B of flash memory cells 11.

In the case, can use 1 outside terminal 13 that is arranged on the semi-conductor chip.From then on outside terminal 13 serial loading routine data by being arranged on the interface (I/F) 15 in the flash memory cells 11, supply to flash memory cells 11, thus the routine data order are written to data storage area B.

Fig. 5 is another example of the circuit structure of expression when writing routine data among the data storage area B of flash memory cells 11.

In the case, can use a plurality of outside terminals 13 that on semi-conductor chip, are provided with.From these a plurality of outside terminal 13 parallel loading routine data, by being arranged on the interface (I/F) 15 in the flash memory cells 11, supply to flash memory cells 11, thus routine data is written to data storage area B.Have, the data path between interface 15 and the flash memory cells 11 both can walk abreast again, and also can be serial.At this moment, can come the position of setting data memory block B according to the data of supplying with from outside terminal.

As shown in Figure 2, preserve subordinate's address side that the data storage area B be used for the routine data programmed in FPGA unit 12 is not limited to the address space of flash memory cells 11.Also can be shown in Fig. 6 (a), data storage area B is arranged on the intermediate address part of address space, and, also can shown in Fig. 6 (b), it be arranged on the higher level address side of address space.

In addition, can be certain size with the fixed size of the data storage area B of flash memory cells 11 also according to specification.If fix the size of data storage area B according to the maximal value of the circuit scale that uses FPGA unit 12 to realize, just can not make the data storage area inadequate.In most cases use the method.

Increase and decrease the routine data amount of in flash memory cells 11, preserving according to the circuit scale that FPGA unit 12 is realized.Under the few situation of routine data amount,, will in data storage area B, produce the useless region of not preserving data if set the size of data storage area B greatly.Therefore, in order to use the data storage area of flash memory cells 11 as far as possible effectively flexibly, also can change the size of data storage area B.

The circuit structure of the size of the data storage area B that is used to change flash memory cells 11 then, is described.

An example of the circuit structure when Fig. 7 represents to change the size of data storage area B of flash memory cells 11.

In the case, can use 1 outside terminal 13 that is arranged on the semi-conductor chip.From then on outside terminal 13 inputs are used for the data of the size of setting data memory block B, by interface (I/F) 15, supply to address area initialization circuit 16.Address area initialization circuit 16 is set the size of using data setting data memory block B in flash memory cells 11 according to size.Have again, the data path between interface 15 and the flash memory cells 11 both can be parallel also can be serial.

In the case, also can use a plurality of outside terminals 13 that are arranged on the semi-conductor chip.From then on a plurality of outside terminal 13 serials inputs are used for the data of the size of setting data memory block B, supply to address area initialization circuit 16 by interface (I/F) 15.

In the circuit of Fig. 7, will be stored in the control circuit 14 of front by the address of the varying sized data storage area B of address area initialization circuit 16.And, during from data storage area B sense data, read out in the data that preserve this address, supply to FPGA unit 12.

In addition, when changing the size of data storage area B, can carry out various changes according to purposes.

When Fig. 8 (a)～(c) is illustrated in the size that changes data storage area B, with the subordinate address of data storage area B be fixed on address space subordinate address, change higher level address side, change the situation of the size of data storage area B thus.

When Fig. 9 (a)～(c) is illustrated in the size that changes data storage area B, with the higher level address of data storage area B be fixed on address space higher level address, change subordinate's address side, change the situation of the size of data storage area B thus.

When Figure 10 (a)～(c) is illustrated in the size that changes data storage area B, with the higher level address of data storage area B be fixed on address space a certain intermediate address, change subordinate's address side, change the situation of the size of data storage area B thus.

When Figure 11 (a)～(c) is illustrated in the size that changes data storage area B, with the subordinate address of data storage area B be fixed on address space a certain intermediate address, change higher level address side, change the situation of the size of data storage area B thus.

When Figure 12 (a)～(c) is illustrated in the size that changes data storage area B, with the higher level address of data storage area B and subordinate address be set in respectively a certain intermediate address of the address space of flash memory cells 11, together change higher level address side and subordinate's address side, change the situation of the size of data storage area B thus.

The concrete formation example of the FPGA unit 12 in Figure 13 presentation graphs 1.This FPGA unit constitutes by a plurality of logical blocks 21 with in the upwardly extending wiring in side regional 22 in length and breadth.

In the FPGA unit of this structure, by being supplied to the routine data among the data storage area B that is kept at flash memory cells 11, use wiring zone 22 to form the wiring that a plurality of logical blocks 21 are connected each other, constitute the circuit of function with responder data.

Figure 14 represents can be used as an example of the CPLD unit that uses the programmable logic device (PLD) unit 12 among Fig. 1.This CPLD by a plurality of PLD pieces 31, the piece of cloth line zone 32 that is used to connect them constitutes.And above-mentioned each PLD piece 31 is by formations such as the AND-OR door that is called macroelement (cell), D flip-flop circuit.

In the CPLD unit of this structure,, use wiring zone 32 to form the wiring that PLD piece 31 is connected each other, constitute circuit with responder data function by being supplied to the routine data of in the data storage area of flash memory cells 11 B, preserving.

The structure of the part of the memory cell array in the Nonvolatile memery unit 11 in Figure 15 and Figure 16 difference presentation graphs 1.

Figure 15 (a) is a situation of using NAND type flash memory cells as Nonvolatile memery unit 11.Non-volatile transistor with 2 layers of gate electrode structure that formed by control grid electrode and floating gate electrode is as unit of cells 41, and a plurality of unit of cells 41 are connected in series, thereby constitutes NAND row 42.The control grid electrode of each unit of cells 41 is connected respectively to many word line WL.One end of each NAND row 42 selects transistor 43 to be connected to bit line BL by first, and its other end selects transistor 44 to be connected to source line SL by second.

Figure 15 (b) is a situation of using NOR type flash memory cells as Nonvolatile memery unit 11.Non-volatile transistor with 2 layers of gate electrode structure that formed by control grid electrode and floating gate electrode is as unit of cells 41, and a plurality of unit of cells 41 are connected between bit line BL and the source line SL.The control grid electrode of each unit of cells 41 is connected respectively to many word line WL.

Figure 16 (a) is a situation of using the mram cell with mram cell as Nonvolatile memery unit 11.A plurality of mram cells 44 are connected in parallel between the node of bit line BL and earthing potential.Each mram cell 44 is by a MTJ (magnetic tunnel-junction, Magnetic Tunnel Junction) element 45 and read selector switch (transistor) 46 formations.Be provided with the word line WWL that is used to write according to the mode parallel with each MTJ element 45, the word line RWL that is used to read is connected with the gate electrode of reading selector switch 46.MTJ element 45 has between free layer and pinning layer (pin layer) structure of inserting tunnel insulator film, stores data according to the relation of the direction of magnetization of the direction of magnetization of the ferromagnetic layer whose of the tunnel insulator film side of free layer and pinning layer.

Figure 16 (b) is a situation of using the FeRAM unit with FeRAM (ferroelectric RAM, Ferroelectric Random Access Memory) unit as Nonvolatile memery unit 11.Piece selector switch (transistor) BST and a plurality of FeRAM unit 47 are connected in series between bit line BL and the plateline PL.On the gate electrode of piece selector switch BST, be connected with piece selection wire BS.The ferro-electric materials capacitor 49 that a plurality of each FeRAM unit 47 are connected in parallel by memory cell transistor 48 with in the source of memory transistor 48, between leaking constitutes.The gate electrode of memory cell transistor 48 is connected to word line WL.

The situation that forms FPGA unit 12 in the semiconductor device of above-mentioned embodiment in the mode of surrounding flash memory cells 11 more than has been described.But the configuration status of flash memory cells 11 and FPGA unit 12 is not limited to above-mentioned embodiment, can carry out various distortion according to its purposes.

Figure 17 (a) expression forms the configuration status of the situation of FPGA unit 12 in the mode on three limits of encirclement flash memory cells 11.

Figure 17 (b) expression with FPGA unit 12 be divided into two parts, with the configuration status of situation about forming from the mode of sandwich flash memory cells 11 with these two part FPGA unit 12.

The mode that Figure 17 (c) expression connects flash memory cells 11 and FPGA unit 12 with 1 limit only is set up in parallel the configuration status of their two situations about forming.

Figure 18 is the planimetric map of semi-conductor chip of the semiconductor device of second embodiment of the present invention.The semi-conductor chip 10 of present embodiment is with the difference of the semi-conductor chip 10 of first embodiment shown in Figure 1, except Nonvolatile memery unit 11, programmable logic device (PLD) unit 12, also be integrated with error correction circuit (error checking and correction, Error Checking and Correcting; ECC) 17 and multiplexer (MUX) 18.

Even in the semiconductor device of second embodiment, an example as Nonvolatile memery unit 11, except NAND type flash memory cells, also can form any one flash memory cells among NOR type and the AND type, have mram cell mram cell, have at least a in the FeRAM unit of FeRAM unit, and, as programmable logic device (PLD) unit 12, the unit that also can form the FPGA unit, have CPLD unit, DFA and other PLD structure of CPLD structure.

In the semiconductor device of above-mentioned this structure, in the data storage area of Nonvolatile memery unit 11 B, preserve in advance and be used for the routine data programmed in FPGA unit 12.Carry out as follows from data storage area B sense data: for example, as shown in figure 19, when energized, the operation by control circuit 14 control Nonvolatile memery units 11 reads out in the routine data of preserving among the data storage area B from flash memory cells 11.Undertaken supplying to FPGA unit 12 after the error correction by 17 pairs of routine datas of reading from Nonvolatile memery unit 11 of error correction circuit.In FPGA unit 12, carry out the operation that is called configuration, form the circuit of function with responder data.The circuit that uses FPGA unit 12 to be realized is various interface circuit and various control circuit, clock generator and the computing circuit etc. of non-volatile memory cells 11.

On the other hand, routine data of storing in the data storage area of Nonvolatile memery unit 11 A and the data of storing in data storage area B are similarly, after carrying out error correction by error correction circuit 17, both can supply to FPGA unit 12 by multiplexer 18, perhaps also can not carry out error correction, supply to FPGA unit 12 by multiplexer 18.

In the SIC (semiconductor integrated circuit) of second embodiment, because also will be used for that FPGA unit 12 is carried out data programmed is kept at Nonvolatile memery unit 11, even also can keep data so cut off the electricity supply, when energized once more, read out in the routine data of preserving among the data storage area B of Nonvolatile memery unit 11, and supply to FPGA unit 12.That is, under the each on-state of power supply, can use FPGA unit 12 to realize having circuit with the front identical function.

In the semiconductor device of second embodiment, by changing the routine data of in the data storage area of Nonvolatile memery unit 11 B, preserving, can after the semi-conductor chip manufacturing, use FPGA unit 12 easily to realize circuit with various functions.Its result can realize having the high semiconductor device of versatility.And, owing to do not need as in the past to each production mask, so can make cost of development cheap.

The programmed element that is provided with in Nonvolatile memery unit 11 is non-volatile programmed element, can write data.The example of the circuit structure under the write-in program data conditions in Nonvolatile memery unit 11 then, is described.

Figure 20 is illustrated in the semiconductor device of Figure 18 and carries out the example that routine data is write fashionable circuit structure in the data storage area of Nonvolatile memery unit 11 B.

In the case, use an outside terminal 13 that is arranged on semi-conductor chip.From then on outside terminal 13 serial loading routine data, by interface (I/F) 15 and the error correction circuit 17 that in Nonvolatile memery unit 11, is provided with, supply to flash memory cells 11, the routine data that will add the symbol that is used for the error recovery data thus is written to data storage area B in proper order.

When from Nonvolatile memery unit 11 sense datas, as previously described, after being kept at data among the data storage area B of Nonvolatile memery unit 11 by 17 pairs of error correction circuits and carrying out error correction, supply to FPGA unit 12.Be kept at data among the data storage area A and carry out after the error correction by error correction circuit 17 or do not carry out error correction, be fed into FPGA unit 12.

Figure 21 is illustrated in another example that carries out the fashionable circuit structure of writing of routine data in the semiconductor device among Figure 18 in the data storage area of Nonvolatile memery unit 11 B.

In the case, can use a plurality of outside terminals 13 that are arranged on the semi-conductor chip.From then on a plurality of outside terminal 13 parallel loading routine data by being arranged on interface (I/F) 15 and the error correction circuit 17 in the Nonvolatile memery unit 11, supply to flash memory cells 11, thus routine data are write data storage area B.Have again, the data path between interface 15 and the flash memory cells 11 both can be parallel also can be serial.At this moment, can come the position of setting data memory block B according to the data of supplying with from outside terminal.The data that are kept among the data storage area A carry out after the error correction or do not proofread and correct just being fed into FPGA unit 12 with error correction circuit 17.Figure 22 is the planimetric map of semi-conductor chip of the semiconductor device of the 3rd embodiment of the present invention.The semi-conductor chip 10 of present embodiment is with the second embodiment semi-conductor chip, 10 differences shown in Figure 180, omitted multiplexer 18, on semi-conductor chip 10, except being integrated with Nonvolatile memery unit 11, FPGA unit 12, also be integrated with error correction circuit 17.

In the semiconductor device of the 3rd embodiment, an example as Nonvolatile memery unit 11, except NAND type flash memory cells, can also form NOR type and AND type any one flash memory cells, have mram cell mram cell, have the FeRAM unit of FeRAM unit, and, as programmable logic device (PLD) unit 12, the unit that can also form the FPGA unit, have CPLD unit, DFA and other PLD structure of CPLD structure.

In the semiconductor device of the 3rd embodiment, because will be used for that FPGA unit 12 is carried out data programmed is kept at Nonvolatile memery unit 11, even also can keep data so cut off the electricity supply, again during energized, read the routine data among the data storage area B that is kept at Nonvolatile memery unit 11, supply to FPGA unit 12.That is, under the each state of connecting of power supply, use FPGA unit 12 just can realize having circuit with the front identical function.

As shown in figure 23, in the semiconductor device of above-mentioned this structure, during from Nonvolatile memery unit 11 sense datas, after error correction circuit 17 execution error correction, supply to FPGA unit 12.

Figure 24 is illustrated in an example that carries out the fashionable circuit structure of writing of routine data in the semiconductor device among Figure 22 in the data storage area of Nonvolatile memery unit 11 B.

In the case, can use 1 outside terminal 13 that is arranged on the semi-conductor chip.From then on outside terminal 13 serial loading routine data, by being arranged on interface (I/F) 15 and the error correction circuit 17 in the Nonvolatile memery unit 11, supply to flash memory cells 11, the routine data that will add the symbol that is used for the error recovery data thus writes data storage area B in proper order.

When from Nonvolatile memery unit 11 sense datas, as previously described, after being kept at data among data area A, the B of Nonvolatile memery unit 11 by 17 pairs of each error correction circuits and carrying out error correction, supply to FPGA unit 12.

Figure 25 is illustrated in another example that carries out the fashionable circuit structure of writing of routine data in the semiconductor device among Figure 22 in the data storage area of Nonvolatile memery unit 11 B.

In the case, can use a plurality of outside terminals 13 that are arranged on the semi-conductor chip.From then on a plurality of outside terminal 13 parallel loading routine data, interface (I/F) 15 and error correction circuit 17 by being provided with in Nonvolatile memery unit 11 supply to flash memory cells 11, thus the routine data order are write data storage area B.Have, the data path between interface 15 and the flash memory cells 11 both can be that what to walk abreast also can be serial again.At this moment, can come the position of setting data memory block B according to the data of supplying with from outside terminal.

The example of the concrete structure of the various circuit that Figure 26 to Figure 49 is to use among Fig. 1, among Figure 18 or the FPGA unit 12 among Figure 22 is realized.Especially, thus Figure 26 to 30 expression is used among Fig. 1, the FPGA unit 12 among Figure 18 or among Figure 22 and as Nonvolatile memery unit 11, the example of concrete structure when using NAND type flash memory cells to realize being used for that NAND type flash memory cells come the employed various circuit of work as flash memory cells.

Figure 26 is to use FPGA unit 12 to have the example of the I/F60 of the interface circuit (NAND interface) (NAND I/F) 59 between flash memory cells (NAND type flash memory cells) 11 and the main frame 50 with realization.In the case, by using FPGA, can freely set the transfer approach, highway width, clock etc. of the data among the NAND I/F 59 according to the chip structure of main frame (host) side.

Have again, in Figure 26, owing to realized substituting NAND type interface with AND interface, NOR interface, although use NAND type flash memory cells, semi-conductor chip also can constitute the structure that is mounted with AND type flash memory cells, NOR type flash memory cells in fact.

In addition, can use NOR type flash memory cells to be used as Nonvolatile memery unit to substitute NAND type flash memory cells, use FPGA unit 12 to realize the NOR interface, and, substitute the NOR interface owing to realize NAND interface, AND interface, although so use NOR type flash memory cells, semi-conductor chip also can constitute the structure that is mounted with AND type flash memory cells, NAND type flash memory cells in fact.

Also have in addition, can use AND type flash memory cells to be used as Nonvolatile memery unit to substitute NAND type flash memory cells, use FPGA unit 12 to realize the AND interface, and, substitute the AND interface owing to realize NAND interface, NOR interface, although so use AND type flash memory cells, semi-conductor chip also can constitute the structure that is mounted with NAND type flash memory cells, NOR type flash memory cells in fact.

Have again, in the above description, though it is any one the situation in NAND type flash memory cells, NOR type flash memory cells, the AND type flash memory cells that Nonvolatile memery unit 11 only has been described, but, any 2 kinds of Nonvolatile memery units or the Nonvolatile memery unit more than 3 kinds also can be set, also can suitably realize interface circuit (I/F) 60 according to them.

In the explanation hereinafter, as Nonvolatile memery unit 11, describe as example to use NAND type flash memory cells, Figure 26 is illustrated as using, Nonvolatile memery unit 11 can use at least a memory cell in the various memory cells.

Figure 27 is to use FPGA unit 12 to realize having the example of the I/F60 of NAND type I/F 59 and error correction circuit (ECC) 61.

Figure 28 is to use that FPGA unit 12 realizes having NAND type I/F 59, the example of the I/F 60 of error correction circuit (ECC) 61 and bad management (Bad Block Management) circuit (BBM) 62.So-called BBM is the circuit that is used to detect, proofread and correct, manage the defective region of the memory cell array in the flash memory cells 11.

The example that Figure 29 is to use that FPGA unit 12 realizes having NAND I/F 59, the I/F 60 of (Wear Leveling Treatment) circuit (WLT) 63 is handled in ECC 61 and loss measurement of the level.So-called WLT is the circuit that is used to realize the long lifetime of the storage unit in the flash memory cells 11.

Figure 30 is to use that FPGA unit 12 realizes having NAND I/F 59, the example of the I/F 60 of ECC 61, BBM 62 and WLT 63.

Have again, Figure 26 is to each circuit shown in Figure 30, as Nonvolatile memery unit 11, except NAND type flash memory cells, can also form NOR type, AND type flash memory cells, mram cell, FeRAM unit, and, as programmable logic device (PLD) unit 12, except the FPGA unit, can also form CPLD unit, DFA unit with CPLD structure and unit with other CPLD structure.

Thereby Figure 31 to Figure 35 represents to use the FPGA unit 12 among Fig. 1 and the example of the concrete structure when using NAND type flash memory cells to realize being used for that NAND type flash memory cells come the employed various circuit of work as register as Nonvolatile memery unit 11.

Figure 31 is to use FPGA unit 12 to realize having the example of the I/F60 of NAND I/F59 and data buffer (register) 64.

Figure 32 is to use that FPGA unit 12 realizes having NAND I/F59, the example of the I/F 60 of data buffer 64 and ECC 61.

Figure 33 is to use that FPGA unit 12 realizes having NAND I/F 59, the example of the I/F 60 of data buffer 64, ECC 61 and BBM 62.

Figure 34 is to use FPGA unit 12 to realize the example of NAND I/F 59, data buffer 64, ECC 61 and WLT 63.

Figure 35 is to use FPGA unit 12 to realize the example of NAND I/F 59, data buffer 64, ECC 61, BBM 62 and WLT 63.

Have, Figure 31 is to each circuit shown in Figure 35, as Nonvolatile memery unit 11 again, except NAND type flash memory cells, can also form NOR type, AND type flash memory cells, mram cell, FeRAM unit, and, as programmable logic device (PLD) unit 12, except that the FPGA unit, can also form CPLD unit with CPLD structure, DFA unit, and unit with other CPLD structure.

Figure 36 to Figure 40 represents, use among Fig. 1, the FPGA unit 12 among Figure 18 or among Figure 22, and use NAND type flash memory cells as Nonvolatile memery unit 11, realize being used for NAND type flash memory cells the concrete formation example when any one comes various circuit that work exercises usefulness as flash memory (NOR type or AND type), SRAM (static RAM), SDRAM (synchronous dram).

Figure 36 is to use FPGA unit 12 to realize having the example of the I/F 60 of NANDI/F59 and data buffer RAM65.Have, data buffer RAM 65 comes down to SRAM again.

Figure 37 is to use that FPGA unit 12 realizes having NAND I/F 59, the example of the I/F 60 of data buffer RAM65 and ECC 61.

Figure 38 is to use that FPGA unit 12 realizes having NAND I/F 59, the example of the I/F 60 of data buffer RAM65, ECC 61 and BBM 62.

Figure 39 is to use that FPGA unit 12 realizes having NAND I/F 59, the example of the I/F 60 of data buffer RAM65, ECC 61 and WLT 63.

Figure 40 is to use that FPGA unit 12 realizes having NAND I/F 59, the example of the I/F 60 of data buffer RAM65, ECC 61, BBM 62 and WLT 63.

In each circuit of Figure 36 to Figure 40, the structure of the I/F by changing data buffer RAM 65 just can be as any one carries out work among flash memory (NOR type or AND type), SRAM and the SDRAM.

Have, Figure 36 is to each circuit shown in Figure 40, as Nonvolatile memery unit 11 again, except that NAND type flash memory cells, can also form NOR type, AND type flash memory cells, MR unit, FeRAM unit, and, as programmable logic device (PLD) unit 12, except that the FPGA unit, can also form CPLD unit with CPLD structure, DFA unit, and unit with other CPLD structure.

Figure 41 to Figure 44 represents, use among Fig. 1, the FPGA unit 12 among Figure 18 or among Figure 22, and use NAND type flash memory cells as Nonvolatile memery unit 11, the concrete formation example when realizing being used for that NAND type flash memory cells come the employed various circuit of work as register and these 2 circuit of flash memory.

Figure 41 is to use that FPGA unit 12 realizes having NAND I/F 59, the example of the I/F60 of data buffer 64 and ECC 61.

Figure 42 is to use FPGA unit 12 to realize the example of NAND I/F 59, data buffer 64, ECC 61 and BBM62.

Figure 43 is to use that FPGA unit 12 realizes having NAND I/F 59, the example of the I/F 60 of data buffer 64, ECC 61 and WLT 63.

Figure 44 is to use FPGA unit 12 to realize the example of NAND I/F 59, data buffer 64, ECC 61, BBM 62 and WLT 63.

Have again, Figure 41 is to each circuit shown in Figure 44, as Nonvolatile memery unit 11, except that NAND type flash memory cells, can also form NOR type, AND type flash memory cells, mram cell, FeRAM unit, and, as programmable logic device (PLD) unit 12, except the FPGA unit, can also form CPLD unit, DFA unit with CPLD structure and unit with other CPLD structure.

In addition, at Figure 41 to each circuit shown in Figure 44, though show the situation that has 2 data paths between main frame (host) 50 and I/F60, it also can constitute and only form a data path, utilize 2 circuit to come to use data path in the mode that the time is cut apart.

Thereby Figure 45 to Figure 48 represents to use the FPGA unit 12 among Fig. 1, among Figure 18 or among Figure 22 and the example of the concrete structure when using NAND type flash memory cells to realize being used for that NAND type flash memory cells carried out the employed various circuit of work as 2 circuit of any one and flash memory (NAND type) among flash memory (NOR type or AND type), SRAM and the SDRAM as Nonvolatile memery unit 11.

Figure 45 is to use that FPGA unit 12 realizes having NAND I/F 59, the example of the I/F 60 of data buffer RAM 65 and ECC 61.

Figure 46 is to use that FPGA unit 12 realizes having NAND I/F 59, the example of the I/F 60 of data buffer RAM65, ECC 61 and BBM 62.

Figure 47 is to use that FPGA unit 12 realizes having NAND I/F 59, the example of the I/F 60 of data buffer RAM65, ECC 61 and WLT 63.

Figure 48 is to use that FPGA unit 12 realizes having NAND I/F 59, the example of the I/F 60 of data buffer RAM65, ECC 61, BBM 62 and WLT 63.

In each circuit of Figure 45 to Figure 48, the structure of the I/F by changing data buffer RAM 65 just can be used as among SRAM and the SDRAM any one and carries out work.

Have again, Figure 45 is to each circuit shown in Figure 48, as Nonvolatile memery unit 11, except NAND type flash memory cells, can also form NOR type, AND type flash memory cells, mram cell, FeRAM unit, and, as programmable logic device (PLD) unit 12, except the FPGA unit, can also form CPLD unit, DFA unit with CPLD structure and unit with other CPLD structure.

In addition, to each circuit shown in Figure 48, show the situation that between main frame 50 and I/F 60, has 2 data paths, but it can constitute also and only forms a data path, utilizes the mode that 2 circuit were cut apart with the time to use data path at Figure 45.

In the above description, illustrated that use Nonvolatile memery unit 11 and FPGA unit 12 constitute the situation of the semiconductor device with a kind of or 2 kinds of functions.But it also can constitute the semiconductor device with function more than 3 kinds.And, at this moment, also can constitute and only form 1 data path, utilize the time to cut apart to carry out data to transmit.

Thereby Figure 49 to represent to use the FPGA unit 12 among Fig. 1, among Figure 18 or among Figure 22 and to use NAND type flash memory cells to realize making in order beginning the example of the concrete structure of NAND type flash memory cells as bootstrapping ROM work, when finishing to make NAND type flash memory cells to wait the employed various circuit of work as flash memory and SRAM after base band writes data as Nonvolatile memery unit 11.

As shown in FIG., use FPGA unit 12, just realized having NAND I/F 59, the I/F 60 of flag register (REG) 66, change-over circuit (MUX) 67 and circuit 68, circuit 68 comprises at least a among the ECC 61, the BBM 62 that have before illustrated, WLT 63, data buffer 64, the data buffer RAM 65.

In this structure, begin by change-over circuit 67, select the bootstrapping zone of NAND type flash memory cells, make NAND type flash memory cells as bootstrapping ROM work thus.

End will be arranged on from the sign of main frame 50 in the flag register 66 after base band writes data, according to the output of flag register 66 at this moment, and the output that utilizes change-over circuit 67 to select from circuit 68.At this moment, according to the structure of circuit 68, carry out work as flash memory and SRAM etc.In the case, also can use NAND type flash memory cells and FPGA unit 12 to constitute semiconductor device with function more than 2 kinds or 2 kinds.And, at this moment, also can constitute and only form 1 data path, utilize the circuit more than 2 or 2, use data path in the mode that the time is cut apart.

Have again, use FPGA unit 12, except that above-mentioned each circuit, can also realize the various interface circuit of Nonvolatile memery unit, various control circuit, for example clock generator and computing circuit etc.In addition, can realize processor (DSP, CPU etc.) according to purposes.

Have again, in Figure 26, the situation of the I/F60 of the interface circuit (NAND interface) (NAND I/F) 59 between use FPGA unit 12 (NAND type flash memory cells) 11 of realizing having flash memory cells and the main frame 50 has been described, but it also can be as shown in figure 50, use the I/F 60 of FPGA unit 12 (NAND I/F) 59 that realize having the NAND interface and NORI/F 69, make NAND type flash memory cells carry out work as NAND type flash memory and NOR type flash memory.

And, shown in Figure 51, also can use the I/F 60 of FPGA unit 12 (NAND I/F) 59 that realize having the NAND interface and SRAM I/F70, make NAND type flash memory cells carry out work as NAND type flash memory and SRAM.

In addition, shown in Figure 52, also can use the I/F 60 of FPGA unit 12 (NAND I/F) 59 that realize having the NAND interface and data buffer 64.

Figure 53 represents to use mram cell as Nonvolatile memery unit 11, use among Fig. 1, the FPGA unit 12 among Figure 18 or among Figure 22, thereby the example of structure under NAND interface 69 situations that realize being used for mram cell is used as NAND type flash memory cells.

Have again, in Figure 53, use FPGA unit 12 to realize that NOR interface, AND interface are to substitute NAND interface 69, mram cell can be used as NOR type flash memory cells, AND type flash memory cells, and, use FPGA unit 12, realize the MRAM interface, mram cell can be used as mram cell.

Figure 54 represents to use the FeRAM unit, use the FPGA unit 12 among Fig. 1, among Figure 18 or among Figure 22 as Nonvolatile memery unit 11, thereby realizes being used for the FeRAM unit as the example of structure under NAND interface 70 situations of NAND type flash memory cells use.

In addition, in Figure 54, use FPGA unit 12, realize that NOR interface, AND interface are to substitute NAND interface 70, the FeRAM unit can be used as NOR type flash memory cells, AND type flash memory cells, and, FPGA unit 12 used, realize the MRAM interface, the FeRAM unit can be used as mram cell.

The Nonvolatile memery unit 11 that forms on aforesaid semi-conductor chip is not limited to a memory cell as NAND type flash memory cells etc.For example, shown in Figure 55,, also can form two memory cells of NAND type flash memory cells 11a and mram cell 11b as Nonvolatile memery unit 11.In the circuit of Figure 55, use FPGA unit 12, can realize NAND I/F 59 and MRAM I/F 71.And, shown in Figure 56,, can also form NAND type flash memory cells 11a, mram cell 11b and three memory cells of FeRAM unit 11c as Nonvolatile memery unit 11.In the circuit of Figure 56, use FPGA unit 12, can realize NANDI/F59, MRAM I/F 71 and FeRAM I/F 72.As Nonvolatile memery unit 11, can also form three or more Nonvolatile memery units.

Have again, in Figure 55 and Figure 56, illustrated with respect to NAND type flash memory cells 11a and connected NAND I/F 59, connect MRAM I/F 71 with respect to mram cell 11b, and the situation that connects FeRAM I/F 72 with respect to FeRAM unit 11c, but also can connect different types of I/F for Nonvolatile memery unit, for example connect MRAM I/F 71 or FeRAMI/F 72 for NAND type flash memory 11a, and, also can connect NAND I/F 59 or FeRAM I/F 72, and can connect NAND I/F 59 or MRAM I/F 71 for FeRAM I/F 72 for mram cell 11b.

In addition, at Nonvolatile memery unit is under the situation of 2 or more memory cell, also can only be stored in a memory cell with being used for that FPGA unit 12 is carried out data programmed, or can also be in 2 or more memory cell respectively storage be used for FPGA unit 12 is carried out data programmed.

Claims (16)

1, a kind of semiconductor device comprises:

Integrated programmable logic device (PLD) unit on semi-conductor chip;

Integrated on above-mentioned semi-conductor chip, will be used for above-mentioned programmable logic device (PLD) unit is carried out the Nonvolatile memery unit that data programmed is saved in a part of zone of data storage area; And

Control above-mentioned Nonvolatile memery unit, when energized, read the data in the above-mentioned a part of zone that is stored in above-mentioned data storage area, and supply to the control circuit of above-mentioned programmable logic device (PLD) unit, described control circuit changes the function of above-mentioned programmable logic device (PLD) unit according to above-mentioned data, and described programmable logic device (PLD) unit is programmed to form and is used for making above-mentioned Nonvolatile memery unit as at least a first interface circuit that carries out work in register, flash memory, random access memory and the ROM (read-only memory).

2, semiconductor device according to claim 1, wherein, above-mentioned Nonvolatile memery unit be in NAND type, NOR type and the AND type any one flash memory cells, have mram cell mram cell, have in the FeRAM unit of FeRAM unit at least any one.

3, semiconductor device according to claim 1, wherein, above-mentioned programmable logic device (PLD) unit has FPGA structure or CPLD structure.

4, semiconductor device according to claim 1, wherein, by being arranged at least one outside terminal on the above-mentioned semi-conductor chip, will be used for the above-mentioned data of programming in above-mentioned programmable logic device (PLD) unit are input to above-mentioned Nonvolatile memery unit.

5, semiconductor device according to claim 1 also comprises:

Above-mentioned first interface circuit by utilizing above-mentioned programmable logic device (PLD) unit to form, and above-mentioned Nonvolatile memery unit between carry out the main frame of exchanges data, above-mentioned main frame comprises second interface circuit, change the structure of above-mentioned first interface circuit according to the specification of above-mentioned main frame, or change the structure of above-mentioned second interface circuit according to the specification of above-mentioned first interface circuit.

6, a kind of semiconductor device comprises:

Integrated programmable logic device (PLD) unit on semi-conductor chip;

Integrated on above-mentioned semi-conductor chip, will be used for that above-mentioned programmable logic device (PLD) unit is carried out data programmed and be saved in Nonvolatile memery unit in a part of zone of data storage area;

Integrated and be connected with above-mentioned programmable logic device (PLD) unit, above-mentioned programmable logic device (PLD) unit carried out the error correction circuit that data programmed is carried out error correction on above-mentioned semi-conductor chip to being used for; And

Control above-mentioned Nonvolatile memery unit, when energized, read the data in the above-mentioned a part of zone that is stored in above-mentioned data storage area, and supply to the control circuit of above-mentioned programmable logic device (PLD) unit, described control circuit changes the function of above-mentioned programmable logic device (PLD) unit according to above-mentioned data, and described programmable logic device (PLD) unit is programmed to form and is used for making above-mentioned Nonvolatile memery unit as at least a first interface circuit that carries out work in register, flash memory, random access memory and the ROM (read-only memory).

7, according to the semiconductor device of claim 6, wherein, above-mentioned error correction circuit carries out error correction to the above-mentioned data of reading from above-mentioned a part of zone of the above-mentioned data storage area of above-mentioned Nonvolatile memery unit, and supplies to above-mentioned programmable logic device (PLD) unit.

8, according to the SIC (semiconductor integrated circuit) of claim 6, wherein, above-mentioned Nonvolatile memery unit be in NAND type, NOR type and the AND type any one flash memory cells, have mram cell mram cell, have in the FeRAM unit of FeRAM unit at least any one.

9, according to the semiconductor device of claim 6, wherein, above-mentioned programmable logic device (PLD) unit has FPGA structure or CPLD structure.

10, according to the semiconductor device of claim 6, wherein, by being arranged at least one outside terminal on the above-mentioned semi-conductor chip, will be used for the above-mentioned data of programming in above-mentioned programmable logic device (PLD) unit are input to above-mentioned Nonvolatile memery unit.

11, according to the semiconductor device of claim 6, also comprise:

By above-mentioned first interface circuit that utilizes above-mentioned programmable logic device (PLD) unit to form, and carry out the main frame of exchanges data between the above-mentioned Nonvolatile memery unit, above-mentioned main frame comprises second interface circuit, change the structure of above-mentioned first interface circuit according to the specification of above-mentioned main frame, or change the structure of above-mentioned second interface circuit according to the specification of above-mentioned first interface circuit.

12, a kind of semiconductor device comprises:

Integrated programmable logic device (PLD) unit on semi-conductor chip;

Integrated on above-mentioned semi-conductor chip, will be used for that above-mentioned programmable logic device (PLD) unit is carried out data programmed and store Nonvolatile memery unit in a part of zone of data storage area into;

Integrated and be connected with above-mentioned programmable logic device (PLD) unit and above-mentioned programmable logic device (PLD) unit carried out the error correction circuit that data programmed is carried out error correction on above-mentioned semi-conductor chip to being used for;

Control above-mentioned Nonvolatile memery unit, when energized, read the data in the above-mentioned a part of zone that is stored in above-mentioned data storage area, and supply to the control circuit of above-mentioned programmable logic device (PLD) unit, described control circuit changes the function of above-mentioned programmable logic device (PLD) unit according to above-mentioned data, and described programmable logic device (PLD) unit is programmed to form and is used for making above-mentioned Nonvolatile memery unit as at least a first interface circuit that carries out work in register, flash memory, random access memory and the ROM (read-only memory); And

Integrated on above-mentioned semi-conductor chip, and with above-mentioned programmable logic device (PLD) unit, above-mentioned Nonvolatile memery unit and above-mentioned error correction circuit connect, be supplied to the data of from the zone different of the above-mentioned data storage area of above-mentioned Nonvolatile memery unit, reading with above-mentioned part zone, and from the zone different of the above-mentioned data storage area of above-mentioned Nonvolatile memery unit, read and carry out data after the error correction, and any one of above-mentioned two kinds of data supplied to the multiplexer of above-mentioned programmable logic device (PLD) unit by above-mentioned error correction circuit with above-mentioned part zone.

13, according to the SIC (semiconductor integrated circuit) of claim 12, wherein, above-mentioned Nonvolatile memery unit be any one flash memory cells in NAND type, NOR type and the AND type, have mram cell mram cell, have in the FeRAM unit of FeRAM unit at least any one.

14, according to the semiconductor device of claim 12, wherein, above-mentioned programmable logic device (PLD) unit has FPGA structure or CPLD structure.

15, according to the semiconductor device of claim 12, wherein, by being arranged at least one outside terminal on the above-mentioned semi-conductor chip, will be used for the above-mentioned data of programming in above-mentioned programmable logic device (PLD) unit are input to above-mentioned Nonvolatile memery unit.

16, according to the semiconductor device of claim 12, also comprise:

By above-mentioned first interface circuit that utilizes above-mentioned programmable logic device (PLD) unit to form, and carry out the main frame of exchanges data between the above-mentioned Nonvolatile memery unit,

Above-mentioned main frame comprises second interface circuit, changes the structure of above-mentioned first interface circuit or changes the structure of above-mentioned second interface circuit according to the specification of above-mentioned first interface circuit according to the specification of above-mentioned main frame.

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