CN100517459C - Image processing device - Google Patents
Image processing device Download PDFInfo
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- CN100517459C CN100517459C CNB2005800113649A CN200580011364A CN100517459C CN 100517459 C CN100517459 C CN 100517459C CN B2005800113649 A CNB2005800113649 A CN B2005800113649A CN 200580011364 A CN200580011364 A CN 200580011364A CN 100517459 C CN100517459 C CN 100517459C
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Abstract
An image processor is provided to increase a speed of entire image processing by efficiently operating a CPU. In the image processor (1), a high-speed bus (10) and a peripheral bus (12) are connected via a bus bridge (11). The CPU (13) for performing calculation and control of image processing, a data transmitting/receiving FIFO memory (18) for transmitting and receiving image compression data to and from a host device (4), a frame memory (16) for storing image decompression data from an electronic camera (2), etc. and displaying the data on a display panel (3), and a compression/decompression circuit (17) for compressing the image decompression data and decompressing the image compression data are connected to the both buses (10, 12). The CPU (13) and the frame memory (16) are connected to the high-speed bus (10), and the data transmitting/receiving FIFO memory (18) is connected to the peripheral bus (12).
Description
Technical field
The present invention relates to carry out the image processing apparatus of the compression/decompression of view data.
Background technology
In recent years, the e-machine as the portable phone on the basis of display image data, carries the Electrofax function and the view data of photography had both been shown storage.Thereby such e-machine need carry out the processing of the complexity of a large amount of view data, the general image processing apparatus (for example, patent documentation 1 and 2) that adopts CPU that uses.Fig. 3 represents an example of existing image processing apparatus.This image processing apparatus 101, in conjunction with the bus structure (bus architecture) of high-speed bus 10 and peripheral bus (peripheral bus) 12, various functional circuits are connected with two buses 10,12 via bus bridge (bus bridge) 11 in employing.That is, following parts are connected with high-speed bus 10: CPU13, and it carries out required computing and control in Flame Image Process etc.; ROM14, the handling procedure of its storage CPU13; RAM15, it is used as workspace of the computing that CPU13 carries out etc.Have again, following parts are connected with peripheral bus 12: frame memory 16, it is preserved from the image decompression data of Electrofax 2 and to the image compression data from host apparatus 4 and carries out image decompression data behind the decompress(ion), and with this data presentation in display panels such as LCD 3; Compression/decompression circuit 17, it carries out the compression of image decompression data and the decompress(ion) of image compression data; Data transmit-receive is with FIFO (FirstIn First Out) storer 18, carries out the transmitting-receiving of image compression data between itself and the host apparatus 4; With general purpose timer circuit 19 etc.In addition, image processing apparatus 101 comprises: frame memory register 20, and it is by the data of CPU13 read/write frame memory 16; Compression/decompression circuit register 21, it is by the data of CPU13 read/write compression/decompression circuit 17; With data transmit-receive register 22, it is by the data of CPU13 read/write data transmitting-receiving with FIFO storer 18.In addition, in this application, image compression data is meant the view data that had been compressed, and the image decompression data are meant the view data that was not compressed.
From the image decompression data of Electrofax 2, be kept at frame memory 16 and be presented at display panel 3, have again, be read into CPU13 via frame memory with register 20 and peripheral bus 12, be compressed by compression/decompression circuit 17 and RAM15 etc.This image compression data is written to data transmit-receive with FIFO storer 18 via peripheral bus 12 and data transmit-receive with register 22, is sent to host apparatus 4 successively.On the other hand, data transmit-receive receives image compression data from host apparatus 4 with FIFO storer 18, this image compression data with register 22 and peripheral bus 12, is read into CPU13 via data transmit-receive in order, is extracted by compression/decompression circuit 17 and RAM15 etc.These image decompression data are saved in frame memory 16 and are presented at display panel 3 with register 20 via peripheral bus 12 and frame memory.
Patent documentation 1: the spy opens the 2001-350461 communique;
Patent documentation 2: the spy opens the 2002-77709 communique.
Summary of the invention
Though, on the bases such as multiple processing of high-qualityization that realizes shown image or dynamic image and still image, more and more require to carry out at high speed Flame Image Process by the above-mentioned Flame Image Process of carrying out like that.Generally, comprise the high speed of the various circuit of CPU, but under the situation of considering consumed power or cost etc., it is also very important that CPU is worked efficiently to the high speed of Flame Image Process.
The present invention proposes in view of the above problems, and its purpose is to provide a kind of CPU that can make more effectively to work, and can realize the image processing apparatus of the high speed of Flame Image Process with this.
In order to solve above-mentioned problem, the image processing apparatus that preferred implementation of the present invention relates to, via bus bridge in conjunction with high-speed bus and peripheral bus, following parts are connected with peripheral bus with high-speed bus: CPU, it carries out the computing and the control of Flame Image Process; Data transmit-receive FIFO storer, itself and host apparatus carry out the transmitting-receiving of image compression data; Frame memory, its preserve image decompression data and with this data presentation at display panel; With the compression/decompression circuit, it carries out in the image processing apparatus of decompress(ion) of the compression of image decompression data and image compression data, above-mentioned CPU is connected with high-speed bus with frame memory, above-mentioned data transmit-receive is connected with peripheral bus with the FIFO storer, above-mentioned compression/decompression circuit is connected with high-speed bus, the processing power of described high-speed bus is higher relatively, and the processing power of described peripheral bus is low relatively.
The image processing apparatus that other preferred implementations of the present invention relate to, have instruction with the direct connecting bus of CPU, data with direct connecting bus of CPU and high-speed bus, following parts are connected with these buses: CPU, it carries out the computing and the control of Flame Image Process; ROM, the handling procedure of its storage CPU; RAM, it is used as the workspace of the computing that CPU carries out; Data transmit-receive FIFO storer, itself and host apparatus carry out the transmitting-receiving of image compression data; Frame memory, its preserve image decompression data and with this data presentation at display panel; With the compression/decompression circuit, it carries out in the image processing apparatus of decompress(ion) of the compression of image decompression data and image compression data, above-mentioned CPU is connected with the direct connecting bus of CPU with the ROM and instruction, above-mentioned CPU, RAM are connected with the direct connecting bus of CPU with data with frame memory, above-mentioned CPU is connected with high-speed bus with the FIFO storer with data transmit-receive.
This image processing apparatus as preferably, is connected with data above-mentioned compression/decompression circuit with the direct connecting bus of CPU.
(invention effect)
According to the present invention, because the frame memory that image processing apparatus is many with data volume is connected the high relatively bus of processing power, the data transmit-receive that data volume is less is connected the low relatively bus of processing power with the FIFO storer, CPU is moved efficiently, can realize the high speed that general image is handled with this.
Description of drawings
Fig. 1 is the block diagram of the image processing apparatus that relates to of preferred implementation of the present invention.
Fig. 2 is the block diagram of the image processing apparatus that relates to of other preferred implementations of the present invention.
Fig. 3 is the block diagram of existing image processing apparatus.
The explanation of symbol: 1,5-image processing apparatus; The 2-Electrofax; The 3-display panel; The 4-host apparatus; The 10-high-speed bus; The 12-peripheral bus; 13,23-CPU; The 16-frame memory; 17-compression/decompression circuit; 18-data transmit-receive FIFO storer; 20-frame memory register; 21-compression/decompression circuit register; 22-data transmit-receive register; 24-instructs with the direct connecting bus of CPU; The 25-data are with the direct connecting bus of CPU.
Embodiment
Below, with reference to description of drawings preferred forms of the present invention.Fig. 1 is the block diagram of the image processing apparatus that relates to of preferred implementation of the present invention.This image processing apparatus 1 adopts the bus structure that combine high-speed bus 10 of working and the peripheral bus 12 that moves via bus bridge 11 under 75MHz high frequency for example under the frequency of for example 25MHz, and various functional circuits are connected with two buses 10,12.That is, following parts are connected with high-speed bus 10: CPU13, it carries out the computing and the control of necessity of Flame Image Process etc.; ROM14, the handling procedure of its storage CPU13; And RAM15, it is used as workspace of the computing that CPU13 carries out etc., also connect: frame memory 16, it is preserved from the image decompression data of Electrofax 2 and to the image compression data from host apparatus 4 and carries out image decompression data behind the decompress(ion), and with this data presentation at display panels such as LCD 3; With compression/decompression circuit 17, it carries out the compression of image decompression data and the decompress(ion) of image compression data.Have, following parts are connected with peripheral bus 12: data transmit-receive is with FIFO storer 18, carries out the transmitting-receiving of image compression data between itself and the host apparatus 4; With general purpose timer circuit 19 etc.Have, image processing apparatus 1 comprises again: frame memory register 20, and it is by the data of CPU13 read/write frame memory 16; Compression/decompression circuit register 21, it is by the data of CPU13 read/write compression/decompression circuit 17; With data transmit-receive register 22, it is by the data of CPU13 read/write data transmitting-receiving with FIFO storer 18.In addition, compression/decompression circuit 17 particularly, is to use in the jpeg circuit of the compression/decompression of still image or is used in the MPEG circuit etc. of the compression/decompression of dynamic image.Have again, host apparatus 4, for example this image processing apparatus 1 is used under the situation of the such e-machine of portable phone, is the processor device etc. of the main functionality of this machine of control.
From the image decompression data of Electrofax 2, be stored in the frame memory 16 and and show have again at display panel 3, be read into CPU13 via frame memory with register 20 and high-speed bus 10, be compressed by compression/decompression circuit 17 and RAM15 etc.This image compression data is written to data transmit-receive FIFO storer 18 via peripheral bus 12 and data transmit-receive with register 22, and is sent to host apparatus 4 in order.On the other hand, the image compression data that data transmit-receive receives from host apparatus 4 with FIFO storer 18, this image compression data with register 22 and peripheral bus 12, is read into CPU13 via data transmit-receive in order, is extracted by compression/decompression circuit 17 and RAM15 etc.These image decompression data are stored in frame memory 16 with register 20 and show in display panel 3 via high-speed bus 10 and frame memory.
At this, high-speed bus 10 is worked under the high frequency of for example 75MHz, and the image decompression data are read into CPU13 at a high speed from frame memory 16, and, be written to frame memory 16 at a high speed from CPU13.Have again, because frame memory 16 is connected the identical bus of RAM15 with the workspace that is used as computing etc., so in a series of computing, can eliminate as switch adding (overhead) time of the dead time that produces because of bus.Like this, CPU works effectively in the transmission of the more image decompression data of data volume, helps the high speed of whole Flame Image Process.Have again, because the data transmission between CPU13 and the compression/decompression circuit 17 is also via high-speed bus 10, so the whole further high speed of Flame Image Process.On the other hand, peripheral bus 12 is for example being worked under the 25MHz frequency, thus image compression data to data transmitting-receivings writing or be comparison low speed with FIFO storer 18 to reading of CPU13.But this image compression data is for example 1/10 and even 1/100 and data volume is fewer of image decompression data, so general image processing speed and less descending.
Like this, this image processing apparatus 1, the frame memory 16 relative higher high-speed buses 10 with processing power that data volume is many connect, and the data transmit-receive that data volume is fewer connects with the relative low peripheral bus 12 with processing power of FIFO storer 18, so CPU13 is worked efficiently, can realize the high speed of Flame Image Process on the whole.In addition, data transmit-receive is connected with peripheral bus 12 with FIFO storer 18, this is because if the functional circuit that is connected with high-speed bus 10 is too much, then the load capacity of high-speed bus 10 becomes big, corresponding to the reason of this frequency that can work decline.
Have again, in this image processing apparatus 1, compression/decompression circuit 17 is connected with high-speed bus 10, but under the situation of the less compression/decompression circuit 17 of the read/write of using CPU13, also this compression/decompression circuit 17 can be connected with peripheral bus 12.
Then, based on Fig. 2 the image processing apparatus that other preferred implementations of the present invention relate to is described.This image processing apparatus 5 has adopted following bus structure, and these bus structure have: the instruction (instruction) that directly connects CPU23 and ROM14 is with the direct connecting bus 24 of CPU; The data that directly connect CPU23 and RAM15 are with the direct connecting bus 25 of CPU; With above-mentioned high-speed bus 10.For example, the instruction of the disposal system of ARM system is with TCM (Tightly Coupled Memory) bus, the TCM bus that data are used, AMBA (Advanced Microcontroller Bus Architecture) bus be equivalent to respectively instruction with the direct connecting bus 24 of CPU, data with the direct connecting bus 25 of CPU, high-speed bus 10.In addition, can have above-mentioned peripheral bus 12 (not shown) as required.
With the direct connecting bus 25 of CPU, also connect above-mentioned frame memory 16 and compression/decompression circuit 17 in data.Have again,, connect above-mentioned data transmit-receive FIFO storer 18 and timer circuit 19 etc. at high-speed bus 10.Have again, image processing apparatus 5, same with image processing apparatus 1, comprise above-mentioned frame memory register 20 and compression/decompression circuit register 21 and data transmit-receive register 22.
Instruction with the direct connecting bus 24 of CPU and data with the direct connecting bus 25 of CPU, the action of in for example 1 cycle of the elemental motion clock of CPU23, reading in or writing.On the other hand, high-speed bus 10, the action of in 5～10 cycles for example, reading in or writing.Thereby image processing apparatus 5 is compared with image processing apparatus 1, and these image decompression data are read into CPU23 more at high speed from frame memory 16, and are written to frame memory 16 more at high speed from CPU23.
Like this, this image processing apparatus 5, the frame memory 16 that data volume is many is connected the high relatively data of processing power with the direct connecting bus 25 of CPU, the data transmit-receive that data volume is less is connected the low relatively high-speed bus of processing power 10 with FIFO storer 18, so can realize the further high speed that general image is handled.In addition, data transmit-receive is connected high-speed bus 10 with FIFO storer 18, and this is because frame memory 16 moves to data with the direct connecting bus 25 of CPU, so the load capacity of high-speed bus 10 also less becomes big reason.
In addition, in this image processing apparatus 5, compression/decompression circuit 17 is connected data with the direct connecting bus 25 of CPU, still under the situation of the less compression/decompression circuit 17 of the read/write of using CPU23, also this compression/decompression circuit 17 can be connected with high-speed bus 10.
More than, the image processing apparatus that relates to for embodiments of the present invention is illustrated, but the present invention is not limited to embodiment, can carry out various design alterations in the scope of the item of being put down in writing within the scope of the claims.For example, in the e-machine that uses image processing apparatus 1,5, do not have under the situation of Electrofax 2, also can omit the function that will be kept at from the image decompression data of Electrofax 2 in the frame memory 16, have again, according to circumstances, also general purpose timer circuit 19 can be do not comprised, in addition, other necessary function circuit can certainly be comprised.
Claims (1)
1, a kind of image processing apparatus, wherein via bus bridge in conjunction with high-speed bus and peripheral bus, following parts are connected with peripheral bus with these high-speed buses: CPU, it carries out the computing and the control of Flame Image Process; Data transmit-receive FIFO storer, itself and host apparatus carry out the transmitting-receiving of image compression data; Frame memory, its preserve image decompression data and with this data presentation at display panel; With the compression/decompression circuit, it carries out the compression of image decompression data and the decompress(ion) of image compression data, it is characterized in that,
Described CPU is connected with high-speed bus with frame memory, described data transmit-receive is connected with peripheral bus with the FIFO storer,
Described compression/decompression circuit is connected with high-speed bus,
The processing power of described high-speed bus is higher relatively, and the processing power of described peripheral bus is low relatively.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP122251/2004 | 2004-04-16 | ||
| JP2004122251 | 2004-04-16 | ||
| JP117354/2005 | 2005-04-14 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1942926A CN1942926A (en) | 2007-04-04 |
| CN100517459C true CN100517459C (en) | 2009-07-22 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005800113649A Expired - Fee Related CN100517459C (en) | 2004-04-16 | 2005-04-15 | Image processing device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN100517459C (en) |
| TW (1) | TW200603529A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8405668B2 (en) * | 2010-11-19 | 2013-03-26 | Apple Inc. | Streaming translation in display pipe |
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2005
- 2005-04-15 CN CNB2005800113649A patent/CN100517459C/en not_active Expired - Fee Related
- 2005-04-15 TW TW094112144A patent/TW200603529A/en unknown
Also Published As
| Publication number | Publication date |
|---|---|
| CN1942926A (en) | 2007-04-04 |
| TW200603529A (en) | 2006-01-16 |
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Granted publication date: 20090722 Termination date: 20130415 |