CN100514271C - Chip set, chips in north bridge, and method for accessing data in magnetic disk - Google Patents
Chip set, chips in north bridge, and method for accessing data in magnetic disk Download PDFInfo
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- CN100514271C CN100514271C CNB2006101435364A CN200610143536A CN100514271C CN 100514271 C CN100514271 C CN 100514271C CN B2006101435364 A CNB2006101435364 A CN B2006101435364A CN 200610143536 A CN200610143536 A CN 200610143536A CN 100514271 C CN100514271 C CN 100514271C
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Abstract
A method of using chip set to carry out data access of redundant disc array includes setting chip set between central processor/system storage and disc array, connecting north bridge chip between central processor and system storage, using disc array accelerator to execute data access function of disc array, setting south bridge chip between north bridge chip and disc array and using south bridge chip to carry out data access of disc array.
Description
Technical field
The invention relates to a kind of computer system, and particularly relevant for a kind of computer system of redundant array of inexpensive disk.
Background technology
For bigger capacity, higher read-write usefulness are provided, or security, modern computer system is all supported redundant array of inexpensive disk (Redundant Array of Independent Disks, function RAID) usually.Simple, RAID utilizes the mode of array to make disk groups several disks, cooperates the design of data dispersed arrangement, promotes safety of data.Simultaneously storage data the time, data can be cut into many sections in being stored in each disk respectively, therefore utilize each disk that the addition effect of data is provided respectively, can promote the usefulness of whole computer system.RAID can also utilize parity checking (parity check) in addition, when making again any disk failures in the array, but sense data still.
Fig. 1 shows the synoptic diagram of the computer system 100 of a redundant array of inexpensive disk.Computer system 100 includes redundant array of inexpensive disks 1 30, South Bridge chip 108, north bridge chips 104, system storage 106 and central processing unit 102.
In Fig. 1, suppose that redundant array of inexpensive disks 1 30 is made up of 3 disks, include disk 132,134 and 136.Include a Magnetic Disk Controller 110 in the South Bridge chip 108, in order to control the storage of disk 132,134 and 136 respectively.And north bridge chips 104 is coupled between South Bridge chip 108, system storage 106 and the central processing unit 102.
Figure 2 shows that computer system 100 execution RAID data write the process flow diagram of example.At first central processing unit 102 can be write (step S201) in the system storage 106 with data D1 earlier, then Magnetic Disk Controller 110 is read another data D2 from disk 134, and data D2 write (step S202) in the system storage 106, afterwards, central processing unit 102 reads out data D2 (step S203) from system storage 106, then central processing unit 102 is done the computing of XOR (XOR) to obtain odd and even data DP (step S204) with data D1 and D2, central processing unit 102 is write (step S205) in the system storage 106 with odd and even data DP afterwards, last Magnetic Disk Controller 110 makes data D1 write (step S206) in the disk 132, and then Magnetic Disk Controller 110 makes odd and even data DP write (step S207) in the disk 136 again.
Summary of the invention
The invention provides a kind of chipset that is used for the redundant array of inexpensive disk data access, this chipset is linked to a central processing unit, between one system storage and a disk array, this chipset includes: the disk array accelerator, according to the disk array control command in order to carrying out first data and second data that access is stored in system storage, and to these first data and this second data actuating logic computing to obtain the function of odd and even data; The north bridge chips buffer, it includes the memory mapping working area, in order to stored disk controller control command; And the image working area, be used for stored disk array control command and; And South Bridge chip, be connected between this north bridge chips and this disk array, in order to the data of this disk array of access; Comprise: Magnetic Disk Controller, be used to control the data access of this disk array, and the South Bridge chip buffer, be used to store this disk array control command.
Moreover, the invention provides a kind of north bridge chips that is used for the redundant array of inexpensive disk data access, this north bridge chips is linked to a central processing unit, between one system storage, this north bridge chips sees through a South Bridge chip and is linked to a disk array, this north bridge chips comprises: a disk array accelerator, it is in order to carrying out first data and second data that access is stored in system storage according to the disk array control command, and to these first data and this second data actuating logic computing to obtain the function of odd and even data; And a north bridge chips buffer, including the north bridge chips buffer, it includes the memory mapping working area, in order to stored disk controller control command; And the image working area, in order to store this disk array control command.
Moreover, the invention provides a kind of data of magnetic disk array access method, include: a disk array control command is videoed to a north bridge chips buffer; One disk array accelerator is stored in one first data and one second data of this system storage according to this disk array control command access; And this disk array accelerator according to this disk array control command to these first data and this second data actuating logic computing obtaining one the 3rd data, and the 3rd data are write this system storage.
Description of drawings
Fig. 1 shows that one supports the computer system synoptic diagram of RAID.
Fig. 2 shows that one carries out the process flow diagram that the RAID data write.
Fig. 3 shows that the present invention one supports the computer system synoptic diagram of RAID.
Fig. 4 shows that the present invention one carries out the process flow diagram that the RAID data write.
Fig. 5 is the computer system synoptic diagram that shows another support of the present invention RAID.
Fig. 6 is the process flow diagram that shows that another execution of the present invention RAID data write.
Fig. 7 shows that the present invention one carries out the process flow diagram of RAID data read.
The primary clustering symbol description
100,300,500～computer system
102,302,502～central processing unit
104,304,504～north bridge chips
106,306,506～system storage
108,308,508～South Bridge chip
110,310,510～Magnetic Disk Controller
130,330,530～disk array
350,550～disk array accelerator
132,134,136,332,334,336,532,534,536～disk
512～South Bridge chip buffer
560～north bridge chips buffer
562～memory mapping working area
564～image working area
Embodiment
For above and other objects of the present invention, feature and advantage can be become apparent, cited below particularlyly go out preferred embodiment, and conjunction with figs., be described in detail below.
Fig. 3 is the synoptic diagram that shows the present invention's one computer system 300.Computer system 300 includes: disk array 330, South Bridge chip 308, north bridge chips 304, system storage 306 and central processing unit 302.
In Fig. 3, suppose that disk array 330 is made up of 3 disks, include disk 332,334 and 336.Include of the storage of a Magnetic Disk Controller 310 in the South Bridge chip 308, and a disk array accelerator (RAIDA) 350 is in order to carry out the function of disk array in order to control disk 332,334 and 336.North bridge chips 304 is coupled between South Bridge chip 308, system storage 306 and the central processing unit 302.
Figure 4 shows that computer system 300 execution RAID data write the process flow diagram of example.At first central processing unit 302 can be write (step S401) in the system storage 306 with data D1 earlier, and then Magnetic Disk Controller 310 is read another data D2 and data D2 is write (step S402) in the system storage 306 via north bridge chips 304 from disk 334.Afterwards, disk array accelerator 350 reads out data D1 and D2 (step S403) via north bridge chips 304 from system storage 106, then disk array accelerator 350 is done XOR (XOR) computing to obtain odd and even data DP (step S404) with data D1 and D2, disk array accelerator 350 is write (step S405) in the system storage 306 with odd and even data DP via north bridge chips 304 afterwards, last Magnetic Disk Controller 310 makes odd and even data DP write (step S406) the disk 336 from system storage 306, and then Magnetic Disk Controller 310 makes data D1 write (step S407) the disk 332 from system storage 306 again.
Inserting a disk array accelerator from the above in South Bridge chip 308 can make the load of central processing unit 302 reduce and then promote the usefulness of computer system 300.But transmit because data constantly see through the bus of 306 of north bridge chips 304 and South Bridge chips, therefore also taken the frequency range of its bus.
Fig. 5 is shown as the synoptic diagram of another computer system 500 of the present invention.Computer system 500 includes: disk array 5 30, chipset 570, system storage 506 and central processing unit 502.
In Fig. 5, chipset 570 comprises north bridge chips 504 and South Bridge chip 508.Suppose that disk array 5 30 is made up of 3 disks, include disk 532,534 and 536.Include in the South Bridge chip 508: Magnetic Disk Controller 510 is in order to the storage of control disk 532,534 and 536; And South Bridge chip buffer 512, in order to the relevant control command of temporary disk array accelerator 550.North bridge chips 504 is coupled between South Bridge chip 508, system storage 506 and the central processing unit 502.In the present embodiment, disk array accelerator (RAIDA) 550 is arranged in the north bridge chips 504, in order to carry out the function of disk array (RAID).North bridge chips 504 also includes a north bridge chips buffer 560 in order to temporary relevant control command in addition.
Be arranged in South Bridge chip 308 owing to disk array accelerator 350 among Fig. 3 of the present invention, so disk array accelerator 350 can be carried out the function of RAID easily according to the setting that is stored in relevant steering order in the South Bridge chip buffer (not shown).
And in Fig. 5 of the present invention, place north bridge chips 504 owing to disk array accelerator 550, therefore before carrying out the RAID function, must earlier disk array accelerator 550 relevant control commands be copied to north bridge chips buffer 560 by South Bridge chip buffer 512, use to offer disk array accelerator 550.
In order to duplicate relevant steering order to north bridge chips buffer 560, north bridge chips 504 can be spied on the memory mapping working area 562 that stores in (snoop) north bridge chips buffer 560 about Magnetic Disk Controller 510 relevant control commands, when operating system or other external command were carried out write operations to memory mapping working area 562, north bridge chips 504 will store disk array control command reflection (mapping) about disk array accelerator 550 in the image working area (shadow register) 564 of north bridge chips buffer 560 in the South Bridge chip buffer 512.And image working area 564 can be the specific region in the north bridge chips working area 560, for example can use the zone of memory mapping output input cycle (MMIO cycle).
For more specific description the present invention, please refer to Fig. 6, it is depicted as computer system 500 and carries out the process flow diagram 600 that the RAID data write example.
At first central processing unit 502 can be write (step S601) in the system storage 506 with data D1 earlier, and then Magnetic Disk Controller 510 is read another data D2 and data D2 is write (step S602) in the system storage 506 via north bridge chips 504 from disk 534.Then, north bridge chips 504 is spied on memory mapping working area 562 (step S603).If when operating system or other external command were carried out write operation to memory mapping working area 562, north bridge chips 504 arrived the disk array control command reflection (mapping) that stores in the South Bridge chip buffer 512 about disk array accelerator 550 among image working area (the shadow register) 564 of north bridge chips buffer 560 (step S604).Afterwards, disk array accelerator 550 reads out data D1 and D2 (step S605) according to the disk array control command in image working area 564 from system storage 506, then disk array accelerator 550 is done the computing of XOR (Exclusive-OR XOR) to obtain odd and even data DP (step S606) with data D1 and D2, disk array accelerator 550 is write (step S607) in the system storage 506 with odd and even data DP afterwards, and last Magnetic Disk Controller 510 makes data D1 and odd and even data DP write respectively disk 532 and the disk 536 (step S608) from system storage 506.
Figure 7 shows that the process flow diagram 700 of another embodiment of the present invention computer system 500 execution RAID data read examples.
At first the Magnetic Disk Controller 510 data D1 that will be stored in the disk 532 is stored to system storage 506 (step S701) through South Bridge chip 508 with north bridge chips 504.Then whether judgment data D1 is correct data (step S702).If data D1 is correct data, then central processing unit 502 directly reads the data D1 (step S703) that is stored in the system storage 506.
If data D1 is incorrect, then computer system 500 must be reduced correct data D1 according to another data D2 and odd and even data DP.Therefore Magnetic Disk Controller 510 can will be stored in the data D2 in the disk 534 and be stored in odd and even data DP in the disk 536 and see through South Bridge chip 508 respectively with north bridge chips 504 and be stored into system storage 506 (step S704).And north bridge chips 504 is spied on the memory mapping working area 562 (step S705) of stored disk controller 510 relevant steering orders.If operating system is carried out write operations to memory mapping working area 562, then north bridge chips 504 can will store in the South Bridge chip buffer 512 about the disk array control command reflection (mapping) of disk array accelerator 550 in the image working area 564 of north bridge chips buffer 560 (step S706).Then, disk array accelerator 550 reads data D2 and the odd and even data DP that is stored in the system storage 506 according to the disk array control command in image working area 564, and carry out anteiso-or (EXCLUSIVE-NOR, XNOR) logical operation is to obtain correct data D1 (step S707).At last, disk array accelerator 550 is with correct data D1 writing system storer 506 (step S708), central processor 502 can read correct data D1 (step S709) from system storage 506 in this, and then Magnetic Disk Controller 510 writes (step S710) in the disk 532 with correct data D1.
Can find because the present invention places north bridge chips 504 with disk array accelerator 550 by above-mentioned, so can reduce data and reside abroad the bus transmission of 506 of chip 504 and South Bridge chips in north, make the frequency range of bus to discharge, and then also reduced the stand-by period (latency) of reading system memory data 506.
Though the present invention with preferred embodiment openly as above; but it is not in order to limit scope of the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking the accompanying Claim book person of defining.
Claims (9)
1. chipset that is used for the redundant array of inexpensive disk data access, this chipset is linked between central processing unit, system storage and disk array, and this chipset comprises:
North bridge chips is connected between this central processing unit and this system storage, includes:
The disk array accelerator, according to the disk array control command in order to carrying out first data and second data that access is stored in system storage, and to these first data and this second data actuating logic computing to obtain the function of odd and even data;
The north bridge chips buffer, it includes the memory mapping working area, in order to stored disk controller control command; And the image working area, be used for stored disk array control command; And
South Bridge chip is connected between this north bridge chips and this disk array, in order to the data of this disk array of access; Comprise:
Magnetic Disk Controller is used to control the data access of this disk array, and the South Bridge chip buffer, is used to store this disk array control command.
2. chipset as claimed in claim 1, wherein the memory mapping output input cycle is used in this image working area, this north bridge chips is spied on this memory mapping working area, when operating system or external command are carried out write operation to this memory mapping working area, the control command that this north bridge chips will be stored in this disk array accelerator of this South Bridge chip this image working area of videoing.
3. north bridge chips that is used for the redundant array of inexpensive disk data access, this north bridge chips is linked between central processing unit, system storage, and this north bridge chips sees through South Bridge chip and is linked to disk array, and this north bridge chips comprises:
The disk array accelerator, it is in order to carrying out first data and second data that access is stored in system storage according to the disk array control command, and to these first data and this second data actuating logic computing to obtain the function of odd and even data; And
The north bridge chips buffer includes the north bridge chips buffer, and it includes the memory mapping working area, in order to stored disk controller control command; And the image working area, in order to store this disk array control command.
4. north bridge chips as claimed in claim 3, wherein the memory mapping output input cycle is used in this image working area; This north bridge chips is spied on this memory mapping working area, when operating system or external command were carried out write operation to this memory mapping working area, this north bridge chips was with this disk array control command that originally is stored in the South Bridge chip buffer this image working area of videoing.
5. data of magnetic disk array access method includes:
The disk array control command is videoed to the north bridge chips buffer;
The disk array accelerator is stored in first data and second data of system storage according to this disk array control command access; And
This disk array accelerator according to this disk array control command to these first data and this second data actuating logic computing obtaining the 3rd data, and the 3rd data are write this system storage.
6. data of magnetic disk array access method as claimed in claim 5, wherein this north bridge chips buffer includes memory mapping working area and image working area, wherein spy on this memory mapping working area, when operating system or external command are carried out write operation to this memory mapping working area, with this disk array control command from South Bridge chip buffer reflection to this image working area.
7. data of magnetic disk array access method as claimed in claim 6 comprises also this disk array control command is videoed to this image working area from the South Bridge chip buffer that wherein memory mapping output input cycle is used in this image working area.
8. data of magnetic disk array access method as claimed in claim 5, wherein when carrying out the data of magnetic disk array write-in functions, central processing unit writes this system storage with these first data, these second data of utilizing a Magnetic Disk Controller will be stored in disk array write to this system storage, this disk array accelerator carries out the XOR computing obtaining odd and even data with these first data and this second data, and makes this Magnetic Disk Controller make these first data and this odd and even data write in this disk array.
9. data of magnetic disk array access method as claimed in claim 5, wherein when carrying out the data of magnetic disk array read functions, these first data and this second data of utilizing a Magnetic Disk Controller will be stored in disk array write to this system storage, this disk array accelerator carries out anteiso-or logical operation to obtain the 3rd data with these first data and this second data, wherein these first data are odd and even data, wherein central processing unit reads the 3rd data that are stored in this system storage, and this Magnetic Disk Controller makes the 3rd data write in this disk array.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101435364A CN100514271C (en) | 2006-11-10 | 2006-11-10 | Chip set, chips in north bridge, and method for accessing data in magnetic disk |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006101435364A CN100514271C (en) | 2006-11-10 | 2006-11-10 | Chip set, chips in north bridge, and method for accessing data in magnetic disk |
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| Publication Number | Publication Date |
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| CN1959620A CN1959620A (en) | 2007-05-09 |
| CN100514271C true CN100514271C (en) | 2009-07-15 |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102609221B (en) * | 2012-02-07 | 2015-07-08 | 无锡众志和达数据计算股份有限公司 | Hardware RAID 5/6 memory system and data processing method |
| CN106873904B (en) * | 2016-12-30 | 2020-02-14 | 深圳忆联信息系统有限公司 | Data writing method and solid state disk |
| CN109189340B (en) * | 2018-08-29 | 2021-11-09 | 上海兆芯集成电路有限公司 | System and method for accessing redundant array of independent hard disks |
| CN112785483B (en) * | 2019-11-07 | 2024-01-05 | 深南电路股份有限公司 | Method and equipment for accelerating data processing |
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