CN100512361C - Apparatus for realizing convolutional interleaving and canceling interleave in asymmetric user line - Google Patents
Apparatus for realizing convolutional interleaving and canceling interleave in asymmetric user line Download PDFInfo
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Abstract
The invention consists of storage unit and storage control circuit used to indicate lead byte, to input data, to indicate input data refresh and clock signal input. The storage unit outputs data signal and indication signal of data refresh. The storage control circuit contains unit of generating address. Base on refresh indication, the storage control circuit first writes a byte and then read a byte when interlace. When de-interlace it first reads a byte and then writes a byte. The units of generating address controls generation of read and write address to implement reading and writing first code word in sequence way and reading and writing remaining code word in convolution way.
Description
Technical field
The present invention is mainly used in the broadband access field, specifically, relates to the processing unit of ADSL (Asymmetric Digital Subscriber Line) (ADSL) " sudden mistake ".
Background technology
The ADSL system can transmit POTS (telephone service) or ISDN (integrated digital network business) and broadband data service simultaneously on a pair of twisted-pair feeder, whole frequency band is divided into 256 DMT (Discrete multi-tone) subchannel (the ADSL+ agreement is divided into 512 DMT subchannels) with the interval of 4.3125Khz.
The operational environment of twisted-pair feeder is more abominable, is subject to lightning or other interference, produces the spiking of transition, and this spiking can cause mistake on the ADSL channel, and error correcting capability will strengthen if channel is introduced the interleaving/deinterleaving link.By the data that will launch being upset it in proper order by interweaving at transmitting terminal, the output of the time slot of demodulation reconfigures through the reverse process of a deinterleaving after receiving, make its sequence that becomes original order, so just adjacent burst error can be distributed to the scope that error correction decoding can error correction.For example for 1 ADSL down link, finish at the telecommunication department machine room and to interweave, through telephone wire transmission data, finish deinterleaving at user's family then.
Interweave and the software implementation method of deinterleaving normally utilizes the DSP device, DSP utilizes the symbol period of chip internal memory according to ADSL, finish the process of writing, the read procedure of the process of writing, read procedure and the deinterleaving that interweave according to the structure of RS (Read-Solomon) code word.The RS code word has 255 bytes at most, if use software approach to realize that interweaving of N*D=255*128 and deinterleaving need the 2*8*255*128=52.224kbits internal memory.
Interweave and the software implementation method of deinterleaving has some shortcomings, special-purpose DSP at first must be arranged, because it is universal day by day that the ADSL cable broadband inserts, cost requirement is more and more lower, and DSP device or Kernel Technology are very complicated, generally all by the research and development of special-purpose manufacturer, the use cost height is because the use in ADSL of DSP device has seriously restricted the further reduction of ADSL nest plate product cost.
Software approach is realized interweaving and deinterleaving simultaneously, both taken memory source, also taken the use resource of DSP itself, owing to carry out the transmitting-receiving of data after the ADSL connection is set up always, memory headroom so be used to interweave with deinterleaving can not discharge, and can only be used to interweave and deinterleaving always, and the use resource of DSP is limited simultaneously, interweave and deinterleaving work if frequently be used for scheduling, then handle and reduce relatively other task time.
Interweave and deinterleaving also has and uses hardware to finish, for example use shift register approach, dual port RAM (static random access memory) method or DRAM (dynamic random access memory) method,
If use shift register, each bit is all wanted a d type flip flop, along with the increase of byte quantity and the increase of interleave depth, need a large amount of d type flip flops, if realize N=255, interweaving of D=128 then needs 52.224k d type flip flop, and so huge d type flip flop is unfavorable for the system integration and the test of chip owing to interweave and deinterleaving is lost more than gain.
Have in GA-HDTV (high definition television) and use dynamic ram to realize interweaving and deinterleaving, the time-delay that interweaves that this method realizes is j (data block label) * 4*52, and time-delay is fixing, can not realize the D-1 time-delay of any byte, wherein interleave depth D=2
m, D can be 1,2,4,8,16,32,64,128.This implementation method very flexible can only be used for the high definition television field, can not be used for the variable byte in ADSL field, the occasion of variable interleave depth.
In some treatises, the reconciliation interweaving method that interweaves also has the convolutional interleave method, and it is to determine the address by look-up method that its convolution realizes, this method control is complicated, loaded down with trivial details, is not easy to realize with hardware.
Summary of the invention
The technical problem to be solved in the present invention provides the implement device of convolutional interleave and deinterleaving in a kind of ADSL (Asymmetric Digital Subscriber Line), can realize the deinterleaving of interweaving of ADSL down channel and ADSL up channel with hardware approach, and definite address that need not to table look-up.
In order to solve the problems of the technologies described above, the invention provides the implement device of convolutional interleave and deinterleaving in a kind of ADSL (Asymmetric Digital Subscriber Line), comprise storage control circuit and memory cell, it is characterized in that:
The input signal of described storage control circuit comprises first byte index signal, input data signal, input Refresh Data index signal and clock signal; It comprises address signal, write data signal and read-write control signal with the signal that is connected between described memory cell, and described memory cell output signal comprises outputting data signals and dateout refresh instructing signal;
Described storage control circuit comprises address generating device, and this control circuit is used in described memory cell writing a byte earlier according to described input Refresh Data indication when interweaving, and reads a byte then; When deinterleaving, then earlier read a byte, write a byte then in described memory cell; Address generating device wherein is used for interweaving or the generation of address is write, read in deinterleaving time control, realizes writing in a sequential manner and reading first code word, writes and read remaining code word in the convolution mode.
Further, the address generating device of above-mentioned implement device can comprise that N*D counter, amalgamation generate writing linage-counter and writing column counter of write address, amalgamation generates reads reading linage-counter and reading column counter of address, described memory cell is divided into the capable D row of N according to byte quantity parameter N and interleave depth parameter D, wherein:
The initial value of described N*D counter is 0, and maximum is the product of N and D, D=2
mWhen described first byte index signal is effective, the low m position of this counter composed to described as initial value write row and read column counter, this counter is removed a high position remaining behind the m position to be composed to described as initial value and writes row and read linage-counter, and finish circulation and add N, reset when being added to maximum, again counting;
The described column counter of writing determines its output valve by the initial value of giving when interweaving; When deinterleaving, whenever write a byte, count value circulation adds 1, reach maximum D-1 after, be reset to 0 counting again;
The described linage-counter of writing whenever writes a byte when interweaving, count value circulation adds 1, reach maximum N-1 after, be reset to 0 counting again; When deinterleaving, whenever write delegation, count value adds 1;
The described column counter of reading whenever reads a byte when interweaving, count value circulation adds 1, reach maximum D-1 after, be reset to 0 counting again; When deinterleaving, determine its output valve by the initial value of giving;
The described linage-counter of reading whenever runs through delegation when interweaving, count value adds 1; When deinterleaving, whenever read a byte, count value circulation adds 1, reach maximum N-1 after, be reset to 0 counting again.
Further, above-mentioned implement device can have following characteristics: the described value of writing row and reading linage-counter is the low level as described address signal, and the described value of writing row and reading column counter is the high position as described address signal.
Further, above-mentioned implement device can have following characteristics: described memory cell realizes with the random asccess memory (RAM) of single port; In order further to be convenient to the assurance of sequential relationship, being connected signal and also can comprising clock signal between described storage control circuit and single port random asccess memory, described single port random asccess memory is the 8 bit synchronous random asccess memory that have clock signal.
Further, in order to make apparatus of the present invention be applicable to the occasion of variable byte, variable interleave depth.Described byte quantity parameter N and interleave depth parameter D can be provided by the signal of input RAM control circuit.
As from the foregoing, apparatus of the present invention can realize interweaving of ADSL channel and deinterleaving with hardware approach, directly generate the read/write address of RAM by hardware, the convolution process is simple, need not table look-up, adopting single port RAM to realize can save area, makes control simple, RAM can conveniently be integrated in the chip, reduces cost.Further, when determining read/write address, can obtain the read-write first byte address of RS code word from the N*D counter, the read-write control of RAM is then carried out " the position assembly is operated " by the figure place of row, column counter and is directly obtained, and does not need complicated control and consideration specially; The present invention also can realize byte quantity variable (1 to 255), the convolutional interleave of interleave depth variable (1 to 128), and real-time operation is carried out in the write-read that interweaves and the read-write of deinterleaving, can realize the time-delay of j (the RS code word joint label) * (D-1) of byte.
Adopt the present invention and cooperate other ADSL channel data to handle, for example hardware such as scrambler, RS coding is realized, can thoroughly solve the Data Stream Processing of ADSL transceiver channel, and the efficient height is low in energy consumption simultaneously.
Description of drawings
Fig. 1 is the hardware circuit implementation figure of embodiment of the invention interleaving/deinterleaving device.
Fig. 2 is embodiment of the invention N=5, the process of writing that interweaves during D=2 and the read procedure of deinterleaving.
Fig. 3 is embodiment of the invention N=5, the process of writing of read procedure that interweaves during D=2 and deinterleaving.
Embodiment
Information unit minimum in the ADSL channel is the byte of 8 bits, interweave and the information unit of deinterleaving is the RS code word, generally be that tens bytes (maximum 255 bytes) are interweaving of a minimum to conciliate interweaving information unit according to actual needs, according to the difference of interleave depth D, finish a plurality of RS code words and interweave and deinterleaving.
As shown in Figure 1, present embodiment ADSL interlaced device/de-interleaving apparatus mainly is made up of RAM control circuit 1 and ram memory cell 2.
The signal that is input to RAM control circuit 1 comprises overall signals such as clock signal clk, reset signal reset and enable signal enable; First byte index signal rsbyte_first, input data signal rsbyte_input[7:0] and input data and control signal such as input Refresh Data index signal rsinput_valid; And the byte number signal n[7:0 of RS code word] and interleave depth signal d[6:0] etc. interweave and conciliate the interleave parameter signal.
Connection signal between RAM control circuit 1 and the ram memory cell 2 comprises: address signal address[14:0], write data signal wrdata[7:0], read-write control signal write_ctrl, RAM enable control signal ram_en and clock signal clk.
Ram memory cell 2 is synchronous random access memories that have clock signal 8 bits of single port, the selection synchronous random access memory is realized, reason is that sequential relationship guarantees easily, and ram memory cell is according to actual input parameter n[7:0], d[6:0], be divided into n capable (maximum 255), d and be listed as (maximum 128).
The data-signal Output_byte[7:0 that comprises output from the signal of ram memory cell 2 outputs] and dateout refresh signal output_vaild.
Following elder generation is the specific implementation of example explanation present embodiment device to interweave.
When a continuous data flow was interweaved, the byte number of supposing the RS code word was N (present embodiment N=5), and interleave depth is D (present embodiment D=2).The interleaving process of N*D byte is at first to write a byte at ram memory cell, reads a byte from ram memory cell then, then writes a byte again, reads a byte again, writes up to N*D byte to run through.By to writing, read the control of address, the order of byte to be upset, the byte-interleaved that makes a plurality of code words is together.The beat of write-read is controlled by clock signal clk, and write or read is then by the signal controlling of read-write control line.
Fig. 2 shows the present embodiment secondary and interweaves and write process.What write when interweaving for the 1st time is that label is the RS code word RS0 and the RS1 of " 0 " and " 1 ", comprise B00～B04, B10～B14 totally 10 bytes respectively, the RS code word RS2 and the RS3 that write when interweaving for the 2nd time comprise B20～B24, B30～B34 totally 10 bytes respectively.Fig. 3 then shows the present embodiment secondary read procedure that interweaves, and what read is the multi-group data of the N byte that interweaved.Introduce the working method of each hardware below respectively:
The N*D counter
Selected N, D might be different when connecting because each ADSL is carrying out link, so the figure place of the N*D counter of at first will determining to interweave evenly is divided into 0 to ram memory cell by the control to the row, column address, 1,2,3 ... N-1 is capable and 0,1,2,3 ... the D-1 row.Present embodiment is to be divided into 5 row, 2 row.
The N*D counter is " byte and " counter, has determined the byte quantity that need interweave.The initial value of counter is zero, and maximum is the product of actual input parameter N and D.When receiving first byte marker pulse signal (being that the RS code word refreshes), according to the form below composes an initial value for the individual count device, and finishes circulation and add N, cumulative process is: N*D counter=N*D counter+N, when reaching maximum, be reset to 0 and restart counting, its cycle period is a N*D byte.
Table 1: counter initial value
| D[6:0] |
0 | 2 | 4 | 64 | |
| Write the column counter initial value | 0 | N*D(0) | N*D(1:0) | ...... | N*D(5:0) |
| Write the linage-counter initial value | N*D(7：0) | N*D(8:1) | N*D(9:2) | ...... | N*D(13:6) |
| Read the column counter initial value | 0 | N*D(0) | N*D(1:0) | ...... | N*D(5:0) |
| Read the linage-counter initial value | N*D(7:0) | N*D(8:1) | N*D(9:2) | ...... | N*D(13:6) |
Find out D=2 from last table
mThe time during initialize, be the low m position of N*D counter to be composed to described write column counter and read column counter, counter removes behind the m position a remaining high position and composes to described as initial value and write linage-counter and read linage-counter.Present embodiment D=2, when preparing to write B00～B04, everybody is 0 the N*D counter, gives and writes row, writes row, reads row, reads the initial value that column counter composes and be zero; When B10～B14 was write in preparation, the N*D Counter Value was 5, and lowest order " 1 " is composed to writing row and reading column counter, be that initial value is 1,, the 9th composed to writing row and reading linage-counter to the 2nd " 00000010 " corresponding to secondary series, be that initial value is 2, corresponding to the third line.When receiving next byte marker pulse signal, the N*D counter reaches maximum 10, directly is reset to zero.
Ram memory cell read-write control
In interleaving process, at first when input Refresh Data index signal is effective, write a byte, and then read a byte, and generation dateout refresh pulse index signal, circulation is gone down so always, and up to the write-read process of finishing a N*D byte, the control of the address of RAM is as follows:
Write address control (interweave and write process)
RAM_address[14:0]=write column counter value position to spell the linage-counter value
Read address control (read procedure interweaves)
RAM_address[14:0]=read column counter value position to combine the linage-counter value into syllables
Write linage-counter, write column counter and writing mode
The effect of writing linage-counter is the write address (low order address) of control RAM, finish circulation according to input Refresh Data index signal and add 1, that is: write linage-counter=write linage-counter+1, maximum is the interleave parameter n[7:0 of actual input] value, after counting reaches maximum N-1, reset to 0.
Writing column counter also is as the write address (high address) of control RAM, is obtained by N*D counter low-order bit according to refreshing directly of RS code word, promptly obtains by initialize.
Writing row and writing column counter and data are write under the control of address, can realize 2 kinds of writing modes in the process of writing that interweave: sequential system writes with the convolution mode and writes.
Sequential system writes first RS code word (N byte) that is used to interweave, and the sequential write process is undertaken by row.Please refer to Fig. 2, when writing the B00 byte of first RS code word, N*D counter, the initial value of writing linage-counter and writing column counter are zero, thereby the B00 byte is write the position of first row, first row, subsequently, it is constant to write the column counter value, whenever writes a byte to ram memory cell, write linage-counter and add 1, thereby respectively with B01, B02, B03, the B04 byte write first row second, third, the 4th and fifth line, write and write column counter after N the byte and add 1 according to the first byte index signal.
The convolution mode write be used for second RS code word, the 3rd RS code word ... up to D RS code word, it also is to write by row that the convolution that interweaves is write process.The initial value of writing linage-counter and writing column counter is by the decision of N*D counter, and the writing position of the first byte of each RS code word is the first byte of every row not necessarily.
Please refer to Fig. 2, after having write the B04 byte, indication adds N to the N*D counter according to RS prefix of code word byte, and its value becomes 5, as mentioned above, behind N*D counter initialize, writing the column counter value is 1, points to secondary series, and writing the linage-counter value is 2, point to the third line, thereby will write on secondary series the third line by the B10 byte, it is constant to write the column counter value then, whenever writes a byte in RAM, write the linage-counter value and add 1, B11 and B12 are write on secondary series the 4th, fifth line, reached maximum 4 owing to write linage-counter this moment, after receiving next input Refresh Data signal, counter reset, since 0 counting, at this moment produce the convolution process, B13 is write secondary series first row, B14 is write secondary series second row, finish the ablation process that once interweaves.The N*D counter reset, beginning writing next time.
The ablation process that interweaves for the 2nd time is identical with the 1st time, and RS2 that obtains and the deposit position of each byte of RS3 code word in ram memory cell are as shown in Figure 2.
Read linage-counter, read column counter and read mode
The effect of reading linage-counter be control RAM read address (low order address), behind initialize, whenever run through 1 row (after being column counter=D-1), finishing circulation and adding 1, promptly read linage-counter=read linage-counter+ 1.
The effect of reading column counter also be control RAM read address (high address), its maximum be actual input d[6:0] value, whenever read a byte and circulate and add 1, promptly read column counter=read column counter+1, after counter reaches maximum D-1, reset to 0.
Go and read under the control of column counter to data read address reading, can realize 2 kinds at the read procedure that interweaves and read mode: sequential system reads with the convolution mode and reads.
Sequential system reads N the byte that is used for first group, reading linage-counter this moment all is 0 with the initial value of reading column counter, the sequential read process that interweaves is undertaken by row, whenever from RAM, read a byte, read the column counter value and add 1, run through D byte after, read linage-counter and add 1, read column counter and be reset to 0, run through up to N byte order.
Please refer to Fig. 2 and 3, with the 2nd write-read process is example, after writing the B20 byte of first RS code word, should read a byte, at this moment read column counter and read the initial value that linage-counter composes from the N*D counter to be zero, thereby to read the address be first row, first row, being about to B20 reads, it is constant to read linage-counter then, reads column counter and adds 1, and reading the address is the first row secondary series, thereby after writing B21, the data of reading are the B13 (simultaneously with reference to Fig. 2) that interweaved last time and write, and read column counter then and reset to 0, and this row runs through, read linage-counter and add 1, read the address and be updated to second row, first row, after writing B22, the data of reading are B21.The rest may be inferred, can know that first group of N byte of reading is followed successively by B20, B13, B21, B14, B22.
The convolution mode is used to read second group of N byte, the 3rd group of N byte ... up to N byte of D group, the convolution mode reads process and is also undertaken by row, reading linage-counter is determined by the N*D counter with the initial value of reading column counter, whenever from RAM, read a byte, read the column counter value and add 1, when Counter Value equals D-1, counter reset to 0, after running through delegation, read linage-counter and add 1.Since second group, the first byte that reads is relevant with the number of N.
As shown in Figure 3, when reading and reading second group of data the 2nd time, reading column counter is 1 from the initial value that the N*D counter obtains, and reading the initial value that linage-counter obtains from the N*D counter is 2, thereby from the third line secondary series, first byte of reading is B30, other byte of second group of N byte be fourth line (B23, B31), fifth line (B24, B32), thus finish the read procedure that once interweaves.
Byte of reading for the 1st time and the 2nd time and the position of reading have been shown among Fig. 3, have wherein read the B13-1 that reads at the first row secondary series for the 1st time and represent it is the 3rd byte and the 4th byte of previous code word of RS0 code word at the B14-1 that the second row secondary series is read.
Deinterleaving is the inverse process that interweaves, and when a continuous data flow was carried out deinterleaving, the byte number of supposing the RS code word was N (present embodiment N=5), and interleave depth is D (present embodiment D=2).The deinterleaving process of N*D byte is at first to read a byte at ram memory cell, writes a byte from ram memory cell then, then reads a byte again, writes a byte again, finishes up to N*D byte read-write.By control to reading, writing address, finish the reconfiguring of the postbyte that interweaves, restore the code word before to interweave.The beat of read-write is controlled by clock signal clk, reads or writes then the signal controlling by read-write control line.
Fig. 3 then shows the secondary deinterleaving of present embodiment and writes process, and what write is the multi-group data of the N byte after interweaving.Fig. 2 shows the secondary deinterleaving read procedure of present embodiment.Read code word RS0 and RS1 the 1st time, read code word RS2 and RS3, code word is restored for the 2nd time.
The device among Fig. 1 is still used in the present embodiment deinterleaving, in the working method of each hardware:
The working method of N*D counter and identical when interweaving, the initial value of composing for each counter according to the first byte index signal is also identical with the division to ram memory cell, does not repeat them here.
The compound mode of ram memory cell read/write address is identical when interweaving, and remains and read row, writes the low level of linage-counter value control reading, writing address, reads to be listed as, to write the high position of column counter value control reading, writing address.But in the deinterleaving process, be when input Refresh Data index signal is effective, to read a byte earlier, and produce dateout refresh pulse index signal, and then write a byte, so circulation.
Reading linage-counter, read column counter and reading then writing linage-counter, write column counter and writing mode is corresponding when interweaving respectively of mode during deinterleaving.Wherein, read linage-counter and finish circulation according to input Refresh Data index signal and add 1, maximum is N-1, when counting reaches maximum, resets to 0.Read the column counter value and be used to control the high position that RAM reads the address, directly obtain by N*D counter low-order bit according to the first byte index signal.In the read procedure of deinterleaving, adopt sequential system when reading first RS code word, undertaken by row, the initial value of read row, reading column counter all zero, run through N byte after column counter add 1.From Fig. 2, read first leu in the 1st read procedure and obtain B00～B04, recover code word RS0.The convolution mode writes other code words that are used for except that first, the convolution read procedure also is to be undertaken by row, the initial value of reading the address is determined by the N*D counter, whenever read a byte, linage-counter adds 1, when reaching maximum N-1, be reset to zero, restart counting, after running through N byte, column counter adds 1 when initialize.B10 from the third line secondary series among Fig. 2 reads, and reads B11, B12, B13 and B14 successively, recovers code word RS1.
During deinterleaving write linage-counter, write column counter and writing mode respectively when interweaving read linage-counter, read column counter and read mode corresponding.Wherein, write linage-counter after having write 1 row, finish circulation and add 1.Writing the column counter maximum is D-1, whenever writes a byte circulation and adds 1, when counter reaches maximum, resets to 0, again counting.Writing in the process of deinterleaving, adopt sequential system when writing first group of N byte, undertaken by row, write the initial value of going, write column counter and be zero, whenever write a byte, write the column counter value and add 1, after having write D byte, write linage-counter and add 1, up to N byte order write.Write the 2nd group and reach employing convolution mode when respectively organizing byte later, also undertaken by row, writing linage-counter is determined by the N*D counter with the initial value of writing column counter, whenever write a byte, write the column counter value and add 1, when Counter Value equals D-1, reset to 0 and count again, after having write delegation, write linage-counter and add 1.Since second group, the first byte that writes is relevant with the value of N, and second group of first byte is to begin to write from the third line secondary series among Fig. 3, as B10, B30.
Please refer to Fig. 2 and 3, read for the 1st of deinterleaving the time among the figure to intersect and carry out, carry out read operation earlier with the process of writing for the 2nd time, write result's first row, first row from the 1st time and read B00, carry out write operation then, write B20 at first row, first row, according to above-mentioned read-write rule, be to read B01 successively, write B13, read B02, write B21, read B03, write B14, read B04, write B22, at this moment, begin read-write, from the third line secondary series to second group of N byte data, because B30 does not write, that read is B10, writes B30 in this position then, read B11 more successively, write B23, read B12, write B31, read B13 (top write), write B24, read B14, write B32.That read as can be seen, is two code word RS0 and RS1 before interweaving.
Claims (6)
1, the implement device of convolutional interleave and deinterleaving in a kind of ADSL (Asymmetric Digital Subscriber Line) comprises storage control circuit and memory cell, it is characterized in that:
The input signal of described storage control circuit comprises first byte index signal, input data signal, input Refresh Data index signal and clock signal; Described storage control circuit comprises address signal, write data signal and read-write control signal with the signal that is connected between described memory cell, and the output signal of described memory cell comprises outputting data signals and dateout refresh instructing signal;
Described storage control circuit comprises address generating device, and described storage control circuit is used in described memory cell writing a byte earlier according to described input Refresh Data indication when interweaving, and reads a byte then; When deinterleaving, then earlier read a byte, write a byte then in described memory cell; Address generating device wherein is used for interweaving or the generation of address is write, read in deinterleaving time control, realizes writing in a sequential manner and reading first code word, writes and read remaining code word in the convolution mode.
2, implement device as claimed in claim 1, it is characterized in that, described address generating device comprise N*D counter, amalgamation generate write address write linage-counter and write column counter, amalgamation generates and reads reading linage-counter and reading column counter of address, described memory cell is divided into the capable D row of N according to byte quantity parameter N and interleave depth parameter D, wherein:
The initial value of described N*D counter is 0, and maximum is the product of N and D, D=2
mWhen described first byte index signal is effective, the low m position of this counter composed to described as initial value write row and read column counter, this counter is removed a high position remaining behind the m position to be composed to described as initial value and writes row and read linage-counter, and finish circulation and add N, reset when being added to maximum, again counting;
The described column counter of writing determines its output valve by the initial value of giving when interweaving; When deinterleaving, whenever write a byte, count value circulation adds 1, reach maximum D-1 after, be reset to 0 counting again;
The described linage-counter of writing whenever writes a byte when interweaving, count value circulation adds 1, reach maximum N-1 after, be reset to 0 counting again; When deinterleaving, whenever write delegation, count value adds 1;
The described column counter of reading whenever reads a byte when interweaving, count value circulation adds 1, reach maximum D-1 after, be reset to 0 counting again; When deinterleaving, determine its output valve by the initial value of giving;
The described linage-counter of reading whenever runs through delegation when interweaving, count value adds 1; When deinterleaving, whenever read a byte, count value circulation adds 1, reach maximum N-1 after, be reset to 0 counting again.
3, implement device as claimed in claim 2 is characterized in that, the described value of writing row and reading linage-counter is the low level as described address signal, and the described value of writing row and reading column counter is the high position as described address signal.
4, implement device as claimed in claim 1 is characterized in that, described memory cell realizes with the random asccess memory of single port.
5, implement device as claimed in claim 4 is characterized in that, described storage control circuit also comprises clock signal with the signal that is connected between the single port random asccess memory, and described single port random asccess memory is the 8 bit synchronous random asccess memory that have clock signal.
6, implement device as claimed in claim 2 is characterized in that, described byte quantity parameter N and interleave depth parameter D are provided by the signal of importing storage control circuit.
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| GB2497154B (en) | 2012-08-30 | 2013-10-16 | Imagination Tech Ltd | Tile based interleaving and de-interleaving for digital signal processing |
| CN107766284B (en) * | 2017-09-11 | 2021-09-07 | 中国航空工业集团公司洛阳电光设备研究所 | Flow statistics method and chip based on off-chip cache |
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