CN100512322C - A system and method for providing multiple network interfaces with MAC address on processor - Google Patents
A system and method for providing multiple network interfaces with MAC address on processor Download PDFInfo
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- CN100512322C CN100512322C CNB2004100151436A CN200410015143A CN100512322C CN 100512322 C CN100512322 C CN 100512322C CN B2004100151436 A CNB2004100151436 A CN B2004100151436A CN 200410015143 A CN200410015143 A CN 200410015143A CN 100512322 C CN100512322 C CN 100512322C
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Abstract
The invention discloses a system and method for providing a plurality of MAC address network ports by one processor, wherein the system includes an embedded high rate interface high-performance processor, which is connected to at least an external Ethernet interchange chip through a back-to-back mode, the Ethernet interchange chip possesses a plurality of Ethernet network ports, and a multiple MAC program module operating on the high-performance processor.
Description
Technical field
The present invention relates to the data communication field, relate in particular to by processor a plurality of system and methods with network interface of independent MAC Address are provided.
Background technology
Having in the communication field in modern times needs to hang up a plurality of Ethernet interfaces with high performance processor and handles and be used for the packet that call control protocol is handled in many occasions (such as soft switch), or is used for the master board of certain communication system.
In this applied environment of mentioning in the above, the correlation technique of available technology adopting generally is with a high performance processor, as 7410 etc. of run quickly 3 series or the motorola of intel, connect a north bridge chips, connect the Ethernet chip of band pci bus then by the pci bus on this north bridge chips, as 82559 of intel, system just offers the needed Ethernet interface of applied environment by these Ethernet chip that hang on this pci bus.Certainly, it is not to hang Ethernet chip by pci bus that some other implementation method is also arranged, but no matter these systems use is MAC (the media access control what bus connects Ethernet, ethernet controller) chip, having any to determine, is exactly that this system needs several network interfaces just must be with the several MAC controller.
There are some defectives and deficiency in the above in the implementation method of these prior aries.Hanging mac controller with pci bus is example, at first be exactly that to hang over the efficient of these network interfaces (each network interface has a mac controller) on this pci bus not high, because this pci bus is usually operated at 33MHz, it is the barrier that the PCI network interface card is communicated by letter with the bridge sheet, a large amount of time has all been expended on pci data is moved, and causes the CPU treatment effeciency obviously to reduce.Be exactly generally to consider the reliability of communication apparatus than higher cost in addition, the Ethernet chip of hanging on pci bus often costs an arm and a leg, and the cost of system is just very high when a plurality of such chip of needs.
Therefore, obviously there is defective in the prior art, and awaits improving and development.
Summary of the invention
Purpose of the present invention is exactly in order to overcome above-mentioned defective of the prior art, provide a kind of processor that a plurality of system and methods that the network interface of MAC Address is arranged are provided, cooperate many MAC program module that a plurality of network interfaces with independent MAC Address are provided by Ethernet switching chip, solve the several network interfaces of needs that exist in the prior art and just must be with the problem of several MAC controller, replace a plurality of mac controllers with ethernet controller, make system have Multi-netmouth disposal ability at a high speed at the economize on hardware cost with when reducing complexity.
Technical scheme of the present invention is:
A kind of processor provides a plurality of systems that the network interface of MAC Address is arranged, it comprises the high-performance processor of an embedded external high-speed interface, by the external at least one Ethernet switching chip of mode of its external high-speed interface butt joint, this Ethernet switching chip has a plurality of Ethernet network interfaces; And the program module of MAC more than, operate on the described high-performance processor; Described Ethernet network interface in the system is arranged to an aggregation of links group with the port that described Ethernet switching chip is connected with described high-performance processor; Described many MAC program module loads the IP agreement to described high-performance processor; Described many MAC program module is that described high-performance processor is provided with a plurality of independently MAC Address and IP address; The interface of described Ethernet switching chip and described high speed processor utilizes the source of the hash value record packet of former MAC Address.
Described system, wherein, described Ethernet switching chip receives and transmits from processor and outside packet under described many MAC program module control, and its each Ethernet interface has oneself MAC Address and IP address.
Described system, wherein, it is the above high speed processor of 600MHz that described high-performance processor adopts dominant frequency.
Described system, wherein, described Ethernet network interface is the 10/100M network interface.
A kind of processor as claimed in claim 1 provides a plurality of methods that the network interface of MAC Address is arranged, and it may further comprise the steps:
A) the described Ethernet switching chip of described many MAC program module initialization, and enable the needed a plurality of Ethernet network interfaces of described system applies;
B) described many MAC program module is provided with the aggregation of links function of described Ethernet switching chip, and the described Ethernet network interface in the described system is arranged to an aggregation of links group with the port that described Ethernet switching chip is connected with described high-performance processor;
C) described many MAC program module loads the IP agreement to described high-performance processor;
D) described many MAC program module is that described high-performance processor is provided with a plurality of independently MAC Address and IP address;
E) described system begins to receive and dispatch the packet of many MAC Address.
A kind of processor provided by the present invention provides a plurality of system and methods that the network interface of MAC Address is arranged, compared with prior art, because system and method for the present invention has adopted with Ethernet switching chip and has cooperated many MAC program module that a plurality of network interfaces with independent MAC Address are provided, saved the hardware cost of system, reduce the complexity of system, and improved the efficient of system handles packet.
Description of drawings
Fig. 1 is the functional block diagram of each included part of system of the present invention;
Fig. 2 is the method step figure that system described in the method for the present invention is provided with many MAC Address.
Embodiment
To the specific embodiment of technical scheme of the present invention be described in further detail below in conjunction with accompanying drawing:
A kind of processor of the present invention provides a plurality of system and methods that the network interface of MAC Address is arranged, particularly in communication field, need to come the packet of a plurality of 100M Ethernet network interfaces is carried out in the applied environment of high speed processing with the high performance processor of (usually above 600MHz) about dominant frequency 1G, it has adopted the high-performance processor of embedded external high-speed interface to dock (as butt joint back-to-back by its external high-speed interface, interconnection etc.) mode is circumscribed with at least one Ethernet switching chip, as shown in Figure 1, utilize the program module of MAC more than to operate on the described high-performance processor, make a plurality of 100M Ethernet network interfaces of this Ethernet switching chip all have independent MAC Address.Compare with existing technical scheme, because the data/address bus bit wide that high-speed interface that high-performance processor is embedded and the interface between the CPU core adopt is very wide, high energy reaches 256, frequency can reach half of CPU core, when CPU frequency is 500M, its bandwidth is 60 times of pci bus bandwidth of 32 33MHZ, the bag of the 100M Ethernet network interface of described Ethernet switching chip is transmitted and is finished by hardware simultaneously, and therefore the network interface efficient of the described Ethernet switching chip of plug-in 100M is far above common PCI network interface card.
Described many MAC of usefulness program module of the present invention makes described high-performance processor mainly consist of the following components by the system that described Ethernet switching chip hangs up a plurality of network interfaces with independent MAC Address: one: be the high-performance processor that the high speed mating interface can externally be provided; Two: be to dock with the high speed external interface of described high-performance processor, and have an Ethernet switching chip of a plurality of 100M Ethernet network interfaces, described Ethernet network interface can be integrated 100M PHY (ethernet transceiver of physical layer), also can not have integrated 100M PHY.The external interface of described high-performance processor is docked with the high-speed interface of described Ethernet switching chip; Three: also need described many MAC program module of moving on described high-performance processor, the part block diagram of system of the present invention as shown in Figure 1.
Described high-performance processor mainly is to be used for handling the packet that needs CPU to handle; Described Ethernet switching chip is used for externally providing uses required 100M Ethernet interface, carries out the reception and the forwarding of packet by it between described high-performance processor and outside.Because described Ethernet switching chip is just done the work that bag is transmitted, its 100M Ethernet interface is not to be with MAC Address, also do not have independent IP address, so the described system of the present invention design also must come to be provided with for these Ethernet interfaces on the described Ethernet switching chip oneself MAC Address and IP address by described many MAC program module.
Below describe a preferred embodiment of system of the present invention in detail:
Described system of the present invention can adopt GMII (Gabit ethernet controller interface) interface that described high-performance processor and described Ethernet switching chip are coupled together.Native system comprises an integrated high-performance processor of gmii interface; A band gmii interface and a plurality of 100M Ethernet network interface, described 100M Ethernet network interface is integrated 100M PHY (ethernet transceiver of physical layer).The gmii interface of described high-performance processor and the GMII of described Ethernet switching chip are done interconnection (both sides all need not hang PHY), and following tabular goes out their annexation:
| Gmii interface holding wire on the processor (network interface E0) | The holding wire (network interface E1) of the gmii interface of the corresponding exchange chip that connects |
| E0_TX0 -E0_TX7 | E1_RX0 -E1_RX7 |
| E0_RX0 -E0_RX7 | E1_DX0 -E1_DX7 |
| E0_TXEN | E1_RXDV |
| E0_RXDV | E1_TXEN |
| E0_TXER | E1_RXER |
| E0_RXER | E1_TXER |
| E0_TCLKO | E1_RCLK |
| E0_RCLK | E1_TCLKO |
Table 1
What list above is the hardware components of present embodiment, and the software section of system of the present invention correspondence is described many MAC program module.
The principle that described many MAC program module realizes is ingeniously to utilize described Ethernet switching chip based on trunking (aggregation of links/relaying) the characteristics design of MAC Address.Common 2 layers of exchange chip have the trunking function based on port or MAC Address, the gmii interface of described Ethernet switching chip and a plurality of 100M Ethernet network interface are set to a trunking group, utilize the trunking function of described Ethernet switching chip, the packet that described high-performance processor sends over by described gmii interface, after entering the gmii interface of described Ethernet switching chip, the gmii interface of this Ethernet switching chip can calculate the HASH value (utilizing Hash hash algorithm) of the former MAC Address of this packet, according to the difference of this HASH value, described Ethernet switching chip can be forwarded to this packet a certain fixedly 100M Ethernet network interface (quite this network interface has specific MAC Address) of trunking group; The packet of coming in from a certain 100M Ethernet network interface of this trunking group simultaneously all can be forwarded to the gmii interface of this Ethernet switching chip, so the gmii interface of described high-performance processor just can the transceive data bag.
Utilize this many MAC program module as driver module, the gmii interface of described high-performance processor is set to have a plurality of MAC Address and IP address, these MAC Address have different HASH values, so packet that sends of described high-performance processor, can have different former MAC Address, because the difference of its MAC Address, described Ethernet switching chip will be forwarded to the corresponding data bag a certain fixedly 100M Ethernet network interface, the packet of coming in simultaneously from these 100M Ethernet network interfaces, the capital enters the gmii interface of described high-performance processor, through such setting, these 100M Ethernet network interfaces of described Ethernet switching chip, just can receive and dispatch the packet of a plurality of particular mac address, as if had oneself independently MAC Address and IP address, it seems that from the outside described high-performance processor has just had a plurality of independently 100M Ethernet network interfaces.
Specifically, described high-performance processor can adopt BCM1125H (a MIPS processor of Broadcom company), described Ethernet switching chip can adopt BCM5382 (a Ethernet switching chip of Broadcom company).Described BCM1125H chip is embedded 2 gmii interfaces, the present invention only uses a GMIIO interface since BCM1125H embedded the DDR sdram controller, so system of the present invention does not need external other bridge sheet again; Described BCM5382 also has been with a gmii interface, and BCM5382 also has 8 integrated 10/100M Ethernet network interfaces of PHY in addition.
According to technical manual explanation, the corresponding gmii interface of described BCM1125H and described BCM5382 is cross interconnected, and couple together according to the gmii interface correspondence of table 1 with them.Described BCM5382 has 8 10/100M Ethernet network interfaces to use, and can determine the number of drawing as required.
Realization high-performance processor of the present invention is by a plurality of systems that the Ethernet network interface of independent MAC Address is arranged of described Ethernet switching chip band, and the actuation step of its many MAC program module is as follows:
A) want the described Ethernet switching chip of initialization before this, and enabled systems is used needed a plurality of 10/100M Ethernet network interface
B) the trunking function of described Ethernet switching chip being set, is that the gmii interface of the BCM5382 in the foregoing description is arranged to a trunking group with all 10/100M Ethernet network interfaces in the system and port that this Ethernet switching chip is connected with described high-performance processor;
C) described high-performance processor is loaded the IP agreement
D) for described high-performance processor a plurality of independently MAC Address and IP address are set, described system need externally provide several Ethernet interfaces just several IP address and MAC Address need be set
E) begin many MAC of circulation transmitting-receiving packet at last.
The specific implementation step of 4 network interfaces below is described, the Multi-netmouth performing step is similar with it
1-enables 4 10/100M Ethernet network interfaces of described Ethernet switching chip BCM5382;
2-is arranged to a trunking group with the gmii interface of these 4 10/100M Ethernet network interfaces and described BCM5382;
3-is provided with the trunking function of described Ethernet switching chip based on MAC Address;
4-is provided with the trunking function of described Ethernet switching chip based on former MAC Address hash value;
5-finds out the MAC Address with 4 different hash values according to the hash algorithm;
6-drives the gmii interface of the correspondence connection of described BCM1125H;
7-is provided with 4 MAC Address and the IP address of the gmii interface of described BCM1125H, and this MAC Address is determined according to above-mentioned different hash values with the IP address;
This moment, described BCM1125H just had 4 10/100M Ethernet network interfaces.
Listed the different trunking group of 4 Ethernet network interfaces of described Ethernet switching chip below, based on the relation between former MAC Address hash value and the forwarding Ethernet network interface:
| The hash value of former MAC Address | The Ethernet network interface of different relaying groups |
| 0x00 -0x3f | First network interface (1 st) |
| 0x40 -0x7f | Second network interface (2 nd) |
| 0x80 -0xbf | The 3rd network interface (3 rd) |
| 0xc0 -0xff | The 4th network interface (4 th) |
Table 2
The hash value that the described Ethernet switching chip of system of the present invention needs only former MAC Address is calculated and is 0x00
-Between the 0x3f, just this packet is transmitted first network interface to described BCM5382, other network interface is judgment processing successively.In the present embodiment, 4 set MAC Address are respectively { 0x00; 0x02; 0x4c; 0xfd; 0x08; 0x2d }, { 0x00; 0x02; 0x4c; 0xfd; 0x08; 0x2c }, { 0x00; 0x02; 0x4c; 0xfd; 0x08; 0x2e }, { 0x00; 0x02; 0x4c; 0xfd; 0x08; 0x2f }, it satisfies the relation between above hash value and the forwarding network interface, utilizes above the setting, just can easily realize 4 100M Ethernet network interfaces of described BCM1125H; Profit uses the same method, and more network interface can be set.In system of the present invention, utilize real time operating system, adopted the C Programming with Pascal Language.
In sum, because the present invention has adopted Ethernet switching chip that the Ethernet interface of a plurality of band MAC Address is provided, therefore improved the efficient of transmitting-receiving bag, processor can better be handled to be needed the communications protocol of its processing (such as calling out control) and has improved overall system efficiency; Simultaneously owing to not be used in plug-in a plurality of mac controller, also provide cost savings and reduced complexity.
Should be understood that, be very detailed for the description of above-mentioned specific embodiment of the present invention, and the concrete feature of foregoing description can not be understood that the qualification to protection scope of the present invention, the determining and should be as the criterion with appended claims of the present invention of protection range.
Claims (5)
1, a kind of processor provides a plurality of systems that the network interface of MAC Address is arranged, it comprises the high-performance processor of an embedded external high-speed interface, by the external at least one Ethernet switching chip of mode of its external high-speed interface butt joint, this Ethernet switching chip has a plurality of Ethernet network interfaces; And the program module of MAC more than, operate on the described high-performance processor; Described Ethernet network interface in the system is arranged to an aggregation of links group with the port that described Ethernet switching chip is connected with described high-performance processor; Described many MAC program module loads the IP agreement to described high-performance processor; Described many MAC program module is that described high-performance processor is provided with a plurality of independently MAC Address and IP address; The interface of described Ethernet switching chip and described high speed processor utilizes the source of the hash value record packet of former MAC Address.
2, system according to claim 1, it is characterized in that, described Ethernet switching chip receives and transmits from processor and outside packet under described many MAC program module control, and its each Ethernet interface has oneself MAC Address and IP address.
3, system according to claim 2 is characterized in that, described high-performance processor adopts the above high speed processor of dominant frequency 600MHz.
4, system according to claim 3 is characterized in that, described Ethernet network interface is the 10/100M network interface.
5, a kind of processor as claimed in claim 1 provides a plurality of methods that the network interface of MAC Address is arranged, and it may further comprise the steps:
A) the described Ethernet switching chip of described many MAC program module initialization, and enable the needed a plurality of Ethernet network interfaces of described system applies;
B) described many MAC program module is provided with the aggregation of links function of described Ethernet switching chip, and the described Ethernet network interface in the described system is arranged to an aggregation of links group with the port that described Ethernet switching chip is connected with described high-performance processor;
C) described many MAC program module loads the IP agreement to described high-performance processor;
D) described many MAC program module is that described high-performance processor is provided with a plurality of independently MAC Address and IP address;
E) described system begins to receive and dispatch the packet of many MAC Address.
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| CNB2004100151436A CN100512322C (en) | 2004-01-15 | 2004-01-15 | A system and method for providing multiple network interfaces with MAC address on processor |
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| CNB2004100151436A CN100512322C (en) | 2004-01-15 | 2004-01-15 | A system and method for providing multiple network interfaces with MAC address on processor |
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| CN100512322C true CN100512322C (en) | 2009-07-08 |
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7545773B2 (en) * | 2005-06-29 | 2009-06-09 | Intel Corporation | Multiple media access control apparatus and methods |
| CN101436901B (en) * | 2008-12-05 | 2011-06-22 | 中兴通讯股份有限公司 | Apparatus and method for managing OLT chip of EPON by Ethernet |
| CN101741664A (en) * | 2009-12-21 | 2010-06-16 | 中兴通讯股份有限公司 | Method and device for realizing Ethernet interface system |
| CN103686079B (en) * | 2013-12-05 | 2017-07-14 | 浙江宇视科技有限公司 | A kind of terminal device |
| CN106209691B (en) * | 2016-07-18 | 2019-05-17 | 南京磐能电力科技股份有限公司 | A kind of network port mirror method having independent mac source address |
| CN109254932B (en) * | 2018-09-18 | 2020-09-18 | 北京无线电测量研究所 | Multi-network-port driving method, device and storage medium |
| CN116781671A (en) * | 2020-12-10 | 2023-09-19 | 福州创实讯联信息技术有限公司 | Multi-network port initialization method and terminal for embedded equipment |
| CN113055313B (en) * | 2021-03-17 | 2022-04-22 | 南方电网科学研究院有限责任公司 | Method and device for network port expansion, electronic equipment and storage medium |
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