CN100510757C

CN100510757C - Over-voltage indication circuit and system circuit and method

Info

Publication number: CN100510757C
Application number: CNB2007101042069A
Authority: CN
Inventors: 熊玟清; 张正道; 赖佳良; 陈冠宇
Original assignee: Faraday Technology Corp
Current assignee: Faraday Technology Corp
Priority date: 2007-05-23
Filing date: 2007-05-23
Publication date: 2009-07-08
Anticipated expiration: 2027-05-23
Also published as: CN101051062A

Abstract

An over-voltage indication circuit is prepared for setting over-voltage indication circuit in signal I/O interface circuit for detecting out whether over-voltage event is occurred on port of I/O interface or not and providing a corresponding indication signal according to detected result. Its method for handing over-voltage is also disclosed.

Description

Overvoltage indicating circuit and circuit system and method

Technical field

The present invention relates to overvoltage indicating circuit and circuit system and method, relate in particular to and to repeat to detect/suspend detecting overvoltage situation at the over-voltage events period and can provide corresponding logic overvoltage indicator signal during over-voltage events, to activate overvoltage indicating circuit and the circuit system and the method for suitable protection process.

Background technology

In modern society, circuit systems such as chip, integrated circuit, system single chip have become one of most important information construction hardware foundation.In general, have the core circuit of main control chip operation and the interface circuit that is used as the signal import and export in the chip.Core circuit can be realized the major function of chip, such as carrying out logical operation, signal Processing/conversion, coding/decoding and storage or the like.Interface circuit then can carry out the exchange of electronic signal with extraneous other circuit via pin of chip, I/o pad; Input, output signal during the core circuit operation are just transmitted by interface circuit.Because I/o pad/pin that interface circuit is direct and chip is external is connected, so the change of electric circumstance also will have certain ability to bear to external world.

Please refer to Fig. 1.Fig. 1 is that a known interface circuit 10 is disposed at the situation among the circuit system S0.Circuit system S0 can be a chip, and 12 of internal circuits can be the core circuit of this chip or the predriver (pre-driver) of signal output.Then can be provided with the buffer circuit 18 that signal drives in the interface circuit 10.This buffer circuit 18 is arranged between an internal circuit 12 and the interface port I/O, and this interface port I/O is exactly the I/o pad (pin) of chip.Internal circuit 12 will export the outer signal of chip to and can import into to interface circuit 10 by input signal IP, IN (two signals be generally differential to).And the buffer circuit 18 in the interface circuit 10 just can drive corresponding output signal DP according to input signal IP, IN on interface port I/O, and it is outer so just the signal of internal circuit 12 to be exported to chip.

But, because interface port I/O is connected directly to chip exterior (such as printed circuit board (PCB) or other chip or the like), so the signal level on the interface port I/O is subjected to the influence of extraneous electric circumstance easily.Such as, over-voltage events may take place on the interface port I/O, that is to say that the voltage on the interface port I/O raises because of factors such as extraneous short circuits undesiredly, even be higher than the Dc bias voltage of interface circuit 12 itself.In order to tackle the generation of overvoltage situation, alleviate the influence of over-voltage events, be provided with a storehouse transistor Mc in the buffer circuit 18 in addition, also be provided with a n trap in the interface circuit 10 in addition and draw high a circuit 16 and a grid tracking circuit 14, as the overvoltage protective device.Wherein, the n trap draws high circuit 16 and is electrically connected on interface port I/O, and it can provide corresponding signal VNW and signal GT to deal with over-voltage events according to the voltage on the interface port I/O.Grid tracking circuit 14 is connected between internal circuit 12 and the buffer circuit 18, and it can control the conducting of 18 of internal circuit 12 and buffer circuits according to signal VNW/GT.

As shown in Figure 1, the buffer circuit 18 in the interface circuit 10, grid tracking circuit 14 and n trap draw high circuit 16 and all are biased between bias voltage VCCA (it can be a positive voltage) and the GNDA (terminal voltage).Be provided with two transistor Md1, Md2 and storehouse (stacked) transistor Mc in the buffer circuit 18; Transistor Md1, Md2 can come output signal DP on the driving interface port I/O according to input signal IP, IN, and storehouse transistor Mc then is located between transistor Md1, Md2.The base stage (body or bulk) that please notes transistor Md1 is come bias voltage by signal VNW.The n trap draws high and is provided with transistor Ma1-Ma3 in the circuit 16; Then form a transmission lock (transmission gate) in the grid tracking circuit 14, and be provided with transistor Mb3 in addition by transistor Mb1, Mb2.Please note that the base stage of transistor Mb2 and the source electrode of transistor Mb3 also come bias voltage by signal VNW.Because transistor Md1, Mb2 and Mb3 are p type MOS (metal-oxide-semiconductor) transistor, so its base stage is to be formed by n type trap, all come bias voltage with signal VNW too.

When the action of (when just over-voltage events does not take place) when normally moving of internal circuit 12, interface circuit 10 can be described below.When normal operation, signal level on the interface port I/O should change between bias voltage VCCA and GNDA, so draw high in the circuit 16 at the n trap, grid bias is in transistor Ma2, the not conductings of Ma3 of VCCA, signal GT is maintained at low level (near the level of bias voltage GNDA), and make transistor Ma1 conducting, allow signal VNW be maintained at high level (near the level of bias voltage VCCA).In grid tracking circuit 14, the voltage of node Np1 should also change between bias voltage VCCA and GNDA, so grid bias can conducting in the transistor Mb3 of bias voltage VCCA, transistor Mb1 conducting, transistor Mb2 is also because of low level signal GT conducting, therefore be conducting between the node Np2 to Np1, allow the signal IP of internal circuit 12 directly transfer to buffer circuit 18, normally carry out signal output via grid tracking circuit 14.

On the other hand, when interface port I/O went up generation overvoltage situation, the operation situation of interface circuit 10 then can be described below.When over-voltage events took place, the level on the interface port I/O can raise above bias voltage VCCA; Such as bias voltage VCCA is 3.3V, and the voltage on the interface port I/O is elevated to 5V because of change all factors such as (such as short circuits) of extraneous electric circumstance, will cause the generation of overvoltage like this.When overvoltage takes place, because can rising, the level (level of signals DP just) on the interface port I/O surpasses bias voltage VCCA, so transistor Ma2, Ma3 that the n trap draws high in the circuit 16 can begin conducting.The transistor Ma3 of conducting can draw high the level of signal GT to approach signal DP, and makes not conducting of transistor Ma1.Similarly, the transistor Ma2 of conducting can draw high the level of signal VNW to approach signal DP.

In buffer circuit 18, the level of the base stage of transistor Md1 and node Np3 is the voltage level excessively of approach signal DP all, so transistor Md1 closes not conducting.Transistor Mc conducting, and the level that makes node Np4 is about VCCA-Vth_Mc (wherein Vth_Mc is the threshold voltage of transistor Mc), therefore storehouse transistor Mc can make overvoltage can directly not damage transistor Md2 by node Np4 with the overvoltage reduction of node Np3 when overvoltage takes place.

In grid tracking circuit 14, the source level by signal VNW bias voltage in the transistor Mb3 can surpass bias voltage VCCA with overvoltage, so transistor Mb3 conducting with the level raising of node Np1, makes the voltage level of crossing of its approach signal DP.Node Np1 goes up the overvoltage that surpasses bias voltage VCCA also can make transistor Mb1 close and not conducting.On transistor Mb2, also because all overvoltages and transistor Mb2 is closed of the level of node Np1, grid (by signal GT bias voltage) and base stage (by signal VNW bias voltage).Thus, just can stop the overvoltage transmission to injure internal circuit 12 via node Np2.

But, known interface circuit 10 also has shortcoming among Fig. 1 when carrying out the overvoltage protection.For instance, when the overvoltage incident took place, transistor Mb2 had the impaired doubt of reliability (reliability).Just as above-mentioned discussion, when the overvoltage incident takes place, transistor Mb2 at the level of node Np1, grid and base stage all with overvoltage so that transistor Mb2 close.Yet if this moment, internal circuit 12 just in time was low level signal toward the signal IP that node Np2 sends, the gate oxide of transistor Mb2 will bear the huge pressure reduction between low level node Np2 and overvoltage signal GT.This overvoltage pressure reduction very easily injures transistor Mb2 and destroys its reliability usually very near the gate oxide disruptive voltage of transistor Mb2.And the doubt of this kind reliability has also highlighted another shortcoming of known technology: known overvoltage guard technology can't make internal circuit 12 can't tackle over-voltage events to the generation of internal circuit 12 announcement over-voltage events.

Summary of the invention

Purpose of the present invention at the defective of only carrying out the overvoltage protection in the above-mentioned known technology in interface circuit, provides a kind of overvoltage indicating circuit, interlock circuit/circuit system and method exactly; By an overvoltage indicating circuit is set in the interface circuit of chip/circuit system, to provide an indicator signal (such as being a logic indicator signal) according to over-voltage events.This indicator signal can be fed back to the core circuit of chip/circuit system, the overvoltage protection process that core circuit can be correlated with when overvoltage takes place, such as be that its signal that exports interface circuit to is maintained at a safety level, in order to avoid destroy the transmission lock grid of grid tracking circuit in the interface circuit.

To achieve these goals, the invention provides a kind of overvoltage indicating circuit, it provides an indicator signal with the signal level size on the reflection interface port; This overvoltage indicating circuit includes: a comparer, be connected between this interface port and the sampling end, this comparer relatively the signal level on this interface port whether greater than a default conduction level; If then this comparer is held this interface port conducting to this sampling; If not, this comparer stops the conducting between this interface port and this sampling end; One switch is connected between a sense terminal and this sampling end; When this switch activator, this switch should be taken a sample the end conducting to this sense terminal; When this switch cut out, this switch stopped the conducting between this sampling end and this sense terminal; One timer, it provides a timing signal; When this timer was triggered, this timer began to carry out timing, and utilized the signal level reflection timing of this timing signal to finish after timing one preset period of time; One detector is connected to this sense terminal, and whether its signal level of detecting on this sense terminal surmounts a preset standard; If then this detector triggers this timer and picks up counting; If not, then this detector does not trigger this timer timing; One keyholed back plate circuit is connected between this timer, this detector and this switch; When this detector detects signal level reflection timing that signal level on this sense terminal do not surmount this preset standard or this timing signal when finishing, this keyholed back plate circuit makes this switch activator; Otherwise this keyholed back plate circuit is closed this switch; One trigger circuit, it provides a trigger pip according to the signal level on the detecting result of detector and the sampling end; And one fasten lock circuit, is connected in this sampling end; This is fastened lock circuit and produces this indicator signal according to the triggering of this trigger pip.Also can include: a load circuit is connected in this sense terminal; When this switch activator and during this comparer stop conducting, this load circuit makes the signal level on this sense terminal can not surmount this preset standard.That is to say, the invention provides a kind of overvoltage indicating circuit, it includes: a comparer, a switch, a timer, a detector, a keyholed back plate circuit, are fastened lock circuit, trigger circuit and a load circuit, to provide an indicator signal to reflect whether overvoltage take place on the interface port.Wherein, comparer is connected between an interface port and the sampling end, and whether comparer can compare signal level on the interface port greater than a default conduction level; If then comparer can be with the interface port conducting to the sampling end; If not, comparer just can conducting between interface port and sampling end.Switch then is connected between a sense terminal and the sampling end; When switch activator, can be with the conducting of sampling end to sense terminal; When switch cuts out, then can stop the conducting between this sampling end and this sense terminal.Timer then can provide a timing signal; When timer was triggered, timer can begin to carry out timing, and utilized the signal level reflection timing of timing signal to finish after timing one preset period of time.Detector is connected to sense terminal, and whether its signal level that can detect on the sense terminal surmounts a preset standard; If then detector can trigger this timer and picks up counting; If not, then detector can not trigger this timer timing.In addition, load circuit also is connected in sense terminal; When switch activator and during the comparer stop conducting, load circuit just can make the signal level on the sense terminal can not surmount this preset standard.The keyholed back plate circuit then is connected between timer, detector and the switch; Do not surmount this preset standard or timing signal reflection timing when finishing when detector detects signal level on the sense terminal, the keyholed back plate circuit can make switch activator; Otherwise the keyholed back plate circuit can make switch close.Trigger circuit then can provide a trigger pip according to the signal level conversion on the detecting result of detector and the sampling end.Fasten lock circuit and be connected in sampling end, it can be according to the triggering of trigger pip and to the sample of signal on the sampling end, to produce indicator signal; This fastens lock circuit and can be a trigger, so indicator signal can be a logic indicator signal.

Utilize above-mentioned each circuit, the present invention also provides a kind of and fastens the overvoltage indicating circuit that lock circuit forms by a comparison means, a detecting control and management device and.Whether comparison means can compare signal level on the interface port greater than a predeterminated voltage (VCCA+Vtp); If then comparison means can provide a logic high (logic high) level on the sampling end.The detecting control and management device can run on a detecting state and a time status; When the detecting control and management device runs on the detecting state, if the signal level on the interface port is then detected the changeable time status that runs on of control and management device greater than conduction level; Otherwise the detecting control and management device is sustainable to be run on the detecting state and provide a logic low (logic low) level on the sampling end; And when detecting control and management device when running on time status, the detecting control and management device can be after timing one preset period of time again switchover operation in the detecting state.Fastening lock circuit then can be triggered to the signal level sampling on the sampling end when detecting control and management device switch mode and adjust the level of indicator signal according to sampling result; And keep the level of indicator signal when fastening the lock circuit Shi Zeke that is not triggered.This comparison means can be realized that the detecting control and management device then can be realized by switch, timer, detector, keyholed back plate circuit and load circuit by aforesaid comparer.

When the detecting control and management device ran on the detecting state, switch conduction, the sense terminal of detector can be switched on the sampling end to comparer.In this case, if overvoltage does not take place interface port, comparer can conducting, and the load circuit of ground connection (such as being a resistance) will to make the sense terminal and the signal level of sampling end be low (this is above-mentioned logic low level); Detector detects the low level on the sense terminal, just can not the triggering timing device.Otherwise, if overvoltage takes place, comparer meeting conducting, switch together with conducting, interface port-mutual the conducting of sampling end-sense terminal meeting the signal level on the sampling end is raise (this is the logichigh level), and detector also can detect the high signal level on the sense terminal.At this moment, the detecting control and management device just moves to time status: detector can be closed switch via the keyholed back plate circuit on the one hand, then can pick up counting by the triggering timing device on the other hand.The switch of cutting out can end the conducting between interface port-sampling end-sense terminal, allows overvoltage be unlikely to damage each circuit system in the overvoltage circuit for detecting because of long conducting.Timer then can one section preset period of time of timing again via keyholed back plate circuit turn-on switch.When switch conduction, move back the detecting state in the equivalence of detecting control and management device again: the switch of conducting makes sampling end, sense terminal conducting.If this moment, over-voltage events also continued, the conducting of comparer and switch makes conducting between interface port-sampling end-sense terminal again, and detector detects high level signal once again, again off switch, reclocking once again once again.On the contrary, if over-voltage events finishes, comparator circuit can conducting, and detector only can detect low level signal, also just can not change the state of timer, switch.Trigger circuit are gone up signal level according to sampling end and are triggered with detector detecting result and fasten the sample of signal that lock circuit is held sampling, just can indicate the generation and the end of over-voltage events in indicator signal with the transformation of signal logic level.

The present invention also provides a kind of circuit system, and it includes:

One buffer circuit, it has an interface port; This buffer circuit drives the output signal of a correspondence on this interface port according to an input signal; One overvoltage indicating circuit, whether it presets the indicator signal that conduction level provides a correspondence greater than one according to the signal level on this interface port; And an internal circuit, be used to provide this input signal; And when this overvoltage indicating circuit indicated signal level on this interface port greater than this predetermined level, this internal circuit made this input signal be maintained at a safety level.Promptly be that above-mentioned overvoltage indicating circuit is arranged in the circuit system (as chip, integrated circuit), draw high circuit and the grid tracking circuit is realized a better overvoltage indication/protective device with internal circuit, buffer circuit, the n trap that cooperates chip.For instance, having served as end finger shows when on the circuit indication interface port overvoltage taking place, internal circuit just can carry out an overvoltage protection process, such as making the signal that inputs to the grid tracking circuit be maintained at a safety level (as high level), to avoid the grid reliability doubt in the grid tracking circuit.

Cooperate the above-mentioned circuit framework of the present invention, the present invention also provides a kind of method of carrying out the overvoltage indication with an overvoltage indicating circuit, this method includes: carry out state detecting, it includes: relatively whether overvoltage (over-voltage) of the signal level on this interface port; If the level that then makes this indicator signal is a logic high, and finishes this detecting state and proceed to a time status via this first loop; If not, then making the level of this indicator signal is a logic low, and is maintained at this detecting state; And this time status includes: finish this time status after timing one preset period of time and proceed to this detecting state via this second loop.This method is to switch between two states; Under a detecting state, relatively whether the signal level on the interface port is greater than (VCCA+Vtp); If the level that then makes indicator signal is a logic high level, and finishes the detecting state and proceed to a time status; If not, the level that then makes indicator signal is a logic low level, and lasting detecting state.Time status then is: finish time status after timing one preset period of time and proceed to the detecting state.This kind running status is switched the generation and the end that not only can suitably detect over-voltage events, also can prevent overvoltage damage overvoltage indicating circuit itself by switching.

The present invention also provides a kind of method that over-voltage events is handled of carrying out in circuit system (chip, integrated circuit).Whether the method includes: carry out overvoltage indication process, indicate over-voltage events to take place so that an indicator signal to be provided; This indicator signal is fed back to internal circuit; When indicator signal indication over-voltage events takes place, make internal circuit carry out a protection process to deal with over-voltage events.Example as the aforementioned just, internal circuit can make the signal that inputs to the grid tracking circuit be maintained at a safety level (as high level) during overvoltage, to avoid the grid reliability doubt in the grid tracking circuit.

By technique scheme, the present invention has following beneficial effect:

Can provide the overvoltage indicator signal to the internal circuit (core circuit) of chip/integrated circuit, make internal circuit carry out more perfect, more fully overvoltage protection, avoid the grid reliability doubt in the grid tracking circuit;

Intermittent during overvoltage, periodicity is detected the overvoltage situation, avoids the overvoltage injury overvoltage indicating circuit itself that continues;

Be easy to be integrated in the present interfaces circuit.

Description of drawings

Fig. 1 is the configuration of internal circuit/interface circuit and overvoltage protective device in the known technology;

Fig. 2 is the configuration of overvoltage indicating circuit of the present invention and internal circuit/interface circuit/overvoltage protective device;

The waveform sequential of coherent signal when Fig. 3 moves for Fig. 2 circuit;

Fig. 4 is the more detailed embodiment of circuit among Fig. 2;

Fig. 5 is the waveform sequential of each coherent signal when realizing timer among Fig. 2 with electrify restoration circuit.

Wherein, description of reference numerals is as follows:

10,20 interface circuits, 12,22 internal circuits

14,24 grid tracking circuits, 16,26 n traps draw high circuit

18,28 buffer circuits, 30 keyholed back plate circuit

32 auxiliary circuits, 36 overvoltage indicating circuits

38 trigger circuit S0, S1 circuit system

I/O interface port CLR clear terminal

TMR timer DFF fastens lock circuit

The DTR detector T period

R resistance IP-IN input signal

DP output signal L1, L3 rejection gate

L2, L4, L6 phase inverter N5VDO indicator signal

N0-N2, Np1-Np4 node DEO detection signal

POR power-on reset signal POR2 timing signal

T0-t15, ta-td be Vov, Vst level constantly

GT signal Tg trigger pip

L5 or door

POR3, N5V, SW, VNW, POR1 signal

Ma1-Ma3, Mb1-Mb3, Mc, Md1-Md2, Qa1-Qa3, Qb1-Qb3, Qc, Qd1-Qd2, Qe1-Qe3 transistor

VCCA, GNDA bias voltage

Embodiment

Please refer to Fig. 2; Fig. 2 is disposed at a kind of embodiment of a circuit system S1 (such as being an integrated circuit or a chip) for overvoltage indicating circuit 36 of the present invention.As shown in Figure 2, can be provided with an internal circuit 22 and an interface circuit 20 among the circuit system S1.Internal circuit 22 can be the core circuit of circuit system S1 or the predriver of signal output.Then can be provided with the buffer circuit 28 that a signal drives in the interface circuit 20.This buffer circuit 28 is arranged between an internal circuit 22 and the interface port I/O, and this interface port I/O then can be the I/o pad (pin) of chip/integrated circuit.Internal circuit 22 will export the outer signal of chip to can import interface circuit 20 into by input signal IP, IN (IP, IN two signals can be differential to).And the buffer circuit 28 in the interface circuit 20 just can drive corresponding output signal DP according to input signal IP, IN on interface port I/O, with the signal output with internal circuit 22.Each circuit in the interface circuit 20 can be biased between bias voltage VCCA (positive bias voltage) and the GNDA (terminal voltage).

As discussed earlier, when interface circuit 20 in when operation, over-voltage events may take place because of all accidents (as short circuit) in interface port I/O.And overvoltage indicating circuit 36 of the present invention just can be detected whether overvoltage of interface port I/O, and indicates the generation and the end of over-voltage events with an indicator signal N5VDO.In preferred embodiment of the present invention, this indicator signal N5VDO can be the logical signal (that is to say its logic high convergence bias voltage VCCA, logic low convergence voltage GNDA) of a standard.And this indicator signal N5VDO can feed back in the internal circuit 22; According to the indication of indicator signal N5VDO, internal circuit 22 just can be taked suitable protection process when over-voltage events takes place, the reply over-voltage events.

In the embodiment of Fig. 2, overvoltage indicating circuit 36 of the present invention can include: as the p type MOS (metal-oxide-semiconductor) transistor Qe1 of a comparer, as the n type MOS (metal-oxide-semiconductor) transistor Qe2 of a level adjusting circuit, as the n type MOS (metal-oxide-semiconductor) transistor Qe3 of a switch, fasten lock circuit DFF as the resistance R of load circuit and a timer TMR, a keyholed back plate circuit 30, a detector DTR, trigger circuit 38 and.Transistor Qe1, Qe2, Qe3 and resistance R are series between interface port I/O and the ground end bias voltage GNDA.Wherein, transistor Qe1 is connected in interface port I/O and node N0, and its grid bias is in bias voltage VCCA.When carrying out the output of normal signal on the interface port I/O, the signal level of interface port I/O should be between bias voltage VCCA and GNDA, so transistor Qe1 can conducting.Otherwise when overvoltage go up to take place interface port I/O, the signal level on the interface port I/O can rise above bias voltage VCCA, and makes the threshold voltage vt p of both pressure reduction greater than transistor Qe1, allowed transistor Qe1 conducting.In other words, transistor Qe1 can be used to be used as a comparer, it can compare the signal level of interface port I/O, and (this conduction level can be VCCA+Vtp greater than default conduction level, Vtp=|Vth_Qe1| wherein, and Vth_Qe1 is the threshold voltage of transistor Qe1), and come conducting or not conducting according to comparative result.

Served as that Hair Fixer is given birth to and during transistor Qe1 conducting, transistor Qe2 also can be with node N0 conducting to node N1.But, overvoltage can directly not transfer to node N1 by node N0, because transistor Qe2 can make the signal level of node N1 be approximately VCCA-Vth_Qe2 (Vth_Qe2 is the threshold voltage of transistor Qe2), make each circuit after overvoltage is unlikely to directly to be transferred to node N1, avoid the injury of overvoltage overvoltage indicating circuit 36.That is to say that this storehouse transistor Qe2 can realize a level adjusting circuit, can with after the crossing voltage level and suitably adjust on the interface port I/O just conducting to node N1.Signal on the node N1 is signal N5V.Transistor Qe3 is the conducting between may command node N1, N2 then, so can be considered a switch.

In the connecting of transistor Qe1-Qe2-Qe3 and resistance R, node N1 can be considered a sampling end, and node N2 then can be considered a sense terminal.Detector DTR just is connected in the node N2 as sense terminal, whether surmounts preset standard with the signal level (such as being voltage) on the detecting node N2, and will detect the result and be reflected in detection signal DEO.Timer TMR can pick up counting according to the triggering of signal DEO, finishes timing after the timing preset period of time; And the beginning of timing will be reflected in each timing signal POR2 and POR3 (in one embodiment of this invention, signal POR2 can be identical signal with POR3) with end.Keyholed back plate circuit 30 can realize that it can provide a signal SW according to detection signal DEO and timing signal POR2 with a rejection gate L1 and a phase inverter L2, and this signal SW with regard to the conducting of may command transistor Qe3 with close.38 available one of trigger circuit or door L5 and phase inverter L6 realize; It can produce trigger pip Tg according to the logic operation result of signal N5V and detection signal DEO.

On the other hand, fasten lock circuit DFF and be connected in node N1, coming sampling according to trigger pip Tg, and provide indicator signal N5VDO signal N5V as sampling end.This fastens lock circuit DFF and can be standard logic trigger (such as a d type flip flop), and the indicator signal N5VDO of its generation logical signal of a standard just.When fastening lock circuit DFF when being triggered, the signal level on the node N1 that can take a sample is also adjusted the level of indicator signal N5VDO according to sampling result; And, fasten the level that lock circuit DFF can keep indicator signal N5VDO when fastening lock circuit DFF when not being triggered.

Situation and the state of integrating operation as for overvoltage indicating circuit 36 of the present invention can illustrate with Fig. 3.Please refer to Fig. 3 (simultaneously in the lump with reference to figure 2); Fig. 3 is the waveform sequential of overvoltage indicating circuit 36 of the present invention each coherent signal when moving, and the transverse axis of each waveform is the time, and the longitudinal axis is represented the size of wave-shape amplitude.At moment t0, when the overvoltage incident does not take place and internal circuit 22 when all normally moving with buffer circuit 28, the signals DP on the interface port I/O can change (straight line with level VCCA among Fig. 3 comes the representation signal DP upper limit under normal circumstances) between bias voltage VCCA and GNDA.In this case, transistor Qe1 can conducting, and can to make the signal level of node N2 be low level (level of convergence bias voltage GNDA) to Duan resistance R with being connected in series to.Detector DTR detects the low level of node N2, can make detection signal DEO and signal Tg all be maintained low level.Low level detection signal DEO can triggering timing device TMR timing, and the high level among the timing signal POR2 just reflects the state that timer TMR does not pick up counting.Timing signal POR2 and detection signal DEO are after the logical operation of keyholed back plate circuit 30, and can make signal SW is high level, keeps the conducting of transistor Qe3.The transistor Qe3 of conducting can make the signal N5V of node N1 maintain low level with node N1 conducting to node N2.Low level signal N5V of stable state and signal Tg can not trigger and fasten lock circuit DFF sampling, so fasten lock circuit DFF indicator signal N5VDO are maintained at low level.In other words, when overvoltage does not take place in interface port I/O, even interface port I/O goes up transmitting the alternation data output signal DP is switched between high-low level, detector DTR in the overvoltage indicating circuit 36, fasten lock circuit DFF and timer TMR also easily is in lower state, each coherent signal N5V, SW, DEO, POR2 also maintain steady state level.

Suppose that arrived t1 constantly, overvoltage begins to attack interface port I/O, makes the signal level of signals DP rise to level Vov, paranormal bias voltage VCCA; Such as normal bias voltage VCCA can be 3.3V, and crossing voltage level Vov then can be up to 5V.In this case, transistor Qe1 will begin conducting, relatedly makes signal N5V on the node N1 also begin to rise; Simultaneously, the transistor Qe3 of conducting can make the signal level on the node N2 together rise with node N1.Arrived t2 constantly, detector DTR can detect signal N5V via the node N1 of conducting and N2 and surmount a preset standard (level Vst), and detector DTR will make the electrical level rising of detection signal DEO, reflects above-mentioned detecting result.The detection signal DEO of high level can make signal SW be reduced to low level at moment t3 via keyholed back plate circuit 30; And low level signal SW will make transistor Qe3 close, and interrupts the conducting between node N1, N2.This can be avoided overvoltage to continue injury overvoltage indicating circuit 36 via the long-time conducting of node N0, N1 and N2.Because no longer conducting of node N1, N2, Duan resistance R can make the level of node N2 descend with being connected serially to; The level that detector DTR detects node N2 descends, and will detection signal DEO be pulled low to low level at moment t4, reflection detecting result.On the other hand, the level of signal DEO changes (such as moment t2 rising edge) also can be reflected in trigger pip Tg via trigger circuit 38, and the level transitions of trigger pip also can trigger the signal N5V sampling of DFF to node N1, allow indicator signal N5VDO rise to high level, represent over-voltage events to begin.

On the other hand, the level transitions of detection signal DEO also can be picked up counting by moment t5 by triggering timing device TMR.Timer TMR can drag down the level of timing signal POR2 at moment t5, represents timing to begin to continue to carry out.Timer TMR can finish timing behind timing preset period of time T, just finish timing at moment t6, and once again timing signal POR2 is drawn high to high level, represents timing to finish.Between moment t5, t6, transistor Qe3 keeps and closes, and makes the level of node N2 be maintained low level.Arrived the moment t6 that timing finishes, because timing signal POR2 changes high level into, keyholed back plate circuit 30 also will make signal SW change high level at moment t7 jointly, allows transistor Qe3 conducting once again.Suppose that overvoltage this moment still continues, then when transistor Qe3 with node N1 conducting once again to node N2, the high level of node N1 will transfer to node N2 (when the moment of transistor Qe3 conducting, the saltus step that may experience the short time by interface port I/O conducting to the electric power of node N2 is to set up high level on node N2, this saltus step meeting is reflected in signal N5V a little).And detector DTR can detect the high level on the node N2 once again, and at the moment t8 level of detection signal DEO is drawn high, and represents detector DTR to detect high level again once again.When the level transitions of detection signal DEO is a high level, keyholed back plate circuit 30 will make the level of signal SW reduce (t9 constantly) according to the change of detection signal DEO.Low level signal SW closes transistor Qe3 again once again, prevents that overvoltage from continuing conducting to node N2.And the signal level of node N2 also can reduce because of resistance R, and jointly, detector DTR also can be pulled low to low level at moment t10 with detection signal DEO after detecting low level.

Behind moment t8, the detecting result of detector DTR changes can trigger DFF again via the trigger pip Tg of trigger circuit 38 once again to signal N5V sampling, so indicator signal N5VDO also can be maintained at high level, represents over-voltage events still to continue.On the other hand, timer TMR also can be triggered and be picked up counting by moment t11 once again, and the level of timing signal POR2 dragged down represents timing to begin.In the embodiment shown in fig. 3, suppose that over-voltage events finishes at moment t12.After over-voltage events finished, transistor Qe1 can close no longer conducting, but, and when moment t12, because also not conducting of transistor Qe3, so signal N5V should be maintained at high level.Timer TMR can finish timing at moment t13 again behind timing preset period of time T, and timing signal POR2 is returned to high level.According to the timing signal POR2 of high level, keyholed back plate circuit 30 can make signal SW raise to high level at moment t14, makes transistor Qe3 conducting once again.At this moment, owing to over-voltage events finishes transistor Qe1 is closed,, the signal level of node N1, N2 is all descended and level off to ground terminal voltage (bias voltage GNDA just) so the transistor Qe3 of conducting can be with node N1, the N2 conducting resistance R to ground connection.Arrived t15 constantly, signal N5V changes the convergence low level, and this signal transition just can be via trigger pip Tg that trigger circuit 38 produced and is triggered and fasten lock circuit DFF and once again signal N5V is taken a sample, will relatedly make indicator signal N5VDO be reduced to low level and fasten after lock circuit DFF is sampled to low level, represent over-voltage events to finish.Similarly, detector DTR detects the low level of node N2, also can keep the low level of detecting DEO, can not trigger TMR timing once again.In other words, when the overvoltage incident finishes, the state when each transistor Qe1 to Qe3, detector DTR, timer TMR, the running status of fastening circuit such as lock circuit DFF will return to t0 constantly.

The above-mentioned operation situation of overvoltage indicating circuit 36 of the present invention can be sketched and be two states, and whether the conducting of the available switching transistor Qe3 of the switching between state is represented; Transistor Qe1, Qe2 can realize a comparison means; Switching transistor Qe3, resistance R and detector DTR, timer TMR, keyholed back plate circuit 30, trigger circuit 38 can join together to be considered as a detecting control and management device.When transistor Qe3 conducting, the detecting control and management device runs on the detecting state, and detector DTR can continue to detect the signal level of node N2; If (such as when moment t0) do not take place in overvoltage, the detecting control and management device can continue to keep running status.Relatively, in case (just when the voltage on the interface port I/O greater than VCCA+Vtp time) takes place in over-voltage events, transistor Qe1, Qe2 in the comparison means can conducting make overvoltage be reflected into node N1 and N2, the detecting control and management device will come off switch transistor Qe3 via " node N2-detector DTR-keyholed back plate circuit 30-switching transistor Qe3 " this loop (can be considered first loop), allows the detecting control and management device switch to time status (such as between moment t5, t6).In time status, switching transistor Qe3 closes, and overvoltage no longer is reflected into node N2, and timer TMR also picks up counting.By the time timing finishes (such as at moment t6), and the timer TMR in " node N2-detector DTR-timer TMR-keyholed back plate circuit 30-switching transistor Qe3 " this loop (can be considered second loop) can make transistor Qe3 conducting once again, gets back to the detecting state.Under the detecting state, if overvoltage continues, the overvoltage meeting is reflected into node N2 via the transistor Qe3 of conducting, come off switch transistor Qe3 via " node N2-detector DTR-keyholed back plate circuit 30-switching transistor Qe3 " this loop (first loop) again, the detecting control and management device runs on time status (such as be constantly t11 after) once again; Otherwise, if overvoltage finishes, the detecting control and management device will continuous service in detecting state (such as be t15 after) constantly.Along with the operational mode of detecting control and management device is switched, fasten the lock circuit DFF sampling that also can be triggered, be reflected in indicator signal N5VDO with course with over-voltage events.

In other words, when the overvoltage incident took place, whether overvoltage indicating circuit 36 of the present invention can off and on, periodically be detected over-voltage events and finish, and can not continue to monitor, with the overvoltage injury overvoltage indicating circuit of avoiding continuing 36.

In the embodiment shown in fig. 3, constantly the mistiming between t2, t3, t4, t5 (and moment t6, t7, t8, t9, t10, t11) be basically by the circuit operation postpone caused, the mistiming is greatly about ns (1ns=10^ (9) second) level.Relatively, the period T of timer TMR timing then is μ s level (1 μ s=1000ns).

Please once again with reference to figure 2.As shown in Figure 2, overvoltage indicating circuit 36 of the present invention can draw high circuit 26 these overvoltage protective devices with the n trap with grid tracking circuit 24 and dispose, to promote the whole overvoltage protection function of circuit system S1.Further embodiment asks for an interview Fig. 4.Fig. 4 shows that in the lump grid tracking circuit 24 and n trap draw high the circuit diagram of circuit 26.The n trap draws high and is provided with p type MOS (metal-oxide-semiconductor) transistor Qa1 to Qa3 in the circuit 26, and signal GT and signal VNW can be provided.Be provided with n type MOS (metal-oxide-semiconductor) transistor Qb1 and p type MOS (metal-oxide-semiconductor) transistor Qb2, Qb3 in the grid tracking circuit 24.Then be provided with p type MOS (metal-oxide-semiconductor) transistor Qd1 and n type MOS (metal-oxide-semiconductor) transistor Qc, Qd2 in the buffer circuit 28.Grid tracking circuit 24 draws high circuit 16 with the grid tracking circuit 14 that operation logic is similar among Fig. 1 with the n trap with the circuit arrangement that the n trap draws high circuit 26, so repeats no more.But, just as discussed earlier, when having served as the Hair Fixer life, the transistor Qb2 in the grid tracking circuit 24 has the reliability doubt easily.When having served as the Hair Fixer life, the signal level of the signal GT of transistor Qb2 and node Np1 all raises with overvoltage, if the signal IP of internal circuit 22 on node Np2 just is again low level (level of convergence bias voltage GNDA), the huge level differences of low level node Np2 and overvoltage signal GT will cross-over connection in the gate oxide two ends of transistor Qb2, very easily cause the gate oxide collapse and damage transistor Qb2.

But, since overvoltage indicating circuit 36 of the present invention can be indicated the generation and the end of over-voltage events with the logic indicator signal N5VDO of standard, the present invention just can be fed back to internal circuit 22 with this indicator signal N5VDO, allows internal circuit 22 can take suitable protection process during overvoltage.For instance, when indicator signal N5VDO reflection over-voltage events took place, internal circuit 22 can be directly be increased to high level with the level of signal IP; So, the pressure reduction between node Np2 and signal GT will be contracted to safe pressure reduction, makes the gate oxide reliability doubt of transistor Qb2 be able to effective releasing.Certainly, internal circuit 22 also can be taked the protection process of other kind.

When the reality realization is of the present invention, can use circuit (such as Schmidt trigger) to realize detector DTR with magnetic hysteresis comparative characteristic with magnetic hysteresis (hysteretic) comparative characteristic.Timer TMR can be a timer by 36 special uses of overvoltage indicating circuit, and the electrify restoration circuit (POR, power-on reset) that all can be provided with in also can the general interface circuit of dual-purpose is realized timer TMR.In general, all an electrify restoration circuit can be set in chip or the integrated circuit, it can provide a power-on reset signal POR (such as being to provide to internal circuit, core circuit) to reflect the state that grid bias power supply is initial.When chip/integrated circuit will power on (power on) and after its bias voltage is increased to a certain predeterminable level gradually, the electrify restoration circuit preset period of time that will pick up counting, and finish the signal level that the back changes power-on reset signal POR in timing; And on behalf of grid bias power supply, the level transitions of signal POR just be ready to complete (ready), and the state machine in internal circuit/core circuit, trigger or the like can begin to set its original state, prepares operation.Because electrify restoration circuit itself just has clocking capability, so can be used to realize timer TMR in the overvoltage indicating device of the present invention.But, in order to keep normal power-on reset signal POR, the present invention can set up an auxiliary circuit 32 in overvoltage indicating circuit 36, shown in Fig. 2 (or Fig. 4).The signal POR2 that timer TMR (electrify restoration circuit just) provides originally can be used to be used as timing signal required in the overvoltage indicating circuit 36 with POR3 (both can be identical signals), and real power-on reset signal POR is then provided by auxiliary circuit 32.Just as shown in Fig. 2 (or Fig. 4), be provided with a phase inverter L4 and a rejection gate L3 in this auxiliary circuit 32, to produce signal POR according to indicator signal N5VDO and timing signal POR3.In addition, timer TMR also provides a signal POR1 to the clear terminal CLR that fastens lock circuit DFF.

Please refer to Fig. 5 (simultaneously in the lump with reference to figure 2); When realizing timer TMR of the present invention with electrify restoration circuit, the timing waveform of each coherent signal is that available Fig. 5 is illustrated.When circuit system S1 start (turn on), the level of bias voltage VCCA can rise gradually; Arrived ta constantly, after the electrical level rising of bias voltage VCCA surpassed a certain predeterminable level, electrify restoration circuit (timer TMR) will pick up counting.Finish in moment tb timing behind the timing and continuous one preset period of time T, and signal POR, POR1-POR3 will change high level into by low level at moment tb, represent grid bias power supply to be ready to complete, internal circuit 22 can begin to reset the operation initial value.Simultaneously, signal POR1 can remove and fasten lock circuit DFF, makes indicator signal N5VDO be maintained at low level.Behind the tb, each circuit among the circuit system S1 (comprising internal circuit 22, interface circuit 20 etc.) will begin normal operation constantly.Suppose to take place in moment tc over-voltage events, electrify restoration circuit will be used to be used as timer TMR required in the overvoltage indicating circuit; Timing signal POR2/POR3 can change level (as shown in Figure 3) with the operation of keyholed back plate arrangement for detecting, and indicator signal N5VDO also can change the generation that high level reflects over-voltage events into by low level, and transfers the end that low level reflects over-voltage events at moment td to by high level.But, because the operation of auxiliary circuit 32, during over-voltage events (or afterwards), signal POR can normal dimensions be held in high level; Also therefore signal POR can be used as real power-on reset signal.In other words, signal POR only can change level during powering on; After bias voltage was ready to complete, no matter whether overvoltage takes place, signal POR can not change level.This also be standard power-on reset signal the sequential that should have.

Because the present invention can utilize electrify restoration circuit to take into account the required clocking capability of overvoltage indication, so overvoltage indicating circuit 36 of the present invention can't take too much extra layout area.Certainly, just as aforementioned, timer TMR also can be a special circuit that is independent of outside the electrify restoration circuit; So, just auxiliary circuit 32 need not be set in the overvoltage indicating circuit 36.

In summary, only in interface circuit, carry out the overvoltage protection compared to known technology, overvoltage indication technology of the present invention can provide the overvoltage indicator signal to the internal circuit (core circuit) of chip/integrated circuit, make internal circuit during overvoltage, take suitable overvoltage protection process, carry out more perfect, more fully overvoltage protection according to the indication of overvoltage indicator signal.In addition, overvoltage indicating circuit of the present invention can intermittence, periodicity be detected the overvoltage situation during overvoltage, avoids the overvoltage injury overvoltage indicating circuit itself that continues.And overvoltage indicating circuit of the present invention is easy to just can be integrated in present interfaces circuit (such as being to utilize electrify restoration circuit to realize timer), can reduce its spent layout area as far as possible.

In sum; the above is only unrestricted for preferred embodiment of the present invention; those of ordinary skill in the art is to be understood that; can make amendment or be equal to replacement technical scheme of the present invention; and do not break away from the spirit and scope of technical solution of the present invention, so protection scope of the present invention is as the criterion when the content with accompanying Claim.

Claims

1. overvoltage indicating circuit, it provides an indicator signal to reflect the signal level size on the interface port; It is characterized in that this overvoltage indicating circuit includes:

One comparer is connected between this interface port and the sampling end, this comparer relatively the signal level on this interface port whether greater than a default conduction level; If then this comparer is held this interface port conducting to this sampling; If not, this comparer stops the conducting between this interface port and this sampling end;

One switch is connected between a sense terminal and this sampling end; When this switch activator, this switch should be taken a sample the end conducting to this sense terminal; When this switch cut out, this switch stopped the conducting between this sampling end and this sense terminal;

One timer, it provides a timing signal; When this timer was triggered, this timer began to carry out timing, and utilized the signal level reflection timing of this timing signal to finish after timing one preset period of time;

One detector is connected to this sense terminal, and whether its signal level of detecting on this sense terminal surmounts a preset standard; If then this detector triggers this timer and picks up counting; If not, then this detector does not trigger this timer timing;

One keyholed back plate circuit is connected between this timer, this detector and this switch; When this detector detects signal level reflection timing that signal level on this sense terminal do not surmount this preset standard or this timing signal when finishing, this keyholed back plate circuit makes this switch activator; Otherwise this keyholed back plate circuit is closed this switch;

One trigger circuit, it provides a trigger pip according to the signal level on the detecting result of detector and the sampling end; And

One fastens lock circuit, is connected in this sampling end; This is fastened lock circuit and produces this indicator signal according to the triggering of this trigger pip.

2. overvoltage indicating circuit as claimed in claim 1 is characterized in that, also includes:

One load circuit is connected in this sense terminal; When this switch activator and during this comparer stop conducting, this load circuit makes the signal level on this sense terminal can not surmount this preset standard.

3. overvoltage indicating circuit as claimed in claim 2 is characterized in that, this load circuit is a resistance.

4. overvoltage indicating circuit as claimed in claim 1 is characterized in that, also includes:

One level adjusting circuit is connected between this interface port and this sampling end; When this comparer with this interface port conducting to this when end sampling, this level adjusting circuit is the signal level skew of this interface port, and the signal conduction of this comparer after with this level deviation is to this sampling end.

5. overvoltage indicating circuit as claimed in claim 1 is characterized in that, this timer is an electrify restoration circuit.

6. overvoltage indicating circuit as claimed in claim 5 is characterized in that, also includes:

One auxiliary circuit is connected in this timer; This auxiliary circuit provides a power-on reset signal; Pick up counting when this detector triggers this timer, this auxiliary circuit is kept the signal level of this power-on reset signal.

7. overvoltage indicating circuit, it provides an indicator signal to reflect the signal level size on the interface port; It is characterized in that this overvoltage indicating circuit includes:

One comparison means, this comparison means relatively the signal level on this interface port whether greater than a predeterminated voltage; If then this comparison means provides a logic high on a sampling end;

One detecting control and management device, it runs on a detecting state and a time status; When this detecting control and management device runs on this detecting state, if the signal level on this interface port, then should be detected the control and management device switchover operation greater than a default conduction level in this time status; Otherwise this detecting control and management device continuous service provides a logic low in this detecting state and on this sampling end; And when this detecting control and management device runs on this time status, this detecting control and management device after timing one preset period of time again switchover operation in this detecting state; And

One fastens lock circuit; When this detecting control and management device switch mode, this fastens that lock circuit is triggered and signal level that this sampling of taking a sample is held, and adjusts the level of this indicator signal according to sampling result; And fasten lock circuit when not being triggered when this, this fastens the level that lock circuit is kept this indicator signal.

8. overvoltage indicating circuit as claimed in claim 7 is characterized in that, when this detecting control and management device ran on this time status, this detecting control and management device did not change the signal level on this sampling end.

9. circuit system is characterized in that it includes:

One buffer circuit, it has an interface port; This buffer circuit drives the output signal of a correspondence on this interface port according to an input signal;

One overvoltage indicating circuit, whether it presets the indicator signal that conduction level provides a correspondence greater than one according to the signal level on this interface port; And

One internal circuit is used to provide this input signal; And when this overvoltage indicating circuit indicated signal level on this interface port greater than this predetermined level, this internal circuit made this input signal be maintained at a safety level.

10. circuit system as claimed in claim 9 is characterized in that, also includes:

One n trap draws high circuit, and it provides the signal of a correspondence according to the signal magnitude on this interface port; When the signal level on this interface port during greater than this default conduction level, this n trap draws high the raise level of this signal of circuit; And

One grid tracking circuit is electrically connected between this internal circuit and this buffer circuit, is used for controlling the conducting between this internal circuit and this buffer circuit; This internal circuit is electrically connected to this grid tracking circuit by a transmission ends, and this grid tracking circuit is provided with a gate terminal in addition to receive this signal;

Wherein, when this overvoltage indicating circuit indicated signal level on this interface port to make this internal circuit that input signal is maintained at a safety level greater than this default conduction level, this internal circuit made signal level difference between this transmission ends and this gate terminal less than a safe pressure reduction.

11. a method of carrying out the overvoltage indication with an overvoltage indicating circuit, it provides an indicator signal to indicate the signal level on the interface port; Be provided with a switch and first loop and second loop that are connected in this switch in this overvoltage indicating circuit, it is characterized in that this method includes:

Carry out state detecting, it includes:

Relatively whether overvoltage of the signal level on this interface port; If the level that then makes this indicator signal is a logic high, and finishes this detecting state and proceed to a time status via this first loop; If not, then making the level of this indicator signal is a logic low, and is maintained at this detecting state;

And this time status includes:

Finish this time status after timing one preset period of time and proceed to this detecting state via this second loop.

12. method as claimed in claim 11 is characterized in that, this first loop is connection one detector, a keyholed back plate circuit and this switch, and this second loop is for connecting this detector, a timer, this keyholed back plate circuit and this switch.