CN100505883C - Digital television course experiment system - Google Patents
Digital television course experiment system Download PDFInfo
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- CN100505883C CN100505883C CN 200710021886 CN200710021886A CN100505883C CN 100505883 C CN100505883 C CN 100505883C CN 200710021886 CN200710021886 CN 200710021886 CN 200710021886 A CN200710021886 A CN 200710021886A CN 100505883 C CN100505883 C CN 100505883C
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Abstract
A test system of digital TV course comprises DVD signal source, audio/video AD/DA module, audio/video signal source coding module, audio/video decoding module, digital TV monitor and video camera shooting head. It is featured as forming audio/video signal source coding module by master chip and peripheral chip of coding module and forming video decoding module by master chip and data receiver as well as buffer chip of D/A conversion module.
Description
Technical field
What digital television course experiment system of the present invention related to is a kind of digital television transmission system that designs and produce according to the Digital Television international standard fully, can provide digital television course required some experiments, the experimental provision when can be used as the training of real figure television transmission course simultaneously.
Background technology
Since the appearance of Digital Television MPEG2 technical standard, constantly release based on the TV station's business solution and the new equipment of MPEG2 technology, attracted numerous sight of broadcast television industry, also attracted the attention of numerous colleges and universities relevant speciality.Current in many cities of China, use the Digital Television of MPEG2 technology realization and come into huge numbers of families.The MPEG technology has won common attention just because of this.Numerous universities and colleges have also begun digital television course in succession, and the fully corresponding experimental facilities of standard does not also possess therewith, so far also do not have a kind of equipment intactly to reflect the usefulness that supplies student experimenting or training to international standard, and the MPEG coding/decoding module of department's special uses such as TV station can not represent current encoding compression technology all sidedly.
Summary of the invention
The objective of the invention is provides a kind of digital television course experiment system at above-mentioned weak point, the digital television transmission system that this system designs and produces according to the Digital Television international standard fully, can provide digital television course required some experiments, the experimental provision when can be used as the training of real figure television transmission course simultaneously.
Digital television course experiment system is to take following scheme to realize: digital television course experiment system comprises the DVD signal source, looks audio A/the DA module, looks the audio sources coding module, looks audio decoder module, digital television monitor, video frequency pick-up head.
Look the master chip of audio sources coding module by coding module, peripheral chip constitutes, the master chip of coding module adopts the MB86391A chip of Fuji Tsu, peripheral chip comprises: main program memory MBM29LV800 able to programme, two video data buffer SDRAM HV57V643220DTP-6, be used as the buffer of the master chip processing video data of coding module, wherein the voice data of audio A/D interface circuit PCM1800 directly links to each other with the voice data interface of the master chip of coding module, and the video data port of coding module master chip receives the normal video dateout from the video a/d chip SAA7114 of PHLIPS; Audio A/D interface circuit PCM1800 links to each other with the crystal oscillator of HO-12B with video a/d chip SAA7114 (frequency is 24.576MHz), and the quantification clock of the two provides by it; Two video data buffer SDRAM HV57V643220DTP-6 are used as the buffer of the master chip processing video data of coding module, also link to each other with the master chip MB86391A of coding module; The crystal oscillator of model HO-12B16.384MHZ also links to each other with the master chip MB86391A of coding module, for its coding provides clock; In addition, the master chip of coding module also provides the external series control interface, and by chip EPM7128 interface (its effect is sequential adjustment and data buffering) suitably cushion with single-chip microcomputer 891v52 carry out the setting and the adjustment of coding parameter, the compression coding mode of setting during the video/audio process single-chip microcomputer initialization of the master chip of this coding module to input is encoded, and then the data after will encoding pass to 2 coupled rectification chip 74HC245D8E380 and carry out rectification, and then give 3 TS flow data generator AM26LV31C chips with signal and form standard TS stream and send system flow by special-purpose code stream output port.
This system flow is sent into parallel DVB interface through the TS transport stream of the processing formation standard of data buffering processing unit, and this interface divides two-way output, and one the tunnel directly delivers to the mpeg decode circuit module decodes the video that obtains reducing, audio frequency simulation output signal; The respective coding parameter can be analyzed for the code stream analysis instrument in another road.The test point that code stream analysis test module wherein (corresponding to the test module among the figure) is corresponding has: the high-order test point of bit stream data, code stream clock test point, code stream useful signal test point, code stream synchronizing signal test point, code stream character error indication test point, video sampling clock test point, video line lock-out pulse test point, video field system chronizing impulse test point, audio frequency left and right acoustic channels clock test point, audio coding clock test point, audio system clock test point.
Look master chip, data sink, buffer chip that the audio decoder module comprises digital-to-analogue conversion.The master chip of digital-to-analogue conversion adopts the MB86H20 of Fujitsu chip, data sink is responsible for receiving and buffering is handled TS stream, and data sink adopts three TS flow data receiver AM26LV32C receiving chips to link to each other with the MB86H20 of master chip Fujitsu of the digital-to-analogue conversion of the demultiplexing of finishing TS stream and video/audio signal; The buffer chip HY57V641620HG that is responsible for bit stream buffer simultaneously also links to each other with the master chip of digital-to-analogue conversion; Signal after the processing is delivered to output interface, and this interface is given digital television monitor (television set) by the transmission line of decoding deck back with signal and shown.The crystal oscillator of 27M also links to each other with the master chip MB86H20 of digital-to-analogue conversion simultaneously, provides clock for it provides the D/A conversion of looking audio frequency.
The digital television course experiment system characteristics:
1, can provide multiple signal input modes such as DVD and color bar signal;
2, support PAL and two kinds of television systems of NTSC;
3, support D1, HALF D1, multiple image display format such as SIF;
4, system adopts software setting, the mode that hardware testing observation combines;
5, able to programme multiple stream rate is set;
6, observation station is many, can measure the various parameters that relate in the standard;
7, mentality of designing is clear, the principle of combining closely
Description of drawings
The invention will be further described below with reference to accompanying drawing.
Fig. 1 be digital television course experiment system look audio sources coding module electronic schematic.
Fig. 2 be digital television course experiment system look audio decoder module electronic schematic diagram.
Fig. 3 is the digital television course experiment system schematic diagram.
Embodiment
With reference to accompanying drawing 1,2,3, digital television course experiment system comprises the DVD signal source, looks audio A/the DA module, looks the audio sources coding module, looks audio decoder module, digital television monitor, video frequency pick-up head.
Look the master chip of audio sources coding module by coding module, peripheral chip constitutes, the master chip of coding module adopts the MB86391A chip of Fuji Tsu, peripheral chip comprises: main program memory MBM29LV800 able to programme, two video data buffer SDRAM HV57V643220DTP-6, be used as the buffer of the master chip processing video data of coding module, wherein the voice data of audio A/D interface circuit PCM1800 directly links to each other with the voice data interface of master chip, and the video data port of coding module master chip receives the normal video dateout from the video a/d chip SAA7114 of PHLIPS; Audio A/D interface circuit PCM1800 links to each other with the crystal oscillator of HO-12B with video a/d chip SAA7114 (frequency is 24.576MHz), and the quantification clock of the two provides by it; Two two video data buffer SDRAM HV57V643220DTP-6 are used as the buffer of the master chip processing video data of coding module, also link to each other with the master chip MB86391A of coding module; The crystal oscillator of model HO-12B16.384MHZ also links to each other with the master chip MB86391A of coding module, for its coding provides clock; In addition, the master chip of coding module also provides the external series control interface, and by chip EPM7128 interface (its effect is sequential adjustment and data buffering) suitably cushion with single-chip microcomputer 891v52 carry out the setting and the adjustment of coding parameter, the compression coding mode of setting during the video/audio process single-chip microcomputer initialization of the master chip of this coding module to input is encoded, and then the data after will encoding pass to 2 coupled 74HC245D8E380 chips and carry out rectification, and then give 3 AM26LV31C chips with signal and form standard TS stream and send system flow by special-purpose code stream output port.
This system flow is sent into parallel DVB interface through the TS transport stream of the processing formation standard of data buffering processing unit, and this interface divides two-way output, and one the tunnel directly delivers to the mpeg decode circuit module decodes the video that obtains reducing, audio frequency simulation output signal; The respective coding parameter can be analyzed for the code stream analysis instrument in another road.The test point that code stream analysis test module wherein (corresponding to the test module among the figure) is corresponding has: the high-order test point of bit stream data, code stream clock test point, code stream useful signal test point, code stream synchronizing signal test point, code stream character error indication test point, video sampling clock test point, video line lock-out pulse test point, video field system chronizing impulse test point, audio frequency left and right acoustic channels clock test point, audio coding clock test point, audio system clock test point.
Look master chip, data sink, buffer chip that the audio decoder module comprises digital-to-analogue conversion.The master chip of digital-to-analogue conversion adopts the MB86H20 of Fujitsu chip, data sink is responsible for receiving and buffering is handled TS stream, and data sink adopts three AM26LV32C receiving chips to link to each other with the MB86H20 of master chip Fujitsu of the digital-to-analogue conversion of the demultiplexing of finishing TS stream and video/audio signal; The buffer chip HY57V641620HG that is responsible for bit stream buffer simultaneously also links to each other with the master chip of digital-to-analogue conversion; Signal after the processing is delivered to output interface, and this interface is given digital television monitor (television set) by the transmission line of decoding deck back with signal and shown.The crystal oscillator of 27M also links to each other with the master chip MB86H20 of digital-to-analogue conversion simultaneously, provides clock for it provides the D/A conversion of looking audio frequency.
With reference to digital television course experiment system shown in the accompanying drawing 3 (JH8000DTV) mainly by the DVD signal source, look audio A/DA module, look audio sources coding module (internal structure such as accompanying drawing 1), look audio decoder module (internal structure such as Fig. 2), digital television monitor, video frequency pick-up head constitutes.Digital television course experiment system also is provided with master switch (total power switch) and module switch is respectively switch 1, switch 2, switch 3.The DVD signal source adopts DVD player.
With reference to accompanying drawing 1, the master chip of coding module adopts the MB86391A chip of Fuji Tsu, peripheral chip comprises: main program memory MBM29LV800 able to programme, two SDRAM HV57V643220DTP-6 are used as the buffer of the master chip processing video data of coding module, wherein the voice data of audio A/D interface circuit PCM1800 directly links to each other with the voice data interface of master chip, and the video data port of the master chip of coding module receives the normal video dateout from the video a/d chip SAA7114 of PHLIPS; PCM1800 links to each other with the crystal oscillator of HO-12B with SAA7114 (frequency is 24.576MHz), and the quantification clock of the two provides by it; Two SDRAM HV57V643220DTP-6 are used as the buffer of the master chip processing video data of coding module, also link to each other with the master chip MB86391A of coding module; The crystal oscillator of model HO-12B16.384MHZ also links to each other with the master chip MB86391A of coding module, for its coding provides clock; In addition, the master chip of coding module also provides the external series control interface, and by chip EPM7128 interface (its effect is sequential adjustment and data buffering) suitably cushion with single-chip microcomputer 89lv52 carry out the setting and the adjustment of coding parameter, the compression coding mode of setting during the video/audio process single-chip microcomputer initialization of the master chip of this coding module to input is encoded, and then the data after will encoding pass to 2 coupled 74HC245D8E380 chips and carry out rectification, and then give 3 AM26LV31C chips with signal and form standard TS stream and send system flow by special-purpose code stream output port.
This system flow is sent into parallel DVB interface through the TS stream of the processing formation standard of data buffering processing unit, and this interface divides two-way output, and one the tunnel directly delivers to the mpeg decode circuit module decodes the video that obtains reducing, audio frequency simulation output signal; The respective coding parameter can be analyzed for the code stream analysis instrument in another road.The test point that code stream analysis test module wherein (corresponding to the test module among the figure) is corresponding has: the high-order test point of bit stream data, code stream clock test point, code stream useful signal test point, code stream synchronizing signal test point, code stream character error indication test point, video sampling clock test point, video line lock-out pulse test point, video field system chronizing impulse test point, audio frequency left and right acoustic channels clock test point, audio coding clock test point, audio system clock test point.
With reference to Fig. 2, data sink is responsible for receiving and buffering is handled TS stream, and three AM26LV32C receiving chips in the data sink link to each other with the MB86H20 of master chip Fujitsu of the digital-to-analogue conversion of the demultiplexing of finishing TS stream and video/audio signal; The HY57V641620HG that is responsible for bit stream buffer simultaneously also links to each other with the master chip of digital-to-analogue conversion; Signal after the processing is delivered to output interface, and this interface is given monitor (television set) by the transmission line of decoding deck back with signal and shown.The crystal oscillator of 27M also links to each other with the master chip MB86H20 of digital-to-analogue conversion simultaneously, provides clock for it provides the D/A conversion of looking audio frequency.
In conjunction with the accompanying drawings 1, accompanying drawing 2, the flow process of accompanying drawing 3 signals is discussed below: signal has the DVD signal source to produce (corresponding to Fig. 1 look the audio analog signals input), interface by the DVD back passes through holding wire (1 video connecting line, 1 left channel signals line, 1 right-channel signals line) passes to mpeg encoded module brassboard (internal structure and signal flow such as Fig. 1), this moment, signal was divided into two-way, one the tunnel is analog video signal, one the tunnel is simulated audio signal, wherein vision signal is sent the sampling quantification of carrying out vision signal as SAA7114, audio signal is sent into PCM1800 and is quantized, obtain behind the 24.576MHz clock division that the crystal oscillator of the quantification clock HO-12B of the two provides, digital signal after the quantification is sent into master chip and is carried out compressed encoding and multiplexing, master chip can be used two models when handling vision signal be SDRAMHV57V643220DTP-6 (cache chip), in chip MBM29LV800, there is simultaneously the required program of master chip, master chip is given 74HC245D8E380 and AM26LV31C with signal and is adjusted the TS stream of handling the formation standard after video/audio signal is disposed, send into parallel DVB interface, this interface divides two-way output, one the tunnel directly delivers to the mpeg decode circuit module decodes the video that obtains reducing, the audio frequency simulation output signal; The respective coding parameter can be analyzed for the code stream analysis instrument in another road.
On computer interface, can change and experimentize parameter relevant in the Digital Television, 232 interfaces of computer 232 interface lines one termination computer, the serial ports of another termination experimental system (being the serial ports among Fig. 1), this serial ports links to each other with master chip with chip EPM7128 by single-chip microcomputer.Receiving terminal mpeg decode module brassboard (as Fig. 2) is by the standard composite bit stream signal of connecting line reception in parallel port from the coding module sign indicating number, then it is given the three chip block AM26LV32C that receive TS stream, chip is given demultiplexing decoding and the inverse quantization (clock is provided by the 27MHZ crystal oscillator) that the decoder module master chip MB86H20 of Fujitsu carries out signal at the signal that receives, and at last the analog signal of recovering is delivered to television set and observes.
It is such that above signal flow is summarized: the DVD signal source
Mpeg encoded module brassboard
Mpeg encoded module brassboard
Monitor (open master switch and switch 2, switch 3 gets final product); The system that also can be constructed as follows of this system in addition: DVD signal source
Look audio A/DA module brassboard
Monitor (open master switch and switch 1 gets final product)
Experiment of the present invention and operation:
(1) in the accompanying drawing 3 there be the experiment of the corresponding AD/DA module correspondence of looking audio frequency:
(this software is corresponding with system for software, based on the VB.net environment) on can carry out: the colourity setting, the contrast setting, input signal source select to be provided with, the signal source standard is provided with, field signal sign row is provided with, and row valid pixel number is provided with, and light tone postpones to be provided with, colour is closed setting, audio sampling frequency is provided with, and the audio quantization bit number is provided with, the silent mode setting
The test that can carry out on the hardware: the line synchronizing signal test of simulated television, the field sync signal test of simulated television, parity field signal FID test point reference clock signal RTC test, data clock DATACLK test, the test of 10bit dateout, left and right sides clock ALRCK test, voice data ADATA test, audio bit clock BCK test, audio bit clock ASCLK test
(2) the video encoding parameter is provided with experiment and the operation that module (corresponding diagram 1) can carry out has:
(this software is corresponding with system for software, develop with VB.net) on can carry out: the system pattern setting, MPEG-1 or MPEG-2 coded system can be set, system coding code stream pattern is provided with, the encoding code stream output format can be set: program stream (PS) or transmission code stream (TS), the gop structure that is provided with able to programme: I, B, the combination of P frame, comprise I, IP, IBP, IBBP etc., the code rate that is provided with able to programme: 512K---15M (NX256K, N=2-57), digital video identification code: the VPID that is provided with able to programme, digital audio identification code: the APID that is provided with able to programme, digital reference clock identification code: the PCRPID that is provided with able to programme, setting able to programme is video coding only, audio frequency is the coding work mode not, audio work layer layer1 and layer2 can be set, audio sample rates is set, the audio coding output speed is set, the audio preemphasis pattern is set, the audio track tupe is set, audio frequency PES sign is set, the coding mode that is provided with able to programme, (NX256K N=2-57), is provided with the image sampling pattern to the code rate that is provided with able to programme: 512K-15M, the GOP pattern that is provided with able to programme, the GOP length that is provided with able to programme, the image encoding that is provided with able to programme: D1,4/3D1,2/3D1,1/2D1, SIF, QSIF, SliceScreen, the image preliminary treatment filter patterns that is provided with able to programme.
The test that can carry out on the hardware: the high bit test of bit stream data, the code stream clock test, the test of code stream useful signal, the test of code stream synchronizing signal, code stream character error indication test, the video sampling clock test, the test of video line lock-out pulse, the test of video field system chronizing impulse, audio frequency left and right acoustic channels clock test, the audio coding clock test, the audio system clock test
(3) looking experiment and the operation that audio decoder sign indicating number module (respective figure 2) can carry out has:
Can survey TS flow data (LSB), TS flows valid data, the encoded clock test point, and the TS flow data is synchronous, left and right acoustic channels output, image output also can be carried out volume setting and program searching and look that audio identification PID checks program etc. by little button
Claims (3)
1, a kind of digital television course experiment system is characterized in that experimental system comprises the DVD signal source, looks audio A/the DA module, looks the audio sources coding module, looks audio decoder module, digital television monitor, video frequency pick-up head;
Looking the audio sources coding module is made of master chip, the peripheral chip of coding module, peripheral chip comprises main program memory MBM29LV800 able to programme, two video data buffer SDRAM HV57V643220DTP-6, be used as the buffer of the master chip processing video data of coding module, wherein the voice data of audio A/D interface circuit PCM1800 directly links to each other the normal video dateout of the video data port receiver, video A/D chip SAA7114 of the master chip of coding module with the voice data interface of the master chip of coding module; Audio A/D interface circuit PCM1800 links to each other with crystal oscillator HO-12B with video a/d chip SAA7114, and the quantification clock of the two provides by it; Two video data buffer SDRAM HV57V643220DTP-6 are used as the buffer of the master chip processing video data of coding module, also link to each other with the master chip of coding module; Crystal oscillator HO-12B also links to each other with the master chip of coding module, for its coding provides clock; In addition, the master chip of coding module also provides the external series control interface, this interface carries out sequential adjustment and data buffering by chip EPM7128, so that single-chip microcomputer 891v52 carries out the setting and the adjustment of coding parameter, the compression coding mode of setting during the video/audio process single-chip microcomputer initialization of the master chip of this coding module to input is encoded, and then the data after will encoding pass to 2 coupled rectification chip 74HC245D8E380 and carry out rectification, and then give 3 TS flow data generator AM26LV31C chips with signal and form standard TS stream and send system flow by special-purpose code stream output port;
Look master chip, data sink, data buffering processing unit that the audio decoder module comprises the D/A conversion; Data sink is responsible for receiving and buffering processing standard TS stream, and data sink adopts three TS flow data receiver AM26LV32C receiving chips to link to each other with the master chip of the D/A conversion of the demultiplexing of finishing standard TS stream and video/audio signal; The buffer chip HY57V641620HG of data buffering processing unit also links to each other with the master chip of D/A conversion simultaneously; Signal after the processing is delivered to output interface, and this interface is given digital television monitor by the transmission line of decoding deck back with signal and shown, crystal oscillator also links to each other with the master chip of D/A conversion simultaneously, for its D/A conversion of looking audio frequency provides clock;
The master chip of described coding module adopts the MB86391A chip of Fuji Tsu.
2, digital television course experiment system according to claim 1, it is characterized in that this system flow forms standard TS stream through the processing of data buffering processing unit, send into parallel DVB interface, this interface divides two-way output, one the tunnel directly delivers to and looks the audio decoder module and decode the video that obtains reducing, audio frequency simulation output signal; The respective coding parameter is analyzed for the code stream analysis instrument in another road; The test point of code stream analysis test module correspondence wherein has: the high-order test point of bit stream data, code stream clock test point, code stream useful signal test point, code stream synchronizing signal test point, code stream character error indication test point, video sampling clock test point, video line lock-out pulse test point, video field system chronizing impulse test point, audio frequency left and right acoustic channels clock test point, audio coding clock test point, audio system clock test point.
3, digital television course experiment system according to claim 1 is characterized in that the master chip of D/A conversion adopts the MB86H20 of Fujitsu master chip.
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| Application Number | Priority Date | Filing Date | Title |
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| CN 200710021886 CN100505883C (en) | 2007-05-09 | 2007-05-09 | Digital television course experiment system |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 200710021886 CN100505883C (en) | 2007-05-09 | 2007-05-09 | Digital television course experiment system |
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| CN100505883C true CN100505883C (en) | 2009-06-24 |
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| CN102316289A (en) * | 2010-07-09 | 2012-01-11 | 深圳Tcl新技术有限公司 | Menu processing method for dual-chip television scheme |
| CN105611317A (en) * | 2016-01-18 | 2016-05-25 | 北京流金岁月文化传播股份有限公司 | Video-audio transcoding device and method capable of supporting audio unvarnished transmission |
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